Counters • 14-Stage Ripple Carry Binary Counters

CD4020BC • CD4040BC • CD4060BC 14-Stage Ripple Carry Binary Counters • 12-Stage Ripple Carry Binary
October 1987
Revised January 1999

CD4020BC • CD4040BC • CD4060BC

14-Stage Ripple Carry Binary Counters •
12-Stage Ripple Carry Binary Counters •
14-Stage Ripple Carry Binary Counters
General Description Features
The CD4020BC, CD4060BC are 14-stage ripple carry ■ Wide supply voltage range: 1.0V to 15V
binary counters, and the CD4040BC is a 12-stage ripple ■ High noise immunity: 0.45 VDD (typ.)
carry binary counter. The counters are advanced one count
on the negative transition of each clock pulse. The ■ Low power TTL compatibility: Fan out of 2 driving 74L
counters are reset to the zero state by a logical “1” at the or 1 driving 74LS
reset input independent of clock. ■ Medium speed operation: 8 MHz typ. at VDD = 10V
■ Schmitt trigger clock input

Ordering Code:
Order Number Package Number Package Description
CD4020BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
CD4020BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CD4040BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
CD4040BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4040BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CD4060BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
CD4060BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams
Pin Assignments for DIP and SOIC Pin Assignments for DIP, SOIC and SOP
CD4020BC CD4040BC

Top View Top View

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CD4020BC • CD4040BC • CD4060BC
Connection Diagrams (Continued)
Pin Assignments for DIP and SOIC
CD4060BC

Top View

Schematic Diagrams
CD4020BC

CD4040BC

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 CD4020BC • CD4040BC • CD4060BC
CD4060BC

CD4060B Typical Oscillator Connections

RC Oscillator

Crystal Oscillator

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CD4020BC • CD4040BC • CD4060BC
Absolute Maximum Ratings(Note 1) Recommended Operating
(Note 2) Conditions
Supply Voltage (VDD) −0.5V to +18V Supply Voltage (VDD) +3V to +15V
Input Voltage (VIN) −0.5V to VDD +0.5V Input Voltage (VIN) 0V to VDD
Storage Temperature Range (TS) −65°C to +150°C Operating Temperature Range (TA) −40°C to +85°C
Package Dissipation (PD) Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
Dual-In-Line 700 mW
that the devices should be operated at these limits. The tables of “Recom-
Small Outline 500 mW mended Operating Conditions” and “Electrical Characteristics” provide con-
ditions for actual device operation.
Lead Temperature (TL)
Note 2: VSS = 0V unless otherwise specified.
(Soldering, 10 seconds) 260°C

DC Electrical Characteristics (Note 2)

−40°C +25°C +85°C
Symbol Parameter Conditions Units
Min Max Min Typ Max Min Max
IDD Quiescent Device Current VDD = 5V, VIN = VDD or VSS 20 20 150 µA
VDD = 10V, VIN = VDD or VSS 40 40 300 µA
VDD = 15V, VIN = VDD or VSS 80 80 600 µA
VOL LOW Level Output Voltage VDD = 5V 0.05 0 0.05 0.05 V
VDD = 10V 0.05 0 0.05 0.05 V
VDD = 15V 0.05 0 0.05 0.05 V
VOH HIGH Level Output Voltage VDD = 5V 4.95 4.95 5 4.95 V
VDD = 10V 9.95 9.95 10 9.95 V
VDD = 15V 14.95 14.95 15 14.95 V
VIL LOW Level Input Voltage VDD = 5V, VO = 0.5V or 4.5V 1.5 2 1.5 1.5 V
VDD = 10V, VO = 1.0V or 9.0V 3.0 4 3.0 3.0 V
VDD = 15V, VO = 1.5V or 13.5V 4.0 6 4.0 4.0 V
VIH HIGH Level Input Voltage VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3 3.5 V
VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 6 7.0 V
VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 9 11.0 V
IOL LOW Level Output Current VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA
(Note 3) VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA
VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA
IOH HIGH Level Output Current VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA
(Note 3) VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA
VDD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 mA
IIN Input Current VDD = 15V, VIN = 0V −0.30 −10−5 −0.30 −1.0 µA
VDD = 15V, VIN = 15V 0.30 10−5 0.30 1.0 µA
Note 3: Data does not apply to oscillator points φ0 and φ0 of CD4060BC. IOH and IOL are tested one output at a time.

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 CD4020BC • CD4040BC • CD4060BC
AC Electrical Characteristics (Note 4)
CD4020BC, CD4040BC TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units

tPHL1, tPLH1 Propagation Delay Time to Q1 VDD = 5V 250 550 ns

VDD = 10V 100 210 ns
VDD = 15V 75 150 ns
tPHL, tPLH Interstage Propagation Delay Time VDD = 5V 150 330 ns
from Qn to Qn+1 VDD = 10V 60 125 ns
VDD = 15V 45 90 ns
tTHL, tTLH Transition Time VDD = 5V 100 200 ns
VDD = 10V 50 100 ns
VDD = 15V 40 80 ns
tWL, tWH Minimum Clock Pulse Width VDD = 5V 125 335 ns
VDD = 10V 50 125 ns
VDD = 15V 40 100 ns
trCL, tfCL Maximum Clock Rise and Fall Time VDD = 5V No Limit ns
VDD = 10V No Limit ns
VDD = 15V No Limit ns
fCL Maximum Clock Frequency VDD = 5V 1.5 4 MHz
VDD = 10V 4 10 MHz
VDD = 15V 5 12 MHz
tPHL(R) Reset Propagation Delay VDD = 5V 200 450 ns
VDD = 10V 100 210 ns
VDD = 15V 80 170 ns
tWH(R) Minimum Reset Pulse Width VDD = 5V 200 450 ns
VDD = 10V 100 210 ns
VDD = 15V 80 170 ns
CIN Average Input Capacitance Any Input 5 7.5 pF
CPD Power Dissipation Capacitance 50 pF
Note 4: AC Parameters are guaranteed by DC correlated testing.

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CD4020BC • CD4040BC • CD4060BC
AC Electrical Characteristics (Note 5)
CD4060BC TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units

tPHL4, tPLH4 Propagation Delay Time to Q4 VDD = 5V 550 1300 ns

VDD = 10V 250 525 ns
VDD = 15V 200 400 ns
tPHL, tPLH Interstage Propagation Delay Time VDD = 5V 150 330 ns
from Qn to Qn+1 VDD = 10V 60 125 ns
VDD = 15V 45 90 ns
tTHL, tTLH Transition Time VDD = 5V 100 200 ns
VDD = 10V 50 100 ns
VDD = 15V 40 80 ns
tWL, tWH Minimum Clock Pulse Width VDD = 5V 170 500 ns
VDD = 10V 65 170 ns
VDD = 15V 50 125 ns
trCL, tfCL Maximum Clock Rise and Fall Time VDD = 5V No Limit ns
VDD = 10V No Limit ns
VDD = 15V No Limit ns
fCL Maximum Clock Frequency VDD = 5V 1 3 MHz
VDD = 10V 3 8 MHz
VDD = 15V 4 10 MHz
tPHL(R) Reset Propagation Delay VDD = 5V 200 450 ns
VDD = 10V 100 210 ns
VDD = 15V 80 170 ns
tWH(R) Minimum Reset Pulse Width VDD = 5V 200 450 ns
VDD = 10V 100 210 ns
VDD = 15V 80 170 ns
CIN Average Input Capacitance Any Input 5 7.5 pF
CPD Power Dissipation Capacitance 50 pF
Note 5: AC Parameters are guaranteed by DC correlated testing.

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 CD4020BC • CD4040BC • CD4060BC
Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D

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 Counters • 14-Stage Ripple Carry Binary Counters
CD4020BC • CD4040BC • CD4060BC 14-Stage Ripple Carry Binary Counters • 12-Stage Ripple Carry Binary

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
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instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.