CD4066BC Quad Bilateral Switch

November 1983
Revised August 2000

CD4066BC
Quad Bilateral Switch
General Description ■ High degree linearity 0.1% distortion (typ.)
High degree linearity @ fis = 1 kHz, Vis = 5Vp-p,
The CD4066BC is a quad bilateral switch intended for the
transmission or multiplexing of analog or digital signals. It is High degree linearity VDD−VSS = 10V, RL = 10 kΩ
pin-for-pin compatible with CD4016BC, but has a much ■ Extremely low “OFF” 0.1 nA (typ.)
lower “ON” resistance, and “ON” resistance is relatively
switch leakage: @ VDD−VSS = 10V, TA = 25°C
constant over the input-signal range.
■ Extremely high control input impedance 1012Ω(typ.)
Features ■ Low crosstalk −50 dB (typ.)
■ Wide supply voltage range 3V to 15V between switches @ fis = 0.9 MHz, RL = 1 kΩ
■ High noise immunity 0.45 VDD (typ.) ■ Frequency response, switch “ON” 40 MHz (typ.)
■ Wide range of digital and ±7.5 VPEAK
analog switching Applications
■ “ON” resistance for 15V operation 80Ω • Analog signal switching/multiplexing
■ Matched “ON” resistance ∆RON = 5Ω (typ.) • Signal gating
over 15V signal input • Squelch control

■ “ON” resistance flat over peak-to-peak signal range • Chopper

■ High “ON”/“OFF” 65 dB (typ.) • Modulator/Demodulator

output voltage ratio @ fis = 10 kHz, RL = 10 kΩ • Commutating switch

• Digital signal switching/multiplexing
• CMOS logic implementation
• Analog-to-digital/digital-to-analog conversion
• Digital control of frequency, impedance, phase, and
analog-signal-gain

Ordering Code:
Order Number Package Number Package Description
CD4066BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
CD4066BCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4066BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram Schematic Diagram

© 2000 Fairchild Semiconductor Corporation DS005665 www.fairchildsemi.com

CD4066BC
Absolute Maximum Ratings Recommended Operating
(Note 1) Conditions (Note 2)
(Note 2)
Supply Voltage (VDD) 3V to 15V
Supply Voltage (VDD) −0.5V to +18V Input Voltage (VIN) 0V to VDD
Input Voltage (VIN) −0.5V to VCC+0.5V Operating Temperature Range (TA) −40°C to +85°C
Storage Temperature Range (TS) −65°C to +150 °C
Power Dissipation (PD) Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
Dual-In-Line 700 mW that the devices should be operated at these limits. The tables of “Recom-
Small Outline 500 mW mended Operating Conditions” and “Electrical Characteristics” provide con-
ditions for actual device operation.
Lead Temperature (TL)
Note 2: VSS = 0V unless otherwise specified.
(Soldering, 10 seconds) 300°C

DC Electrical Characteristics (Note 2)

−40°C +25°C +85°C

Symbol Parameter Conditions Units
Min Max Min Typ Max Min Max
IDD Quiescent Device Current VDD = 5V 1.0 0.01 1.0 7.5 µA
VDD = 10V 2.0 0.01 2.0 15 µA
VDD = 15V 4.0 0.01 4.0 30 µA
SIGNAL INPUTS AND OUTPUTS
RON “ON” Resistance RL = 10 kΩ to (VDD − VSS/2)
VC = VDD, V SS to VDD
VDD = 5V 850 270 1050 1200 Ω
VDD = 10V 330 120 400 520 Ω
VDD = 15V 210 80 240 300 Ω
∆RON ∆“ON” Resistance Between RL = 10 kΩ to (VDD − VSS/2)
Any 2 of 4 Switches VCC = V DD, VIS = VSS to VDD
VDD = 10V 10 Ω
VDD = 15V 5 Ω
IIS Input or Output Leakage VC = 0 ±50 ±0.1 ±50 ±200 nA
Switch “OFF”
CONTROL INPUTS
VILC LOW Level Input VIS = V SS and VDD
Voltage VOS = V DD and VSS
IIS = ± 10µA
VDD = 5V 1.5 2.25 1.5 1.5 V
VDD = 10V 3.0 4.5 3.0 3.0 V
VDD = 15V 4.0 6.75 4.0 4.0 V
VIHC HIGH Level Input VDD = 5V 3.5 3.5 2.75 3.5 V
Voltage VDD = 10V (Note 7) 7.0 7.0 5.5 7.0 V
VDD = 15V 11.0 11.0 8.25 11.0 V
IIN Input Current VDD−VSS = 15V ± 0.3 ± 10−5 ± 0.3 ± 1.0 µA
VDD≥VIS≥V SS
VDD≥VC≥V SS

www.fairchildsemi.com 2
 CD4066BC
AC Electrical Characteristics (Note 3)
TA = 25°C, tr = tf = 20 ns and VSS = 0V unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
tPHL, tPLH Propagation Delay Time Signal VC = VDD, CL = 50 pF, (Figure 1)
Input to Signal Output RL = 200k
VDD = 5V 25 55 ns
VDD = 10V 15 35 ns
VDD = 15V 10 25 ns
tPZH, tPZL Propagation Delay Time RL = 1.0 kΩ, CL = 50 pF, (Figure 2, Figure 3)
Control Input to Signal VDD = 5V 125 ns
Output High Impedance to VDD = 10V 60 ns
Logical Level VDD = 15V 50 ns
tPHZ, tPLZ Propagation Delay Time RL = 1.0 kΩ, CL = 50 pF, (Figure 2, Figure 3)
Control Input to Signal VDD = 5V 125 ns
Output Logical Level to VDD = 10V 60 ns
High Impedance VDD = 15V 50 ns
Sine Wave Distortion VC = VDD = 5V, VSS = −5V 0.1 %
RL = 10 kΩ, VIS = 5Vp-p, f= 1 kHz, (Figure 4)
Frequency Response-Switch VC = VDD = 5V, VSS = −5V, 40 MHz
“ON” (Frequency at −3 dB) RL = 1 kΩ, VIS = 5Vp-p,
20 Log10 VOS/VOS (1 kHz)−dB,
(Figure 4)

Feedthrough — Switch “OFF” VDD = 5.0V, VCC = VSS = −5.0V, 1.25

(Frequency at −50 dB) RL = 1 kΩ, VIS = 5.0Vp-p, 20 Log10,
VOS/VIS = −50 dB, (Figure 4)
Crosstalk Between Any Two VDD = VC(A) = 5.0V; VSS = VC(B) = 5.0V, 0.9 MHz
Switches (Frequency at −50 dB) RL1 kΩ, VIS(A) = 5.0 Vp-p, 20 Log10,
VOS(B)/VIS(A) = −50 dB (Figure 5)
Crosstalk; Control Input to VDD = 10V, RL = 10 kΩ, RIN = 1.0 kΩ, 150 mVp-p
Signal Output VCC = 10V Square Wave, CL = 50 pF
(Figure 6)
Maximum Control Input RL = 1.0 kΩ, CL = 50 pF, (Figure 7)
VOS(f) = ½ VOS(1.0 kHz)
VDD = 5.0V 6.0 MHz
VDD = 10V 8.0 MHz
VDD = 15V 8.5 MHz
CIS Signal Input Capacitance 8.0 pF
COS Signal Output Capacitance VDD = 10V 8.0 pF
CIOS Feedthrough Capacitance VC = 0V 0.5 pF
CIN Control Input Capacitance 5.0 7.5 pF
Note 3: AC Parameters are guaranteed by DC correlated testing.
Note 4: These devices should not be connected to circuits with the power “ON”.
Note 5: In all cases, there is approximately 5 pF of probe and jig capacitance in the output; however, this capacitance is included in CL wherever it is
specified.
Note 6: VIS is the voltage at the in/out pin and VOS is the voltage at the out/in pin. VC is the voltage at the control input.
Note 7: Conditions for VIHC: a) VIS = VDD, IOS = standard B series IOH b) VIS = 0V, IOL = standard B series IOL.

3 www.fairchildsemi.com
CD4066BC
Typical Performance Characteristics

“ON” Resistance vs Signal “ON” Resistance as a Function

Voltage for TA = 25°C of Temperature for
VDD−VSS = 15V

“ON” Resistance as a Function “ON” Resistance as a Function

of Temperature for of Temperature for
VDD−VSS = 10V VDD−VSS = 5V

Special Considerations
In applications where separate power sources are used to avoid drawing VDD current when switch current flows into
drive VDD and the signal input, the VDD current capability terminals 1, 4, 8 or 11, the voltage drop across the bidirec-
should exceed VDD/RL (RL = effective external load of the 4 tional switch must not exceed 0.6V at TA ≤ 25°C, or 0.4V at
CD4066BC bilateral switches). This provision avoids any TA > 25°C (calculated from RON values shown).
permanent current flow or clamp action of the VDD supply No VDD current will flow through RL if the switch current
when power is applied or removed from CD4066BC. flows into terminals 2, 3, 9 or 10.
In certain applications, the external load-resistor current
may include both VDD and signal-line components. To

www.fairchildsemi.com 4
 CD4066BC
AC Test Circuits and Switching Time Waveforms

FIGURE 1. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output

FIGURE 2. tPZH, tPHZ Propagation Delay Time Control to Signal Output

FIGURE 3. tPZL, tPLZ Propagation Delay Time Control to Signal Output

VC = VDD for distortion and frequency response tests

VC = VSS for feedthrough test

FIGURE 4. Sine Wave Distortion, Frequency Response and Feedthrough

5 www.fairchildsemi.com
CD4066BC
AC Test Circuits and Switching Time Waveforms (Continued)

FIGURE 5. Crosstalk Between Any Two Switches

FIGURE 6. Crosstalk: Control Input to Signal Output

FIGURE 7. Maximum Control Input Frequency

www.fairchildsemi.com 6
 CD4066BC
Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A

7 www.fairchildsemi.com
CD4066BC
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D

www.fairchildsemi.com 8
 CD4066BC Quad Bilateral Switch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
to perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.

9 www.fairchildsemi.com