INSTALLATION * OPERATION » MAINTENANCE INSTRUCTIONS TYPE SDF-1 SOLID STATE UNDERFREQUENCY RELAY FOR CLASS 1E APPLICATIONS Westinghouse ILL. 41-504.11A, CAUTION It is recommended that the user of this equip- © ment become acquainted with the information in this instruction leaflet before energizing the equipment. Failure to observe this precaution may result in damage to the equipment. Printed circuit modules should not be removed or inserted while the relay is energized unless speci- fic instructions elsewhere in this instruction leaf- let state that such action is permissible. Failure to observe this precaution can result in an unde- sired tripping output, and cause component damage. APPLICATION The SDF-1 Relay (Figures 1 and 2) is a solid state, single-frequency setting, high-accuracy under-frequency relay for use in automatic load- saving schemes. (See setting section page 5 for further application data.) “Class 1E” is the safety classification of the electric equipment and systems in nuclear power generating stations that are essential to emergency shutdown of the reactor, containment isolation, cooling of the reactor, and heat removal from the containment and reactor, or otherwise are essen- tial in preventing significant release of radioactive material to the environment. These relays have been specially designed and tested to establish their suitability for Class 1E applications. Materials have been selected and tested to insure that the relays will perform their intended function for their design life when operated in a normal environment as defined by ANSI standard C37.90-1978, when exposed to radiation levels up to 10* rads, and when sub- jected to seismic events producing a Shock Re- sponse Spectrum within the limits of the relay rating. CONSTRUCTION & OPERATION The type SDF-1 Underfrequency Relay is composed of (1) an isolation transformer, (2) a zero crossing voltage detector, and synchronizer printed circuit module, (3) a main clock and four binary counter printed circuit module, (4) a twelve bit binary counter printed circuit module, (5) a trip control circuit and delay timer printed circuit module, (6) a power supply printed cir cuit module, (7) a front panel mounted digital underfrequency trip-point setting assembly, (8) an indicating contactor switch unit (ICS), and (9) an input/output trip relay module. All components are identified on the internal schematic in Figure 3 ISOLATING TRANSFORMER The isolation transformer is a 1:1 transformer which provides de isolation ZERO CROSSING, VOLTAGE DETECTOR, AND SYNCHRONIZER PRINTED CIRCUIT MODULE The zero crossing, voltage detector, and syn- chronizer printed circuit module contains a two- All possible contingencies which may arise during installation, operation, or maintenance, and all details and variations of this equipment do not purport to be covered by these instructions, If further information is desired by purchaser regarding his particular installation, operation or maintenance of his equipment, the local Westinghouse Electric Corporation representative should be contacted. SUPERSEDES ILL. 41-504.11 DATED SEPTEMBER 1980 @DENOTES CHANGE SINCE PREVIOUS ISSUE EFFECTIVE DECEMBER 1984cell symmetrical low pass filter to provide tran- sient and high frequency noise suppression, a zero crossing detector that generates a low voltage square wave signal having the same frequency as the fundamental of the input signal, and a syn- chronizer for the synchronization of the output signals from the zero-crossing detector with the main clock signals. Also contained on this module are the two power supply voltage detectors to pre- vent spurious tripping at the time of power turn- on, and an undervoltage detector which provides an inhibiting signal to avoid incorrect operation of the relay if the input line voltage drops below © the minimum prescribed value (25 to 45 volts). Refer to Figure 5 for component location and board layout. MAIN CLOCK AND FOUR BIT BINARY COUNTER PRINTED CIRCUIT MODULE The main clock and four bit binary counter printed circuit module contains the main clock and the first four bits of the binary counter. The main clock, consisting of a crystal controlled oscillator to provide the reference frequency and a driving state, supplies clock pulses to the main counter and to the synchronizer, The first four bits of the 16-bit binary counter are also contained on this module. Refer to Figure 6 for component location and board layout. TWELVE BUT BINARY COUNTER PRINTED CIRCUIT MODULE The twelve bit binary counter printed circuit ‘module contains the last 12 bits of the 16 bit binary counter and the timing control circuit, The timing control circuit accomplishes the generation of the proper signals required by the trip control circuit to perform the specified trip enabling or inhibiting sequences as well as generation of the reset signal for the binary counter. Refer to Figure 7 for com- ponent location and board layout. TRIP CONTROL CIRCUIT AND DELAY TIMER PRINTED CIRCUIT MODULE The trip control circuit and delay timer printed circuit module contains the coincidence output cir- cuit, a trip control, a trip timer, and a trip output circuit. The coincidence output circuit generates a signal that is stored by the trip control circuit when the period set on the underfrequency trippoint set- ting is exceeded. The trip control circuit stores the information whether or not a trip condition oc- curred during the actual cycle and before the reset signal initiates the next period timing. This circuit also steps up on one of the required counting se- quences of three consecutive trip cycles for trip- ping or two consecutive no-trip cycles required for reset. The trip timer starts after the first trip cycle is recognized. Before three consecutive trip cycles have occurred it is reset by the first no-trip cycle; after three consecutive trip cycles have occurred it is reset only if two consecutive no-trip cycles oc- cur. The timer energizes the trip output circuit after the delay time is expired. The delay time, after the first trip cycle is recognized, can be set from 1 to 99 cycles (60 Hz base) with the front panel decade switches; the prescribed range however goes from a minimum of 2 cycles, since three consecutive trip cycles are required by the trip control circuit for a trip condition, to a max- imum of 99 cycles. The trip output circuit provides the required signal characteristics in order to drive the trip relay. The trip output circuit is set in the trip condition by the completion of the trip delay time and is reset by either a low voltage inhibit signal or the trip control circuitry. Refer to Figure 8 for component location and board layout. POWER SUPPLY PRINTED CIRCUIT MODULE The power supply printed circuit module con- tains a dual voltage regulated switching power supply with an 18 volt de output for most relay functions and a 5 volt de output for the integrated circuit functions. The main supply is of the switching regulator design giving high efficiency @and relative insensitivity to input voltage. Refer to Figure 9 for component location and board layout. DIGITAL UNDERFREQUENCY TRIP-POINT SETTING ASSEMBLY The digital underfrequency trip-point setting assembly is where the frequency trip-point is set as maximum allowed period. The setting corresponds to the binary coded number of main clock pulses that can be counted during the maximum periodLL, 41804,114 duration, If the actual period exceeds the set value, the coincidence generates a signal to the trip con- trol circuit. The two trip delay timer decade setting switches are located on the underfrequency trip- point setting assembly and can be set in any com- bination yielding from 2 to 99 cycles of time delay (60 Hz base). INPUT/OUTPUT TRIP RELAY MODULE The operation of the trip relay is controlled by the trip output circuit on the trip control circuit and delay timer printed circuit module. The trip relay, when energized, allows the indicating con- tractor switch unit to operate. A capacitive pro- tection scheme is used to make the SDF-I less susceptible to transients and noise. Indicating Contactor Switch Unit (ICS) The indicating contactor switch is a small de operated clapper type device. A magnetic ar- mature, to which leaf-spring mounted contacts are attached, is attracted to the magnetic core upon energization of the switch. When the switch closes, the moving contacts bridge two stationary con- tacts, completing the trip circuit, Also during this operation two fingers on the armature deflect a spring located on the front of the switch which allows the operation indicator target to drop. The target is reset from the outside of the case by a push rod located at the bottom of the cover. UNDERFREQUENCY TEST MODULE 1489C14G01 (Optional) The underfrequency test module consists of a printed circuit module with an 11 bit binary keyboard mounted on the front module panel. The complete circuit diagram is shown in Figure 11. To obtain a desired test frequency, the corresponding binary code (Table I) is set on the keyboard, Diodes D1 through D11 operate as a coincidence detector for the main counter bits connected to the closed switches on the test module. Refer to Figure 12 for component location and board layout. THEORY OF OPERATION Operation of the SDF-1 underfrequency relay will be described with the aid of Figure 3 internal schematic drawing 1725F14, and Figure 4 external schematic and logic diagram drawing 719B252. The SDF-I underfrequency relay utilizes the period of the alternating waveform being monitored for underfrequency measurement. The input signal is isolated, filtered to remove tran- sients and high frequency noise, checked for under- voltage, and fed into the zero-crossing detector, where positive-going zero-crossing signals are generated to define the period of the waveform. The positive-going zero-crossing signals are brought into synchronization with the main clock signal of 1.966080 megahertz and are used to reset the binary counter at each synchronized positive- going zero-crossing. The main clock increments the binary counter ata 1.966080 megahertz rate so that bit [15] of the counter changes to a logic “1” signal in 16.6667 milliseconds, the period of a 60 hertz waveform. The underfrequency trip point setting corresponds to the binary coded number of main clock pulses that can be counted after bit 15] goes to “1”, or period in excess of the 16.6667 millisecond (60 hertz period). The binary settings for frequencies from 60.00 to 54,00 Hz in .0S Hz steps are given in Table 1 If the actual period exceeds this set value (underfrequency condition), the coincidence circuit ‘generates a signal to the trip control circuity where it is stored. The trip control circuit stores the infor- mation whether or not a trip condition occurred during the actual cycle and before the reset signal which initiates the next period timing. The trip timer starts after the first trip cycle is recognized. Before the required counting sequence of three consecutive trip cycles for a trip condition is com- pleted, the trip control circuit can be reset by the first no-trip cycle; after three consecutive trip cycles have occurred it is reset only if two con- secutive non-trip cycles occur. The timer energizesLL. 41.504,114 the trip output circuitry to energize the trip relay after the delay time set is expired. The delay time can be set from the minimum 2 cycles to 99 cycles (60 Hz base). The trip output circuit to the trip relay is reset by either a low voltage inhibit signal or the trip control circuitry. A more detailed look at the underfrequency measurement circuitry of the SDF-I relay is as follows (refer to Figures 1 and 3): The period of the alternating waveform is measured by circuitry on the zero crossing, volt- age detectors, and synchronizer printed circuit module. The voltage being monitored is supplied through 1:1 isolation transformer to the low pass filter which removes transient and high frequency noise from the ac signal. It is then clipped by diodes DS and D6 to limit the differential range to a nominal + .7 volts being fed into the input stage of the zero-crossing detector. Positive going zero-crossings are detected by differential amplifier Q4D, Q4E, and Q4F and transistors Q6 and Q7. When the input signal on the base of Q4E is more positive than the base Q4D, corresponding to Q4E on and Q4D, Q6, and Q7 off, the voltage at pin 10 of NAND gate B is high resulting in a “0” output on pin 8 of gate B, which is the syn- chronizer. When the input signal on the base of Q4D is more positive than the base of Q4E, cor- responding to Q4E off and Q4D, Q6 and Q7 on, the voltage at pin 10 of NAND gate B is low resulting in a “1” output on pin 8 of gate B for the zero-crossing input into the synchronizer. The zero-crossing of the voltage waveform being monitored are thus converted into either a “0” or a “1” zero-crossing “D” signal which is fed into the synchronizer for synchronization with the signals from the main clock. The positive-going zero crossings are then used to propagate the reset pulse (RES) from the timing control circuit located on the twelve bit binary counter printed circuit module to reset the 16 bits of the binary counter to zero at the end of each period. The clock signal to the binary counter is provided on the main clock and 4 bit binary crystal CL-1 in the circuitry associated with field- effect transistor Q8 to produce a 1.966080 megahertz clock signal, CPO. The 16 bit binary counter is located on the main clock and four bit binary counter printed cir- cuit module (bits 0}, [1], (2). and (3),) and the twelve bit binary counter printed circuit module (bits [4] through [15]). With a 1.966080 MHz clock frequency (CPO), bit [15] changes status every 16,6667 milliseconds. Since all the bits of the counter are reset to Zero at the beginning of each period [15] goes to “1” only if the actual period is longer than the 60 Hz. period. For frequencies ranging from 60 to $4 Hz the actual period ranges from 16,6667 to 18.5185 milliseconds. When [15] goes to “1” all bits from [0] to [14] go to ZERO During the 1.8518 ms corresponding to the difference between 54 and 60 Hz periods there are 1821 CPI clock pulses. (Bit [0] is used as a scaling stage to obtain a CP! output at half the frequency of CPO). With the condition [15] = ONE, only the first 11 bits must be then decoded to detect if the input frequency falls below a present value from 60.00 Hz to $4.00 Hz set on the digital under- frequency trip-point setting assembly per Table | This is accomplished by the coincidence circuit generating a signal to the trip control circuitry where it is stored and utilized in a manner previously described. CHARACTERISTICS FREQUENCY RANGE (HZ) The SDF-I relay can be set at values from 54,00 to 60.00 Hz in increments of 0.05 Hz, with an accuracy of +0.007 Hz from the set point. The repeatability is thus +0.007 Hz. (See Table 1) Increments of less than 0.05 Hz can be ob- tained if needed for unusual applications. DC CONTROL VOLTAGE The SDF-1 relay is designed to operate on counter printed circuit module by a stable crystal @either 48 or 125 volts de by selecting jumper oscillator which uses the parallel resonance of the combination on de power supply.LL, 41.504.114 ENERGY REQUIREMENTS AC Burden 7.3 Volt-Amperes at 120VAC 60 Hz. DC Burden 14 Watts at 48 VDC Control Voltage 16 Watts at 125VDC Control Voltage TIME DELAY RANGE 2 to 99 cycles in I-cycle setting increments with a tolerance of better than +5%. The total minimum operating time of the relay is 4 cycles 3 cycles of underfrequency detection and 1 cycle operating time for the trip relay. The timer will start after the first detected underfrequency cycle and, if set for 2 cycles of delay, will time out at the same time that tripping is enabled by the trip contro! logic. OPERATING TIME The operating time for the SDF-1 relay, taken from the first positive-going zero crossing of the ac potential wave after the underfrequency set-point is crossed, is equal to the time delay set on the front panel decade switches plus 2 cycles. This is because one cycle is used by the period-checking circuitry to determine that an underfrequency con- dition exists before the timer can be started; also, the tripping relay requires one cycle to pick up after the time delay expires. Trip control logic will not allow tripping to take place until at least 3 un- derfrequency cycles have been detected, regardless of a lower time delay setting; the minimum total operating time is thus 4 cycles if trip relay pickup time is included Examples of SDF-1 timing are illustrated in the figures, Refer to figure 14, Note that the relay senses frequency by measuring the time between positive going zero crossings. If the frequency is initially above the trip setting and then declines fairly linearly, as will occur in service, the relay will measure the average frequency over each cycle, Thus, it will detect the underfrequency condition during a given cycle only if the trip setting is crossed before that cycle is half- completed, Otherwise, detection will occur during the following cycle. The resultant timing variation is less than +'% cycle. In the example of figure 14, the relay has a delay setting of 6 cycles on the front panel decade switches. The total time from underfrequency set-point crossing to trip contact closure will be between 7.5 and 8.5 cycles, de- pending on the position of the ac wave when the frequency setting is crossed. Now refer to figure 15. Suppose that ac is suddenly applied at a frequency below the trip set- ting, as might occur during bench testing of the relay, or possibly in the midst of a frequency dis- turbance. In this case there will be a delay of up to, but less than, one cycle before the SDF-1 starts to measure the underfrequency condition. This variable time is in addition to the trip delay setting plus 2 cycles, In the example, the time from energization to contact closure will be between 8 and 9 cycles. TRIP CIRCUIT The main contacts will close 30 amperes at 250 volts de and the seal-in contacts of the indicating contactor switch will safely carry this current long enough to trip a circuit breaker. Seismic ICS units are available in 0.2, 1.0, and 2.0 ampere (fixed rating) sizes. TEMPERATURE RANGE The SDF-1 is designed to operate over a temperature range from —30°C to + 70°C. SETTINGS UNDERFREQUENCY TRIP POINT The SDF-1 relay is set for underfrequency trip by the tap screws in the underfrequency trip point setting assembly on the front panel of the relay. The binary settings for frequencies from 60.00 to 54,00 Hz in 0.05 Hz steps are given in Table I ‘When the tap screw is in the “1” upper position it contributes to the frequency setting as in the following weighting table. TABLE! Undertrequency Set Point Position Weights Binary Code Position |A|B]C|D}E|F/G]| H] J [K | L Weight ("1 Position) 16|32| 64] 128]256|512)0241b, 41-504,114 When the tap screw is in the “0” lower position it contributes 0 to the weight. The tap screws must, be firmly tightened by hand in either of the two positions. Note: a screwdriver may be used to tighten the tap screws but caution should be ex- ercised not to exert too much pressure on the screws. An illustrative example is the assumption that a tripping point of 59.50 Hz is desired. The tap screws should be fastened in the following com- bination according to Table I. alB[c[p] Ef Fic fH] s]KiL x x x ox, [x Xx [x PIERS Settings in increments as fine as the accuracy of the relay are possible, if needed for an un- usual application. A request for the binary setting for a frequency not listed in Table I (but between 54,0 and 60.0 Hz) can be made through the nearest Westinghouse sales office. Selecting 2 Frequency Setting For load-shedding, the frequency is normally set as high as possible without approaching the region of normal system frequency swings (usually set 59.5 Hz or below). High settings, combined with short time delay, will provide greatest protec- tion from severe system overload (see “Selecting a Time Delay” in the following section). A number of relays may be set in successively lower steps for more selective load-saving Trip Time Delay Setting The trip time relay is set in I-cycle increments with the decade switches on the front panel from the minimum of 2 cycles to 99 cycles (60 Hz base). The delay settings of the two controls are additive. A delay of less than 2 cycles is not possible because of trip control logic (as explained in “Theory of Operation”); setting below 2 cycles will be of no benefit. The timer will start after the first under- frequency cycle is recognized; the combined presence of outputs from the timer and from the trip control logic (indicating 3 consecutive under- frequency cycles) will enable tripping. The closing of the trip relay contact will require one additional cycle after the time delay has elapsed. Note that the cycle calibrations assume a 60 Hz reference (i.e., one cycle equals 16.67 ms). The time delay is an analog function, unrelated to the ac input cycles, Selecting a Time Delay When a system overload occurs, underfrequen- cy relays must disconnect load to arrest frequency decline, The output of generating plants may be impared below 57-57.5 Hz, so shedding must be completed before this level is reached. Shortest possible time delay is usually advantangeous. Note that, due to the frequency-checking technique of the SDF-1 relay, no intentional time delay is re- quired to avoid misoperation for transients of short duration (such as phase-single shifts due to fault inception or clearing). However, time delay may be used to prevent response to misleading in- puts (such as line excitation by a slowing motor load); or, in some schemes, to coordinate a number of relays set to the same frequency. Fig. 13 shows the effect of time delay on the ac- tual frequency at which tripping takes place under declining frequency conditions. The curves show how the frequency continues to drop in the time in- terval required for the relay to operate after its frequency set-point is crossed. For example, suppose that for a system of iner- tia constant H = 2, it is required that the frequen- cy not dip below 57.5 Hz for any overload up to 46%. Assume the relay is set to trip at 59.20 Hz. The scale at the bottom of figure 13 indicates that a 46% overload will cause a 6 Hz/sec rate of decline, According to Figure 13, the SDF-1 relay with 15 cycles of delay setting will close its trip contact when the frequency has dropped 1.7 Hz below the set point, or $7.5 Hz, for this overload condition. Thus, 15 cycles is the maximum accep- table time delay setting to obtain the desired protection. Now suppose the relay trips a S-cycle breaker. Since load must actually be disconnected to arrest frequency decline, the breaker operating time has the same effect as additional time delay settingLL, 41-504,114 Because 15 cycles is the longest tolerable delay, the relay should not have more than 10 cycles of delay setting The curves in Figure 13 have been plotted to in- The following procedure can be used for this purpose. NOTE clude the effect of the delay setting, as labeled on © The relay is wired for 125 Vac, when it is shipped each curve, along with two additional cycles for in- itial underfrequency detection and telephone relay operation. Thus, the curve corresponding to 2 cycles of delay setting is plotted for 4 cycles total SDF-I operating time, etc. Use the curve whose label corresponds to the actual setting of the decade switches. INSTALLATION The relays should be mounted on switchboard panels or their equivalent in a location free from dirt, moisture, excessive vibration and heat Mount the relay vertically by means of the moun- ting stud for the type FT projection case or by means of the four mounting holes on the flange for the semi-flush type FT case. Either the stud or the mounting screws may be utilized for grounding the relay. The electrical connections may be made directly to the terminals by means of screws for steel panel mounting or to the terminal stud fur- nished with the relay for thick panel mounting. The terminal stud may be easily removed or in- serted by locking two nuts on the stud and then turning the proper nut with a wrench. See Fig. 16 for Outline and Drilling plan. For detailed information on the FT case, refer to LL. 41-076, ADJUSTMENTS & MAINTENANCE The proper adjustments to insure correct operation of this relay have been made at the fac- tory, Upon receipt of the relay no customer ad- justments, other then those covered under “SETTINGS” should be required. ACCEPTANCE CHECK It is recommended that an acceptance check be applied to the SDF-I relay to verify that the cir- cuits are functioning properly. from the factory. For 48 Vac application, change the jumper positions shown on the internal schematic drawing, 1, Settings Check front panel settings; they should be as follows: a, Underfrequeney trip point desired set on the underfrequency trip point setting assembly as per Table I. b. Trip time delay set for the desired cycles delay on the trip time delay decade setting knobs. 2. Indicating Contactor Switch Close the trip relay contacts and pass sufficient de current through the trip circuit (Relay ter- minals 1 and 10) to close the contacts of the ICS. This value of current should not be greater than the particular ICS value being used. The indicator target should drop freely. 3. Underfrequency Trip Point Setting Connect SDF-I Relay per test diagram Figure 10. Using a variable frequency source apply 120 volts at set tripping frequency. Relay should trip within + .007 Hz of set trip frequency in the time set on the digital trip time setting plus 16 milliseconds operating time of the trip relay Raise frequency of source above the trip point setting (.007 Hz. or higher) and the trip relay should drop out after approximately two cycles delay, 4, Undervoltage Detector Lower frequency of source so relay once again trips; lower voltage of source below 25 volts, and the trip relay should drop out.LLL. 41-504,114 5. Test Module 1469C14G01 (Optional) Test module 1469C14G01 may be utilized to test the underfrequency trip setting of the SDF- I relay. Disconnect AC to relay terminals 8 and 9 when using this test module, When inserted into its relay connector and test points TS and T9 on module 1469C14GO1 are connected together, underfrequency trip point settings may be checked by switching the same binary number on the test module that is set on the un- derfrequency trip point setting assembly to trip the relay. Likewise, dropping the test module setting down by a weight of one or greater (see Table II), corresponding to a higher frequency, will allow the relay to reset ROUTINE MAINTENANCE All relays should be checked at least once every year or at such other intervals as may be dictated by experience to be suitable to the particular application, CALIBRATION Use the following procedures for calibrating the relay if the relay has been taken apart for repairs or the adjustments have been disturbed. This procedure should not be used unless it is ap- parent that the relay is not in proper working order. (See “Acceptance Check”) INDICATING CONTACTOR SWITCH (ICS) Close the trip relay contacts and pass sufficient de current through the trip circuit (Relay terminals 1 and 10) to close the contacts of the ICS. This value of current should not be greater than the par- ticular ICS value being used. The indicator target should drop freely. The contact gap should be approximately 047°” between the bridging moving contact and the adjustable stationary contact. The bridging, mov- ing contact should touch both stationary contact simultaneously. DC REGULATED SUPPLIES The 5 Ve supply is adjustable and can be ad- justed by potentiometer Pl on power supply module 1600C9SG01. The 18 Vde supply is referenced to the 5 volt supply and needs no adjustment, Both de supplies should be main- tained within £5% for the de power supply be- tween 90 V and 140 V or 42 V and 56 V for the supply voltage of 125 Vde or 48 Vde respectively. MAIN CLOCK ADJUSTMENT Inductor L-1 should be adjusted to obtain the correct clock signal CPO at TP2 on module 1469C15GOI. The correct signal is 1.966080 MHz. with a tolerance range of 1.965980 MHz. to 1.966180 MHz. UNDERFREQUENCY TRIP TEST Connect the SDF-1 Relay per test diagram Figure 10. Using a variable frequency source apply 120 volts at set tripping frequency. Relay should trip within +0.007 Hz. of set trip frequency in the time set on the trip time delay setting plus 16 milliseconds operating time of the trip relay. Raise frequency of source 0,007 Hz or higher above the trip point setting and the trip relay should drop out after approximately two cycles delay. TRIP CONTROL CIRCUIT AND DELAY TIMER ADJUSTMENT Potentiometer R46 on module 1469C17G01 must be adjusted to bring the 99 cycle delay setting to 99 cycles (60 Hz base), ie., 1.650 seconds. Remember that the total operating time is equal to the delay setting plus 2 additional cycles. Thus, at 99 cycles delay setting the potentiometer R46 should be set so that the total operating time is 101 cycles or 1.683 seconds. The delay timer should be tested at each position on the selector switch. (Note: Delay settings for 1 to 2 cycles will give the minimum delay of 2 cycles and can only be check- ed at a higher setting: ie. 1 cycle has to be checked at 11 cycles delay setting, or 21, 31, etc.). TEST MODULE 1469C14G01 (Optional) Test module 1469C14GOI may be utilized to test the underfrequency trip setting of the SDF-1 relay. Disconnect AC to relay terminals 8 and 9 when using this test module, When inserted into its relay connector and test points T8 and T9 on u uLL, 41.504,114 module 1469C16G01 are connected together, un- derfrequency trip point settings (Table I) may be checked by switching the same binary number on the test module that is set on the underfrequency trip point setting assembly to trip the relay. Likewise, dropping the test module setting down by a weight of one or greater (see Table II), cor- responding to a higher frequency, will allow the relay to reset. RENEWAL PARTS Repair work can be done most satisfactorily at the factory. However, interchangeable parts can be furnished to the customers who are equipped for doing repair work, When ordering parts, always give the complete nameplate data.hee ee _c_ TABLE | UNDERFREQUENCY UNDERFREQUENCY ago. | reno TRIP POWT SETTING waa | reco TRIP POINT SETTING alele [ole [Flelm[s [xe ajele Plelrle[m]s[e[e 0.00 | 16.6867 |o Jo {oJo|o[o|o|o[o]ofo | sa.s0 | 17.0980 Jo}o]1 JoJo |i Jo] 1) 1 Jo] 0 59.95 16.6806 | 0 |1 ifa o}o| oo} olo jo} 58.45 | 17.1086 }o}1}0 jo }1 |i jo} 1) 1/0) 0 so.90 | s5.0s |1|1|0]2|1/ 0] 0/ofolo|o ] ss.s0 | sz.zzss ]1) 0/0 Jo[o /o|z]s)1]0]o 59.85 | 16.7084 | 1/0) 0 tjojrto ele oO | 58.35 17.1380 | 1 oie 1 o fo 1/1} 1/0/0 39.80 | 16.7224 {1/1} 1/0 /1/1/0/o|o/o Jo | 58.30 | 17.1527 Joj1)1 fi |i jofajajajoyo so.10 | soso |o|1|o|o|1)0/ 1/0/0)0/0] se20 | rr.rear |x]aloli {1 ja|s|a]s]o]o 9.63 | 17.7615 | fo |o] 6] 1) 1]0] 0/0 Jo 58.15 | 17.1969 [1/0 0 Jojo jojojrfo 59.60 | 16.7765 Jo 1|1{1|ol 1) 1/0/o/o/o| sszo | sz.2117 Jolofo|1/1 Jojo oloj1| 0 59.50 | 16,8067 |o [1/0] 1/0/0jo 1/0/00 | 58.00 | iv.aaia Jrjo]1Jof1)zjolojolr]o 59.45 | 16.8209 |o/o/0[1/1/0Jo 1/ojo{o} 57.95 | 17.2563 |o/0|1|0]0 ]o}1 ilo | soso | teaas0 |1/0/1]0/0/1/0/1) ojo|0 | sz90] sana }o]1/olo]1 0/1 Jo) 0/10 | soos | seeisz |1|1lofo|1/1]o, 1/0folo] 5785 | 17.2801 ]1)0/0/0/0|1|1/0) 0) 1] 0 | soso | 1eseae [1/0 0)0/0/0/1/ 1) 0/0/0| 57.80 | 17.3010 ofo| uirfololilo | 59.25 | se.sr76 || of oli} 1jo}olo | sr7s | sz.sie0 | 0) 1 ritfolej1}o | 59.20 | 16.8919 rfol1l1|1joj1| 1} ofojo 57.70 | 17.3310} 1)0]1/1/0]0/0; 1) 0/1] 0 | 50.15 | 16.9062 | 1 ale ae 1} i}ofolo| 97.65 | 17.3461 | jo | ° 59.10 | 16.9: ol1{ofai1} a) a) aolo jo} 57.60 | 173611 | i | 0 50.05 | 16.9848 |0}0}0| 1/0/00 /0/ 1/0 /0] 57.55 | 17.3762 | i o sooo | iss4s2 {0/1 |1/0|1)o/0/ofs Joo] szs0] 17.2013 | | c 0.95 | 16.9515 ]0/0/1/0)0/1,0 0/1/00 | sta | 1z406s | 0 38.90 | 16.979 Jo) 1/0 0/1 1/00 1 o]o} S740) rn4216 0 seas | sos [0] 0[o| 0/0/01) 0/1) 0/0] 57.95] 17.4200 0 58.75 | 17.0213 | 1) 0] 1] 1)1) 0) 1/0 1Jo|o] 57.25 | 17.4672 0 58.70 }alols}of a} afo)x[o]o| sz20| 124525 ‘ 56.65] 17.0503 | 1) 0/0]1 1/1) 1/0] 1ofo} sz.15 | inso7e 0 50.60 | 1.0618 | 1)1/1Jofo/olo}1/1}ofo] 57.10] 17.5131 o} rzor4 [of 1/1 Jo} rio ei tfolo| 57.05 | 17.5285 j of L J} 10LL. 41-504.114 TABLE | (Cont.) UNDERFREQUENCY UNDERFREQUENCY rrea. | Perion TRIP POINT SETTING rrea. | PERIOD TRIP POINT SETTING oz) | cs) czy | (as) ; alele|ojelr lela [s «le alelelolelrle]afs [ke s1.00 | 11539 {0 2 {1 [1J1/o|1|o]1]1/o0] 55.50 | 18.0180 fo|o]o jo} 1}1 Jo] 0/1 Jo} 1 36.05 | 17.5503 {1/0/12 [1/0 fa /1Jo|1|1 fof 55.45 | 18.0343 ofo}ojo}1}ofs}o}s 56.90 | 7.5747 {1 folafajafi |r foals fo} $54 | 18.0505 Pd idl baal Nall | 55. | sss | 175e01 Jo jot 1fofo/o |i /1/1 Jo 59.35 | 18.0668 jojololajajolx|ola | 5 | 56.0 | 17.6056 }1J1/0]1J1j0/0 1 |1|1 Jo} 55-30 | 18.0832 eal yen der “ i | 6 56.75 | 17.6211 ofr ofrfolrjojilijijo nT ee hea faa hea hand il a «70 | 17.6367 ofr ofujur 0 js fala fo} 2° ss.1iso [1 ]ofo fof fo fol sls jolt | 55.15 24 fi 1 36.65 | 17.6523 }1 0 0}1)0 0/1 /1] 1] 1/0 18.1324 [1/0/00 fo /1 jo} aia jolt 55.10 | 18.488 |1Jolo|o|1]1]o| |i fo}x 36.60 | 17.6678 ]0/0 0/1/1/0!1 1 /1/1 Jo ia | 55.05 | 18.1653 |1]o|o|o]olo]1|1|1 fot 17.6835 |o/o/0/1/oja jaja) iiafo 55.00 | is.tate |i folojo]1foji} ra fofa wear fa la)afoliirii)}r jaja lo yet i 1° 54.95 | ae.tges Jolrfolofo ja fal ala fofa 56.45 | 17.7148 |0|1/1/0|0/0/0]0]o/0/1 | | \ 54.90 | 1.2149 Jofalololifa]aja|a fofa s6.40 | 17.7305 |o|1/1/0|1/0/0/o]o}o/1 | | ' 54.35 | 18.2315 Jo]1/0}o/0 /o/ojolo |1|1 56.35 | 17.7462} 1]0)1/0]/0/1j0|0Jo/0/1 | | . i s4.a0 | 18.2182 1/1 /0 }o}1/0ofolo |r| 1 ] 36.30 | 17.7620} 1/0 1]0|1/1/0|0/ 0/0) 1 | | i 54.75 | 18.2618 [11/0 }0/0 |1]o]ofo fiji 5 irq} oo 1|o/o/ol1/0/ 0/0) 1 | | 54.70 | 18.285 [11 jo /0/1/1]o]ofo fi |i 17.1936 |o}0/ 1] 0/1/ 0/1) 0) 0/0) 1 | | | st.e5 | 16.2080 ]o|os }o/0 [0] 1) ojo |1 | 56.15 | 17. 1} 1/0] 0/0) 1/1 {0} o/o/ 2 [eee eaeec | i s4.60 | 18,2150 folo|1/o/1/0]1]ojo |r| 1 5 Maze 1/0 | 1 | cect) eae Opt ry typo} 0) a sess | assais J2]o la foo |r ]afolofa}y | 56.05 | 17.812 | 1] 1/0} 0)0)0/ 0/11 0/0) 4) os cy | se aga6 lato ls (ola li i} op |]. | f seoe | rare oft ofa) o)0) 2/072] tf suas | anase fo js fo/a}o op |s [3 33.95] 17.g7a1| 0} 1/0) 0f0/ 1/0] 2] 0/0) HF 5449 | ag sg04 falas fof alo F 5 1! ssao] reer} o/ 10/0) 1110/1) 0/0) 4) s5.o5 | aesoee fa}i|1 {ool sss | rzans1| 1) 0 0] 0/0] 0) 1] 1] 0/0) 1) sso | reaise Jolo fos |1{1 fo! 55.80 | 17.9211 | 1) 0) 0) 0] 1) 0) 1 | 34.25 | 18.4332 Jo )o)elofo/s/afo : 88.15 | 17,9372 HIGIOIG gic ays) cioe sa.z0 | 18.4502 |1fofo jr {1jola}alo fs |i | | 85.70] av.esa0] 1) 0} of 0) 1) 1) 1) 1/0) 0 4) sais | te.sor2 fo]ajo ji jot ufafo fafa | 35.65] 17,9695] 1) 0/ 0 ofo/ 0/0! of 1/0) 1) 54.10 | se.aas3 fafo fa fala fay afo fafa | 55.60{ 17.9856] 1] 0| 0| of 1| 0] of o| 1] 0) af 54.05 | as.sora folo|1 j1}olofojo|: |r |a \ | | | 55.55| 18.0018] 0| o| “ae 1] of of 1] 0] a} 54.00 | 18.5185 Jofo]x J1 ja jo lolol: |r fa | | | | i w - "LL. 41.504.110, © ELECTRICAL PARTS LIST WESTINGHOUSE CIRCUIT SYMBOL, DESCRIPTION STYLE NUMBER RESISTORS RI 68 KOhm 5% 1/2W 184A763H71 R2 4.3 KOhm 5% 1/2W 184A763H42 R3, Ra, R7, R30, R32, RA] 3 KOhm 5% 1/2W 1844763138 Rs S.A KOhm 5% 1/2W 184A763H44 R6, R33, 18 KOhm 5% 1/2W 1844763133, RB 33. KOhm 5% 1/2W 1844763139 RO 357K Ohm 1% 1/2W 862A376H54 RIO 1.78 K Ohm 1% 1/2W 862A376H25 RU, RI3 243K Ohm 1% 1/2W 862A376H38 RI2 15 KOhm 5% 1/2W 184A763HSS Rid 11 KOhm 1% 1/2W 862A376H0S RIS, R54, RSS 10 KOhm 1% 1/2W 862A377H30 RI7 9.1 KOhm 5% 1/2W 1844763H50 RIS 15 KOhm 5% 1/2W 1844763131 R19, R20 221K Ohm 1% 1/2W 862377134 R21, R22, R23, R24 2. KOhm 1% 1/2W 763A126H18 R25 2.7 KOhm 5% 1/2W 1844763137 R26, R27 1.2 KOhm 5% 1/2W 1844763129 R28 56 KOhm 5%1/2W 1844763169 R29, R39 5.6 KOhm 5% 1/2W 184A763H45 R31, R38 24 KOhm 5% 1/2W 1848763136 R34, R37 330 KOhm 5% 1/2W 184A763HI5 R35, R36 300 KOhm 5% 1/2 184476386 R40 22 KOhm 5% 1/2W 1844763135 Ra? 120 Ohm 5% 1/2W 184A763HOS Ras 75 KOhm 5%1/2W 184A763H72, Ras 11K Ohm 1% 1/2W 862A377H05 R46 2 K Ohm 10% 1/2W 862A406HO1 Ra7 187K Ohm 1% 1/2W 862A376H27 R50 49.9 Ohm 1% 1/2W 862A374H68 R51, R56, RSS 3) KOhm 5% 1/2W 1844763138 R52 39 KOhm 5% 1/2W 1844763165 R57, R16 10 KOhm 5%1/2W 184A763H51 R59 10 Ohm 5% 25W 04D1297H27 R53 100 K Ohm 5% 1/2W 1844763H75 R90, R91, R92, R93, R94, RIT, RS 121K Ohm 1% 1/2W 848A829H56 R100, 101, 102, 103, 104, 105, 106, 107, 108 121K Ohm 1% 1/2W 848A820H53 R200 47 Ohm 5% 1/2W 187A290H17 CAPACITORS C1, C16, C20, C30, €33, C36, C39 47 MED SOV 20% 762A680HO4 €2,€8, C11, C40 I MED 100V 10% 836A620H03 3, ¢5 47 MED 200V 10% 188A669HOI co 100 PFD 200V 10% 836A620H01 ¢6,¢7 50 PFP SOOV 2% 762A7S7H25 oo. 10_PFD 200V 879A989H01 12© ELECTRICAL PARTS LIST (Contd.) LL, 41.504,114 WESTINGHOUSE CIRCUIT SYMBOL DESCRIPTION STYLE NUMBER CAPACITORS (Contd.) cio 018 MED 100V 10% 836A620H04 12 500 PFD Soov 184A663HOS C13 51 PED SOOV 2% 763A209H18 cia 250 PFD S0OV 2% 861A46H11 C15, C17, C19 100 PFD 1000V 2% 184A663H06 cis 8 MED 30V 5% 862A177H07 32, C38 1.0 MED 200V 20% 876A409H10 34 4.7 MED 35V+10% 184A661H12 C35 5.6 PFD 200V +10% 880A403H0S DIODES D1, D2, D7, D8, D10, D12, D13, Di4, DIS D28, A,B, C,D, E, F,G,H,J,K,L 1N4148 836A928H06 D3,D4, DS, D6 1N645 837A692H03 D9,DiL 1N4S7A 184A85SHO7 ZENER DIODES 21,27 IN7A7A 837A398H08 2 1N965B 186A797H08 2B 1N962B 837A398H09 wa IN7S3A 862A606HO1 INPUT/OUTPUT MODULE RIA,R2A 150 Ohm 1/2W 1724641 DIA 1.5 KE6S 878A619HO2 CIA, C3A, CAA 022 MFD 1544921 C2A 0S MFD 1728695 C6A, C7A, C9A, C1OA, C14A, CISA 01 MFD 3516A36H03 CSA, CBA, CIA, C13A, CI6A 004 MFD 879A911H12 cl7A 01 MFD 879A911HI2 Telephone Relay 407C733H04 TRANSISTORS Q1, 02, Q3, 95, 07, Q9, Q11, Q12, Q13, Q1S 2N2905A 762A672HI1 04,06, Q10, Q16, Q29 2N2905A 762A672H10 Qs 2N4222, 878AS77HOL 14 DIBTI 878A289HOI Q27 2N3055 1874673108 Q28 DTSD410 1874673H09 13© ELECTRICAL PARTS LIST (Contd.) WESTINGHOUSE CIRCUIT SYMBOL DESCRIPTION STYLE NUMBER INTEGRATED CIRCUITS Joa CA3026 717B20SHO1 A,Q,V.W. U6A993059x 204C328H04 B,K,L,R,S,T,U UGA994659X 204C328H03 CD,E,F,13,P U6A993259X 204C328HO1 GH U6A993659X 204C328H02 COUNTER BITS 0-1, 2-3, 45, 6-7, 8.9, 10-11, 12-13, 14.15 TRIP 1.2 164909959 204C331H01 TRANSFORMERS-INDUCTORS Tl Input Isolation Transformer 878A574HO1 u Inductor 878A654HOL 13,14 Inductor 3500A27H02 MISCELLANEOUS TR Trip Relay S41D514H36 CLI (602) Crystal 187A857H23 TEST MODULE 1469C14G01 (Optional) RI 1200hm 1/2W 5% 184A763HOS cl 47 MED 35V 10% 187ASO8HOS a 100 PFD 200V 10% 836A620H01 3 1 MED 100V 10% 836A620H03 Di toDIL 1N4148 878A469HO01 A 1U6A993089X 204C328H04 B U6A994659X 204C328H03 c U6A993259X 204C328HO1 Switch (11 Req'd) 878A645HOL POWER SUPPLY MODULE — STYLE 1600C95G01 comp PART NAME DESCRIPTION STYLE NO. cot Capacitor 001 MF 20% 3000V Cer 3536A32H01 cos Capacitor <1 MED +5% SOV 184A663H14 Cos Capacitor <1 MED +5% S00V 184A663H14 C06 Capacitor 5 MED +75/-10% 25V 186A341H07 co7 Capacitor 1 MED +5% SO0V. 184A663H14 co8 Capacitor 210 MFD 250V 2-5/8x1 3529A07HO1 cos Capacitor 1000 PF IKV £10% Cer 762N680HO2 c10 Capacitor AT MED £5% 200V Mylar 876A409H17 4© ELECTRICAL PARTS LIST (Contd.) LL. 41-604,118 —— POWER SUPPLY MODULE — STYLE 1600C95G01 comp PART NAME DESCRIPTION STYLE NO. cu Capacitor 470 PF IKV £10% Cer 879A911H10 cz Capacitor 470 PF 1KV +10% Cer 879A911H10 cB Capacitor 100 MFD +100/-10% SOV EL 3535A92HOL ci4 Capacitor 1500 PF #10% IKV Cer 762A680H05 cis Capacitor 1000 PF 1KV +10% Cer 762A680H02 cis Capacitor 1500 PF £10% IKV Cer 762A680HOS c17 Capacitor 100 UF SOV #100/-10% EL 9641 A08HO2 cis, Capacitor 1000 PF 1KV +10% Cer 762A680H05 cy Capacitor 100 UF 20V +100/-10% EL 9641 A08HO1 20 Capacitor 270 PF SOOV +2% Mica 762A7STHI2 c2l Capacitor 1 MED 100V #20% Cer 762A680H14 c22 Capacitor 22 MFD 100V #20% Cer 3512A08HO2 23 Capacitor 1 MED 100V 420% Cer 762A680H14 C24 Capacitor 1 MED 100V +20% Cer 762A680H14 2s Capacitor 01 MED 200V +5% Met-Poly Carb 3534A68H03 C26 Capacitor 100 MFD +75/-10% 25V EL. 1864341102 car Capacitor 027 MED £10% 188669114 C28 Capacitor 01 MED 100V +20% Cer 184A663HO1 Dol Zener 1,5KE200 200V 10% SW 1.5KW SG 878A619H01 02 Diode 1N4936 400V 1A 836A928H10 03 Diode IN645A 225V 2 Amp 837A692H03 Dos Diode ING45A 225V 2 Amp 837A692H03 Dos Diode 1N4148 100V 836A928H06 06 Diode MR8S1 100V 3A Rectifier 3535A29H03 07 Diode MR851 100V 3A Rectifier 3535A29H03 Dos Diode MR851 100V 3A Rectifier 3535A29H03 Do Diode MR851 100V 3A Rectifier 3535A29H03 DI0 Diode IN64SA 225V 2 Amp 837A692H03 Du Diode 1N4148 100V 836A928HO6 Zol Zener 1N5352B 1SV 5% SW 862A288H04 Z03 Zener 1N966B 16V 5% 400MW 862A288HOS Z04 Zener 1N305OB 180V 5% IW 187A936H17 05, Zener UZ5240 400V 10% SW 837A693H17 208 Zener 1N959 8.2V 20% 400MW 837A398H12 209 Zener |1N9S7B 6.8V 5% 400MW 186A797H06 Qo1 Transistor 2N2222A NPN 762A672H15 Q02 Transistor 2N2907A PNP 7624672417 203 Transistor IRF720 400V 3A 9641 A07HO1 Q04 Transistor 2N2222A NPN 7624672415 05 Transistor 2N2222A NPN 762A672H15 06 Transistor 2N2222A NPN 762A672H15 Q07 Transistor 2N2222A NPN 762K672H15 08 Transistor 2N2222A NPN 762A672H15 6© ELECTRICAL PARTS LIST (Contd.) POWER SUPPLY MODULE — STYLE 1600C95G01 comp PART NAME DESCRIPTION STYLE NO. Ico Int Cit UATAIC 6277061H08 Ico2 Int Cit SG1524 Pulse Width Modulator 3534A92H01 103 Int Ckt MC14011 Bal Quad-2 Inpat Nand 3527A09H02 1co4 Int Ckt MC14011 Bal Quad-2 Input Nand 3527A09H02 Tol Core 1492B01G01 Lol Car Coil 1.28MH 3535A63G01 102 Car Coil 1.28MH 3535A63G01 PO2 Pot 2K 10% .SW Pot (Top Adjust) 3523A42H03 PO3 Pot Vat 1K Ohm 1DT (Top Adjust) 3523A42H03 Jol Jumper Bluechip Jumper 3532A54H01 Jo2 Jumper Bluechip Jumper 3532AS4HO1 303 Jumper Bluechip Jumper 3532AS4HO1 Joa Jumper Bluechip Jumper 3532AS4HO1 05 Jumper Bluechip Jumper 3532AS4HOI Jol Connector 3 Position 9640A47H01 302 Connector 3 Position 9640A47H01 303 Connector 3 Position 9640A47HO1 Jos Connector 3 Position 9640A47H01 305 Connector 3 Position 9640A47HOI Rol Resistor 10 Ohm SW 3% 629A923H15 Roz Resistor 10K 3W 5% W.W. 763A 127H15 R03 Resistor 2000 Ohm 2W 5% 185A207H34 Rod Resistor Ohm 862A478H01 ROS Resistor 30.1 Ohm 1/4W 1% Metal Film 848A818H01 ROG Resistor 1 Ohm .SOW 5% WW. 863A164H01 Ro7 Resistor 1. Ohm .SOW 5% WW. 863A164H01 R08 Resistor 250 Ohm 1% SW Min. Wire Wound 3529A28HO1 Roo Resistor 20K Ohm .SW 2% M.G. 6294531163 R10 Resistor 1K 1% .25W 863A174H01 RI Resistor 2K 1% .25W 863174130 R12 Resistor 10K 1% 25 863A175HOL R13 Resistor 10K 1% 25 863A17SHOL Ri4 Resistor 2K 2% 1/2W MG. 629531139 RIS Resistor 100K 19% .25W 863A17SH97 R16 Resistor 16K SOW 42% 6294531137 RI7 Resistor 100 Obm SW 2% 629A531H08 R18 Resistor 1K 1% 25 863A174H01 Rig Resistor 100 Ohm .sW 2% 629A531H08 R20 Resistor 20K 1% .25W 863A175H30 RII Resistor 20K 1% .25W 863A175H30 R22 Resistor 3.01K .25W 1% Metal Film 848A819H94 R23 Resistor 10K 2% 1/2 MG. 6294531156 R24 Resistor 30.1K 1% .25W 863A175H47 R25 Resistor S1.IK 1% .25W 863A175H69 R26 Resistor 100 Ohm SW 2% 6294531108 16© ELECTRICAL PARTS LIST (Contd.) LL, 41-504,114 POWER SUPPLY MODULE — STYLE 1600C95G01 comP PART NAME DESCRIPTION STYLE NO. R27 Resistor 100 Ohm .SW 2% 629A531H08 R28 Resistor 150 Ohm 1% .25W 863A173H18 R29 Resistor 1K 1% .25W 863A174HO1 R30 Resistor 780 Ohm 1% .25W 863A173H85 R31 Resistor 2K 1% .2SW 863A174H30 R32 Resistor 20K 1% .25W 863A175H30 R33 Resistor S.LIK 1% .25W 863A174H69 R34 Resistor S.L1K 1% .25W 863A 174H69 R35 Resistor S.LIK 1% .25W 863A1741169 R36 Resistor 1K 1% 25W 863A174H01 R37 Resistor 4.7K Ohm 1% .125W 863174166 R38 Resistor 2.4K 1% .25W 863A175HSO R39 Resistor 4.7K Ohm 1% .125W 863A174H66 R40 Resistor 100 Ohm SW I% WW. 763A130H03 R41 Resistor 13.0K Ohm .125W 1% MF. 863A 175H12 R42 Resistor S.11K 1% .25W 863A174H69 R43 Resistor 2K 1% .25W 863A174H30 Rad Resistor 10K 1% .25W 863A17SHOL Ras Resistor 2.Ohm IW 5% Molded Comp 629A371H23 R46 Resistor 383 Ohm 3W 1% 763A531H01 R47 Resistor S1.1K 1/4W 1% Metal Film 848A821H14 17LL, 41-504,114 Fig. 1. Type 1E SOF-1 Undertrequency Relay Front View (Without Case)LL. 41-504.118 (© Fig. 2. Type 1E SDF-1 Undertrequency Relay Rear View (Without Case)ALAR Hae edie LL, 41-504,118 Fig. 2A. Optional Test Module (Style 1469C14G01) See page 7. 20LL, 41-504.114 Sub. 4 (71982: Tas9e1sG01 ‘aan (OF © Ze Craving, vgy Onan 00 Schoen ip 6. Ma Oop a Fur Bary Cun rtd Crea e Pai Sree iat Sea ee Sompinn setes= "Sees (Ce ese om | = = gO ex] = os he pew fc bes] | 3 bes) fa] 8 oz fg) Sl 3 for) & B : : eS ‘Sub. — ‘Sub. 2 2) ss26a01) esz0as) Fig. 7. Twolve Bit Binary Counter Printed Circuit Module Component Location Fig. 8 Trip Control Gircult and Delay Timer Printed Circuit Module Component Location, Fig. 9. Power Supply Printed Circuit Module Component Location. 24 Sub 1 (964099),41.504.110 Test B0AR0 = D1 Toon wise 930 246 932 ‘sub. 2 (7178374) Fig. 10. Test Module Internal Schematic (Optional) sort netae l0990@ come S909) suv 2 (@804a10) Sub. 2 (3526404) Fig. 11. Diagram of Test Connections for SDF-1 Relay. Fig. 12. Test Module Component Location. 25LL. 41-504.118 5 MAX, i ‘ 8 3 20 = é Pa f s = 15 a : : z Z 2 2 o : g & 5 Foy a of) a) 2 ass) 0 7 lense pre[orTerenoeterdoeeonetra eee » 8 mm wD Ln mn oem ato CYCLES OF DELAY SETTING (60 HZ BASE) Fig. 19. SDF-1 Relay Tripping Delay Under Declining Frequency Conditions. 26LINEAR FREQUENCY DECAY FREQUENCY, Ser- POINT PLS gp evece rooereer onormrneauency conoion”™ FR TRIP. CONTROL LOGIC Tiwen DeLay je +8 CYCLES DESIRED INTERNAL DELAY——+ enna eae 1s roescveces Total Time 10 TRIP pie CONTACT Seno ‘cxosene 4 ——4— ° 4 it0s82 (7740485) Fig. 14. Linear Frequency Decey. SUDDEN ENERGIZATION BELOW SET-POINT ' \+—6 CYCLES DELAY SETTING —™ ir Mt + 4 | BCYCLES DESIRED INTERNAL DELAY (r44pase) Fig. 16, Sudden Energization Below Set-Point. 271L,41-504.114 mae fe oth 1] Ram icen p> ee ni ‘Sub.1 (3519468) Sub. 2 (1481869) Fig. 17. Input Output Module Component Location 28JL 41-504,114 © Fig. 18 Internal Schematfe Drawing with Two NC ContactsWESTINGHOUSE ELECTRIC CORPORATION RELAY AND TELECOMMUNICATIONS DIVISION CORAL SPRINGS, FL 33065 Printed in USA. e