EGCP 446: Advanced Digital Design: Part One - Moore State Machine On FPGA

Nate Ruppert 1
EGCP 446: Advanced Digital Design

Lab No 3: Finite State Machines
Introduction
This lab focuses on Finite state machines, Mealy and Moore, and how to verify and prototype them
within Xilinx Vivado. In Lab 4, we take our designs from the previous lab and implement them directly on
the hardware board. We can expect through this lab to implement complex and practical state machines
on FPGAs as well as learn essential Verilog components such as using case statements and if-else blocks.
Procedure and Discussion

Part One – Moore State Machine on FPGA
For part one of the lab we were instructed to first create a clock divider, and then implement the moore
design utilizing the clock divider as shown in the schematic below.
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In a non-exhaustive showcase, I provided the states of the machine at two points of the implementation
below, the first being normal operation (State 3 [0 indexed]) and the second showcasing Reset switch
being toggled setting state back to the first Moore state.
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Part Two – Mealy State Machine on FPGA

For Part two of the lab, we took the code from a debouncer provided in vhdl, translated it to Verilog,
and implemented it on the FPGA board based on the schematic below.
I took three pictures for this part of the lab: The first showcases Debouncer toggle with UP not active,
Debouncer toggle with Reset active (sets to state 0), and Debouncer toggle with UP active and reset not
active (moves to next state).
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Conclusion
In completing this lab, both a mealy and moore state machine were created, allowing us to see potential
use cases for both as well as refine our understanding of Verilog with case statements and if-else-else if
blocks. Furthermore, both mealy and moore state machines were implemented on FPGA showcasing
practical implementation and understanding of FPGA IO assignment and live demo capabilities. The
most important takeaway from this lab is furthering our understanding of Verilog and its practical uses
in designing machines in Vivado. As we are now on the third lab, we are improving our understanding of
creating everything required of a Verilog setup, such as a testbench, usage of registers, wires, case
switch, if-else, and many more.
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References
No references were used for this lab.
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Appendix
Lab Code
Mealy.v
`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/06/2021 11:54:38 AM
// Design Name:
// Module Name: mealy
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mealy(
input CLK,
input RST,
input UP,
output [1:0] Q
);
parameter a = 2'b00;
parameter b = 2'b01;
parameter c = 2'b10;
parameter d = 2'b11;
reg [1:0] STATE, NEXT;
always @(posedge CLK, posedge RST)

if (RST) STATE <= a;
else STATE <= NEXT;
always @(*)
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case (STATE)
a:
if (UP) NEXT = b;
else NEXT = d;
b:
if (UP) NEXT = c;
else NEXT = a;
c:
if (UP) NEXT = d;
else NEXT = b;
d:
if (UP) NEXT = a;
else NEXT = c;
endcase
assign Q = STATE;
endmodule
Moore.v

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/06/2021 11:54:38 AM
// Design Name:
// Module Name: moore
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
//
//////////////////////////////////////////////////////////////////////////////////
module moore(
input CLK,
input RST,
output [3:0] W
);
parameter S0 = 4'b0001;
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reg RV;
reg [4:0] STATE, NEXT;
always @(posedge CLK, posedge RST)

if (RST) STATE <= S0;
else STATE <= NEXT;
always @(*)
case (STATE)
S0:
NEXT = S1;
S1:
begin
if (RV) NEXT = S0;
else NEXT = S2;
RV = 0;
end
S2:
if (RV) NEXT = S1;
else NEXT = S3;
S3:
begin
NEXT = S2;
RV = 1;
end
endcase
assign W = STATE;
endmodule
Tb_Mealy.v

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/06/2021 11:54:38 AM
// Design Name:
// Module Name: tb_moore
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
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//
// Dependencies:
//
// Revision:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_mealy(
);
reg CLK, RST, UP;
wire [1:0] OUT;
mealy UUT(CLK, RST, UP, OUT);
always
begin
CLK = 1;
#20;
CLK = 0;
#20;
end
always
begin
UP = 1;
#200;
UP = 0;
#200;
end
initial
begin
RST = 1;
#60;
RST = 0;
end
endmodule
Tb_Moore.v

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/06/2021 11:54:38 AM
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// Design Name:
// Module Name: tb_moore
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_moore(
);
reg CLK, RST;
wire [3:0] OUT;
moore UUT(CLK, RST, OUT);
always
begin
CLK = 1;
#20;
CLK = 0;
#20;
end
initial
begin
RST = 1;
#60;
RST = 0;
end
endmodule
Package

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/16/2021 01:20:10 PM
// Design Name:
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// Module Name: package

// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
//
//////////////////////////////////////////////////////////////////////////////////
module package(
input Clk,
input Reset,
output [3:0] Q
);
wire clock;
clk_divider div0 (Clk, Reset,clock);
moore moore0 (clock, Reset, Q);
endmodule
Clock_Divider

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/16/2021 01:20:10 PM
// Design Name:
// Module Name: clk_divider
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
//
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//////////////////////////////////////////////////////////////////////////////////
module clk_divider(
input Clk,
input Reset,
output reg S_Clk
);
localparam constNum = 50000000;

reg [31:0] count;
always@ (posedge Clk, posedge Reset)
begin
if(Reset)
begin
count <= 32'b0;
S_Clk <= 1'b0;
end
else if (count == constNum - 1)
begin
count <= 32'b0;
S_Clk <= ~S_Clk;
end
else
begin
count <= count + 1;
S_Clk <= S_Clk;
end
end
endmodule
M_Package

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/18/2021 09:48:11 AM
// Design Name:
// Module Name: m_package
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
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//
// Revision:
//
//////////////////////////////////////////////////////////////////////////////////
module m_package(
input Clk,
input Btn,
input Reset,
input UP,
output [1:0] Q
);
wire clock;
//clk_divider div0 (Clk, Reset,clock); (test to ensure code works)
debouncer d0 (Clk, Btn, clock);

mealy m0 (clock, Reset, UP, Q);
endmodule
Debouncer

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/18/2021 09:34:14 AM
// Design Name:
// Module Name: debouncer
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
//
//////////////////////////////////////////////////////////////////////////////////
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module debouncer(
input clk,
input button,
output reg result
);
localparam constNum = 5000000;

reg [31:0] count = 0;
always@ (posedge clk)

begin
if (count == constNum - 1)
begin
count <= 0;
result <= button;
end
else
begin
count <= count + 1;
result <= result;
end
end
endmodule
Constraints
set_property IOSTANDARD LVCMOS18 [get_ports {W[3]}]

set_property PACKAGE_PIN H17 [get_ports {W[0]}]
set_property PACKAGE_PIN K15 [get_ports {W[1]}]
set_property PACKAGE_PIN J13 [get_ports {W[2]}]
set_property PACKAGE_PIN N14 [get_ports {W[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {Q[3]}]

set_property IOSTANDARD LVCMOS18 [get_ports Clk]
set_property IOSTANDARD LVCMOS18 [get_ports Reset]
set_property PACKAGE_PIN E3 [get_ports Clk]
set_property PACKAGE_PIN J15 [get_ports Reset]
set_property PACKAGE_PIN N14 [get_ports {Q[3]}]
set_property PACKAGE_PIN J13 [get_ports {Q[2]}]
set_property PACKAGE_PIN K15 [get_ports {Q[1]}]
set_property PACKAGE_PIN H17 [get_ports {Q[0]}]
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set_property IOSTANDARD LVCMOS18 [get_ports UP]

set_property IOSTANDARD LVCMOS18 [get_ports Btn]
set_property PACKAGE_PIN P18 [get_ports Btn]
set_property PACKAGE_PIN L16 [get_ports UP]

EGCP 446: Advanced Digital Design: Part One - Moore State Machine On FPGA

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Nate Ruppert 1

EGCP 446: Advanced Digital Design

Procedure and Discussion

Part Two – Mealy State Machine on FPGA

`timescale 1ns / 1ps

reg [1:0] STATE, NEXT;

always @(posedge CLK, posedge RST)

`timescale 1ns / 1ps

always @(posedge CLK, posedge RST)

`timescale 1ns / 1ps

`timescale 1ns / 1ps

`timescale 1ns / 1ps

// Module Name: package

`timescale 1ns / 1ps

localparam constNum = 50000000;

`timescale 1ns / 1ps

debouncer d0 (Clk, Btn, clock);

`timescale 1ns / 1ps

localparam constNum = 5000000;

always@ (posedge clk)

set_property IOSTANDARD LVCMOS18 [get_ports {W[3]}]

set_property IOSTANDARD LVCMOS18 [get_ports {Q[3]}]

set_property IOSTANDARD LVCMOS18 [get_ports UP]

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