Digital Techniques Complete Manual

Department of Aviation Engineering Technology
Lab Manual
Digital Techniques
AT-2226
Faculty of Engineering & Technology

List of Experiments
1. Introduction to Digital Logic Trainer.....................................................................................4
2. Verification of Truth Tables of Basic Logic Gates.................................................................7
3. Realization of Gates using Universal Gate (NAND Gate)...................................................14
4. Realization of Gates using Universal Gate (NOR Gate)......................................................21
5. Verification of theorems of Boolean Algebra.......................................................................27
6. Implementation of Full Adder and 4-Bit Parallel Adder using IC 7483............................41
7. Implementation of Full Subtractor and 4-Bit Parallel Subtractor using IC 7483............48
8. Design of Combinational Circuits..........................................................................................56
9. Implementation of Code Converters using Gates................................................................63
10. 4-bit Magnitude Comparator.................................................................................................75
11. Implementation of Multiplexer and Demultiplexer using IC74151 & IC74138................82
12. Verification of Latch and Flip Flop Operation using Gates...............................................89

Superior University
Digital Techniques
AT-2226
Experiment No.1
Introduction to Digital Logic Trainer
Prepared for
By:
Name:
ID:
Section:
Semester:
Total Marks:
Obtained Marks:
Signature:
Date:
Digital Techniques Lab 1
Introduction to Digital Logic Trainer
Objective:
To familiarize our self with the use of trainer and to explore the different components of
Digital Trainer.
Equipment:
Digital Logic Trainer
Theory:
All experiments included in this manual have been performed on the EES-2001 logic trainer.
Before starting actual experiments; let us first familiarize our self with the use of EES-2001
trainer.
Measuring Power Supplies:

Connect the EES-2001 Trainer to the 220V AC power source and turn ON the Trainer.
Observe
+5V, + 12V, +15V and -15V LED’s ON, indicating these supplies are available for
experimentation. Verify +5V, +12V, 15V and -15V voltages using a Multimeter.
Measuring Logic Levels:

Try using the LED’s (L0-L15) to monitor the logic level.
1. Connect +5V power to the LED indicator L0. The LED should be ON indicating logic
1.
2. Connect LED indicator L0 to GND. the LED should be OFF indicating logic 0.
Test the clock:

Rotate the timer rate knob to counter clock wise position until extreme position is reached.
Connect the output CLK to the input of LED L0.the light should blink ON and OFF slowly.
The light blinks rapidly as the timer rate knob is rotated clock wise. It will stop blinking at
some point and then LED will be ON indicating a higher frequency.
Measure the Logic Level Coming from One of the Logic Switch (S2 to S9):
Connect the outputs S2 AND S2’ of switch (S2) to L0 and L1 respectively. The LED’s should
indicate the logic levels originating from the S2 switch.
1. Set switch S2 at a higher position, L0 should be OFF and L1 should be ON.

2. Set switch S2 at a lower position, L0 should be ON and L1 should be OFF.
4
BCD logic input:
Connect switches S2, S3, S4 and S5 to the four input marked as 8 4 2 1 on the SBB-63 board.
Apply BCD input using switches, it would be decoded and displayed on the seven- segment
display.
1. Set switch S2 at logic ‘1’ and rest of the switches at ‘0’, BCD digit ‘8’ will be
displayed.
displayed.
displayed.
displayed.
5. Set switches at the appropriate positions to display BCD numbers (0-9)
Conclusion:
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Superior University
Digital Techniques
AT-2226
Experiment No.2
Verification of Truth Tables of Basic Logic Gates
Prepared for
By:
Name:
ID:
Section:
Semester:
Total Marks:
Obtained Marks:
Signature:
Date:
Verification of Truth Tables of Basic Logic Gates
Objective:
To check the operation of Basic logic gates according to their truth tables, using proper IC
chips.
Equipment:
1. Logic Trainer
2. Components (IC’s):
74LS08, 74LS04, 74LS32
3. Connecting/Jumper Wires
Theory:
In logic operations two possible conditions exist for any input or output: true or false. The
binary number system uses only two digits, 1 and 0, so it is perfect for representing these
states. Digital logic gates provide the basic building blocks these gates perform different
operations on the binary information. These logic gates are used in different combinations to
implement large complex systems. Digital logic gates are represented and identified by
unique symbols. These symbols are used in circuit diagrams to describe the function of a
digital circuit.
Digital Logic Gates function is represented by a function table or a truth table that describes
all the Logic gate outputs for every possible combination of inputs. As the logic gates operate
on binary values therefore these function tables describe the relationship between the input
and output in terms of binary values. The function of a logic gate is also described in terms
of an expression.
Logic gates are practically used in circuits where the inputs to the logic gates vary in time.
Timing diagrams are used to describe the response of the logic gates in a certain period of
time with respect to changing input. Timing diagrams graphically show the actual
performance of the logic gate to changing inputs for a predetermined period of time or
sequence of input signals.
The three fundamental gates are the AND, OR and NOT gates.
Logic gates are electronic circuits which perform logical functions on one or more inputs to
produce one output. There are seven logic gates. When all the input combinations of a logic
gate are written in a series and their corresponding outputs written along them, then this
input/ output combination is called Truth Table. OR, AND, NOT are basic gates. Various
gates and their working are explained here.
7
AND Gate:
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the
inputs is low.
Logic Symbol
A
Y
B
Figure 2. 1:Logic Symbol of AND Gate
Pin Configuration:
7408
A
1 VCC 14
B
2 B 13
3 Y 12
4 Y 11
A
B B
5 10
6 Y A 9
7 GND Y 8
Figure 2. 2: Pin Configuration of AND Gate IC
OR Gate:
The OR gate performs a logical addition commonly known as OR function. The output is high
when any one of the inputs is high. The output is low level when both the inputs are low.
Logic Symbol
A
Y
B
Figure 2. 3: Logic Symbol of OR Gate

Pin Configuration:
7432
1 A 14
VCC
2 B B 13
3 Y 12
A
4 A Y 11
B
B
5 10
Y A
6 9
7 Y 8
GND
Figure 2. 4: Pin Configuration of OR Gate
NOT Gate:
The NOT gate is called an inverter. The output is high when the input is low. The output is low
when the input is high.
Logic Symbol:
A Y
Figure 2. 5: Logic Symbol of NOT Gate
Pin Configuration:
7404
1 A 14
VCC
A
2 Y 13
A Y
3 12
4 Y A 11
A Y
5 10
6 Y A 9
7 GND 8
Y
Figure 2. 6: Pin Configuration of NOT Gate IC

Task # 1
Logical “and” operation:

The AND Gate performs a logical multiplication function. An AND gate has multiple inputs
and a single output. Most commonly used AND gates are two input AND gates.
Truth Table:
The AND operation produces an output of 1 (or high) when all of the inputs are 1 (or high). It
produces an output of 0 (or low) when any or all of the inputs are 0 (or low). “Truth Table”
for AND operation is as given below:
Table 2. 1: Truth Table of AND Gate
Inputs Outputs
A B Desired Y=A.B A.B Observed
0 0 0
0 1 0
1 0 0
1 1 1
Task # 2
Logical “or” operation:

The OR Gate performs a logical Addition function. An OR gate has multiple inputs and a
single output. Most commonly used OR gates are two input OR gates.
Truth Table:
The OR operation produces an output of 1 (or high) when any one input is at logic level 1 (or
high). It produces an output of 0 (or low) when all of the inputs are 0 (or low). “Truth Table”
for OR operation is as given below:
Table 2. 2: Truth Table of OR Gate
Inputs Outputs
Desired
A B Observed
Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1
Task # 3
Logical “not” operation:
NOT gate is also known as an inverter. The name indicates that the NOT gate should be
performing an inversion function. The NOT gate has a single input and a single output.
Truth Table:
The input signal applied across the single input of the NOT gate is inverted and is available at
the output. The function of the NOT gates is described by the function table or truth table
represented
Table 2. 3: Truth table of NOT Gate
Input Output
Desired
A Observed
Y
0 1
1 0
Procedure:
1. Insert the IC 74xx on the trainer’s breadboard.

2. Use any two Logic Switches (S2 to S9) of the trainer for Input and any one of the
LEDs (L0 to L15) of the trainer for Output indication.
3. Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
4. By setting various combinations of the two switches verify that the output of
the gate is in accordance with the Truth Table shown above.
5. Record your observation.
Conclusion:
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Superior University
Digital Techniques
AT-2226
Experiment No.3
Realization of Gates using Universal Gate (NAND Gate)
Prepared for
By:
Name:
ID:
Section:
Semester:
Total Marks:
Obtained Marks:
Signature:
Date:
Realization of Gates using Universal Gate (NAND Gate)
Objective:
To check the operation of NAND Gate according to their truth tables, using proper IC chips.
Equipment:
1. Digital Logic Trainer
2. IC 7400
3. Connecting wires
Theory:
Digital circuits are more frequently constructed with NAND or NOR gates than with
AND and OR gates. NAND and NOR gates are easier to fabricate with electronic
components and are the basic gates used in all IC digital logic families.
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both inputs
are low and any one of the input is low. The output is low level when both inputs are
high.
Logic eqn. Y = (A.B)’
Logic Symbol
A
Y
B
Figure 3.1: Logic Symbol of NAND Gate
Pin Configuration & Truth Table:

7400
Table 3.1: Truth Table of NAND Gate
A
1 VCC 14
B B
Inputs Outputs
2 13
Y
A
A B Y = (A+B)’
3 12
4
A Y
11
0 0 1
B
5
B
10 0 1 0
Y A
6 9 1 0 0
Y
7 GND 8
1 1 0
Figure 3.2: Pin Configuration of NAND Gate IC-7400
14
EX-OR GATE:
The output is high when any one of the inputs is high. The output is low when both the inputs are
low and both the inputs are high.
Logic eqn. Y = (A’B+AB’)
Logic Symbol:
A
Y
B
Figure 3.3: Logic Symbol of EX-OR Gate
7486 Table 3.2: Truth Table of EX-OR Gate

1 A 14
VCC
B B
2 13
A
3 Y 12
Y
4 A 11
5 B B 10
6 Y A 9
Y
7 GND 8
Inputs Outputs
A B Y = A’B+AB’
0 0 0
0 1 1
1 0 1
1 1 0
Figure 3.4: Pin Configuration of EX-OR Gate

NAND Gate Implementation
Task 1:
NAND Gate as AND Gate:
A NAND produces complement of AND gate. So, if the output of a NAND gate is inverted, overall
output will be that of an AND gate.
Y = ((A.B)’)’= (A.B)
A (A.B) A.B
B
Figure 3.5: Logic Circuit of NAND Gate as AND Gate

 Verify AND gate operation using NAND gates (See Figure 3.5)
 Show your results to the lab instructor.
Table 3.3: Truth Table of NAND Gate as AND Gate
Inputs Output
Desired
A B Observed
x=A.B
0 0 0
0 1 0
1 0 0
1 1 1
Task 2:
NAND gates as OR gate:
From De Morgan’s theorems:
(A.B)’ = A’ + B’
Similarly,
(A’. B’)’ = A’’ + B’’ = A + B
So, give the inverted inputs to a NAND gate, obtain OR operation at output
A A
(A B ) = A+B
B
B
Figure 3.6: Logic circuit of NAND Gate as OR Gate
 Verify OR gate operation using NAND gates (See Figure 3.6)

Table 3.4: Truth table of NAND Gate as OR Gate
Inputs Output
Desired
A B Observed
x=A+B
0 0 0
0 1 1
1 0 1
1 1 1
Task 3:
NAND gates as NOT gate:
A NOT produces complement of the input. It can have only one input, tie the inputs of a NAND gate
together. Now it will work as a NOT gate. Its output is
Y = (A.A)’ = (A)’
A A
Figure 3.7: Logic circuit of NAND Gate as NOT Gate
 Verify NOT gate operation using NAND gates (See Figure 3.7)
Table 3.5: Truth table of NAND Gate as NOT Gate

Inputs Output
A Desired Observed
X=A'
0 1
1 0
Task 4:
NAND gates as EX-OR gate:
The output of a two input EX-OR gate is given by:
Y = A’B + AB’
EX-OR gate can be implemented using four NAND gates as follows.
Gate No. Inputs Output

1 A, B (AB)’
2 A, (AB)’ (A (AB)’)’
3 (AB)’, B (B (AB)’)’
4 (A (AB)’)’, (B (AB)’)’ A’B + AB’
Now the output from gate no. 4 is the overall output of the configuration.
Q = [(A (AB)’)’ (B (AB)’)’]’
= (A (AB)’)’’ + (B (AB)’)’’
= (A (AB)’) + (B (AB)’)
= (A (A’ + B)’) + (B (A’ + B’))
= (AA’ + AB’) + (BA’ + BB’)
= (0 + AB’ + BA’ + 0)
= AB’ + BA’
So Q = AB’ + A’B = (A+B). (A’+B’)
A
Figure 3.8: Logic Circuit of NAND Gate as EX-OR Gate

Table 3.6: Truth table of NAND Gate as EX-OR Gate
Inputs Output
Desired
A B Observed
Q = AB’ + A’B
0 0 0
0 1 1
1 0 1
1 1 0
Procedure:
2. Use any two Logic Switches (S2 to S9) of the trainer for Input and any one of the LEDs (L0 to
L15) of the trainer for Output indication.
4. By setting various combinations of the two switches verify that the output of the gate is in
accordance with the Truth Table shown above.
Conclusion:
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Superior University
Digital Techniques
AT-2226
Experiment No.4
Realization of Gates using Universal Gate (NOR Gate)
Prepared for
By:
Name:
ID:
Section:
Semester:
Total Marks:
Obtained Marks:
Signature:
Date:
Realization of Gates using Universal Gate (NOR Gate)
Objective:
To check the operation of Universal NOR gate according to their truth tables, using proper IC chips.
Equipment:
2. IC 7402
3. Connecting wires
Theory:
Digital circuits are more frequently constructed with NAND or NOR gates than with
AND and OR gates. NAND and NOR gates are easier to fabricate with electronic
components and are the basic gates used in all IC digital logic families.
NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The output
is low when one or both inputs are high.
Logic eqn. Y = (A+B)’
Logic Symbol:
A
Y
B
Figure 4.1: Logic Symbol of NOR Gate
7402 Table 4.1: Truth Table of NOR Gate
1 Y 14
VCC
A Y
2 13
B B 12
3
4 Y A 11
A
5 Y 10
B B
6 9
7 GND 8
A
21
Inputs Outputs
A B Y = (A.B)’
0 0 1
0 1 1
1 0 1
1 1 0
Figure 4.2: Pin Configuration of NOR Gate IC-7402
22
NOR Gate Implementation
Task 1:
NOR Gate as AND Gate:
From De Morgan’s theorems:
(A+B)’ = A’. B’
Similarly,
(A’+B’)’ = A’’. B’’ = A.B
So, give the inverted inputs to a NOR gate, obtain AND operation at output.
A
Figure 4.3: Logic Circuit of NOR Gate as AND Gate
 Verify AND gate operation using NOR gates (See Figure 4.3)
Table 4.2: Truth table of NOR Gate as AND Gate
Inputs Output
Desired
A B Observed
Q=A.B
0 0 0
0 1 0
1 0 0
1 1 1
Task 2:
NOR gates as OR gate:
A NOR produces complement of OR gate. So, if the output of a NOR gate is inverted, overall output
will be that of an OR gate.
Q = ((A+B)’)’= (A+B)
A
Q
Figure 4.4: Logic Symbol of NOR Gate as OR Gate
 Verify OR gate operation using NOR gates (See Figure 4.4)

Table 4.3: Truth table of NOR Gate as OR Gate
Inputs Output
Desired
A B Observed
Q=A+B
0 0 0
0 1 1
1 0 1
1 1 1
Task 3:
NOR gates as NOT gate:
A NOT produces complement of the input. It can have only one input, tie the inputs of a NOR gate
together. Now it will work as a NOT gate. Its output is
Q = (A+A)’ = (A)’
A Q
Figure 4.5: Logic Circuit of NOR Gate as NOT Gate
 Verify NOT gate operation using NOR gates (See Figure 3.13)
Table 4.4: Truth table of NOR Gate as NOT Gate
Inputs Output
A Desired Observed
Q=A'
0 1
1 0
Task 4:
NOR gates as EX-NOR gate:
The output of two input EX-NOR gate is given by: Y = AB + A’B’. EX-NOR gate can be
implemented using four NOR gates as follows.
Gate No. Inputs Output

1 A, B (A + B)’
2 A, (A + B)’ (A + (A+B)’)’
3 (A + B)’ B (B + (A+B)’)’
4 (A + (A + B)’)’ (B + (A+B)’)’ AB + A’B’
Now the output from gate no. 4 is the overall output of the configuration.
Y = ((A + (A+B)’)’ (B + (A+B)’)’)’

= (A+ (A+B)’)’’. (B+ (A+B)’)’’
= (A+ (A+B)’). (B+ (A+B)’)
= (A+A’B’). (B+A’B’)
= (A+ A’). (A+ B’). (B+A’)(B+B’)
= 1. (A+ B’). (B+ A’).1
= (A+B’). (B+ A’)
= A. (B + A’) +B’. (B+A’)
= AB + AA’ +B’B+B’A’
= AB + 0 + 0 + B’A’
= AB + B’A’
So Y = AB + A’B’
Figure 4.6: Logic Circuit of NOR Gate as EX-NOR Gate
 Verify EX-NOR gate operation using NOR gates (See Figure 3.14)
Table 4.5: NOR Gate as Ex-NOR
Inputs Output
Desired
A B Observed
Q = AB + A’B’
0 0 1
0 1 0
1 0 0
1 1 1
Procedure:
Conclusion:
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Superior University
Digital Techniques
AT-2226
Experiment No.5
Verification of theorems of Boolean Algebra
Prepared for
By:
Name:
ID:
Section:
Semester:
Total Marks:
Obtained Marks:
Signature:
Date:
Verification of theorems of Boolean Algebra
Objective:
To verify theorems of Boolean algebra through Logic Gates
Equipment:
2. IC 7408, IC 7432, IC 7404
3. Connecting wires
Theory:
Digital Logic Gates function is represented by a function table or a truth table that Digital Logic
describes all the Logic gate outputs for every possible combination of inputs. As the logic gates
operate on binary values therefore these function tables describe the relationship between the input
and output in terms of binary values. The function of a logic gate is also described in terms of an
expression.
The basic Laws of Boolean Algebra that relate to the Commutative Law allowing a change in
position for addition and multiplication, the Associative Law allowing the removal of brackets for
addition and multiplication, as well as the distributive Law allowing the factoring of an expression,
are the same as in ordinary algebra.
Each of the Boolean Laws above are given with just a single or two variables, but the number of
variables defined by a single law is not limited to this as there can be an infinite number of variables
as inputs too the expression. These Boolean laws detailed above can be used to prove any given
Boolean expression as well as for simplifying complicated digital circuits.
27
Task # 1
De morgan’s Law:
Expression 1:
(X+Y)’=X’. Y’
This can be proof by the use of truth table.
L.H.S
Circuit Diagram:
x
(X + Y) (X + Y)
Figure 5.1 Logical Circuit

Truth table:
Table 5.1: Truth Table
Inputs Outputs
X Y X+Y (X+Y)’
0 0
0 1
1 0
1 1
R.H.S
Circuit Diagram:
x X
X .Y
y Y
Figure 5.2: Logic Circuit

Truth table:
Inputs Outputs
X Y X’ Y’ X’.Y’
0 0
0 1
1 0
1 1
Expression 2 :
(X.Y)’=X’+Y’
This can be proof by the use of truth table.
L.H.S
Circuit Diagram:
X
(X.Y) (X.Y)
Y
Figure 5.3: Logic circuit
Truth table:
Inputs Outputs
X Y X.Y (X.Y)’
0 0
0 1
1 0
1 1
R.H.S
Circuit Diagram:
x X
X +Y
y Y
Figure 5.4:Logic circuit
Table 5.4: Truth table
Inputs Outputs
X Y X’ Y’ X’+Y’
0 0
0 1
1 0
1 1
Task # 2
Absorption theorem:
Expression 1:
X + (X.Y) = X
1. Verify absorption theorem

2. Show your results to the lab instructor
L.H.S
Circuit Diagram:
X
X + (X.Y)
X.Y
Y
Truth table:
Table 5.5:Truth table
Inputs Outputs
X Y Observed
0 0
0 1
1 0
1 1
Expression 2:
X . (X +Y) = X
1. Verify absorption theorem

2. Show your results to the lab instructor
L.H.S
Circuit Diagram:
X X . (X+Y)
X+Y
Y
Truth table:
Table 5.6: Truth table
Inputs Outputs
X Y Observed
0 0
0 1
1 0
1 1
Procedure:
Conclusion:
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Superior University
Digital Techniques
AT-2226
Experiment No.6
Usage of K-map to simplify Boolean function
Prepared for
By:
Name:
ID:
Section:
Semester:
Total Marks:
Obtained Marks:
Signature:
Date:
Usage of K-map to simplify Boolean function
Objective:
Simplification of Boolean functions by using K-map
Equipment:
2. IC 7408, IC 7432, IC 7404
3. Connecting wires
Theory:
Karnaugh maps:
Karnaugh maps or K-maps for short provide another means of simplifying and optimizing logical
expressions. This is a graphical technique that utilizes a sum of product (SOP) form. SOP forms
combine terms that have been AND together that then get OR together. This format lends itself to the
use of De Morgan's law which allows the final result to be built with only NAND gates. The K-map
is best used with logical functions with four or less input variables.
One of the advantages of using K-maps for reduction is that it is easier to see when a circuit has been
fully simplified. Another advantage is that using K-maps leads to a more structured process for
minimization.
In order to use a K-map, the truth table for a logical expression is transferred to a K-map grid. The
grid for two, three, and four input expressions are provided in the tables below. Each cell corresponds
to one row in a truth table or one given state in the logical expression. The order of the items in the
grid is not random at all; they are set so that any adjacent cell differs in value by the change in only
one variable. Because of this, items can be grouped together easily in rectangular blocks of two, four,
and eight to find the minimal number of groupings that can cover the entire expression. Note that
diagonal cells require that the value of more than two inputs change, and that they also do not form
rectangles.
Table 6.1: Four-Variable Map Table 6.2: Two-Variable Map Table 6.3: Three-Variable Map
C’D’ C’D’ C’D’ C’D’

00 00 00 00
A’B’
00
A’B’ B’ B’
00 0 0
A’B’ A’
00 0
A’B’ A’
00 0
35
B’C’ B’C BC BC’
00 01 11 10
A’
0
A
1
36
Task
Let the Boolean function
F = A’BC+ AB’C + ABC’ + ABC
Circuit Diagram:
Figure 6. 1: Logic Circuit Diagram
Truth Table:
A B C Observed
We get the above truth table and want to simplify it by using Karnaugh Map.
K-MAP:
By using K-map simplify the Boolean expression.
00 01 11 10
0
1
Circuit Diagram:
Figure 6. 2: Simplified Logic Circuit Diagram
Truth Table:
A B C Observed
Simplification of Boolean expressions using algebraic manipulation is tedious and time consuming,
and lacks specific rules to predict each succeeding step in the manipulative process. The map method
is an efficient and straightforward procedure for minimizing Boolean functions of up to 4 variables.
Maps for more than 4 variables are not easy to use. However, we will be working only with functions
of up to 4 variables.
Procedure:
2. Use any two Logic Switches (S2 to S9) of the trainer for Input and any one of the LEDs (L0
to L15) of the trainer for Output indication.
Conclusion:
Superior University
Digital Techniques
AT-2226
Experiment No.7
Implementation of Full Adder and 4-Bit Parallel Adder using IC 7483
Prepared for
By:
Name:
ID:
Section:
Semester:
Total Marks:
Obtained Marks:
Signature:
Date:
Implementation of Full Adder and 4-Bit Parallel Adder using IC 7483
Objective:
1. To learn Half and Full Adder Operations

2. To learn 4- Bit Binary Parallel Adder Operations
Equipment:
2. IC 7408, 7404, 7483 & IC 7486
3. Connecting wires
Theory:
Digital computers perform a variety of information-processing tasks. Among the basic functions
encountered are various arithmetic operations. The most basic arithmetic operations are, no doubt,
the addition and subtraction of binary digits (bit).
HALF ADDER:
The possible operations, when we want to add only two bits, would be the followings:
0+0=0
0+1=1
1+0=1
1 + 1 = 0 & Carry 1
Above mentioned operation could be performed by a Half Adder circuit.
FULL ADDER:
We know that in practice, all addition operations must take into account the Carry bit (or digit) from
the previous operation. Adders in digital computers also take into account the Carry bit from last
operation and add it with the Augend and Addend bits of the present operation to complete the
addition operation. The possible operations are:
0 + 0 + 0 (carry) = 0
0 + 0 + 1 (carry) = 1
0 + 1 + 0 (carry) = 1
0 + 1 + 1 (carry) = 0 & carry 1 (to be added to next higher digit)
41
The adder that performs the addition of three bits (two significant bits and a previous carry) is called
a Full Adder.
TASK 1: HALF ADDER
We arbitrarily assign symbols A and B to the two inputs and S (for sum) and Cout (for Carry) to the
two outputs. Truth table for Half Adder as shown below
Table 7. 1: Truth Table of Half Adder
Output
Input Observed
Desired
A B S Cout S Cout
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
The simplified Boolean function for the two outputs can be written from this truth table as:
S = A'.B +A.B'
or
Cout = A.B
The circuit diagram for the Half Adder to implement above mentioned Boolean function could
be quite a few. We will however verify only one.
A
S
B
A
Cout
B
Figure 7. 1: Logic Circuit diagram of Half Adder

TASK 2: FULL ADDER
As mentioned in the beginning, a full-adder is a combinational circuit that forms the arithmetic
sum of three input bits (two significant bits and a previous carry bit) and two output bits. We
arbitrarily assign symbols A and B to the two significant bit inputs and Cin for the Carry from the
previous lower significant position, and S (for sum) and Cout (for Carry) to the two outputs. Truth
table for the Full Adder is shown below:
Table 7. 2: Truth Table of Full Adder
Output Output
Input
Desired Observed
A B Cin S Cout S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Simplified Boolean function for the two outputs can be written from this truth table as:
S = C’ (A’B+AB’) +C (A’B+AB’)’
= C’ (A’B+AB’) +C (AB+A’B’)
= C’A’B + C’AB’ + ABC + A’B’C
Cout = (A’B+AB’) C +A.B

= A’BC+AB’C+A.B
The circuit diagram for the Full Adder is as under:

Cin
S
A
B
Cout
Figure 7. 2: Logic Circuit of Full Adder
TASK 3: 4 BIT BINARY PARALLEL ADDERS
Adders that are available in integrated circuit form are parallel binary adders. A 4- Bit parallel
adder actually consists of four full adders connected in parallel. The carry output of each adder
is internally connected to the carry input of the next higher order adder. Fig 5 shows the
internal functional structure of 7483 IC in which 4 full adders are shown as separate entity.
Figure 6 is connection diagram for full adder function.
Figure 7. 3: 4bit Binary parallel Adder
Figure 7. 4: IC-7483 Pin Configuration
44
Table 7. 3: Truth Table of 4 bit binary parallel adder IC-7483 to be verified
Inputs Desired Output Observed Output
Binary Augend Binary Decimal Binary Output Decimal Binary Output

Addend Value value for
for Ref Ref
A A A A B B B B C S S S S C S S S S
A B Sum
3 2 1 0 3 2 1 0 o 3 2 1 0 o 3 2 1 0
0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 2
0 0 1 1 0 0 0 1 3 1 0 0 1 0 0 4
0 1 0 0 0 0 1 0 4 2 0 0 1 1 0 6
0 1 0 0 0 1 0 0 4 4 0 1 0 0 0 8
0 1 0 1 0 1 0 0 5 4 0 1 0 0 1 9
0 1 0 1 0 1 0 1 5 5 0 1 0 1 0 10
1 0 0 0 0 1 0 0 8 4 0 1 1 0 0 12
1 0 0 1 0 1 1 0 9 6 0 1 1 1 1 15
1 0 0 1 1 0 0 0 9 8 1 0 0 0 1 17
1 0 0 1 1 0 0 1 9 9 1 0 0 1 0 18
Procedure:
45
Conclusion:
Superior University
Digital Techniques
AT-2226
Experiment No.8
Implementation of Full Subtractor and 4-Bit Parallel Subtractor using IC 7483
Prepared for
By:
Name:
ID:
Section:
Semester:
Total Marks:
Obtained Marks:
Signature:
Date:
Implementation of Full Subtractor and 4-Bit Parallel Subtractor using

IC 7483
Objective:
1. To learn Half and Full subtractor Operations

2. To learn 4- Bit Binary subtractor Operations
Equipment:
2. IC 7408, 7404, 7483 & IC 7486
3. Connecting wires
Theory:
In binary subtraction, when larger digit is to be subtracted from a smaller digit, it becomes necessary
to BORROW a value from the next higher position. Thus the binary subtraction results in the
following basic operations
0-0=0
0 - 1 = 1, with a 1 borrowed from next higher digit position (which became 11 binary on reaching
current position).
1-0=1
1-1=0
The arithmetic element that performs this subtraction operation is called a Half Subtractor.
FULL SUBTRACTOR:
When we have borrowed a value from a higher position, then it must be accounted for when
subtraction is performed at that higher position. The way it is done can be explained with the
following example:
Posn 4 Posn 3 Posn 2 Posn 1 Posn 0
Minued 26 = 1 1 0 1 0
Subtrahend -12 = 0 1 1 0 0
48
14 = 0 1 1 1 0
49
We borrowed a ‘1’ from position 3 to carry out subtraction. When we move to position 3 for
subtraction, the position 2 should have returned the borrowed ‘1’ which will be added to the
subtrahend at position 3. (Note: Minuend at posn3 will remain 1)
We need to have two arrangements to carry out above mentioned action:
First, in addition to the subtraction result (call it DO), the position 2 should give out another output as
high (or 1) (call it Bo- borrow out) which would indicate its obligation to return the borrowed ‘1’ to
position 3
Second, position 3 should have some input arrangement (call it Bin- borrow in) which would take the
‘1’ returned by position 2 and add it to the subtrahend of position 3.
The possible combinations for full subtraction would be;
0 - 0 with a 0 as Bin = 0
0 - 0 with a 1 as Bin = 1, only if a 1 is borrowed from next higher digit position
0 - 1 with a 1 as Bin = 0, only if a 1 is borrowed from next higher digit position.
The arithmetic element that performs this subtraction operation is called Full Subtractor.
TASK 1: HALF SUBTRACTOR
We arbitrarily assign symbols A and B to the two inputs and D (for Difference) and Bo (for
Borrow) to the two outputs. Truth table for Half Subtractor as shown below:
Logic Circuit:
A
D
B
B B
A
Figure 8.1: Logic Circuit diagram of Half Subtractor

Truth Table:
Table 8.1: Truth Table of Half Subtractor
Output
Input Observed
Desired
A B B D B D
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
The simplified Boolean function for the two outputs can be written from this truth table as:
D = A'B +AB'
or
B = A'B
The circuit diagram for the Half Subtractor to implement above mentioned Boolean function could be
quite a few. We will however verify only one.
TASK 2: FULL SUBTRACTOR
A full Subtractor is a combinational circuit that performs subtraction involving three bits, namely
minuend, subtrahend, and borrow-in.
Simplified Boolean function for the two outputs can be written from this truth table as:
D = C’ (A’B+AB’) +C (A’B+AB’)’
= C’ (A’B+AB’) +C (AB+A’B’)
= C’A’B + C’AB’ + ABC + A’B’C
Take the value of ‘Bo’ and Simplify it by using K-Map, we have
Bo = A’B+A’C+BC
Logic Circuit:
Z D
A
B
Figure 8.2: Logic Circuit of Full Subtractor
Truth Table:
Table 8.2: Truth Table of Full Subtractor
Output Output
Input
Desired Observed
A B Z B D B D
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
TASK 3: 4 BIT BINARY SUBTRACTOR
4 bit Subtractor that that is available in integrated circuit to form. A 4-Bit subtractor actually
consists of four full subtractors connected in parallel. The borrow output of each adder is
internally connected to the carry input of the next higher order subtractor. Figure 8.3 shows the
internal functional structure of 7483 IC in which 4 full subtractors are shown as separate entity.
Figure 8.4 is connection diagram for full subtractor function.
Figure 8.3: 4bit Binary parallel Subtractor
B3 A2 A1 B1 A0 B0
A3 B2
Mode Selection
B Cin A B Cin A B Cin A B Cin M = 0 (Addition)
M = 1 (Subtraction)
Co/Bo S3
Co S2 Co S1 Co S0
Figure 8.4: IC-7483 Pin Configuration for 4

bit Subtractor
1 5
vCC
A3 3 14
C0/B0
A2
8 15 L3
A1
10 2 L2
7483
A0
16 6 L1
B3
4 9 L0
B2
7 12 GND
B1
B0 11 13
Mode Selection
M = 0 (Addition)
M = 1 (Subtraction)
Truth Table:
Table 8.3: Truth Table of 4 bit binary Subtractor IC-7483 to be verified
Desired Output Observed Output
Binary Binary Output

Binary Minuend Binary Output
Subtrahend Observed
A A A A B B B B B S S S S C S S S S
O o 0
3 2 1 0 3 2 1 0 u 3 2 1 0 3 2 1
t
1 0 0 0 0 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 1 0
1 0 1 0 1 0 1 1 0 1 1 1 1
1 1 1 0 1 1 1 1 0 1 1 1 1
1 0 1 0 1 1 0 1 0 1 1 0 1
Procedure:
Conclusion:
Superior University
Digital Techniques
AT-2226
Experiment No.9
Design of Combinational Circuits
Prepared for
By:
Name:
ID:
Section:
Semester:
Total Marks:
Obtained Marks:
Signature:
Date:
Design of Combinational Circuits
Objective:
1. Design a combinational circuit whose input is a four-bit number and whose output is the 2’s
complement of the input number.
2. Show that the circuit can be constructed using exclusive-OR gates
Equipment:
2. IC 7486
3. Connecting wires
Theory:
A combinational circuit is a circuit made up by combining logic gates such that the required logic at
thorough put depends only on the input logic present condition, both completely specified by either a
truth table or by a Boolean expression.
Characteristics:
1. An output remains constant, as long input conditions do not require change in output.
2. An output depends solely on the current input condition and not on any past input condition
or past output condition.
As combinational logic circuits are made up from individual logic gates only, they can also be
considered as “decision making circuits” and combinational logic is about combining logic gates
together to process two or more signals in order to produce at least one output signal according to the
logical function of each logic gate. Common combinational circuits made up from individual logic
gates that carry out a desired application include Multiplexers, De-multiplexers, Encoders, Decoders,
Full and Half Adders etc.
56
Truth Table:
INPUTS OUTPUTS
A B C D W X Y Z
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Simplification using K-Map
W=
X=
Y=
Z=
Boolean Function:
X=
Y=
Z=
Logic Diagrams:
Procedure:
Conclusion:
Superior University
Digital Techniques
AT-2226
Experiment No.10
Implementation of Code Converters using Gates
Prepared for
By:
Name:
ID:
Section:
Semester:
Total Marks:
Obtained Marks:
Signature:
Date:
Implementation of Code Converters using Gates

Objective:
1. To learn about BCD to Seven Segment Display Code

2. BCD to Gray Code Conversion
3. BCD to Excess-3 Code Conversion
Equipment:
2. IC 7447, IC 7486, AND, OR, NOT gates
3. Connecting wires
4. Resistors 180 ohms
Theory:
The availability of large variety of codes for the same discrete elements of information results in the
use of different codes by different digital systems. Sometimes it becomes necessary to use output one
system as input to another system.
A conversion circuit must be inserted between the two systems, if each uses different code for the
same information. When a decimal number is decoded such that each digit of the number is
represented by a 4-bit binary number, it is called 8421 Binary Coded Decimal Code or more simply
a BCD code.
Here, ten out of sixteen possible combinations of the code are selected to represent decimal 0 through
9. Most commonly used BCD codes are given below:
63
Table 10.1: Truth Table of BCD to Gray Code and Excess-3
EXCESS-3
DECIMAL BCD GRAY CODE
CODE
0 0000 0000 0011
1 0001 0001 0100
2 0010 0011 0101
3 0011 0010 0110
4 0100 0110 0111
5 0101 0111 1000
6 0110 0101 1001
7 0111 0100 1010
8 1000 1100 1011
9 1001 1 1 01 1100
The important characteristics of the Gray code is that only one digit changes as we count from top to
bottom; that is why it is termed as minimum change code. The Gray code is used for input and
output devices. Primary use is in numeric input encoding applications, where we expect
nonrandom input value change (i.e. value n changes either to n-1 or to n+1).
Another decimal code that has been used in some old computers is Excess-3 code. Its code
assignment is obtained from the corresponding value of BCD after the addition of 3. The code is
used in many arithmetic circuits because it is self- complementing (i.e. the 9’s complement value
of the decimal number can be obtained by complementing each bit of the code).
Task 1: BCD to Seven Segment Display Code Conversion
Most Digital equipment has some means for displaying information in a form that can be understood
readily by the user or operator. One of the simplest and most popular methods for displaying
numerical digits uses a 7-segment configuration. To form decimal characters 0 through 9 and
sometimes hex characters A through
A BCD to 7-Segment Driver (IC 7447) is used to take four bit BCD input and provide the outputs
that will pass current through the appropriate segment of the display to generate desired output/
number. Truth Table for Active High and Active Low cases are shown below:
1 16 vCC
S2 2 f15
f
S1
3 g 14
10 9 8 7 6
g
4 a13 g fcomm a b
7447 a a
f b
5 b 12 g
b e c
d
6 c 11
S0 c
e dcomm cDp
1 2 3 4 5
7 d10 d
S3
GND8 e9 e
Figure 10.1: Pin Configuration of BCD to 7-Segment IC
The segments of Seven Segment display are made of LEDs. Depending on the arrangements of the
LEDs, the display could be Common Anode or Common Cathode type. We are using common anode
type of display, which would require that either pin 3 or pin 8 is connected to Vcc and the input is
active low.
Truth Table:
Table 10.2: Truth Table of BCD to 7-Segment (Active High)
Input Output-Seven Segment Decoder
Decimal
BCD (Active High)
Display
So S1 S2 S3 a b c d e f g
Output
0 0 0 0 0 1 1 1 1 1 1 0 0
0 0 0 1 1 0 1 1 0 0 0 0 1
0 0 1 0 2 1 1 0 1 1 0 1 2
0 0 1 1 3 1 1 1 1 0 0 1 3
0 1 0 0 4 0 1 1 0 0 1 1 4
0 1 0 1 5 1 0 1 1 0 1 1 5
0 1 1 0 6 0 0 1 1 1 1 1 6
0 1 1 1 7 1 1 1 0 0 0 0 7
1 0 0 0 8 1 1 1 1 1 1 1 8
1 0 0 1 9 1 1 1 0 0 1 1 9
Truth Table:
Table 10.3: Truth Table of BCD to 7-Segment (Active Low)
Input Output- Seven Segment Decoder
Decimal
BCD (Active Low -IC 7447) Display
Output
S0 S1 S2 S3 a b c d e f g
0 0 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 1 1 0 0 1 1 1 1 1
0 0 1 0 2 0 0 1 0 0 1 0 2
0 0 1 1 3 0 0 0 0 1 1 0 3
0 1 0 0 4 1 0 0 1 1 0 0 4
0 1 0 1 5 0 1 0 0 1 0 0 5
0 1 1 0 6 1 1 0 0 0 0 0 6
0 1 1 1 7 0 0 0 1 1 1 1 7
1 0 0 0 8 0 0 0 0 0 0 0 8
1 0 0 1 9 0 0 0 1 1 0 0 9
Task 2: BCD to Gray Code Conversion
The bit combination for the BCD and Gray code are listed in the table below. Since each code uses
four bits to represent a decimal digit, there must be four input variables and four output variables.
Truth Table:
Table 10.4: Truth Table of BCD to Gray Code
Input
Output Gray Code Observed Output
BCD
A B C D W x y z W x y z
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
Logic Circuit Diagram:
D
Z
C
Y
B
X
A W
Figure 10.2: Logic Circuit Diagram of BCD to 7-Segment
Task 3: BCD to Excess-3 Conversion
The bit combination for the BCD and Excess-3 code are listed in the table below. Since each code
uses four bits to represent a decimal digit, there must be four input variables and four output
variables.
Truth Table:
Table 10.5: Truth Table of BCD to Excess-3
Input Output Excess-3 Observed Output

Code
BCD
A B C D w x y z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
Simplify using K-MAP:
Obtain the simplified outputs with the help of K-MAP

Logic Circuit Diagram:
Procedure:
Conclusion:
Superior University
Digital Techniques
AT-2226
Experiment No.11
4-bit Magnitude Comparator
Prepared for
By:
Name:
ID:
Section:
Semester:
Total Marks:
Obtained Marks:
Signature:
Date:
4-bit Magnitude Comparator

Objective:
To learn the implementation of 1-bit, 2-bit, and 4-bit magnitude comparator.
Equipment:
2. IC 7408, 7404, 7402, IC 7486, IC 74LS85
3. Connecting wires
Theory:
Another common and very useful combinational logic circuit is that of the Digital Comparator
circuit. Digital or Binary Comparators are made up from standard AND, NOR and NOT gates that
compare the digital signals present at their input terminals and produce an output depending upon
the condition of those inputs.
For example, along with being able to add and subtract binary numbers we need to be able to
compare them and determine whether the value of input A is greater than, smaller than or equal to
the value at input B etc. The digital comparator accomplishes this using several logic gates that
operate on the principles of Boolean algebra. There are two main types of Digital Comparator
available and these are.
1. Identity Comparator – an Identity Comparator is a digital comparator that has only one output
terminal for when A = B either “HIGH”
A = B = 1 or “LOW” A = B = 0
2. Magnitude Comparator – a Magnitude Comparator is a type of digital comparator that has

three output terminals, one each for equality, A = B greater than, A > B and less than A < B
The purpose of a Digital Comparator is to compare a set of variables or unknown numbers, for
example A (A1, A2, A3 ... An) against that of a constant or unknown value such as B (B1, B2,
B3… Bn) and produce an output condition or flag depending upon the result of the comparison.
For example, a magnitude comparator of two 1-bits, (A and B) inputs would produce the
following three output conditions when compared to each other
A>B, A=B, A<B

Which means: A is greater than B, A is equal to B and A is less than B
This is useful if we want to compare two variables and want to produce an output when any of the
above three conditions are achieved. For example, produce an output from a counter when a certain
count number is reached. Consider the simple 1-bit comparator below.
75
Task 1: 1-bit Digital Comparator
Circuit Diagram:
A A A<B
A=B
A>B
B
B
Figure 11.1: Logic Circuit Diagram of 1-bit Magnitude Comparator
Truth Table:
Table 11.1: Truth Table of 1-bit Magnitude Comparator
Inputs Outputs Observed
B A A>B A=B A<B A>B A=B A<B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
There are two distinct features about the comparator from the above truth table. Firstly, the circuit
does not distinguish between either two “0” or two “1”„s as an output A = B is produced when they
are both equal, either A = B = “0” or A = B = “1”. Secondly, the output condition for A = B
resembles that of a commonly available logic gate, the Exclusive-NOR or Ex-NOR function
(equivalence) on
each of the n-bits giving: Q = A ⊕ B

As well as comparing individual bits, we can design larger bit comparators by
cascading together n of these and produce n-bit comparator just as we did for the n- bit adder in the
previous tutorial. Multi-bit comparators can be constructed to compare whole binary or BCD words
to produce an output if one word is larger, equal to or less than the other.
A very good example of this is the 4-bit Magnitude Comparator. Here, two 4-bit words (“nibbles”)
are compared to each other to produce the relevant output with one word connected to inputs A
and the other to be compared against connected to input B as shown below.
Task-2: 4-Bit Magnitude Comparator
IC Pin Configuration:
B3 1 16 vCC
A<B 2 f 15 A3
ENTREES
A=B 3 g 14 B2
A>B 4 a 13 A2
7485
A>B 5 12 A1
b
SORTIES
A=B 6 c 11 B1
A<B 7 d 10 A0
GND 8 e 9 B0
Figure 11.2: Pin Configuration of 4-bit Magnitude Comparator IC 7485

4-bit Magnitude Comparator Logic Circuit Diagram:
A3
x3
B3
A2
x2
B2
(A<B)
A1
x1
B1
A0
(A>B)
x0
B0
(A=B)
Figure 11.3: Logic Circuit Diagram of 4-bit Magnitude Comparator

Truth Table:
Inputs Desired Output
A3 A2 A1 A0 B3 B2 B1 B0 A>B A=B A<B
0 0 0 1 0 0 0 1
0 0 1 1 0 0 0 1
0 1 0 0 0 0 1 0
0 1 0 0 0 1 0 0
0 1 0 1 0 1 0 0
0 1 0 1 0 1 0 1
1 0 0 0 0 1 0 0
1 0 0 1 0 1 1 0
1 0 0 1 1 0 0 0
1 0 0 1 1 0 0 1
Procedure:
Conclusion:
Superior University
Digital Techniques
AT-2226
Experiment No.12
Implementation of Multiplexer and Demultiplexer using Ic74151& Ic74138
Prepared for
By:
Name:
ID:
Section:
Semester:
Total Marks:
Obtained Marks:
Signature:
Date:
Implementation of Multiplexer and Demultiplexer using IC74151 &

IC74138
Objective:
To learn about Multiplexer and Demultiplexer
Equipment:
2. IC 74151, 74138
3. Connecting wires
Theory:
MULTIPLEXER:
1. The multiplexer circuit is used to place two or more digital signals (from two or more
sources) onto a single line, by placing them there at different time intervals (technically it is
known as time-division- multiplexing).
2. The multiplexer (also known as data selector) will select data from several transmission lines
to be gated to the single output transmission line.
3. The multiplexer will have a number of control inputs that are used to select the appropriate
data channel for input.
4. The number of data inputs is equal to 2n where n is the number of control selecting
leads.
5. A multiplexer can be used to convert parallel data to serial data.
DEMULTIPLEXER:
1. A demultiplexer (data distributor) will receive information from a single line and selectively
transmits it to several output lines/channels (one at a time).
2. Demultiplexer has several control select lines which are used to determine (or select) the
output transmission path.
3. The number of data output lines is 2n, where N is the number of control select leads.
4. Demultiplexers are used to convert serial data to parallel data.
82
Task 1: Multiplexer
IC 74151 is 8-to-1-Line Multiplexer. It has following features:
1. 8 Data Inputs (DO- D7)

2. Three Select Inputs (A, B, C)
3. An Enable (or Strobe) G
4. One-bit output Y (and its complement W)
Clock Input to
Data Input Pins
Data Input D3 1 16
D3 VCC
Data Input D2 2
D2 D4 15 Data Input D4
Data Input D1 Data Input D5

3 D1 14
D5
Data Input D0
4
D0 Data Input D6
74151 D6
L0 Data Input D7
5 13
Y
Switch S1
6 W D7
GND Switch S2
12
7 G
GND
A 11 Switch S3
8 GND
B 1
0
C 9
Figure 12.1: Pin Configuration of Multiplexer IC-74151
Procedure:
1. Wire the circuit as per figure above.
2. Connect “Clock Input” (very low frequency) to Input pins of the IC (D0 – D1) and see if the
Output LED is pulsating. Confirm your finding on the truth table.
Truth Table:
Table 12.1: Truth Table of Multiplexer
Select Strobe Output Output
C B A G (or S) Y Observed
Output Y is linked with input present

0 0 0 0
at D0
Output Y is linked with input present at

0 0 1 0
D1

0 1 0 0
at D2

0 1 1 0
at D3

1 0 0 0
at D4

1 0 1 0
at D5

1 1 0 0
at D6

1 1 1 0
at D7
Task 2: Demultiplexer
A 1-Line-to-8-Line demultiplexer distributes one input to 8 output lines. IC 74138 which was used
as a decoder in the last experiment will be used here as Demultiplexer. The only difference between
the previous circuit and present circuit will be addition of an INPUT (through Enable AND gate)
to the 4th pin of all the 8 NAND gates. The A, B and C inputs will serve as SELECT input (to
select a particular output line).
1 16
Switch S2 A VCC
Switch S1 2 15 O0
B Y0
3 14 O1
Switch S0 C Y1
4 13 O2
G2A Y2
74138
5 12 O3
G2B Y3
+5V 6
G1 Y4 11 O4
O7 7
Y7 Y5
10 O5
8 9 O6
GND Y6
Figure 12.2: Pin Configuration of Demultiplexer IC-74138
Truth Table:
Table 12.2: Truth Table of Demultiplexer
Input Output
C B A O7 O6 O5 O4 O3 O2 O1 O0
0 0 0 1 1 1 1 1 1 1 0
0 0 1 1 1 1 1 1 1 0 1
0 1 0 1 1 1 1 1 0 1 1
0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 1 1 0 1 1 1 1
1 0 1 1 1 0 1 1 1 1 1
1 1 0 1 0 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1
Task 3: Data Communication using Multiplexer & Demultiplexer
Multiplexer IC 74151 and Demultiplexer IC 74138 have been utilized to demonstrate single-line data
communication. The 3-bit select code will determine which data input will be steered to the Y output
of the Demultiplexer.
Circuit Diagram:
Figure 12.3: Multiplexer and Demultiplexer circuit
Switch S2
Switch S1
Switch S0
Data Input D31D3 16 1 A 16

VCC VCC
Data Input D2 2 15 2 B Y0 15 O0
D2 D4 Data Input D4
Data Input D5 3 C 14 O1
Data Input D13D1 D5 14 Y1
Data Input D04 13Data Input D6

4 G2A Y2 13 O2
D0 D6 74138
74151
Data Input D7
5
G2B Y3
12 O3
5 12
Y D7
6W A 11
GND7 G 10
B
GND C
GND8 9
Procedure:
Wire the circuit as per figure above and verify result first by giving clock signal to One Input pin at a
time of the IC (D0 – D1) and then to all the pins simultaneously.
Truth Table:
Table 12.3: Truth Table of Demultiplexer
Observed
Applied Signal When Clock Signal
Select Signal at is Applied At All of
Out at
Data Input Output D Pins of MUX
Pin Pin
Observed Output
A B C D Y
at Pin of
DEMUX
0 0 0 D0 Y0
0 0 1 D1 Y1
0 1 0 D2 Y2
0 1 1 D3 Y3
1 0 0 D4 Y4
1 0 1 D5 Y5
1 1 0 D6 Y6
1 1 1 D7 Y7
Conclusion:
Superior University
Digital Techniques
AT-2226
Experiment No.13
Verification of Latch and Flip Flop Operation using Gates
Prepared for
By:
Name:
ID:
Section:
Semester:
Total Marks:
Obtained Marks:
Signature:
Date:
Verification of Latch and Flip Flop Operation using Gates

Objective:
To learn about various types of Latches and Flip-Flops
Equipment:
2. 2. IC 7402, 7400, 7404
3. Connecting wires
Theory:
A Flip Flop is a logic circuit that has two stable states Low or High. Enable input signal may be used
to enable or disable a flip flop. Clock signal is used to synchronize operations of flip flops. Most (if
not all) of the system output can change state only when the clock makes a transition.
Latches are a form of Flip Flop, which do not require clock pulse to latch or hold data present at its
input.
89
Task 1: SR (or RS or SC) Latch
The SR is the simplest form of Flip Flop or Latch. It could be constructed from NOR gates or NAND
gates. Standard logic symbol of SR flip flop and its truth table is given below
S Q
R Q
Input Output
S R Q
Set Reset
0 0 Last state
1 0 1
0 1 0
1 1 Forbidden
NOR Gate SR Latch:
R
Clear
Q
S Q
Set
Figure 13.1: Logic Circuit Diagram of SR Latch
Table 13.1: Truth Table of SR Latch
Input Output
Action Observation
S R
Q
Set Reset
1 0 1 Set
0 0 Last state No change

0 1 0 Clear
0 0 Last state No change
1 1 Forbidden Forbidden
Task 2: Gates SR Flip Flop
Works only when Enable is high
S
Set
Q
EN
Enable
Q
R
Clear
Figure 13.2: Logic Circuit Diagram of Gated SR Flip Flop
Table 13.2: Truth Table of Gated SR Flip Flop
Input Output
En S R Action Observation
Q
Enable Set Clear/Reset
1 1 0 1 Set
1 0 0 Last State No Change
1 0 1 0 Clear
1 1 1 Forbidden Forbidden
0 x x Last State No Change

Task 3: J-k Flip Flop
S
Set
Q
EN
Enable
Q
R
Clear
Figure 13.3: Logic Circuit Diagram of Gated JK Flip Flop
Table 13.2: Truth Table of Gated SR Flip Flop
Input Output
En J K Action Observation
Q
Enable Set Clear/Reset
1 1 0 1 Set
1 0 1 0 Clear
1 1 1 Qn’ Toggle
0 x x Last State No Change

Procedure:
2. Use any two Logic Switches (S2 to S9) of the trainer for Input and any one of the LEDs
(L0 to L15) of the trainer for Output indication.
Conclusion:

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Department of Aviation Engineering Technology

Faculty of Engineering & Technology

1. Introduction to Digital Logic Trainer.....................................................................................4

2. Verification of Truth Tables of Basic Logic Gates.................................................................7

3. Realization of Gates using Universal Gate (NAND Gate)...................................................14

4. Realization of Gates using Universal Gate (NOR Gate)......................................................21

5. Verification of theorems of Boolean Algebra.......................................................................27

6. Implementation of Full Adder and 4-Bit Parallel Adder using IC 7483............................41

7. Implementation of Full Subtractor and 4-Bit Parallel Subtractor using IC 7483............48

8. Design of Combinational Circuits..........................................................................................56

9. Implementation of Code Converters using Gates................................................................63

10. 4-bit Magnitude Comparator.................................................................................................75

11. Implementation of Multiplexer and Demultiplexer using IC74151 & IC74138................82

12. Verification of Latch and Flip Flop Operation using Gates...............................................89

Introduction to Digital Logic Trainer

Digital Logic Trainer

Measuring Power Supplies:

Measuring Logic Levels:

Test the clock:

1. Set switch S2 at a higher position, L0 should be OFF and L1 should be ON.

Figure 2. 1:Logic Symbol of AND Gate

Figure 2. 2: Pin Configuration of AND Gate IC

Figure 2. 3: Logic Symbol of OR Gate

Figure 2. 4: Pin Configuration of OR Gate

Figure 2. 5: Logic Symbol of NOT Gate

Figure 2. 6: Pin Configuration of NOT Gate IC

Logical “and” operation:

Table 2. 1: Truth Table of AND Gate

Logical “or” operation:

1. Insert the IC 74xx on the trainer’s breadboard.

Figure 3.1: Logic Symbol of NAND Gate

Pin Configuration & Truth Table:

Figure 3.2: Pin Configuration of NAND Gate IC-7400

Logic eqn. Y = (A’B+AB’)

Figure 3.3: Logic Symbol of EX-OR Gate

Pin Configuration & Truth Table:

7486 Table 3.2: Truth Table of EX-OR Gate

Figure 3.4: Pin Configuration of EX-OR Gate

Figure 3.5: Logic Circuit of NAND Gate as AND Gate

Table 3.3: Truth Table of NAND Gate as AND Gate

(A’. B’)’ = A’’ + B’’ = A + B

Figure 3.6: Logic circuit of NAND Gate as OR Gate

 Verify OR gate operation using NAND gates (See Figure 3.6)

Table 3.4: Truth table of NAND Gate as OR Gate

Figure 3.7: Logic circuit of NAND Gate as NOT Gate

Table 3.5: Truth table of NAND Gate as NOT Gate

Gate No. Inputs Output

Figure 3.8: Logic Circuit of NAND Gate as EX-OR Gate

Logic eqn. Y = (A+B)’

Figure 4.1: Logic Symbol of NOR Gate

Pin Configuration & Truth Table:

7402 Table 4.1: Truth Table of NOR Gate

Figure 4.2: Pin Configuration of NOR Gate IC-7402

Figure 4.3: Logic Circuit of NOR Gate as AND Gate

Table 4.2: Truth table of NOR Gate as AND Gate

Figure 4.4: Logic Symbol of NOR Gate as OR Gate

 Verify OR gate operation using NOR gates (See Figure 4.4)

Table 4.3: Truth table of NOR Gate as OR Gate

Figure 4.5: Logic Circuit of NOR Gate as NOT Gate

Gate No. Inputs Output