Department of Electrical Engineering

Riphah College of Science & Technology

Faculty of Engineering & Applied Sciences
Riphah International University, Lahore

Program: B.Sc. Electrical Engineering Semester: III

Subject EE-203 Digital Logical Design Date: ……………….

Experiment 09: Investigate the operation of encoders and decoders.

Student Name: ……………………………………………………………

Lab Performance

No. Title Marks Obtained

Marks
1 Ability to conduct experiment 5
2 Data Analysis & Interpretation 5
3 Total 10

Lab Reports

No. Title Marks Obtained

Marks
1 Calculations and Data Presentation 5
2 Total 5

Remarks (if any): ………………………………….

Name & Signature of faculty: …………………………………

 Part A

1 Objective
Investigate the operation of Multiplexer.

2 Purpose
Having completed this experiment you will be able to:
• Understand the operating principles and construction of multiplexers.

3 Apparatus
• Logic Trainer (SMT-8005)
• Logic Trainer (SMT-800)
• Power Supply
• Connecting wires

4 Theory
Multiplexer, or MUX, is a logic circuit that select and route any number of
inputs to a single output. One of the multiple inputs are selected by the selector
gate and routed to the single output. The numbers of selector gates determine
the capacity of a multiplexer. For example, if a certain MUX has only one
selector gate, it is referred to as a 2 line-to-1 line MUX because one selector can
only selector from two inputs. A MUX with 3 selector gates is called 8 line-to-1
line MUX, since 3 selectors are capable of selecting an output from 8 inputs
(23 = 8). MUX is also referred to as Data Selector because it selects one output
from among many inputs. P
Function expression, such as F (CBA) = (0, 1, 2, 6, 7), can be easily executed
on MUX. The function F generates the sum of products (CB + CB) from states
0, 1, 2, 6, 7. Refer to the 4 line-to-1 line MUX below, the output is determined
by states of selectors A, B and C. When CBA = 000, 001, 010, 110, 111 the
output F is 1. In all other states F=0.
Actually, A0 is not connected to the gate input. If A1 = 1 then Q2 Q1 Q0 = 001.
When A2 = 1 the output Q2 Q1 Q0 = 010. There cant be more than one 1 among

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 Figure 1: 2-1 line MUX.

the inputs. For example, if A2 = 1 and A3 = 1 simultaneously, Q2 Q1 Q0 = 011.

If A3 , A4 both are 1 at the same time, Q2 Q1 Q0 = 111. Both outputs are
incorrect.

4.1 Using Multiplexer to Create Function (Module SM T −

8005 block Multiplexer 2)
4.1.1 Procedure
• Block Multiplexer 2 of module SMT-8005 will be used in this section of
the experiment to create functions.

Figure 2: Schematic diagram of 74LS151.

• Use U3 (74LS151) to create the function given below:

X
F (D, C, B, A) = (0, 2, 4, 5, 7, 8, 10, 11, 15)
Place connection leads according to Fig. 1.2 to complete the function
shown above. Since D, C, B, A has 16 possible variations and the 74LS151
has only 8 variations, D will be used as the data input.
• Connect inputs D, C, B, A to Data Switches SW3, SW2, SW1 and SW0
respectively. Connect output Q to Logic Indicator L0. Follow the input
sequences below and record output states.

2
 Table 1: Truth Table to create the function by using Multiplexer.
D C B A Q
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

4.2 Constructing a 2-to-1 Multiplexer

4.2.1 Procedure

– Block Multiplexer 1 of module SMT-8005 will be used as a 2-to-1

MUX.

Figure 3: 2-to-1 Multiplexer.

• Connect inputs A, B to Data Switches SW0 , SW1 ; selector C to SW2 .

Connect output F3 to Logic Indicator L0 .

• Follow the input sequences in Table 2 and record states of F3 . Which

input (A or B) determines the output?

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 Table 2: Truth Table of 2-to-1 Multiplexer.
B A F3
0 0
0 1
1 0
1 1

4.3 Constructing a 8 to 1 Multiplexer Circuit with TTL

IC
4.3.1 Procedure
• U3 (74LS151) on block Multiplexer 2 of module SMT-8005 will be used
in section of the experiment.

Figure 4: 8 to 1 Multiplexer Circuit with TTL IC.

• Refer to the data sheet specifications of the 74LS151.

– When CBA = 000, data at D0 is send to output F.
– When CBA = 010, data at D2 is send to output F.
– When CBA = 111, data at D7 is send to output F.
– The IC will function properly only when ST ROBE = 0.
– Q will remain 0 when ST ROBE = 1.
• Connect inputs D0 D7 to DIP Switch 1.0 1.7; inputs C, B, A to Data
Switches SW2 , SW1 , SW0 . Follow the input sequences in Table 3, adjust
D0 D7 and record output states. Determine on which input among D0 D7
does Q depend on.

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 Table 3: Truth Table of 8 to 1 Multiplexer Circuit with TTL IC.
C B A F3
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

5 Conclusion
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 Part B

1 Objective
Investigate the operation of De-Multiplexer.

2 Purpose
Having completed this experiment you will be able to:

• Understand the operating principles and construction of de-multiplexer

circuits.

3 Apparatus
• Logic Trainer (SMT-8005)
• Logic Trainer (SMT-800)
• Power Supply

• Connecting wires

4 Theory
A demultiplexer, or DMUX, is basically a logic circuit that is exact opposite
of a multiplexer. DMUX has a single input and multiple outputs. The input
can be connected to any one of the many outputs through the selector terminal.
The DMUX is also referred to as Data Distributor or Data Router. Its pin
assignment diagram is shown in Fig. 1.

When all three selector terminals A, B and C are in low logic state (CBA = 000),
data at input D is send to output number 0. When CBA = 010, the input is
send to output number 2. Collective state of selectors determines the location of
output data. When CBA = 111, data is send to the last output (output number
7). By combining MUX and DMUX, long distance transmission systems can
be set up, increasing the efficiency of transmission lines. Fig. 1 shows a MUX-
DMUX combinational circuit with 16 inputs, 16 outputs with 4 selectors.

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 Figure 1: Multiplexer and De-multiplexer.

4.1 Constructing a 2-output De-multiplexer with Basic

Logic Gates
4.1.1 Procedure
• Block Multiplexer 1 of module SMT-8005 will be used in this section.
Insert connection clip according to Fig. 2. Connect A to Data Switch
SW0 ; to SW3 ; F1 and F2 to Logic Indicators L0 and L1 respectively.

Figure 2: 2-output De-multiplexer with Basic Logic Gates.

• Set C to 0 and change data at input A. Observe how F1 and F2 changes.

Set C to 1, change A and observe how F1 and F2 react to changes of A.

4.2 Constructing a 8-output De-multiplexer with CMOS

IC
4.2.1 Procedure

– U6 (4051) on block De-multiplexer of module SMT-8005 is used in

this section of the experiment.

7
 Figure 3: 8-output De-multiplexer with CMOS IC.

• Connect E to SW0 ; D to SW1 ; A to SW2 ; B to SW3 ; C to SW4 ; outputs

Y0 Y7 to Logic Indicators L0 L7 respectively.
• At D=0, apply the input sequence 1 − 0 − 1 − 0 to the common input E
and observe outputs Y0 Y7 .

– Did the outputs change as the input sequence is applied?

• At D=1, apply the input sequence 1 − 0 − 1 − 0 to the common input E
and observe outputs Y0 Y7 .
– Did the outputs change as the input sequence is applied?

• Which state of D changes the outputs?

• Using the same sequence for E (1 − 0 − 1 − 0), follow the sequence for A,
B and C given in Table 1. Record output states.

Table 1: 8-output De-multiplexer with CMOS IC.

C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

• Reconstruct the circuit by removing the connections done in step 2. Con-

nect Y0 Y7 to SW0 SW7 ; E to L0 ; D to SW8 ; C to SW9 ; B to SW10 ; A to
SW11 .

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 • Change the state of Y0 Y7 from 1 to 0 to 1 (1-0-1) and observe E. Did E
follow changes to Y0 Y7 ?
• Follow the input sequence for C, B, A in Table 3 and observe the relation-
ship between E and Y0 Y7 . Is Table 2 is correct?

Table 2:
C B A E
0 0 0 Y0
0 0 1 Y1
0 1 0 Y2
0 1 1 Y3
1 0 0 Y4
1 0 1 Y5
1 1 0 Y6
1 1 1 Y7

• Does the relationship between E and Y0 Y7 in Table 2 still apply, when D

changes state?

5 Conclusion
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