®

ADS
781
8
ADS7818

For most current data sheet and other product

information, visit www.burr-brown.com

12-Bit High Speed Low Power Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES DESCRIPTION
● 500kHz THROUGHPUT RATE The ADS7818 is a 12-bit sampling analog-to-digital
● 2.5V INTERNAL REFERENCE converter (A/D) complete with sample/hold, internal
2.5V reference, and synchronous serial interface. Typi-
● LOW POWER: 11mW
cal power dissipation is 11mW at a 500kHz through-
● SINGLE SUPPLY +5V OPERATION put rate. The device can be placed into a power down
● DIFFERENTIAL INPUT mode which reduces dissipation to just 2.5mW. The
● SERIAL INTERFACE input range is zero to two times the reference voltage,
and the internal reference can be overdriven by an
● GUARANTEED NO MISSING CODES
external voltage.
● MINI-DIP-8 AND MSOP-8
Low power, small size, and high-speed make the
● UNIPOLAR INPUT RANGE ADS7818 ideal for battery operated systems such as
wireless communication devices, portable multi-chan-
APPLICATIONS nel data loggers, and spectrum analyzers. The serial
interface also provides low-cost isolation for remote
● BATTERY OPERATED SYSTEMS data acquisition. The ADS7818 is available in a plas-
● DIGITAL SIGNAL PROCESSING tic mini-DIP-8 or an MSOP-8 package and is guaran-
● HIGH SPEED DATA ACQUISITION teed over the –40°C to +85°C temperature range.
● WIRELESS COMMUNICATION SYSTEMS

CLK
SAR
CONV

+In
CDAC Serial
–In Interface DATA

S/H Amp Comparator

Buffer Internal
+2.5V Ref

VREF
10kΩ ±30%

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Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®

©
1998 Burr-Brown Corporation 1
PDS-1408B ADS7818
Printed in U.S.A. May, 2000
SBAS078
SPECIFICATIONS
At TA = –40°C to +85°C, +VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, internal reference, unless otherwise specified.

ADS7818P, E ADS7818PB, EB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

ANALOG INPUT
Full-Scale Input Span(1) +In – (–In) 0 5 ✻ ✻ V
Absolute Input Range +In –0.2 VCC +0.2 ✻ ✻ V
–In –0.2 +0.2 ✻ ✻ V
Capacitance 15 ✻ pF
Leakage Current 1 ✻ µA
SYSTEM PERFORMANCE
Resolution 12 ✻ Bits
No Missing Codes 12 ✻ Bits
Integral Linearity Error ±1 ±2 ±0.5 ±1 LSB(2)
Differential Linearity Error ±0.8 ±0.5 ±1 LSB
Offset Error ±2 ±5 ±1 ✻ LSB
Gain Error(3) 25°C ±12 ±30 ±7 ±15 LSB
–40°C to +85°C ±50 ±35 LSB
Common-Mode Rejection DC, 0.2Vp-p 70 ✻ dB
1MHz, 0.2Vp-p 50 ✻ dB
Noise 150 ✻ µVrms
Power Supply Rejection Worst Case ∆, +VCC = 5V ±5% 1.2 ✻ LSB
SAMPLING DYNAMICS
Conversion Time 1.625 ✻ µs
Acquisition Time 0.350 ✻ µs
Throughput Rate 500 ✻ kHz
Aperture Delay 5 ✻ ns
Aperture Jitter 30 ✻ ps
Step Response 350 ✻ ns
DYNAMIC CHARACTERISTICS
Signal-to-Noise Ratio VIN = 5Vp-p at 100kHz 72 ✻ dB
Total Harmonic Distortion(4) VIN = 5Vp-p at 100kHz –78 –72 –82 –75 dB
Signal-to-(Noise+Distortion) VIN = 5Vp-p at 100kHz 68 70 70 72 dB
Spurious Free Dynamic Range VIN = 5Vp-p at 100kHz 72 78 75 82 dB
Usable Bandwidth SINAD > 68dB 350 ✻ kHz
REFERENCE OUTPUT
Voltage IOUT = 0 2.475 2.50 2.525 2.48 ✻ 2.52 V
Source Current(5) Static Load 50 ✻ µA
Drift IOUT = 0 20 ✻ ppm /°C
Line Regulation 4.75V ≤ VCC ≤ 5.25V 0.6 ✻ mV
REFERENCE INPUT
Range 2.0 2.55 ✻ ✻ V
Resistance(6) to Internal Reference Voltage 10 ✻ ✻ ✻ kΩ
DIGITAL INPUT/OUTPUT
Logic Family CMOS ✻
Logic Levels:
VIH |IIH| ≤ +5µA 3.0 VCC +0.3 ✻ ✻ V
VIL |IIL| ≤ +5µA –0.3 0.8 ✻ ✻ V
VOH IOH = –500µA 3.5 ✻ ✻ V
VOL I OL = 500µA 0.4 ✻ ✻ V
Data Format Straight Binary ✻
POWER SUPPLY REQUIREMENT
+VCC Specified Performance 4.75 5.25 ✻ ✻ V
Quiescent Current fSAMPLE = 500kHz 2.2 ✻ mA
Power Down 0.5 ✻ mA
Power Dissipation fSAMPLE = 500kHz 11 20 ✻ ✻ mW
Power Down 2.5 ✻ mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻ ✻ °C

✻ Specifications same as ADS7818P,E.

NOTES: (1) Ideal input span, does not include gain or offset error. (2) LSB means Least Significant Bit, with VREF equal to +2.5V, one LSB is 1.22mV. (3) Measured
relative to an ideal, full-scale input (+In – (–In)) of 4.999V. Thus, gain error includes the error of the internal voltage reference. (4) Calculated on the first nine
harmonics of the input frequency. (5) If the internal reference is required to source current to an external load, the reference voltage will change due to the internal
10kΩ resistor. (6) Can vary ±30%.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

ADS7818 2
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
+VCC to GND ............................................................................ –0.3V to 6V
Analog Inputs to GND .............................................. –0.3V to (VCC + 0.3V) DISCHARGE SENSITIVITY
Digital Inputs to GND ............................................... –0.3V to (VCC + 0.3V)
Power Dissipation .......................................................................... 325mW Electrostatic discharge can cause damage ranging from per-
Maximum Junction Temperature ................................................... +150°C formance degradation to complete device failure. Burr-
Operating Temperature Range ......................................... –40°C to +85°C Brown Corporation recommends that all integrated circuits
Storage Temperature Range .......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C be handled and stored using appropriate ESD protection
methods.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum condi- ESD damage can range from subtle performance degrada-
tions for extended periods may affect device reliability. tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.

PIN CONFIGURATION
Top View

VREF 1 8 +VCC VREF 1 8 +VCC

+In 2 7 CLK +In 2 7 CLK

ADS7818 ADS7818
–In 3 6 DATA –In 3 6 DATA

GND 4 5 CONV GND 4 5 CONV

Plastic Mini-DIP-8 MSOP-8

PIN ASSIGNMENTS
PIN NAME DESCRIPTION
1 VREF Reference Output. Decouple to ground with a 0.1µF ceramic capacitor and a 2.2µF tantalum capacitor.
2 +In Non-Inverting Input.
3 –In Inverting Input. Connect to ground or to remote ground sense point.
4 GND Ground.
5 CONV Convert Input. Controls the sample/hold mode, start of conversion, start of serial data transfer, type of serial transfer, and power
down mode. See the Digital Interface section for more information.
6 DATA Serial Data Output. The 12-bit conversion result is serially transmitted most significant bit first with each bit valid on the rising edge
of CLK. By properly controlling the CONV input, it is possibly to have the data transmitted least significant bit first. See the Digital
Interface section for more information.
7 CLK Clock Input. Synchronizes the serial data transfer and determines conversion speed.
8 +VCC Power Supply. Decouple to ground with a 0.1µF ceramic capacitor and a 10µF tantalum capacitor.

PACKAGE/ORDERING INFORMATION
MAXIMUM MAXIMUM
INTEGRAL DIFFERENTIAL
LINEARITY LINEARITY PACKAGE SPECIFICATION
ERROR ERROR DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT (LSB) (LSB) PACKAGE NUMBER(1) RANGE MARKING(2) NUMBER(3) MEDIA

ADS7818E ±2 N/S(4) MSOP-8 337 –40°C to +85°C A18 ADS7818E/250 Tape and Reel
" " " " " " " ADS7818E/2K5 Tape and Reel
ADS7818EB ±1 ±1 MSOP-8 337 –40°C to +85°C A18 ADS7818EB/250 Tape and Reel
" " " " " " " ADS7818EB/2K5 Tape and Reel
ADS7818P ±2 N/S(4) Plastic DIP-8 006 –40°C to +85°C ADS7818P ADS7818P Rails
ADS7818PB ±1 ±1 " " " ADS7818PB ADS7818PB Rails

NOTE: (1) For detail drawing and dimension table, please see end of data sheet or Package Drawing File on Web. (2) Performance Grade information is marked
on the reel. (3) Models with a slash(/) are available only in Tape and reel in quantities indicated (e.g. /250 indicates 250 units per reel, /2K5 indicates 2500 devices
per reel). Ordering 2500 pieces of ”ADS7818E/2K5“ will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to the
www.burr-brown.com web site under Applications and Tape and Reel Orientation and Dimensions. (4) N/S = Not Specified, typical only. However, 12-Bits no missing
codes is guaranteed over temperature.

3 ADS7818
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified.

CHANGE IN FULL-SCALE ERROR

vs TEMPERATURE CHANGE IN OFFSET vs TEMPERATURE
2 2.0

0 1.6
Delta from 25°C (LSB)

Delta from 25°C (LSB)

–2 1.2

–4 0.8

–6 0.4

–8 0.0

–10 –0.4
–40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100
Temperature (°C) Temperature (°C)

POWER-DOWN SUPPLY CURRENT

vs TEMPERATURE SUPPLY CURRENT vs TEMPERATURE
470 2.3
Power-down Supply Current (µA)

460 2.2
450
Supply Current (mA)

2.1 fSAMPLE = 500kHz

440
2.0
430
1.9
420
1.8 fSAMPLE = 125kHz
410

400 1.7

390 1.6
–40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100
Temperature (°C) Temperature (°C)

CHANGE IN INTEGRAL LINEARITY and

SUPPLY CURRENT vs SAMPLE RATE DIFFERENTIAL LINEARITY vs SAMPLE RATE
2.4 0.4
Delta from fSAMPLE = 500kHz (LSB)

2.3 0.3
Supply Current (mA)

2.2 0.2

2.1 0.1 Change in Integral

Linearity (LSB)
2.0 0.0

1.9 –0.1

1.8 –0.2 Change in Differential

Linearity (LSB)
1.7 –0.3
100 200 300 400 500 600 100 200 300 400 500 600
Sample Rate (kHz) Sample Rate (kHz)

ADS7818 4
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified.

CHANGE IN FULL-SCALE ERROR CHANGE IN OFFSET

vs EXTERNAL REFERENCE VOLTAGE vs EXTERNAL REFERENCE VOLTAGE
0.2 0.5

0.4
0.0
Delta from VREF = 2.5V (mV)

Delta from VREF = 2.5V (mV)

0.3
–0.2
0.2
–0.4 0.1

–0.6 0.0

–0.1
–0.8
–0.2
–1.0
–0.3

–1.2 –0.4
2.0 2.1 2.2 2.3 2.4 2.5 1.9 2.1 2.3 2.5 2.7 2.9 3.1
External Reference Voltage (V) External Reference Voltage (V)

PEAK-TO-PEAK NOISE POWER SUPPLY REJECTION

vs EXTERNAL REFERENCE VOLTAGE vs POWER SUPPLY RIPPLE FREQUENCY
0.70 30

0.65 Power Supply Rejection (mV/V) 25

Peak-to-Peak Noise (LSB)

0.60 20

0.55 15

0.50 10

0.45 5

0
0.40
1 10 100 1k 10k 100k 1M
2.0 2.1 2.2 2.3 2.4 2.5
Power Supply Ripple Frequency (Hz)
External Reference Voltage (LSB)

FREQUENCY SPECTRUM FREQUENCY SPECTRUM

(4096 Point FFT; fIN = 10.9kHz, –0.2dB) (4096 Point FFT; fIN = 102kHz, –0.2dB)
0 0

–20 –20

–40 –40
Amplitude (dB)

Amplitude (dB)

–60 –60

–80 –80

–100 –100

–120 –120
0 62.5 125 187.5 250 0 62.5 125 187.5 250
Frequency (kHz) Frequency (kHz)

5 ADS7818
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified.

SIGNAL-TO-NOISE RATIO and

FREQUENCY SPECTRUM SIGNAL-TO-(NOISE+DISTORTION)
(4096 Point FFT; fIN = 247kHz, –0.2dB) vs INPUT FREQUENCY
0 76

–20 74 SNR

SNR and SINAD (dB)

–40 72
Amplitude (dB)

SINAD
–60 70

–80 68

–100 66

–120 64
0 62.5 125 187.5 250 1k 10k 100k 1M
Frequency (kHz) Input Frequency (Hz)

SPURIOUS FREE DYNAMIC RANGE AND CHANGE IN SIGNAL-TO-NOISE RATIO

TOTAL HARMONIC DISTORTION and SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY vs TEMPERATURE
90 –90 0.3
SFDR

85 –85 0.2
SNR
Delta from +25°C (dB)

THD❉ 0.1
80 –80
SFDR (dB)

THD (dB)

0.0
SINAD
75 –75
–0.1

70 –70 –0.2
❉ First nine harmonics fIN = 100kHz, –0.2dB
of the input frequency
65 –65 –0.3
–40 –20 0 20 40 60 80 100
1k 10k 100k 1M
Temperature (°C)
Input Frequency (Hz)

CHANGE IN SPURIOUS FREE DYNAMIC RANGE

AND TOTAL HARMONIC DISTORTION
vs TEMPERATURE
1.0 –1.0
fIN = 100kHz, –0.2dB
0.5 –0.5
SFDR Delta from +25°C (dB)

THD Delta from +25°C (dB)

0.0 THD❉ 0.0

–0.5 0.5
SFDR
–1.0 1.0

–1.5 ❉ First
1.5
nine harmonics
of the input frequency
–2.0 2.0
–40 –20 0 20 40 60 80 100
Temperature (°C)

ADS7818 6
THEORY OF OPERATION are common to both inputs. Thus, the –IN input is best used
to sense a remote ground point near the source of the +IN
The ADS7818 is a high speed successive approximation signal. If the source driving the +IN signal is nearby, the
register (SAR) analog-to-digital converter (A/D) with an –IN should be connected directly to ground.
internal 2.5V bandgap reference. The architecture is based
The input current into the analog input depends on input
on capacitive redistribution which inherently includes a
voltage and sample rate. Essentially, the current into the
sample/hold function. The converter is fabricated on a 0.6µ
device must charge the internal hold capacitor during the
CMOS process. See Figure 1 for the basic operating circuit
sample period. After this capacitance has been fully charged,
for the ADS7818.
there is no further input current. The source of the analog
The ADS7818 requires an external clock to run the conver- input voltage must be able to charge the input capacitance to
sion process. This clock can vary between 200kHz (12.5Hz a 12-bit settling level within the sample period—which can
throughput) and 8MHz (500kHz throughput). The duty cycle be as little as 350ns in some operating modes. While the
of the clock is unimportant as long as the minimum HIGH converter is in the hold mode or after the sampling capacitor
and LOW times are at least 50ns and the clock period is at has been fully charged, the input impedance of the analog
least 125ns. The minimum clock frequency is set by the input is greater than 1GΩ.
leakage on the capacitors internal to the ADS7818.
Care must be taken regarding the input voltage on the +In
The analog input is provided to two input pins: +IN and –IN. and –IN pins. To maintain the linearity of the converter, the
When a conversion is initiated, the differential input on these +In input should remain within the range of GND – 200mV
pins is sampled on the internal capacitor array. While a to +VCC + 200mV. The –IN input should not drop below
conversion is in progress, both inputs are disconnected from GND – 200mV or exceed GND + 200mV. Outside of these
any internal function. ranges, the converter’s linearity may not meet specifications.
The range of the analog input is set by the voltage on the
VREF pin. With the internal 2.5V reference, the input range
is 0 to 5V. An external reference voltage can be placed on REFERENCE
VREF, overdriving the internal voltage. The range for the The reference voltage on the VREF pin directly sets the full-
external voltage is 2.0V to 2.55V, giving an input voltage scale range of the analog input. The ADS7818 can operate
range of 4.0V to 5.1V. with a reference in the range of 2.0V to 2.55V, for a full-
The digital result of the conversion is provided in a serial scale range of 4.0V to 5.1V.
manner, synchronous to the CLK input. The result is pro- The voltage at the VREF pin is internally buffered and this
vided most significant bit first and represents the result of buffer drives the capacitor DAC portion of the converter.
the conversion currently in progress—there is no pipeline This is important because the buffer greatly reduces the
delay. By properly controlling the CONV and CLK inputs, dynamic load placed on the reference source. However, the
it is possible to obtain the digital result least significant bit voltage at VREF will still contain some noise and glitches
first. from the SAR conversion process. These can be reduced by
carefully bypassing the VREF pin to ground as outlined in the
sections that follow.
ANALOG INPUT
The +IN and –IN input pins allow for a differential input INTERNAL REFERENCE
signal to be captured on the internal hold capacitor when the
The ADS7818 contains an on-board 2.5V reference, result-
converter enters the hold mode. The voltage range on the
ing in a 0V to 5V input range on the analog input. The
–IN input is limited to –0.2V to 0.2V. Because of this, the
specification table gives the various specifications for the
differential input can be used to reject only small signals that

+5V

+ +
2.2µF 0.1µF ADS7818 0.1µF 10µF

1 VREF +VCC 8
0 to 5V
2 +In CLK 7 Serial Clock
Analog Input from
3 –In DATA 6 Serial Data Microcontroller
or DSP
4 GND CONV 5 Convert Start

FIGURE 1. Basic Operation of the ADS7818.

7 ADS7818
internal reference. This reference can be used to supply a
small amount of source current to an external load, but the tCKP
load should be static. Due to the internal 10kΩ resistor, a tCKH tCKL
dynamic load will cause variations in the reference voltage, CLK
and will dramatically affect the conversion result. Note that
even a static load will reduce the internal reference voltage tCKDS
tCKDH
seen at the buffer input. The amount of reduction depends on DATA
the load and the actual value of the internal “10kΩ” resistor.
The value of this resistor can vary by ±30%.
The VREF pin should be bypassed with a 0.1µF capacitor FIGURE 2. Serial Data and Clock Timing.
placed as close as possible to the ADS7818 package. In
addition, a 2.2 µF tantalum capacitor should be used in SYMBOL DESCRIPTION MIN TYP MAX UNITS
parallel with the ceramic capacitor. Placement of this ca- tACQ Acquisition Time 350 ns
pacitor is not as critical. tCONV Conversion Time 1.5 µs
tCKP Clock Period 125 5000 ns
EXTERNAL REFERENCE tCKL Clock LOW 50 ns
tCKH Clock HIGH 50 ns
The internal reference is connected to the VREF pin and to the tCKDH Clock Falling to Current Data 5 15 ns
internal buffer via a 10kΩ series resistor. Thus, the reference Bit No Longer Valid
voltage can easily be overdriven by an external reference tCKDS Clock Falling to Next Data Valid 30 50 ns
voltage. The voltage range for the external voltage is 2.0V tCVL CONV LOW 40 ns
to 2.55V, corresponding to an analog input range of 4.0V to tCVH CONV HIGH 40 ns
5.1V. tCKCH CONV Hold after Clock Falls(1) 10 ns
tCKCS CONV Setup to Clock Falling(1) 10 ns
While the external reference will not source significant tCKDE Clock Falling to DATA Enabled 20 50 ns
current into the VREF pin, it does have to drive the series tCKDD Clock Falling to DATA 70 100 ns
10kΩ resistor that is terminated into the 2.5V internal High Impedance
reference (the exact value of the resistor will vary up to tCKSP Clock Falling to Sample Mode 5 ns
±30% from part to part). In addition, the VREF pin should tCKPD Clock Falling to Power-down Mode 50 ns

still be bypassed to ground with at least a 0.1 µF ceramic tCVHD CONV Falling to Hold Mode 5 ns
(Aperture Delay)
capacitor (placed as close to the ADS7818 as possible). The tCVSP CONV Rising to Sample Mode 5 ns
reference will have to be stable with this capacitive load. tCVPU CONV Rising to Full Power-up 50 ns
Depending on the particular reference and A/D conversion tCVDD CONV Changing State to DATA 70 100 ns
speed, additional bypass capacitance may be required, such High Impedance
as the 2.2µF tantalum capacitor shown in Figure 1. tCVPD CONV Changing State to 50 ns
Power-down Mode
Reasons for choosing an external reference over the internal tDRP CONV Falling to Start of CLK 5 µs
reference vary, but there are two main reasons. One is to (for hold droop < 0.1 LSB)
achieve a given input range. For example, a 2.048V refer- Note: (1) This timing is not required under some situations. See text for more information.
ence provides for a 0V to 4.095V input range—or 1mV per
TABLE I. Timing Specifications (TA = –40°C to +85°C,
LSB. The other is to provide greater stability over tempera-
CLOAD = 30pF).
ture. The internal reference is typically 20ppm/°C which
translates into a full-scale drift of roughly 1 output code for
every 12°C (this does not take into account other sources of The asynchronous nature of CONV to CLK raises some
full-scale drift). If greater stability over temperature is needed, interesting possibilities, but also some design consider-
then an external reference with lower temperature drift will ations. Figure 3 shows that CONV has timing restraints in
be required. relation to CLK (tCKCH and tCKCS). However, if these times
are violated (which could happen if CONV is completely
asynchronous to CLK), the converter will perform a conver-
DIGITAL INTERFACE
sion correctly, but the exact timing of the conversion is
Figure 2 shows the serial data timing and Figure 3 shows the indeterminate. Since the setup and hold time between CONV
basic conversion timing for the ADS7818. The specific and CLK has been violated in this example, the start of
timing numbers are listed in Table I. There are several conversion could vary by one clock cycle. (Note that the
important items in Figure 3 which give the converter addi- start of conversion can be detected by using a pull-up
tional capabilities over typical 8-pin converters. First, the resistor on DATA. When DATA drops out of high-imped-
transition from sample mode to hold mode is synchronous to ance and goes LOW, the conversion has started and that
the falling edge of CONV and is not dependent on CLK. clock cycle is this first of the conversion.)
Second, the CLK input is not required to be continuous
during the sample mode. After the conversion is complete, In addition if CONV is completely asynchronous to CLK
the CLK may be kept LOW or HIGH. and CLK is continuous, then there is possibility that CLK
will transition just prior to CONV going LOW. If this occurs

ADS7818 8
faster than the 10ns indicated by tCKCH, then there is a Figure 4 shows the typical method for placing the A/D into
chance that some digital feedthrough may be coupled onto the power-down mode. If CONV is kept LOW during the
the hold capacitor. This could cause a small offset error for conversion and is LOW at the start of the 13 clock cycle,
that particular conversion. then the device enters the power-down mode. It remains in
Thus, there are two basic ways to operate the ADS7818. this mode until the rising edge of CONV. Note that CONV
CONV can be synchronous to CLK and CLK can be con- must be HIGH for at least tACQ in order to sample the signal
tinuous. This would be the typical situation when interfacing properly as well as to power-up the internal nodes.
the converter to a digital signal processor. The second There are two different methods for clocking the ADS7818.
method involves having CONV asynchronous to CLK and The first involves scaling the CLK input in relation to the
gating the operation of CLK (a non-continuous clock). This conversion rate. For example, an 8MHz input clock and the
method would be more typical of an SPI-like interface on a timing shown in Figure 3 results in a 500kHz conversion
microcontroller. This method would also allow CONV to be rate. Likewise, a 1.6MHz clock would result in a 100kHz
generated by a trigger circuit and to initiate (after some conversion rate. The second method involves keeping the
delay) the start of CLK. These two methods are covered clock input as close to the maximum clock rate as possible
under DSP Interfacing and SPI Interfacing. and starting conversions as needed. This timing is similar to
that shown in Figure 4. As an example, a 50kHz conversion
POWER-DOWN TIMING rate would require 160 clock periods per conversion instead
of the 16 clock periods used at 500kHz.
The conversion timing shown in Figure 3 does not result in
the ADS7818 going into the power-down mode. If the The main distinction between the two is the amount of time
conversion rate of the device is high (approaching 500kHz), that the ADS7818 remains in power down. In the first mode,
then there is very little power that can be saved by using the the converter only remains in power down for a small
power-down mode. However, since the power-down mode number of clock periods (depending on how many clock
incurs no conversion penalty (the very first conversion is periods there are per each conversion). As the conversion
valid), at lower sample rates, significant power can be saved rate scales, the converter always spends the same percentage
by allowing the device to go into power-down mode be- of time in power down. Since less power is drawn by the
tween conversions. digital logic, there is a small decrease in power consump-
tion, but it is very slight. This effect can be seen in the
typical performance curve “Supply Current vs Sample Rate.”

tCVL tCVCK

CONV

tCKCS
tCKCH

CLK 14 15 16 1 2 3 4 11 12 13 14 15 16 1
(1)

tCKDE tCKDD

DATA D11 D10 D9 D2 D1 D0

(MSB) (LSB)

tACQ
tCVHD tCKSP

SAMPLE/HOLD SAMPLE HOLD SAMPLE HOLD

MODE
(2)

tCONV
INTERNAL
CONVERSION IDLE CONVERSION IN PROGRESS IDLE(3)
STATE

NOTES: (1) Clock periods 14 and 15 are shown for clarity, but are not required for proper operation of the ADS7818, provided that the
minimum tACQ time is met. The CLK input may remain HIGH or LOW during this period. (2) The transition from sample mode to hold
mode occurs on the falling edge of CONV. This transition is not dependent on CLK. (3) The device remains fully powered when
operated as shown. If the sample time is longer than 3 clock periods, power consumption can be reduced by allowing the device to
enter a power down mode. See the power down timing for more information.

FIGURE 3. Basic Conversion Timing.

®

9 ADS7818
 CONV

CLK 1 2 3 12 13

D11 D0
DATA (MSB) D10 D1 (LSB)

tCVSP tACQ

SAMPLE/HOLD
SAMPLE HOLD SAMPLE HOLD
MODE
(3)

INTERNAL
CONVERSION IDLE CONVERSION IN PROGRESS IDLE
STATE
tCKPD tCVPU

POWER MODE FULL POWER LOW POWER FULL POWER

(1) (2)

NOTES: (1) The low power mode (“power-down”) is entered when CONV remains LOW during the conversion and is still LOW at the
start of the 13th clock cycle. (2) The low power mode is exited when CONV goes HIGH. (3) When in power-down, the transition from
hold mode to sample mode is initiated by CONV going HIGH.

FIGURE 4. Power-down Timing.

tCVH

CONV

tCKCH

CLK 1 2 3 12 13 14 23 24

tCKCS
tCVDD
D11 D0 D11
DATA (MSB) D10 D1 (LSB) D1 D10 (MSB) LOW...
(1) (2)

SAMPLE/HOLD
MODE SAMPLE HOLD

INTERNAL
CONVERSION IDLE CONVERSION IN PROGRESS IDLE
STATE
tCVPD

POWER MODE FULL POWER LOW POWER

(3)

NOTES: (1) The serial data can be transmitted LSB first by pulling CONV LOW during the 13th clock cycle. (2) After the MSB has been
transmitted, the DATA output pin will remain LOW until CONV goes HIGH. (3) When CONV is taken LOW to initiate the LSB first transfer,
the converter enters the power-down mode.

FIGURE 5. Serial Data “LSB-First” Timing.

In contrast, the second method (clocking at a fixed rate) duces total power consumption by a considerable amount.
means that each conversion takes X clock cycles. As the For example, a 50kHz conversion rate results in roughly
time between conversions get longer, the converter remains 1/10 of the power (minus the reference) that is used at a
in power-down an increasing percentage of time. This re- 500kHz conversion rate.

ADS7818 10
Table II offers a look at the two different modes of operation the conversion will terminate immediately, before all 12-bits
and the difference in power consumption. have been decided. This can be a very useful feature when
a resolution of 12-bits is not needed. An example would be
when the converter is being used to monitor an input voltage
POWER WITH POWER WITH
fSAMPLE CLK = 16 • fSAMPLE CLK = 8MHz until some condition is met. At that time, the full resolution
500kHz 11mW 11mW
of the converter would then be used. Short-cycling the
250kHz 10mW 7mW conversion can result in a faster conversion rate or lower
100kHz 9mW 4mW power dissipation.
There are several very important items shown in Figure 6.
TABLE II. Power Consumption versus CLK Input.
The conversion currently in progress is terminated when
CONV is taken HIGH during the conversion and then taken
LSB FIRST DATA TIMING LOW prior to tCKCH before the start of the 13th clock cycle.
Figure 5 shows a method to transmit the digital result in a Note that if CONV goes LOW during the 13th clock cycle,
least-significant bit (LSB) format. This mode is entered then the LSB first mode will be entered (Figure 5). Also,
when CONV is pulled HIGH during the conversion (before when CONV goes LOW, the DATA output immediately
the end of the 12th clock) and then pulled LOW during the transitions to high impedance. If the output bit that is present
13th clock (when D0, the LSB, is being transmitted). The during that clock period is needed, CONV must not go LOW
next 11 clocks then repeat the serial data, but in an LSB first until the bit has been properly latched into the receiving
format. The converter enters the power-down mode during logic.
the 13th clock and resumes normal operation when CONV
goes HIGH. DATA FORMAT
The ADS7818 output data is in straight binary format as
SHORT-CYCLE TIMING shown in Figure 7. This figure shows the ideal output code
The conversion currently in progress can be “short-cycled” for the given input voltage and does not include the effects
with the technique shown in Figure 6. This term means that of offset, gain, or noise.

(1) tCVL

CONV

tCVH

CLK 1 2 3 4 5 6 7

tCVDD
D11
DATA (MSB) D10 D9 D8 D7 D6

SAMPLE/HOLD
SAMPLE HOLD
MODE

INTERNAL
CONVERSION IDLE CONVERSION IN PROGRESS IDLE
STATE
tCVPD

POWER MODE FULL POWER LOW POWER

NOTE: (1) The conversion currently in progress can be stopped by pulling CONV LOW during the conversion. This must occur at
least tCKCS prior to the start of the 13th clock cycle. The DATA output pin will tri-state and the device will enter the power-down
mode when CONV is pulled LOW.

FIGURE 6. Short-cycle Timing.

11 ADS7818
 microcontrollers form various manufacturers. CONV would
FS = Full-Scale Voltage = 2 • VREF be tied to a general purpose I/O pin (SPI) or to a PCX pin
1 LSB = FS/4096 (QSPI), CLK would be tied to the serial clock, and DATA
would be tied to the serial input data pin such as MISO
1 LSB (master in slave out).
11...111
Note the time tDRP shown in Figure 9. This represents the
11...110
Output Code

maximum amount of time between CONV going LOW and

11...101
the start of the conversion clock. Since CONV going LOW
places the sample and hold in the hold mode and because the
hold capacitor looses charge over time, there is a require-
00...010 ment that time tDRP be met as well as the maximum clock
00...001 period (tCKP).
00...000

0V 4.999V(1) LAYOUT
Input Voltage (V) (2) For optimum performance, care should be taken with the
physical layout of the ADS7818 circuitry. This is particu-
NOTES: (1) For external reference, value is 2 • VREF – 1 LSB. (2) Voltage
at converter input: +IN–(–IN).
larly true if the CLK input is approaching the maximum
input rate.
The basic SAR architecture is sensitive to glitches or sudden
FIGURE 7. Ideal Input Voltages and Output Codes.
changes on the power supply, reference, ground connec-
tions, and digital inputs that occur just prior to latching the
DSP INTERFACING output of the analog comparator. Thus, during any single
Figure 8 shows a timing diagram that might be used with a conversion for an n-bit SAR converter, there are n “win-
typical digital signal processor such as a TI DSP. For the dows” in which large external transient voltages can easily
buffered serial port (BSP) on the TMS320C54X family, affect the conversion result. Such glitches might originate
CONV would tied to BFSX, CLK would be tied to BCLKX, from switching power supplies, nearby digital logic, and
and DATA would be tied to BDR. high power devices. The degree of error in the digital output
depends on the reference voltage, layout, and the exact
timing of the external event. The error can change if the
SPI/QSPI INTERFACING
external event changes in time with respect to the CLK
Figure 9 shows the timing diagram for a typical serial input.
peripheral interface (SPI) or queued serial peripheral inter-
face (QSPI). Such interfaces are found on a number of

CONV

CLK 15 16 1 2 3 12 13 14 15 16 1 2 3 4

D11 D0 D11
DATA (MSB) D10 D1 (LSB) (MSB) D10 D9

FIGURE 8. Typical DSP Interface Timing.

tDRP tACQ

CONV

CLK 1 2 3 4 13 14 15 16 1 2 3

D11 D0 D11
DATA (MSB) D10 D1 (LSB) (MSB)

FIGURE 9. Typical SPI/QSPI Interface Timing.

ADS7818 12
With this in mind, power to the ADS7818 should be clean capacitor. An additional larger capacitor may also be used,
and well bypassed. A 0.1µF ceramic bypass capacitor should if desired. If the reference voltage is external and originates
be placed as close to the device as possible. In addition, a from an op-amp, make sure that it can drive the bypass
1µF to 10µF capacitor is recommended. If needed, an even capacitor or capacitors without oscillation.
larger capacitor and a 5Ω or 10Ω series resistor my be used The GND pin should be connected to a clean ground point.
to lowpass filter a noisy supply. In many cases, this will be the “analog” ground. Avoid
The ADS7818 draws very little current from an external connections which are too near the grounding point of a
reference on average as the reference voltage is internally microcontroller or digital signal processor. If needed, run a
buffered. However, glitches from the conversion process ground trace directly from the converter to the power supply
appear at the VREF input and the reference source must be entry point. The ideal layout will include an analog ground
able to handle this. Whether the reference is internal or plane dedicated to the converter and associated analog
external, the VREF pin should be bypassed with a 0.1µF circuitry.

13 ADS7818
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