Combinational Logic Circuits

Prof. David Márquez Viloria

library IEEE;
use IEEE.STD_LOGIC_1164.all;
Multiplexer
entity mux_4to1 is
port(
A,B,C,D : in STD_LOGIC;
S0,S1: in STD_LOGIC;
Z: out STD_LOGIC
);
end mux_4to1;
architecture bhv of mux_4to1 is
begin
process (A,B,C,D,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
Z <= A;
elsif (S0 ='1' and S1 = '0') then
Z <= B;
elsif (S0 ='0' and S1 = '1') then
Z <= C;
else
Z <= D;
end if;
end process;
end bhv;
 Multiplexer 4x1 4-bits
library IEEE;
use IEEE.STD_LOGIC_1164.all;
ENTITY mux IS
PORT(a : IN std_logic_vector(3 DOWNTO 0);
b : IN std_logic_vector(3 DOWNTO 0);
c : IN std_logic_vector(3 DOWNTO 0);
sel : IN std_logic_vector(1 DOWNTO 0);
salida : OUT std_logic_vector(3 DOWNTO 0));
END mux;
ARCHITECTURE synth OF mux IS
BEGIN
PROCESS (sel, a, b, c) IS
BEGIN
CASE sel IS
WHEN "00" => salida <= (others => '0');
WHEN "01" => salida <= a;
WHEN "10" => salida <= b;
WHEN "11" => salida <= c;
WHEN OTHERS => salida <= (others => '0');
END CASE;
END PROCESS;
END synth;
 Multiplexer 4x1 4-bits
library IEEE;
use IEEE.STD_LOGIC_1164.all;
ENTITY mux IS
PORT(a : IN std_logic_vector(3 DOWNTO 0);
b : IN std_logic_vector(3 DOWNTO 0);
c : IN std_logic_vector(3 DOWNTO 0);
sel : IN std_logic_vector(1 DOWNTO 0);
salida : OUT std_logic_vector(3 DOWNTO 0));
END mux;
ARCHITECTURE synth OF mux IS
BEGIN
PROCESS (sel, a, b, c) IS
BEGIN
CASE sel IS
WHEN "00" => salida <= (others => '0');
WHEN "01" => salida <= a;
WHEN "10" => salida <= b;
WHEN "11" => salida <= c;
WHEN OTHERS => salida <= (others => '0');
END CASE;
END PROCESS;
END synth;
 Structural: Mux 4x1 using Mux 2x1
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
entity mux2_1 is entity mux4_1 is
port(A,B : in STD_LOGIC; port(
A,B,C,D : in STD_LOGIC;
S: in STD_LOGIC;
S0,S1: in STD_LOGIC;
Z: out STD_LOGIC); Z: out STD_LOGIC);
end mux2_1; end mux4_1;
architecture Behavioral of mux2_1 is architecture Behavioral of mux4_1 is
begin component mux2_1
process (A,B,S) is port( A,B : in STD_LOGIC;
begin S: in STD_LOGIC;
if (S ='0') then Z: out STD_LOGIC);
end component;
Z <= A;
signal temp1, temp2: std_logic;
else begin
Z <= B; m1: mux2_1 port map(A,B,S0,temp1);
end if; m2: mux2_1 port map(C,D,S0,temp2);
end process; m3: mux2_1 port map(temp1,temp2,S1,Z);
end Behavioral; end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
DeMultiplexer
entity demux_1to4 is
port(
F : in STD_LOGIC;
S0,S1: in STD_LOGIC;
A,B,C,D: out STD_LOGIC
);
end demux_1to4;
architecture bhv of demux_1to4 is
begin
process (F,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
A <= F;
elsif (S0 ='1' and S1 = '0') then
B <= F;
elsif (S0 ='0' and S1 = '1') then
C <= F;
else
D <= F;
end if;
end process;
end bhv;
 library IEEE;
Encoder use IEEE.STD_LOGIC_1164.all;
entity encoder1 is
port(
library IEEE;
a : in STD_LOGIC_VECTOR(3 downto 0);
use IEEE.STD_LOGIC_1164.all;
b : out STD_LOGIC_VECTOR(1 downto 0)
entity encoder is
);
port(
end encoder1;
a : in STD_LOGIC_VECTOR(3 downto 0);
architecture bhv of encoder1 is
b : out STD_LOGIC_VECTOR(1 downto 0)
begin
);
process(a)
end encoder;
begin
architecture bhv of encoder is
if (a="1000") then
begin
b <= "00";
process(a)
elsif (a="0100") then
begin
b <= "01";
case a is
elsif (a="0010") then
when "1000" => b <= "00";
b <= "10";
when "0100" => b <= "01";
elsif (a="0001") then
when "0010" => b <= "10";
b <= "11";
when "0001" => b <= "11";
else
When others => b <= "ZZ";
b <= "ZZ";
end case;
end if;
end process;
end process;
end bhv;
end bhv;
 library IEEE;
library IEEE;
Decoder use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_1164.all; entity decoder1 is
entity decoder is port(
port( a : in STD_LOGIC_VECTOR(1 downto 0);
a : in STD_LOGIC_VECTOR(1 downto 0); b : out STD_LOGIC_VECTOR(3 downto 0)
b : out STD_LOGIC_VECTOR(3 downto 0) );
); end decoder1;
end decoder; architecture bhv of decoder1 is
architecture bhv of decoder is begin
begin process(a)
process(a) begin
begin if (a="00") then
case a is b <= "0001";
when "00" => b <= "0001"; elsif (a="01") then
when "01" => b <= "0010"; b <= "0010";
when "10" => b <= "0100"; elsif (a="10") then
when "11" => b <= "1000"; b <= "0100";
end case; else
end process; b <= "1000";
end bhv; end if;
end process;
end bhv;
 BCD to 7 Segment Decoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bcd_7seg is
Port ( B0,B1,B2,B3 : in STD_LOGIC;
A,B,C,D,E,F,G : out STD_LOGIC);
end bcd_7seg;
architecture Behavioral of bcd_7seg is
begin
A <= B0 OR B2 OR (B1 AND B3) OR (NOT B1 AND NOT B3);
B <= (NOT B1) OR (NOT B2 AND NOT B3) OR (B2 AND B3);
C <= B1 OR NOT B2 OR B3;
D <= (NOT B1 AND NOT B3) OR (B2 AND NOT B3) OR (B1 AND
NOT B2 AND B3) OR (NOT B1 AND B2) OR B0;
E <= (NOT B1 AND NOT B3) OR (B2 AND NOT B3);
F <= B0 OR (NOT B2 AND NOT B3) OR (B1 AND NOT B2) OR (B1
AND NOT B3);
G <= B0 OR (B1 AND NOT B2) OR ( NOT B1 AND B2) OR (B2 AND
NOT B3);
end Behavioral;
 BCD to 7 Segment Decoder
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY bcd7seg IS
PORT ( bcd :IN std_logic_vector(3 downto 0); -- entrada BCD
segment7 : OUT std_logic_vector(6 downto 0) -- salida 7 bit );
END bcd7seg; --'a' corresponde al MSB y g corresponde al LSB
ARCHITECTURE bcd7seg_arqOF bcd7seg IS BEGIN
WITH (bcd) SELECT
ARCHITECTURE bcd7seg_arq OF bcd7seg IS
segment7<= "1000000" WHEN "0000", -- '0' [gfedcba]="1000000"]
BEGIN PROCESS (bcd)
"1111001" WHEN "0001", -- '1’
BEGIN CASE bcd IS
"0100100“WHEN "0010", -- '2’
WHEN "0000"=>segment7<="1000000"; --'0' [gfedcba]="1000000"]
"0110000" WHEN "0011", -- '3’
WHEN "0001"=>segment7<="1111001"; --'1’
"0011001" WHEN "0100", -- '4’
WHEN "0010"=>segment7<="0100100"; --'2’
"0010010" WHEN "0101", -- '5’
WHEN "0011"=>segment7<="0110000"; --'3’
"0000010" WHEN "0110", -- '6’
WHEN "0100"=>segment7<="0011001"; --’4’
"1111000" WHEN "0111", -- '7’
WHEN "0101"=>segment7<="0010010"; --'5’
"0000000" WHEN "1000", -- '8’
WHEN "0110"=>segment7<="0000010"; --'6’
"0010000" WHEN "1001", -- '9’
WHEN "0111"=>segment7<="1111000"; --'7’
"1111111" WHEN OTHERS; -- Si es cualquier otro núm.
WHEN "1000"=>segment7<="0000000"; --'8’
END bcd7seg_arq;
WHEN "1001"=>segment7<="0010000"; --'9'
WHENOTHERS=>segment7<="1111111";
END CASE; END PROCESS;
END bcd7seg_arq;
 Full Adder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity full_adder_vhdl_code is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end full_adder_vhdl_code;

architecture gate_level of full_adder_vhdl_code is

begin
S <= A XOR B XOR Cin ;
Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;
end gate_level;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
4 Bit Ripple Carry Adder
entity Ripple_Adder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end Ripple_Adder;
architecture Behavioral of Ripple_Adder is
-- Full Adder VHDL Code Component Decalaration
component full_adder_vhdl_code
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;
-- Intermediate Carry declaration
signal c1,c2,c3: STD_LOGIC;
begin
-- Port Mapping Full Adder 4 times
FA1: full_adder_vhdl_code port map( A(0), B(0), Cin, S(0), c1);
FA2: full_adder_vhdl_code port map( A(1), B(1), c1, S(1), c2);
FA3: full_adder_vhdl_code port map( A(2), B(2), c2, S(2), c3);
FA4: full_adder_vhdl_code port map( A(3), B(3), c3, S(3), Cout);
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Tb_Ripple_Adder IS
END Tb_Ripple_Adder;
ARCHITECTURE behavior OF Tb_Ripple_Adder IS
-- Component Declaration for the Unit Under Test (UUT)
4 Bit Ripple Adder Testbench
COMPONENT Ripple_Adder
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
Cin : IN std_logic;
S : OUT std_logic_vector(3 downto 0);
Cout : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal Cin : std_logic := '0';
--Outputs
signal S : std_logic_vector(3 downto 0);
signal Cout : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Ripple_Adder PORT MAP (
A => A,
B => B,
Cin => Cin,
S => S,
Cout => Cout
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
A <= "0110";
B <= "1100";
wait for 100 ns;
A <= "1111";
B <= "1100";
wait for 100 ns;
A <= "0110";
B <= "0111";
wait for 100 ns;
A <= "0110";
B <= "1110";
wait for 100 ns;
A <= "1111";
B <= "1111";
wait;
end process;
END;
Adder using Library – Arith/Unsigned
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY sumador4bits IS
PORT ( a,b :IN std_logic_vector(3 downto 0); -- entradas a sumar
cin : IN std_logic; -- acarreo en la entrada
cout: OUTstd_logic; -- acarreo de salida
suma : OUT std_logic_vector(3 downto 0) --resultado );
END sumador4bits;

ARCHITECTURE sumador4bits_arqof sumador4bits IS

SIGNAL ax,bx,sumax: std_logic_vector(4 downto 0) --Señales de 5 bits
CONSTANT cinx:std_logic_vector(3 downto 0) := "0000";
BEGIN
ax<='0'&a; -- ax(4)<='0’;
ax(3 DOWNTO 0)<=a;
bx<='0'&b; -- bx(4)<='0’;
bx(3 DOWNTO 0)<=b;
sumax <=ax+bx+ (cinx &cin); -- Suma tres objetos de 5 bits
suma <=sumax(3DOWNTO0); -- suma será los 4 LSBs de sumax
cout <=sumax(4); -- cout será el bit más signific. de sumax
END sumador4bits_arq;
 Adder using Library – Numeric
architecture Behavioral of ejemplo_num_lib is

signal Au, Bu: unsigned(3 downto 0) := "0000";

signal Fu: unsigned(7 downto 0) := (others => '0');

begin

library IEEE; Au <= unsigned(A);

use IEEE.STD_LOGIC_1164.ALL; Bu <= unsigned(B);
use IEEE.NUMERIC_STD.ALL; FL <= std_logic_vector(Fu(3 downto 0));
FM <= std_logic_vector(Fu(7 downto 4));
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values process(Au, Bu, S)
begin
entity ejemplo_num_lib is case S is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0); when "00" =>
B : in STD_LOGIC_VECTOR (3 downto 0); Fu(7 downto 5) <= "000";
S : in STD_LOGIC_VECTOR (1 downto 0); Fu(4 downto 0) <= '0'&Au + Bu;
FM, FL : out STD_LOGIC_VECTOR (3 downto 0)); when "01" =>
end ejemplo_num_lib; Fu(7 downto 4) <= "0000";
Fu(3 downto 0) <= Au - Bu;
when "10" => Fu <= Au * Bu;
when others =>
Fu(7 downto 4) <= "0000";
Fu(3 downto 0) <= Au / Bu;
end case;
end process;

end Behavioral;