4X1 MULTIPLEXER

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity mux is Port ( i0 : in std_logic; i1 : in std_logic; i2 : in std_logic; i3 : in std_logic; sel : in std_logic_vector(1 downto 0); z : out std_logic); end mux;

architecture Behavioral of mux is begin process(i0,i1,i2,i3,sel) begin case sel is when "00" => z <= i0; when "01" => z <= i1; when "10" => z <= i2; when others => z <= i3; end case; end process; end Behavioral;

3:8 DECODER
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity decoder is port( input : in std_logic_vector(2 downto 0);

output : out std_logic_vector(7 downto 0) ); end decoder;

architecture Behavioral of decoder is

begin output(0) <= (not input(2)) and (not input(1)) and (not input(0)); output(1) <= (not input(2)) and (not input(1)) and input(0); output(2) <= (not input(2)) and input(1) and (not input(0)); output(3) <= (not input(2)) and input(1) and input(0); output(4) <= input(2) and (not input(1)) and (not input(0)); output(5) <= input(2) and (not input(1)) and input(0); output(6) <= input(2) and input(1) and (not input(0)); output(7) <= input(2) and input(1) and input(0);

end Behavioral;

4-BIT MAGNITUDE COMPARATOR

entity compare is port( num1 : in std_logic_vector(3 downto 0); --input 1 num2 :in std_logic_vector(3 downto 0); --input 2 less : out std_logic; -- indicates first number is small equal : out std_logic; -- both are equal greater :out std_logic -- indicates first number is bigger ); end compare;

architecture Behavioral of compare is begin process(num1,num2) begin if (num1 > num2 ) then less <= '0'; equal <= '0'; greater <= '1'; elsif (num1 < num2) then less <= '1'; equal <= '0'; greater <= '0';

else less <= '0'; equal <= '1'; greater <= '0'; end if; end process; end Behavioral;

HALF ADDER
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity halfadder is Port ( a : in std_logic; b : in std_logic; s : out std_logic; c : out std_logic); end halfadder;

architecture Behavioral of halfadder is

begin s<= a xor b; c <= a and b;

end Behavioral;

FULL ADDER
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity fulladder is Port ( x : in std_logic; y : in std_logic; cin : in std_logic; s : out std_logic; cout : out std_logic); end fulladder;

architecture Behavioral of fulladder is

begin s <= x xor y xor cin ; cout <= (x and y) or (cin and x) or (cin and y) ;

end Behavioral;

BCD ADDER
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity BCD_Adder is port( X3, X2, X1, X0 : in std_logic; Y3, Y2, Y1, Y0 : in std_logic; S3, S2, S1, S0, Cout : out std_logic); end BCD_Adder;

architecture struct of BCD_Adder is

component fulladder is port( X, Y, Cin : in std_logic; s, Cout : out std_logic); end component;

signal C1, C2, C3, C4, C5, C6: std_logic; signal FA1, FA2, FA3 : std_logic; signal andOut1, andOut2, orOut : std_logic;

begin

G_FA0: fulladder port map(X0, Y0, '0', S0, C1); G_FA1: fulladder port map(X1, Y1, C1, FA1, C2);

G_FA2: fulladder port map(X2, Y2, C2, FA2, C3); G_FA3: fulladder port map(X3, Y3, C3, FA3, C4); andOut1<= FA1 and FA3; andOut2<= FA2 and FA3; orOut<= andOut1 or andOut2 or C4; G_FA4: fulladder port map(FA1, orOut, '0', S1, C5); G_FA5: fulladder port map(FA2, orOut, C5, S2, C6); S3<= C6 xor FA3; Cout <= orOut;

end struct;

JK FLIP FLOP
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity jkff is Port ( j : in std_logic; k : in std_logic; q : out std_logic; qb : out std_logic; clk : in std_logic); end jkff;

architecture Behavioral of jkff is signal p:std_logic_vector(1 downto 0); begin process (clk) variable t:std_logic:='0';

begin p(0)<= k; p(1)<= j; if(clk='1' and clk'event) then case p is when "00" => t:= t; when "01" => t:= '0';

when "10" => t:= '1'; when "11" => t:= not t; when others => t:=t; end case; end if; q<=t; qb<= not t; end process; end Behavioral;

T FLIP FLOP
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity tff is Port ( t : in std_logic; clk : in std_logic; q : out std_logic; qb : out std_logic); end tff;

architecture Behavioral of tff is

begin process (clk) variable a: std_logic:='0'; begin if(clk='1' and clk'event) then case t is when '0' => a:=a; when '1' => a:= not a; when others => a:=a; end case; end if; q<=a;

qb<=not a; end process; end Behavioral;

D FLIP FLOP
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity dff2 is Port ( d : in std_logic; clk : in std_logic; reset : in std_logic; q : out std_logic; nq : out std_logic); end dff2;

architecture Behavioral of dff2 is begin process (clk,reset) begin if (reset= '1') then q<='0'; nq<='1'; elsif(clk='1' and clk'event) then q<=d; nq<=not d; end if; end process; end Behavioral;

3 BIT COUNTER
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity tbc is Port ( clk1 : in std_logic; a0 : inout std_logic; a1 : inout std_logic; a2 : inout std_logic); end tbc;

architecture Behavioral of tbc is component tff port( t : in std_logic; clk : in std_logic; q : out std_logic; qb : out std_logic); end component; signal q: std_logic; begin q<=a1 and a0; t2: tff port map(q,clk1,a2,open); t1: tff port map(a0,clk1,a1,open); t0: tff port map('1',clk1,a0,open); end Behavioral;

UP DOWN COUNTER
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity UD_COUNTER1 is port ( CLK,UP : in std_logic; Q : out std_logic_vector(3 downto 0)); end UD_COUNTER1;

architecture Behavioral of UD_COUNTER1 is signal Q_IN : std_logic_vector(3 downto 0):=(others => '0'); begin Q <= Q_IN; process( CLK, UP ) begin if CLK='1' and CLK'event then if UP='1' then Q_IN <= Q_IN + '1'; else Q_IN <= Q_IN - '1'; end if; end if; end process; end Behavioral;

JOHNSON COUNTER
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity johnson_counter is port ( DAT_O : out std_logic_vector(3 downto 0); CLK_I : in std_logic ); end johnson_counter;

architecture Behavioral of johnson_counter is signal temp :std_logic_vector(3 downto 0):=(others => '0'); begin DAT_O <= temp; process(CLK_I) begin if( CLK_I='1' and CLK_I'event ) then temp(1) <= temp(0); temp(2) <= temp(1); temp(3) <= temp(2); temp(0) <= not temp(3); end if; end process; end Behavioral;

SEQUENCE DETECTOR