EECS2070 02

Introduction to SystemVerilog

黃稚存

國立清華大學
Lecture 19
資訊工程學系
l SystemVerilog (SV) is a Hardware Description and
Verification language (HDVL)
l SystemVerilog for RTL is an extension of IEEE 1364
Verilog-2005 standards
u SystemVerilog is the superset of Verilog
u IEEE standard 1800-2017 standard
l SystemVerilog for verification uses extensive object-
oriented programming techniques
u This portion is more closely related to C/C++/Java than
Verilog
u These constructs are generally not synthesizable

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SystemVerilog vs. Verilog

Src: http://www.asicguru.com/system-verilog/tutorial/introduction/1/
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Advantages of SystemVerilog

l More compact code compared to Verilog

l Structures and enumerated types for better
scalability
l Interfaces for higher level of abstraction
l Supported in Vivado synthesis

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HDL vs. Programming Language
l Have syntactically similar constructs:
u Data types, variables, assignments, if statements, loops, ...
l But very different mentality and semantic model: everything
runs in parallel, unless specified otherwise
u Statement model hardware
u Hardware is inherently parallel
l Software programs are composed of subroutines (mostly)
u Subroutines call each other
u when in a callee, the caller’s execution is paused
l Hardware descriptions are composed of modules (mostly)
u A hierarchy of modules connected to each other
u Modules are active at the same time

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New Two-State Integer Types

l New two-state {0, 1} integer types, in addition to Verilog

four-state {0, 1, X, Z} ones
u For-loop variables, testbenches
u For faster simulation
Type Description Example
bit User-defined size bit [3:0] a_nibble;
byte 8 bits, signed byte a, b;
shortint 16 bits, signed shortint c, d;
int 32 bits, signed int i,j;
longint 64 bits, signed longint lword;

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More Data Types
Four-state integer types
Type Description Example
reg User-defined size reg [7:0] a_byte;
Identical to reg in
logic every way, but a logic [7:0] a_byte;
better name
integer 32 bits, signed integer i, j, k;
Non-integer types
Type Description Example
time 64-bit unsigned time now;
shortreal As float in C shortreal f;
real As double in C real g;
realtime Identical to real realtime now;
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Arrays

l Multidimensional array
logic [1:0][2:0] my_register[0:9];
u Packed dimensions are [3:0] and [7:0]
u Unpacked dimension is [0:9]
l Packed dimensions:
u to be laid out contiguously in memory
u can be copied on to any other packed object
u can be sliced ("part-selects")
u are restricted to the "bit" types (bit, logic, int etc.),
some of which (e.g. int) have a fixed size.

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Complex Data Types

l Enumerated data types

typedef enum logic [2:0] {
RED, GREEN, BLUE, CYAN, MAGENTA, YELLOW
} color_t;

color_t my_color = GREEN;

initial $display("The color is %s",
my_color.name());

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Structures and Unions

l C-like structures and unions

u Typedef as in C and C++
u Packed attribute
u Tagged attribute

typedef struct packed {

bit [10:0] expo;
bit sign;
bit [51:0] mant;
} FP;
FP zero = 64'b0;

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 Port Connection
Verilog SystemVerilog
module Design (
input Clock, Reset,
input [7:0] Data, Design DUT ( .Clock, .Reset, .Data, .Q );
output [7:0] Q
); Or even
...
Design DUT ( .* );
module testbench;
reg Clock, Reset;
reg [7:0] Data;
wire [7:0] Q;

Design DUT (
.Clock(Clock), .Reset(Reset),
.Data(Data), .Q(Q)
);

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New Procedural Blocks

l Combinational logic
always_comb begin
tmp = b * b - 4 * a * c;
no_root = (tmp < 0);
end
l Level-sensitive latch
always_latch
if (en) q <= d;
l Synchronous edge-sensitive sequential logic
always_ff @(posedge clk)
count <= count + 1;

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 Interfaces
l Simplifying port-name declarations and enabling the abstraction of groups
of signals
// Interface definition module RAM (Bus MemBus);
interface Bus;
logic [7:0] Addr, Data; logic [7:0] mem[0:255];
logic RWn;
endinterface always @*
// Using the interface if (MemBus.RWn)
module TestRAM; MemBus.Data = mem[MemBus.Addr];
// Instance the interface else
Bus TheBus();
logic[7:0] mem[0:7]; mem[MemBus.Addr] = MemBus.Data;
// Connect it endmodule
RAM TheRAM (.MemBus(TheBus));

initial begin
// Drive and monitor the bus
TheBus.RWn = 0;
TheBus.Addr = 0;
for (int I=0; I<7; I++)
TheBus.Addr = TheBus.Addr + 1;
TheBus.RWn = 1;
TheBus.Data = mem[0];
end
endmodule

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 Interface Ports

interface ClockedBus (input Clk); // Using the interface

logic[7:0] Addr, Data; module Top;
logic RWn; reg Clock;
endinterface
// Instance the interface with an
module RAM (ClockedBus Bus); // input, using named connection
always @(posedge Bus.Clk) ClockedBus TheBus (.Clk(Clock));
if (Bus.RWn) RAM TheRAM (.Bus(TheBus));
Bus.Data = mem[Bus.Addr]; ...
else endmodule
mem[Bus.Addr] = Bus.Data;
endmodule

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 Modports in Interfaces

l Provides direction information

interface MSBus (input Clk); module RAM (MSBus.Slave MemBus);
logic [7:0] Addr, Data; // MemBus.Addr is an input of RAM
logic RWn; endmodule
modport Slave (
input Addr, inout Data
);
endinterface

module TestRAM;
logic Clk;
MSBus TheBus(.Clk(Clk));
RAM TheRAM (.MemBus(TheBus.Slave));
...
endmodule

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 Verification Features

» Not synthesizable
» Assisting in creation of test benches

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New Data Types: string

l Variable-length text
string s1 = "Hello";
string s2 = "world";
string p = ".?!";

// string concatenation
string s3 = {s1, ", ", s2, p[2]};

// simulation will print:

// "[13] Hello, world!”
$display("[%d] %s", s3.len(), s3);

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New Data Types:
dynamic arrays, associative arrays, queues
// # elements for dynamic array
int cmdline_elements;

// dynamic array
int da[];

// associative array, indexed by int

int ai[int];

// associative array, indexed by string

int as[string];

// queue, indexed as an array, or by built-in methods

int qa[$];

initial begin
cmdline_elements = 16;
// Allocate array with 16 elements
da = new[ cmdline_elements ];
end

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Classes
l User-defined data type with data (properties), tasks and functions to access
data (methods)
u Object-oriented: encapsulation, data hiding, inheritance and polymorphism
u For testbench automation
l Abstract base class: virtual
virtual class Memory;
virtual function bit [31:0] read(bit [31:0] addr); endfunction
virtual function void write(bit [31:0] addr, bit [31:0] data); endfunction
endclass

class SRAM #(parameter AWIDTH=10) extends Memory;

bit [31:0] mem [1<<AWIDTH];

virtual function bit [31:0] read(bit [31:0] addr);

return mem[addr];
endfunction
virtual function void write(bit [31:0] addr, bit [31:0] data);
mem[addr] = data;
endfunction
endclass

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Assertions

l Assertions are test constructs

u Automatically validated as design is simulated
u Written for properties that must always be true
l Makes it easier to test designs
u Don’t have to manually check for these conditions

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Example

l Imagine you have a FIFO queue

u When queue is full, it sets status_full to true
u When queue is empty, it sets status_empty to true

l When status_full is true, wr_en must be false

l When status_empty is true, rd_en must be false
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 Assertions for the FIFO

l A procedural statement that checks an

expression when statement is executed

In addition, there is $warning for less severity level,, and $info with
no specific severity
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Concurrent Assertions

l SV also has Concurrent Assertions that are continuously monitored

and can express temporal (sequence) conditions
u Complex but very powerful
p "The Read and Write signals should never be asserted together.”
assert property (!(Read && Write));
p "A Request should be followed by an Acknowledge occurring no more than
two clocks after the Request is asserted.”
assert property (@(posedge Clock) Req |-> ##[1:2] Ack);

u See http://www.doulos.com/knowhow/sysverilog/tutorial/assertions/ for

an introduction

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General Improvement over Verilog (1/3)

l Procedural assignment (<=, =) can operate

directly on arrays
l Ports (inout, input, output) support more data
types: struct, enum, real, and multi-dimensional
types
l For-loop allows automatic variable declaration
inside the for statement
u Loop flow control is improved by the continue and
break statements
l New do/while loop in addition to while loop
l New const for constant variables
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General Improvement over Verilog (2/3)

l Variable initialization can operate on arrays

l Increment and decrement operators are
supported
u x++, ++x, x--, --x
l Compound assignment operators are supported
u x += a, x -= a, x *= a, x /= a, x %= a,
x <<= a, x >>= a, x &= a, x ^= a, x /= a,
x |= a
l Improved `define macro-substitution capabilities
l The fork/join construct has been expanded with
join_none and join_any
l Each source file can have a local timescale
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General Improvement over Verilog (3/3)

l Task ports can now be declared ref

u "pass by reference" in computer programming
l Functions can return void
l Parameters can be declared any type, including
user-defined typedefs
l Coverage can help designers examine all
desired corner and edge cases in the design
space
l Convenient interface to foreign languages (like
C/C++), by SystemVerilog DPI (Direct
Programming Interface).
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Online Materials

l https://www.doulos.com/knowhow/sysverilog/
l http://www.asic-
world.com/systemverilog/index.html

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