VHDL - Introduction: CP323L1: Advance Logic Design

VHDL - Introduction
CP323L1: Advance Logic Design
Introduction
Hardware description languages (HDL)
Language to describe hardware Two popular languages
VHDL: Very High Speed Integrated Circuits Hardware Description Language
Developed by DOD from 1983 IEEE Standard 1076-1987/1993/200x Based on the ADA language
Verilog
IEEE Standard 1364-1995/2001/2005 Based on the C language
2
Introduction
VHDL is a programming language that allows one to model and develop complex digital systems in a dynamic environment.
Object Oriented methodology for you C people can be observed -- modules can be used and reused. Allows you to designate in/out ports (bits) and specify behavior or response of the system.
3
Basic VHDL Concepts

Interfaces -- i.e. ports Behavior Structure Test Benches Analysis, simulation Synthesis
Applications of HDL
Model and document digital systems
Different levels of abstraction
Dataflow , Behavioral, Structural.
Verify design Synthesize circuits

Convert from higher abstraction levels to lower abstraction levels
Modeling the Dataflow way

uses statements that defines the actual flow of data.....
such as, x <= y -- this is NOT less than equal to -- its not C
this assigns the Boolean signal x to the value of Boolean signal y... i.e. x = y this will occur whenever y changes....
Input-Output specification of circuit

Example: my_ckt Inputs: A, B, S Outputs: X, Y VHDL description:
X my_ckt Y
B
S
entity my_ckt is port ( A: in bit; B: in bit; S: in bit; X: out bit; Y: out bit); end my_ckt ;
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VHDL entity
entity my_ckt port ( A: in B: in S: in X: out Port names or Signal names Y: out ); end my_ckt; is bit; bit; bit; bit; bit;
Datatypes: In-built User-defined
Name of the Name of the circuit circuit User-defined User-defined as circuit name Filename same Example. Filename same as circuit name Circuit name: my_ckt recommendedmy_ckt.vhd Filename: A Example: Circuit name: my_ckt Filename: my_ckt.vhd
X Y
B S
my_ckt
Direction of port 3 main types: in: Input out: Output inout: Bidirectional
Note the absence of semicolon ; at the end of the last signal and the presence at the end of the closing bracket
8
Modeling the Behavior way

Architecture body describes an implementation of an entity may be several per entity Behavioral architecture describes the algorithm performed by the module contains process statements, each containing
sequential statements, including signal assignment statements and wait statements
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Modeling the Behavior way

architecture behav of reg4 is begin sensitivity list process (d0, d1, d2, d3, en, clk) variable stored_d0, stored_d1, stored_d2, stored_d3 : bit; begin if en = '1' and clk = '1' then notice := syntax used for equating values stored_d0 := d0; from signals... stored_d1 := d1; stored_d2 := d2; stored_d3 := d3; end if; q0 <= stored_d0 after 5 ns; simulates real-world q1 <= stored_d1 after 5 ns; propagation delays. q2 <= stored_d2 after 5 ns; q3 <= stored_d3 after 5 ns; end process; end behav;
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VHDL syntax to know..

Omit entity at end of entity declaration Omit architecture at end of architecture body Omit is in process statement header
entity reg4 is port ( d0, d1, d2 : in bit d3, en, clk : in bit; q0, q1, q2, q3 : out bit ); end reg4;
architecture behav of reg4 is begin process (d0, ... ) ... begin ... end process ; end behav;
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Modeling the Structural way

Structural architecture implements the module as a composition of subsystems contains
signal declarations, for internal interconnections the entity ports are also treated as signals component instances instances of previously declared entity/architecture pairs port maps in component instances connect signals to component ports
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d0
bit0 d_latch d q clk bit1 d_latch d q clk bit2 d_latch d q clk bit3 d_latch d q gate and2 a y b clk int_clk
q0
d1
q1
d2
q2
d3
q3
en clk
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Structural way
First declare D-latch and and-gate entities and architecturesnotice semicolon placements -- odd as it is, omit from last statement
entity d_latch is port ( d, clk : in bit; q : out bit ); end entity d_latch; architecture basic of d_latch is begin process (clk, d) begin if clk = 1 then q <= d after 2 ns; end if; end process; end basic; entity and2 is port ( a, b : in bit; y : out bit ); end entity and2; architecture basic of and2 is begin process (a, b) begin y <= a and b after 2 ns; end process ; end basic;
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Structural way
Declare corresponding components in register architecture body
architecture struct of reg4 is component d_latch port ( d, clk : in bit; q : out bit ); end component; component and2 port ( a, b : in bit; y : out bit ); end component; signal int_clk : bit; ...
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Structural way
Now use them to implement the register
... begin bit0 : d_latch port map ( d0, int_clk, q0 ); bit1 : d_latch port map ( d1, int_clk, q1 ); bit2 : d_latch port map ( d2, int_clk, q2 ); bit3 : d_latch port map ( d3, int_clk, q3 ); gate : and2 port map ( en, clk, int_clk ); end struct;
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Signals vs Variables
Variables Variables do not have notion of events Variables can be defined and used only inside the process block and some other special blocks. Variable declaration and assignment example:
process () Variables can only variable K : bit; be defined and used inside the process begin construct and can -- Assign the value of signal defined only K be L to var. in immediately this place K := L; end process;
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Simulation
Simulation is modeling the output response of a circuit to given input stimuli For our example circuit: Given the values of A, B and S
A X my_ckt Y
Determine the values of X and Y Event driven simulator is used popularly Simulation tool we shall use: ModelSim
B
S
Many types of simulators used
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Simulation
architecture behav_seq of my_ckt is signal Xtmp: bit; begin p1: process (A,B,S,Xtmp) variable XtmpVar: bit; begin if (S=0) then Xtmp <= A; else Xtmp <= B; end if;
Time T 00 0+d 0+2d 1
A U 0 0 0 0
B U 1 1 1 1
S U 0 0 0 1
Xtmp X X 0 0 0
Y X X 0 1 1
XtmpVar X X 0 0 0
X X X X 0 0
1+d
0
0
1
1
1
1
1
1
0
0
0
0
0
1
if ((Xtmp = 0) and (S = 0)) then 1+2d Y <= 1; else Y <= 0; Scheduled events Scheduled events end if; X <= Xtmp; XtmpVar := Xtmp; end process p1; end;
executed: list: Xtmp = 0= (0,0+d) Xtmp Y =Y0= (0,0+d) 1 X =XX(X,0+d) 0=
Scheduled events Assignments executed: list: XtmpVar = X (empty) Xtmp = (0,0+2d) Y = (1,0+2d) X = (0,0+2d)
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Assignments executed: ELEC2200-002 Lecture 7 XtmpVar = 0

(updated)
Synthesis
Synthesis: Conversion of behavioral level description to structural level netlist
Structural level netlist
Abstract behavioral description maps to concrete logic-level implementation For ex. Integers at behavioral level mapped to bits at structural level Implementation of behavioral description Describes interconnection of gates
Synthesis tool we shall use: Leonardo Spectrum
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VHDL - Introduction

CP323L1: Advance Logic Design

Basic VHDL Concepts

Verify design Synthesize circuits

Modeling the Dataflow way

Input-Output specification of circuit

Datatypes: In-built User-defined

Modeling the Behavior way

Modeling the Behavior way

VHDL syntax to know..

Modeling the Structural way

Many types of simulators used

Time T 00 0+d 0+2d 1

executed: list: Xtmp = 0= (0,0+d) Xtmp Y =Y0= (0,0+d) 1 X =XX(X,0+d) 0=

Assignments executed: ELEC2200-002 Lecture 7 XtmpVar = 0

Structural level netlist

Synthesis tool we shall use: Leonardo Spectrum

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