NT7603

Single-Chip 16C X 2L Dot-Matrix LCD Controller / Driver

Features
! Internal LCD drivers ! Character Generator ROM (CG ROM):
16 common signal drivers 2 kinds of CG ROM sizes:
80 segment signal drivers 192 characters:
! Maximum display dimensions 160 5 X 8 dot patterns
16 characters X 2 lines or 32 5 X 10 dot patterns
32 characters X 1 line 240 characters:
! Interfaces with 4-bit or 8-bit MPU 192 5 X 8 dot patterns
! Versatile display functions provided on chip: 48 5 X 10 dot patterns
Display Clear, Cursor Home, Display ON/OFF, Custom CG ROM is also available
Cursor ON/OFF, Character Blinking, Cursor ! Built-in power-on reset function
Shift, and Display Shift ! Logic power supply: 2.8V ~ 5.5V
! Three duty factors, selected by PROGRAM: ! LCD driver power supply: V1 ~ V5
1/8, 1/11, and 1/16 (VDD + 0.3 - VDD - 7.0), divided by Built-in LCD power
! Displays Data RAM (DD RAM): 80 X 8 bits division resister.
(Displays up to 80 characters) ! Two oscillator operations
! Character Generator RAM (CG RAM): (Freq. = 500KHz - 540KHz):
64 X 8 bits for general data, • Built-in RC oscillation
8 5 X 8 programmable dot patterns, or • External clock
4 5 X 10 programmable dot patterns ! CMOS Process
! Low voltage reset ! Available in COG FORM
! ITO option for A-type and B-type LCD waveform

General Description
The NT7603 is a dot matrix LCD controller and driver LSI The NT7603 also contains Character Generator RAM where
that can operate with either a 4-bit or an 8-bit the user can store 8 different character patterns at run time.
microprocessor (MPU). The NT7603 receives control These memory features make the character display flexible.
character codes from the MPU, stores them in an internal NT7603 also provides many display instructions to achieve
RAM (up to 80 characters) before transforming each versatile LCD display functions. The NT7603 is fabricated on
character code into a 5 X 7, 5 X 8, or 5 X 10 dot matrix a single LSI chip using the CMOS process, resulting in very
character pattern and then displaying the codes on the LCD low power requirements.
panel. The built-in Character Generator ROM consists of
256 different character patterns.

1 V2.3
 NT7603
Pad Configuration
149 84
150 83

166 67
1 66

Size
Item Pad No. Unit
X Y
Chip size - 5156 1349
µm
Pad pitch 1 - 166 70

2 V2.3
 NT7603
Block Diagram

V1
V2
V3 OPT_R0
V4 OPT_R1
V5 OPT_LCD

VDD INSTRUCTION
GND DECODE TEST
8
OSC1 TIMING
7 TESTM
OSC2 GENERATOR

8 INSTRUCTION LCD DRIVER

ADDRESS
REGISTER VOLTAGE
COUNTER 7
(IR) GENERATOR
RS

7 7
R/W 7
7
DISPLAY
E CURSOR DATA 16-BIT 16 COMMON 16 COM1
ADDRESS RAM SHIFT SIGNAL I
COUNTER (DD RAM) REGISTER DRIVER COM16
80 X 8 BITS
I/O
BUFFER 8

DATA CURSOR
8 REGISTER /BLINK
DB7 ~ DB4
(DR) 8 7 8 CONTROLLER
4

DB3 ~ DB0
CHARACTER
4 GENERATOR CHARACTER 80-BIT 80 SEGMENT SEG1
80
BUSY RAM GENERATOR LATCH SIGNAL I
FLAG (CG RAM) ROM (CG ROM) CIRCUIT DRIVER SEG80
(BF) 64 X 8 BITS

5 5

PARALLER - TO - SERIAL TESTD

CONVERTER

3 V2.3
 NT7603
Pad Description (Total 166 pads for COG type)

External
Pad No. Designation I/O Description
Connection

1 - 15 GND P Power supply GND: 0V

16 OSC1 I For external clock operation, clock inputs to OSC1
17 OSC2 O Clock output
18 V1 P Power supply Power supply for LCD driver. VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 ≥ GND
19 V2 P Power supply Power supply for LCD driver
20 V3 P Power supply Power supply for LCD driver
21 V4 P Power supply Power supply for LCD driver
22 - 25 V5 P Power supply Power supply for LCD driver
The built-in bias resister select:
OPT_R0, OPT_R1, OPT_R0: No ITO = 1. ITO on = 0
26, 28 I ITO Option
OPT_R1 1, 1: 2.2KΩ; 1, 0: 4KΩ;
0, 1: 6.8KΩ; 0, 0:No built-in bias resistor
29 - 43 VDD P Power supply VDD: +5V
Register select signal
44, 45 RS I MPU 0: Instruction register (write), Busy flag, address counter (read)
1: Data register (write, read)
Read/Write control signal
46, 47 R/W I MPU 0: Write 1: Read
48, 49 E I MPU Read/Write start signal
50, 51 DB0
52, 53 DB1 Lower 4 tri-state bi-directional data bus for transmitting data
I/O MPU
54, 55 DB2 between MPU and NT7603. Not used during 4-bit operation.

56, 57 DB3
58, 59 DB4
60, 61 DB5 Higher 4 tri-state bi-directional data bus for transmitting data
I/O MPU
62, 63 DB6 between MPU and NT7603. DB7 is also used as a busy flag.

64, 65 DB7
No ITO. (Option = 1): B-Type waveform
66 OPT_LCD I ITO Option
ITO On. (Option = 0): A-Type waveform
68 TESTD O Test output Test data output. (No connect for user)
164 - 157 COM1 - 8 O LCD panel Common signal output pins, for place on the upper glass
(IC face up)
69 - 76, COM9 - 16 O LCD panel
156 - 77 SEG1 - 80 O LCD panel Segment signal output pins
165 TEST I Test pin Test pin (internal pull down) (No connection for user)
166 TESTM O Test output LCD driver clock output. (No connection for user)
67, 27 GND_OUT P GND output pin, used for pull-down ITO option

4 V2.3
 NT7603
Functional Description
The NT7603 is a dot-matrix LCD controller and driver LSI. It 1. 192 Characters:
operates with either a 4-bit or an 8-bit microprocessor The CG ROM contains 160 5 X 8 dot character patterns and
(MPU). The NT7603 receives both instructions and data 32 5 X 10 dot character patterns. The relation between the
from the MPU. Some instructions set operation modes, such character codes and character patterns is shown in Table 1.
as the function mode, data entry mode, and display mode; The character codes from 00H to 0FH are used to get
as well as some control LCD display functions, such as clear character patterns from the CG RAM. Character codes from
display, restore display, shift display, and cursor. Other 10H to 1FH, from 80H to 9FH and 20H map to null character
instructions include reading and writing both data and patterns. Character codes from E0H to FFH are assigned to
addresses. All instructions allow users convenient and generate 5 X 10 dot character patterns, and other codes are
powerful functions to control the LCD dot-matrix displays. used to generate 5x8 dot character patterns.
Data is written into, and read from the Data Display RAM 2. 240 Characters:
(DD RAM) or the Character Generator RAM (CG RAM). As The CG ROM contains 192 5 X 8 dot character patterns and
display character codes, the data stored in the DD RAM 48 5 X 10 dot character patterns. The relation between the
decodes a set of dot-matrix character patterns that are built character codes and character patterns is shown in Table 2.
into the Character Generator ROM (CG ROM). The CG The character codes from 00H to 0FH are used to get
ROM, with many character patterns (up to 256 patterns), character patterns from the CG RAM. Character codes from
defines the character pattern fonts. The NT7603 regularly 10H to 1FH and from E0H to FFH are assigned to generate 5
scans the character patterns through the segment drivers. X 10 dot character patterns, and other codes to generate 5 X
The CG RAM stores character pattern fonts at run time if 8 dot character patterns. Only one null character pattern
users intend to show character patterns that are not defined exists in this type. Note that the underlined cursor, displayed
in the CG ROM. This feature makes character display on the 8th duty may be obscure if the 8th row of a dot
flexible. Other unused bytes can be used as character pattern is coded. We recommend that users
general-purpose data storage. display the cursor in the blinking mode if they code 5x8 dot
character patterns as their custom CG ROM.
The LCD driver circuit consists of 16 common signal drivers
and 80 segment signal drivers allowing a variety of Custom character patterns are available by
application configurations to be implemented. mask-programming ROM. For convenience of character
pattern development, NOVATEK has developed a
user-friendly editor program for the NT7603 to help
determine the character patterns users prefer. By executing
Character Generator ROM (CG ROM) the program on the computer, users can easily create and
modify their character patterns. By transferring the resulting
The character generator ROM generates LCD dot character files generated by the program through a modem or some
patterns from the 8-bit character pattern codes. The NT7603 other communication method, the user and NOVATEK will
provides 2 CG ROM configurations: have established a reliable, fast link for programming the CG
ROM.

5 V2.3
 NT7603
Absolute Maximum Ratings* *Comments
Power Supply Voltage (VDD) . . . . . . . . . . -0.3V to + 7.0V Stresses above those listed under "Absolute Maximum
Power Supply Voltage (V1 to V5) . . . . . . . . . . . . . . . . . . Ratings" may cause permanent damage to this device.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VDD + 0.3V These are stress ratings only. Functional operation of this
Input Voltage (VI) . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V device at these or any other conditions above those
Operating Temperature (TOPR) . . . . . . .-20°C to + 70°C indicated in the operational sections of this specification is
Storage Temperature (TSTG) . . . . . . . .-55°C to + 125°C not implied or intended. Exposure to the absolute maximum
rating conditions for extended periods may affect device
reliability.

! All voltage values are referenced to GND = 0V

! V1 to V5, must maintain VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 ≥ GND

DC Electrical Characteristics (VDD = 5.0V, GND = 0V, TA = 25°C)

Symbo
Parameter Min. Typ. Max. Unit Conditions Applicable Pin
l

VDD Operating Voltage 2.8 5.0 5.5 V

DB0 - DB7, RS,
VIH1 "H" Level Input Voltage (1) 0.8 VDD - VDD V
R/W,
VIL1 "L" Level Input Voltage (1) -0.3 - 0.2 VDD V E,OSC1
VOH1 "H" Level Output Voltage (1) VDD - 0.6 - - V IOH = -1.2mA DB0 - DB7
VOL1 "L" Level Output Voltage (1) - - GND + 0.6 V IOL = 1.2mA (CMOS)
VCOM Driver Voltage Descending (COM) - - 0.3 V ID = 5µA COM1 - 16
VSEG Driver Voltage Descending (SEG) - - 0.3 V ID = 5µA SEG1 - 80
Not include
IIL Input Leakage Current -1 - 1 µA VIN = 0 to VDD
OSC1
RS, R/W,
-IP Pull-up MOS Current 50 125 250 µA VDD = 5V
DB0-DB7
Rf oscillation,
from external
clock VDD = 5V,
IOP Power Supply Current - 1 1.5 mA fOSC = fCP = VDD
540KHz,
include LCD
bias current.
External Clock Operation
fCP External Clock Operating Frequency 380 540 750 KHz
tDUTY External Clock Duty Cycle 45 50 55 %
tRCP External Clock Rising Time 0.1 - 0.5 µS
tFCP External Clock Falling Time 0.1 - 0.5 µS
Internal Clock Operation (Built-in RC Oscillator)
fOSC Oscillator Frequency 380 540 750 KHz VDD = 2 .8V ~ 5.5V
VLCD LCD Driving Voltage 3.0 - VDD V VDD - V5

6 V2.3
 NT7603
DC Electrical Characteristics (continued) (VDD = 3.0V, GND = 0V, TA = 25°C)

Symbol Parameter Min. Typ. Max. Unit Conditions Applicable Pin

VDD Operating Voltage 2.8 3.0 5.5 V

DB0 - DB7, RS,
VIH1 "H" Level Input Voltage (1) 0.8 VDD - VDD V
R/W,
VIL1 "L" Level Input Voltage (1) -0.3 - 0.2 VDD V E,OSC1
VOH1 "H" Level Output Voltage (1) VDD - 0.4 - - V IOH = -0.8mA DB0 - DB7
VOL1 "L" Level Output Voltage (1) - - GND + 0.4 V IOL = 0.8mA (CMOS)
VCOM Driver Voltage Descending (COM) - - 0.3 V ID = 5µA COM1 - 16
VSEG Driver Voltage Descending (SEG) - - 0.3 V ID = 5µA SEG1 - 80
Not include
IIL Input Leakage Current -1 - 1 µA VIN = 0 to VDD
OSC1
RS, R/W,
-IP Pull-up MOS Current 30 75 150 µA VDD = 3V
DB0-DB7
Rf oscillation,
from external
clock VDD =
3.0V,
IOP Power Supply Current - 1 1.5 mA VDD
fOSC = fCP =
540KHz,
include LCD
bias current.
External Clock Operation
External Clock Operating
fCP 380 540 750 KHz
Frequency
tDUTY External Clock Duty Cycle 45 50 55 %
tRCP External Clock Rising Time 0.1 - 0.5 µS
tFCP External Clock Falling Time 0.1 - 0.5 µS
Internal Clock Operation (Built-in RC Oscillator)
Rf = 50KΩ (reference only)
fOSC Oscillator Frequency 380 540 750 KHz
VDD = 2 .8V ~ 5.5V
VLCD LCD Driving Voltage 2.5 - VDD V VDD - V5

7 V2.3
 NT7603
AC Characteristics
Read Cycle (VDD = 5.0V, GND = 0V, TA = 25°C)

Symbol Parameter Min. Typ. Max. Unit Conditions

tCYCE Enable Cycle Time 500 - - ns Figure 1

tWHE Enable "H" Level Pulse Width 300 - - ns Figure 1

tRE, tFE Enable Rising/Falling Time - - 25 ns Figure 1

1
tAS RS, R/W Setup Time 60 - - ns Figure 1
2
100

tAH RS, R/W Address Hold Time 10 - - ns Figure 1

tRD Read Data Output Delay - - 190 ns Figure 1

tDHR Read Data Hold Time 20 - - ns Figure 1

Write Cycle (VDD = 5.0V, GND = 0V, TA = 25°C)

Symbol Parameter Min. Typ. Max. Unit Conditions

tCYCE Enable Cycle Time 500 - - ns Figure 2

tWHE Enable "H" Level Pulse Width 300 - - ns Figure 2

tRE, tFE Enable Rising/Falling Time - - 25 ns Figure 2

1
tAS RS, R/W Setup Time 60 - - ns Figure 2
2
100

tAH RS, R/W Address Hold Time 10 - - ns Figure 2

tDS Data Output Delay 100 - - ns Figure 2

tDHW Data Hold Time 10 - - ns Figure 2

Notes: 1: 8-bit operation mode

2: 4-bit operation mode

Power Supply Conditions Using Internal Reset Circuit

(VDD = 5.0V, GND = 0V, TA = 25°C)

Symbol Parameter Min. Typ. Max. Unit Conditions

tRON Power Supply Rising Time 0.1 - 10 ms Figure 3

tOFF Power Supply OFF Time 1 - - ms Figure 3

8 V2.3
 NT7603
AC Characteristics (continued)
Read Cycle (VDD = 3.0V, GND = 0V, TA = 25°C)

Symbol Parameter Min. Typ. Max. Unit Conditions

tCYCE Enable Cycle Time 500 - - ns Figure 1

tWHE Enable "H" Level Pulse Width 300 - - ns Figure 1

tRE, tFE Enable Rising/Falling Time - - 25 ns Figure 1

1
tAS RS, R/W Setup Time 60 - - ns Figure 1
2
100

tAH RS, R/W Address Hold Time 10 - - ns Figure 1

tRD Read Data Output Delay - - 190 ns Figure 1

tDHR Read Data Hold Time 20 - - ns Figure 1

Write Cycle (VDD = 3.0V, GND = 0V, TA = 25°C)

Symbol Parameter Min. Typ. Max. Unit Conditions

tCYCE Enable Cycle Time 500 - - ns Figure 2

tWHE Enable "H" Level Pulse Width 300 - - ns Figure 2

tRE, tFE Enable Rising/Falling Time - - 25 ns Figure 2

1
tAS RS, R/W Setup Time 60 - - ns Figure 2
2
100

tAH RS, R/W Address Hold Time 10 - - ns Figure 2

tDS Data Output Delay 150 - - ns Figure 2

tDHW Data Hold Time 10 - - ns Figure 2

Notes: 1: 8-bit operation mode

2: 4-bit operation mode

Power Supply Conditions Using Internal Reset Circuit

(VDD = 3.0V, GND = 0V, TA = 25°C)

Symbol Parameter Min. Typ. Max. Unit Conditions

tRON Power Supply Rising Time 0.1 - 10 ms Figure 3

tOFF Power Supply OFF Time 1 - - ms Figure 3

9 V2.3
 NT7603
Timing Waveforms
Read Operation

VIH1 VIH1
RS
VIL1 VIL1
tAS tAH

R/W tWHE
tFE
VIH1
E VIL1
tRE VIL1 VIL1
tRD tDHR

VOH1 VOH1
DB0 ~ DB7 VOL1 VAILD DATA
VOL1
tCYCE

Figure 1. Bus Read Operation Sequence

(Reading out data from NT7603 to 8-bit MPU)
Write Operation

VIH1 VIH1
RS
VIL1 VIL1
tAS
tAH
R/W
VIL1
tWHE
VIH1 tFE
E VIL1
tRE VIL1 VIL1
tDS tDHW

VIH1 VIH1
DB0 ~ DB7 VIL1 VAILD DATA
VIL1
tCYCE

Figure 2. Bus Write Operation Sequence

(Writing data from 8-bit MPU to NT7603)

Interface Signals with Segment Driver LSI

4.5V

0.2V 0.2V 0.2V

VDD
0.1ms > tRON > 10ms tOFF > 1ms
tRON tOFF

Figure 3. tOFF stipulates the time of power OFF for instantaneous

Power supply to or when power supply repeats ON and OFF

10 V2.3
 NT7603
Note 1: The NT7603 has two clock options:
A. Internal Oscillator (Built-in RC)

OSC1 OSC2

OPEN OPEN

B. External Clock Operation

OSC1 OSC2

PULSE INPUT
OPEN

Note 2: Input/Output Terminals:

A. Input Terminal
Applicable Terminal: E (No Pull Up MOS)

VDD

PMOS

NMOS

Applicable Terminal: RS, R/W (with Pull Up MOS)

VDD VDD
Pull Up MOS
PMOS PMOS

NMOS

11 V2.3
 NT7603
B. Output Terminal
Applicable Terminal: TESTM

VDD

PMOS

NMOS

C I/O Terminal

Applicable Terminal: DB0 to DB7

VDD VDD
Pull Up MOS
PMOS PMOS
VDD
ENABLE

PMOS

NMOS

DATA
NMOS
(OUTPUT CIRCUIT)
(TRISTATE)

Note 3: ITO Options:

Set Option = 0: Place ITO on the Option Pad
Set Option = 1: No ITO on the Option Pad
No ITO: ITO On:

GND OUTPUT
GND OUTPUT OPTION PAD PAD OPTION PAD
PAD

OPTION OPTION
GND_OUT (Internal GND_OUT (Internal
pull up) pull up)

ITO

Option = 1 Option = 0

12 V2.3
 NT7603
Table 1. NT7603H-BDT01 Correspondence between Character Codes and Character Patterns
(NOVATEK Standard 192 Character CG ROM)

13 V2.3
 NT7603
Instruction Set
Execution
Code Function time (max)
Instruction
(fOSC =
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 540KHz)
Clear entire display area,
Restore display from shift, and
Display Clear 0 0 0 0 0 0 0 0 0 1 1.64ms
load address counter with DD
RAM address 00H.
Restore display from shift and
Display/
0 0 0 0 0 0 0 0 1 * load address counter with DD 1.64ms
Cursor Home
RAM address 00H.
Specify direction of cursor
movement and display shift
Entry Mode
0 0 0 0 0 0 0 1 I/D S mode. This operation takes 40µs
Set
place after each data transfer
(read/write).
Specify activation of display
Display (D) cursor (C) and blinking of
0 0 0 0 0 0 1 D C B 40µs
ON/OFF character at cursor position
(B).
Display/
0 0 0 0 0 1 S/C R/L * * Shift display or move cursor. 40µs
Cursor Shift
Set interface data length (DL),
Function Set 0 0 0 0 1 DL N F * * number of display line (N), and 40µs
character font (F).
Load the address counter with
RAM a CG RAM address.
0 0 0 1 ACG Subsequent data access is for 40µs
Address Set
CG RAM data.
Load the address counter with
DD RAM a DD RAM address.
0 0 1 ADD Subsequent data access is for 40µs
Address Set
DD RAM data.
Busy Flag/
Address Read Busy Flag (BF) and
Counter 0 1 BF AC contents of Address Counter 1µs
Read (AC).
CG RAM/
DD RAM 1 0 Write data Write data to CG RAM or DD
40µs
Data Write RAM.
CG RAM/
DD RAM 1 1 Read data Read data from CG RAM or
40µs
Data Read DD RAM.
I/D = 1 : Increment I/D = 0 : Decrement
S = 1 : Display Shift On
DD RAM : Display Data RAM
D = 1 : Display On
C = 1 : Cursor Display On
CG RAM : Character Generator
B = 1 : Cursor Blink On
RAM
S/C = 1 : Shift Display S/C = 0 : Move Cursor
ACG : Character Generator
R/L = 1 : Shift Right R/L = 0 : Shift Left
RAM Address
DL = 1 : 8-Bit DL = 0 : 4-Bit
ADD : Display Data RAM
N = 1 : Dual Line N = 0 : Signal Line
Address
F = 1 : 5x10 dots F = 0 : 5 X 8 dots
AC : Address Counter
BF = 1 : Internal Operation
BF = 0 : Ready for Instruction

Note 1: Symbol "*" signifies an insignificant bit (disregard).

Note 2: Correct input value for "N" is predetermined for each model.
Note 3: The variation of execution time depends on the change of oscillator frequency; for example:
if fOSC = 380KHz, then execution time = 40µs× (540KHz / 380KHz) = 57µs

14 V2.3
 NT7603
Interface to LCD
(1) Character Font and Number of Lines
The NT7603 provides a 5 X 7 dot character font 1-line mode, Three types of common signals are available as displayed in
a 5 X 10 dot character font 1-line mode and a the table. The number of lines and the font type can be
5 X 7 dot character font 2-line mode, as shown in the table selected by the program.
below.

Number of Lines Character Font Number of Common Signals Duty Factor Bias

1 5 X 7 dots + Cursor 8 1/8 1/4

(or 5 X 8 dots)

1 5 X 10 dots + Cursor 11 1/11 1/4

2 5 X 7 dots + Cursor 16 1/16 1/5

(or 5 X 8 dots)

(2) Connection to LCD

The following 4 LCD connection examples show the various combinations between characters and lines.
NT7603 can directly drive the following combinations:
(a) 5 X 8 Font - 16 character X 1 line (1/8 duty cycle, 1/4 bias)

LCD PANEL

COM1

COM8

SEG1

NT7603

SEG80

15 V2.3
 NT7603
(b) 5 X 10 Font - 16 character X 1 line (1/11 duty cycle, 1/4 bias)

LCD PANEL

COM1

COM8

NT7603
SEG1

SEG80
COM11
COM9

(c) 5 X 8 Font - 16 character X 2 line (1/16 duty cycle, 1/5 bias)

LCD PANEL

COM1

COM8

NT7603

SEG1

SEG80

COM16

COM9

16 V2.3
 NT7603
(d) 5 X 8 Font - 32 character X 1 line (1/16 duty cycle, 1/5bias)

LCD PANEL

COM1

COM8

SEG1

NT7603

SEG80
COM16

COM9

(3) Orientation type of NT7603:

Place the chip on the upper glass (IC face up)

C1, S1

C8, S1 LCD PANEL

C9, S80

C16, S80
NT7603
1

17 V2.3
 NT7603
(4) Bias Power Connection
NT7603 provides 1/4 or 1/5 bias for various duty cycle applications. The built-in power division resistor divide voltage is
described in the following table. The division resistor is the connection of the NT7603, power supply, and resistors are also
shown as follows:

Power Division 1/8, 1/11 Duty Cycle - 1/4 Bias 1/16 Duty Cycle - 1/5 Bias

V1 VDD - 1/4 VLCD VDD - 1/5 VLCD

V2 VDD - 1/2 VLCD VDD - 2/5 VLCD

V3 VDD - 1/2 VLCD VDD - 3/5 VLCD

V4 VDD - 3/4 VLCD VDD - 4/5 VLCD

V5 VDD - VLCD VDD - VLCD

The bias is auto selected by duty cycle. When the LCD is set to 1/16 duty, the bias is set to 1/5. Otherwise, the bias is set to 1/4.
The ITO Option can then select the division resistor value:
VDD
VDD
OPT_R1 OPT_R0 Division Resister
V1
No ITO (1) No ITO (1) 2.2KΩ
V2 VLCD
No ITO (1) ITO On (0) 4KΩ NT7603 Built-in bias resister
V3
2.2K,4K or 6.8K ohm.
ITO On (0) No ITO (1) 6.8KΩ V4

V5
No built-in resister
ITO On (0) No ITO (0)
(external input) VR
GND

VDD VDD
VDD VDD
R R
V1 V1
R R
V2 V2
VLCD R VLCD
NT7603 NT7603
V3 V3
R R

V4 V4
R R
V5 V5

VR VR
GND GND

Exit Power division. (The resistance value depends on the LCD panel size)

18 V2.3
 NT7603
(4) LCD Waveform
A-type, 1/8 Duty Cycle, 1/4 Bias
800 CLOCKS
COM1 1 2 3 4 5 8 1 2

VDD

V1

V2 (V3)

V4

V5

1 Frame

1 sec 1
1 Frame = × 800 × 8 = 11 .9ms Frame Frequency = = 84 .3Hz
540K 11 .9ms

A-type, 1/11 Duty Cycle, 1/4 Bias

800 CLOCKS
COM1 1 2 3 4 5 11 1 2

VDD

V1

V2 (V3)

V4

V5

1 Frame

1 sec 1
1 Frame = × 800 × 11 = 16.3ms Frame Frequency = = 61.4Hz
540K 16.3ms

A-type, 1/16 Duty Cycle, 1/5 Bias

400 CLOCKS
COM1 1 2 3 4 5 16 1 2

VDD

V1

V2

V3

V4

V5

1 Frame

1 sec 1
1 Frame = × 400 × 16 = 11.9ms Frame Frequency = = 84.3Hz
540K 11.9ms

19 V2.3
 NT7603
B-type, 1/8 Duty Cycle, 1/4 Bias

800 CLOCKS
COM1 1 2 3 4 5 6 7 8 9 16 1 2

VDD

V1

V2 (V3)

V4

V5

1 Frame

1sec 1
1 Frame = × 800 × 8 = 11.9ms Frame Frequency = = 84.3Hz
540K 11.9ms

B-type, 1/11 Duty Cycle, 1/4 Bias

800 CLOCKS
COM1 1 2 3 4 5 6 7 8 9 10 11 12 21 22 1 2

VDD

V1

V2 (V3)

V4

V5

1 Frame

1sec 1
1Frame = × 800 × 11 = 16.3ms Frame Frequency = = 61.4Hz
540K 16.3ms

B-type, 1/16 Duty Cycle, 1/5 Bias

400 CLOCKS
COM1 1 2 3 4 5 13 14 15 16 17 31 32 1 2

VDD

V1

V2

V3

V4

V5

1 Frame

1sec 1
1Frame = × 400 ×16 = 11.9ms Frame Frequency = = 84.3Hz
540K 11.9ms

20 V2.3
 NT7603
Low Voltage Reset
The Low voltage reset function is used to monitor the supply voltage and applies an internal reset at the time when low voltage
is detected.
Functions of the Low Voltage Reset Circuit
The Low voltage reset circuit has the following functions:
# Generates an internal reset signal when VDD ≤ VLVR
# Cancels the internal reset signal when VDD > VLVR
Here, VDD: power supply voltage, VLVR: Low voltage reset detect voltage, about 2.0V.

Application Circuit (for reference only)

VDD

COM1 ~ 16 LCD PANEL

NT7603

SEG1 ~ 80

DB0 ~ 7

MPU

E, R/W, RS

V5
VR GND

21 V2.3
 NT7603
Example (for reference only)
Interface with 8-bit MPU (read status)

RS

R/W

Internal
Internal operation
signal

NO
DB7 DATA BUSY DATA
BUSY BUSY

Instruction Busy flag check Instruction

Interface with 4-bit MPU (read status)

RS

R/W

Internal
Internal operation
signal

NO
DB7 D7 D3 AC3 BUSY AC3 BUSY D7 D3

Instruction Busy flag check Instruction

22 V2.3
 NT7603
Interface with 8-bit MPU (read data)

RS

R/W

DB7~DB0 D7~D0 D7~D0 D7~D0 D7~D0

Write Data Read Data Write Instruction

Interface with 4-bit MPU (read data)

RS

R/W

DB7~DB4 D7~D4 D3~D0 D7~D4 D3~D0 D7~D4 D3~D0 D7~D4 D3~D0

Write Data Read Data Write Instruction

23 V2.3
 NT7603
Initializing by instruction
1. 8-bit interface

Power On

Wait for more than 30 ms

after VDD on

0 1-line mode
Function set N
1 2-line mode
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 1 1 N F X X 0 5 x 7 dots
F
1 5 x 10 dots

Wait for more than 40 µs

0 display off
D
1 display on
Display ON/OFF Control
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 cursor off
C
0 0 0 0 0 0 1 D C B 1 cursor on

0 blink off
B
Wait for more than 40 µs 1 blink on

Clear Display
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 1

Wait for more than 1.64ms

0 decrement mode
Entry Mode Set I/D
1 increment mode
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 1 I/D S 0 entire shift off
S
1 entire shift on

Initialization end

Write date to DDRAM: Write N

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 0 0 1 0 0 1 1 1 0

..........

24 V2.3
 NT7603
2. 4-bit interface

Power On

Wait for more than 30 ms

after VDD on

Function set 0 1-line mode

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 N
1 2-line mode
0 0 0 0 1 0 X X X X
0 0 0 0 1 0 X X X X 0 5 x 7 dots
F
0 0 N F X X X X X X 1 5 x 10 dots

Wait for more than 40 µs

0 display off
D
Display ON/OFF Control 1 display on

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 cursor off
0 0 0 0 0 0 X X X X C
1 cursor on
0 0 1 D C B X X X X
0 blink off
B
1 blink on
Wait for more than 40 µs

Clear Display
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 X X X X
0 0 0 0 0 1 X X X X

Wait for more than 1.64ms

Entry Mode Set 0 decrement mode

I/D
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 increment mode

0 0 0 0 0 0 X X X X 0 entire shift off

0 0 0 0 I/D S X X X X S
1 entire shift on

Initialization end

Write date to DDRAM: Write N

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 0 0 1 0 0 X X X X
1 0 1 1 1 0 X X X X

..........

25 V2.3
 NT7603
Ordering Information

Part No. CG ROM Package Shipment Style

NT7603H-BDB01 192 CGROM (ref P13) COG CHIP FORM Bumped Die on Blue tape

NT7603H-BDT01 192 CGROM (ref P13) COG CHIP FORM Bumped Die on chip Tray

NT7603-BDW01 192 CGROM (ref P13) COG CHIP FORM Bumped Die on Wafer

26 V2.3
 NT7603
Pad Configuration of NT7603 Unit: µm
1220 X 5010 µm
2
Chip Window:

A2
A1
A1
N N
B1 B1
150 M 149 B3 M 83
N 84

L M
B4
Y
r r

L
L

B2

0,0 X

L
M
1 N 66
166
B3
67 B
B1
1
C1
C2 C1
C2

A1 230 C1 66
A2 5010 C2 511.55
B1 50 r 35
B2 1220 M 42
B3 70 N 90
B4 500.2 L 70

PAD Location

NO. PAD NAME X Y NO. PAD NAME X Y

1 GND -2275 -540 13 GND -1435 -540
2 GND -2205 -540 14 GND -1365 -540
3 GND -2135 -540 15 GND -1295 -540
4 GND -2065 -540 16 OSC1 -1225 -540
5 GND -1995 -540 17 OSC2 -1155 -540
6 GND -1925 -540 18 V1 -1085 -540
7 GND -1855 -540 19 V2 -1015 -540
8 GND -1785 -540 20 V3 -945 -540
9 GND -1715 -540 21 V4 -875 -540
10 GND -1645 -540 22 V5 -805 -540
11 GND -1575 -540 23 V5 -735 -540
12 GND -1505 -540 24 V5 -665 -540

27 V2.3
 NT7603

NO. PAD NAME X Y NO. PAD NAME X Y

21 V4 -875 -540 67 GND 2439 -560
22 V5 -805 -540 68 TESTD 2439 -490
23 V5 -735 -540 69 COM[9] 2439 -420
24 V5 -665 -540 70 COM[10] 2439 -350
25 V5 -595 -540 71 COM[11] 2439 -280
26 OPT_R0 -525 -540 72 COM[12] 2439 -210
27 GND -455 -540 73 COM[13] 2439 -140
28 OPT_R1 -385 -540 74 COM[14] 2439 -70
29 VDD -315 -540 75 COM[15] 2439 0
30 VDD -245 -540 76 COM[16] 2439 70
31 VDD -175 -540 77 SEG[80] 2439 140
32 VDD -105 -540 78 SEG[79] 2439 210
33 VDD -35 -540 79 SEG[78] 2439 280
34 VDD 35 -540 80 SEG[77] 2439 350
35 VDD 105 -540 81 SEG[76] 2439 420
36 VDD 175 -540 82 SEG[75] 2439 490
37 VDD 245 -540 83 SEG[74] 2439 560
38 VDD 315 -540 84 SEG[73] 2275 540
39 VDD 385 -540 85 SEG[72] 2205 540
40 VDD 455 -540 86 SEG[71] 2135 540
41 VDD 525 -540 87 SEG[70] 2065 540
42 VDD 595 -540 88 SEG[69] 1995 540
43 VDD 665 -540 89 SEG[68] 1925 540
44 RS 735 -540 90 SEG[67] 1855 540
45 RS 805 -540 91 SEG[66] 1785 540
46 RW 875 -540 92 SEG[65] 1715 540
47 RW 945 -540 93 SEG[64] 1645 540
48 E 1015 -540 94 SEG[63] 1575 540
49 E 1085 -540 95 SEG[62] 1505 540
50 DB[0] 1155 -540 96 SEG[61] 1435 540
51 DB[0] 1225 -540 97 SEG[60] 1365 540
52 DB[1] 1295 -540 98 SEG[59] 1295 540
53 DB[1] 1365 -540 99 SEG[58] 1225 540
54 DB[2] 1435 -540 100 SEG[57] 1155 540
55 DB[2] 1505 -540 101 SEG[56] 1085 540
56 DB[3] 1575 -540 102 SEG[55] 1015 540
57 DB[3] 1645 -540 103 SEG[54] 945 540
58 DB[4] 1715 -540 104 SEG[53] 875 540
59 DB[4] 1785 -540 105 SEG[52] 805 540
60 DB[5] 1855 -540 106 SEG[51] 735 540
61 DB[5] 1925 -540 107 SEG[50] 665 540
62 DB[6] 1995 -540 108 SEG[49] 595 540
63 DB[6] 2065 -540 109 SEG[48] 525 540
64 DB[7] 2135 -540 110 SEG[47] 455 540
65 DB[7] 2205 -540 111 SEG[46] 385 540
66 OPT_LCD 2275 -540 112 SEG[45] 315 540

28 V2.3
 NT7603

NO. PAD NAME X Y NO. PAD NAME X Y

113 SEG[44] 245 540 141 SEG[16] -1715 540
114 SEG[43] 175 540 142 SEG[15] -1785 540
115 SEG[42] 105 540 143 SEG[14] -1855 540
116 SEG[41] 35 540 144 SEG[13] -1925 540
117 SEG[40] -35 540 145 SEG[12] -1995 540
118 SEG[39] -105 540 146 SEG[11] -2065 540
119 SEG[38] -175 540 147 SEG[10] -2135 540
120 SEG[37] -245 540 148 SEG[9] -2205 540
121 SEG[36] -315 540 149 SEG[8] -2275 540
122 SEG[35] -385 540 150 SEG[7] -2439 560
123 SEG[34] -455 540 151 SEG[6] -2439 490
124 SEG[33] -525 540 152 SEG[5] -2439 420
125 SEG[32] -595 540 153 SEG[4] -2439 350
126 SEG[31] -665 540 154 SEG[3] -2439 280
127 SEG[30] -735 540 155 SEG[2] -2439 210
128 SEG[29] -805 540 156 SEG[1] -2439 140
129 SEG[28] -875 540 157 COM[8] -2439 70
130 SEG[27] -945 540 158 COM[7] -2439 0
131 SEG[26] -1015 540 159 COM[6] -2439 -70
132 SEG[25] -1085 540 160 COM[5] -2439 -140
133 SEG[24] -1155 540 161 COM[4] -2439 -210
134 SEG[23] -1225 540 162 COM[3] -2439 -280
135 SEG[22] -1295 540 163 COM[2] -2439 -350
136 SEG[21] -1365 540 164 COM[1] -2439 -420
137 SEG[20] -1435 540 165 TEST -2439 -490
138 SEG[19] -1505 540 166 TESTM -2439 -560
139 SEG[18] -1575 540 ALK_L -1993.45 109.8
140 SEG[17] -1645 540 ALK_R 1993.45 109.8

29 V2.3
 NT7603
Tray Information
Y

e
f

H20-210*60-34

SECTION Y-Y
X X

W1
W2

T
d

7*20
g
Y

h
W1
W2
a b
e g

f T

SECTION X-X

Tray Outline Dimensions unit: mm

Symbol Dimensions in mm Symbol Dimensions in mm

a 5.33 g 0.85
b 5.93 h 4.05
c 1.52 W1 50.70
d 2.12 W2 45.50
e 1.75 T 45.75
f 1.45

30 V2.3
 NT7603
Product Spec. Change Notice

NT7603 Specification Revision History

Version Content Date

Modify 4-bits Interface check busy sequence (page 22) (Document

2.3 mistake corrected) Juy.2003
Adding 8-bits and 4-bits interface read data sequence (page 23)

Adding Note 3 and modified fosc from 270KHz to 540KHz

(Page 14, Document mistake corrected)
2.2 Modify the number of clock in single duty from 400 to 800 (1/8 duty Jun.2002
and 1/11 duty),200 to 400(1/16 duty) and fosc from 270K to
540K(Page 21) ( Document mistake corrected)
ROM Table deleted(Page 14)
2.1 B-type waveform content modified(Page 20 , Document mistake Apr.2002
corrected)
2.0 Nov.2001

1.0 Original Feb.2001

31 V2.3