ISSN (Print) : 0974-6846

Indian Journal of Science and Technology, Vol 10 (3), DOI: 10.17485/ijst/2017/v10i3/109413, January 2017 ISSN (Online) : 0974-5645

Design and Implementation of FPGA based 64-bit

MAC Unit using VEDIC Multiplier and Reversible
Logic Gates
P. SivaNagendra Reddy* and M. Saraswathi
Department of ECE, Kuppam Engineering College, Kuppam - 517425, Andhra Pradesh, India;
snreddy715@gmail.com, m.saraswathi448@gmail.com

Abstract
Now a days in VLSI technology size, power, and speed are the main constraints to design any circuits. In normal multipliers
delay will be more and the number of computations also will be more. Because of that speed of the circuits designed with
the normal multipliers will be low and it will consume more power. This paper describes Multiply and Accumulate Unit us-
ing Vedic Multiplier and DKG reversible logic gates. The Vedic multiplier is designed by using UrdhavaTriyagbhayam sutra
and the adder design is done by using reversible logic to perform high speed operations. Reversible logic gates are also the
essentialconstraint for the promising field of Quantum computing. The UrdhavaTriyagbhayam multiplier is used for the
multiplication function to reduce partial products in the multiplication process and to get high concert and less area.The
reversible logic is used to get less power. The MAC is designed using Verilog code, simulation, synthesis is done in both RTL
compiler using Xilinx and implemented on Spartan 3e FPGA Board.

Keywords: MAC, Reversible Gates, Vedic Multiplier

1.  Introduction speed operations. The design of adder elements deter-

mines performance of the system. We have Serial adders.
Multiplication Multiplier design is the most important Parallel adders, Carry Select Adders, Carry Save Adders,
factor in the design of Multiply accumulate unit. In digi- Ripple carry adders and Reversible adders.
tal signal processing applications multipliers plays major In many Digital Signal Applications Multiplier block
role in many applications ling FFT, DFT and convolution consumes more power and occupies large area. Area and
applications. In such cases the number of computations power consumptions also depends on the number of
performed also very important. Why because If the num- computations of the design of multiplier block and adder
ber of computations increases the delay also increases. block13.
So that the speed of processor reduced. In VLSI multipli-
ers can be designed in many ways. By using logic gates
2.  Literature Review
or by using transmission gates or by using multiplexers
we can design multipliers. We have booth’s Multipliers, Nareshnaik, SivaNagendra Reddy proposed “Design of
Array multipliers, Baugh Wooley Multipliers and Vedic Vedic Multiplier for Digital Signal Processing Applications”1.
Multipliers1. In this method design of adders is difficult and design may
One the most important factor in the MAC design is be complex and also its require more power.
Adder. Adders are key elements in the design of multipli- Anitha, Kumar proposed “A 32 BIT MAC Unit Design
ers. Such that high speed adders requires to perform high Using Vedic Multiplier and Reversible Logic Gate” design.

*Author for correspondence

 Design and Implementation of FPGA based 64-bit MAC Unit using VEDIC Multiplier and Reversible Logic Gates

In this paper they designed for 32-bit Multiplier. But most

of the multipliers used in Digital signal processing appli-
cations 64-bit multipliers.
So many researchers proposed many methods to
design multipliers and adders. Among all the methods
multiplier design with reversible logic gate design is the
efficient method. In reversible gates also different revers-
ible gate are available4.Some researchers used Kogge stone
Adders, some researchers used Toffiligates5.DKG is the one
of the gate used in the MAC design. This proposed method
represents 64-bit MAC design using reversible logic gates.

3.  Proposed Method

MAC (Multiply Accumulate) uses both Adders and mul-
tipliers and from both the result is accumulated .MAC is
used in so many applications like DSP advanced micro- Figure 1.  64 bit multiply accumulator architecture.
processors and so many logic functional units. this
particular block in processors is one of the major impor- In most cases the delay in the architecture is due to the
tant factor to determine the speed which uses efficient addition in parallel stages which we have to concentrate
FFT/IFFT algorithms. in general, these two techniques more to improve the speed. Finally, we are going to com-
use most of the time addition and multiplication which pare our Vedic MAC unit with the Conventional MAC
are building blocks in operating faster. Delay in proces- unit based on the parameters like Speed, area and power
sors is due to irregular structure of the adders. this is one consumption2.
factor we need to consider for improving the speed. A multiplying block function can be conceded in three
A multiplication operation in processors is done gen- different ways: conventional addition, Partial Product
erally in three different factors.1.Addition 2.Intermediate Addition (PPA) and finally Partial Product Generation
product addition.3.Final result generation. Our proposed (PPG). The two bud vase materials that must be consid-
design uses of one of the most efficient multiplier i.e. vedic ered are raising the speed of MAC which is accumulator
multiplier and reversible logic gate and it can be done in two block partial and product reduction7, 8
stages. in the initial stage we will replace the normal multi-
plier with vedic multiplier using one of the old multiplication 4.1  Vedic Multiplier
technique which is known as urdhava tiryakabhyamsutra. Vedic Mathematics is part of four Vedas (books of wisdom).
speed is primarily determined by the multiplication block It is part of Sthapatya- Veda (book on civil engineer-
which later will effect on area, power consumption and dis- ing and architecture), which is an upa-veda (supplement)
sipation to avoid these we will go for one of the efficient of Atharva Veda. Vedic Mathematics existed in ancient
multiplication operation in DSP Processors. The later part India and was revived by a popular mathematician, Sri
is reversible logicgate system in which the information lost Bharati Krishna Tirthaji. He divided Vedic mathemat-
was determined by the kT*log2where k is the Boltzmann’s ics into ­sixteen formulae (sutras). Those are Chalana
constant and T is the absolute temperature at which com- Kalanabyham,Gunakasamuchyah,NikhilamNavatashcaramam
putation operation is done. Dashatah, ParaavartyaYojayet, (Anurupye) Shunyamanyat,
Shunyam Saamyasamuccaye, Ekanyunena Purvena,
4.  Design of MAC Architecture Vyashtisamanstih, Puranapuranabyham, Shesanyankena
Charamena, EkadhikinaPurvena, Yaavadunam,
The design of MAC architecture consists Design of Sopaantyadvayamantyam, Sankalanavyavakalanabhyam,
Accumulator which integrates both multiplier and adder Gunitasamuchyah and Urdhva-tiryakbhyam.
stages, Design of 64 X 64-bit Vedic Multiplier and Design of These formulae deal with Algebra, Analytical
128 bit DKG adder of three sub designs is shown in figure 1. Geometry, Algebra, Trigonometry, Geometry etc.

2 Vol 10 (3) | January 2017 | www.indjst.org Indian Journal of Science and Technology
 P. SivaNagendra Reddy and M. Saraswathi

The ease in the Vedic mathematics sutras covers way

for its application in several prominent domains of
engineering like Signal Processing, VLSI andControl
Engineering.

4.2  UrdhwaTiryakbhyam Algorithm

Let us consider two eight bit numbers X(7:0) and Y(7:0) ,
where 7 signify Most Significant Bit and 0 represent
Least Significant Bit. P0 to P15 signify each bit of the
final computed product. It can be seen from equation (1)
to (15), that P0 to P15 are calculated by adding partial
products, which are calculated previously using the AND
­operation.
The individual bits attained from equation (1) to Graphically exemplifies the step by step procedure
equation (15), in turn when concatenated produce the of multiplying two eight bit signals using the Urdhwa
final product of multiplication which is represented in Tiryakbyam Vedic Multiplication Sutra20. The black encir-
equation (16).The carry bits produced during the com- cles state the bits of the multiplier and multiplicand, and
putation of the individual bits of the final product are the two-way arrows specify the bits to be multiplied in
corresponded from C(1) to C(30). The carry bits pro- order to arrive at the individual bits of the final product.
duced in equation (14) and equation (15) are ignored The architecture of the 8x8 Urdhwa Tiryakbyam vedic-
while they are redundant13-15. multiplier is shown in Figure 2. Design of 32 X 32 and
64 X 64-bit Vedic Multiplier and Design of 128 bit DKG
adder designs is shown in figure 3 and 4.

5. Design of Adder using

Reversible Logic DKG Gate
Reversible logic is a distinct method diverse from other
logic. Loss of information is not probable here. In this

Figure 2.  Pictorial illustration of UrdhwaTiryakbhyam Sutra

Vol 10 (3) | January 2017 | www.indjst.org Indian Journal of Science and Technology 3
 Design and Implementation of FPGA based 64-bit MAC Unit using VEDIC Multiplier and Reversible Logic Gates

Figure 5a.  DKG gate.

Figure 3.  32 ×32 vedic multiplier using 16 × 16 vedic

multiplier.
Figure 5b.  Parallel adder using DKG gate.

Figure 6a.  RTL schematic of MAC unit.

Figure 4.  64× 64 vedic multiplier using 32x32vedic
multiplier.

logic, the numbers of output signals are identical to the

number of input signals.
A Boolean function is reversible if and only if all the
values in the input signal set can be mapped with a single
value in the output position. Landauer and Bennet both
demonstrated that the usage of conventional irreversible
circuits will construct us to power dissipation a circuit
consisting of only reversible gates does not dissipate
power. The following points necessity be reserved in mind
to realize an optimized circuit:
• Loops are not authorized
• Minimum delay Figure 6b.  RTL schematic of MAC unit.

4 Vol 10 (3) | January 2017 | www.indjst.org Indian Journal of Science and Technology
 P. SivaNagendra Reddy and M. Saraswathi

Figure 6c.  Technology schematic of64 X 64 MAC

• Zero energy dissipation

• Fan-out is not authorized
• Garbage outputs must be small
• Lowest quantum cost

5.1  DKG Gate

A 4 X 4 reversible DKG gate that preserve work singly as a
reversible full adder and parallel adder is shown in below
Figure 521. If input A is zero, the DKG gate performed Full
adder operation, and if input A is 1 then reversible logic
gate performed Full subtractor operation10,19.

5.2  Accumulator Stage

Accumulator is also one of the most important block in Figure 7.  Synthesis report of 64-bit MAC using Vedic
MAC design. In this method the result of the multiplier Multiplier using RCA,DKG and KSA Reversible logic gates.

Vol 10 (3) | January 2017 | www.indjst.org Indian Journal of Science and Technology 5
 Design and Implementation of FPGA based 64-bit MAC Unit using VEDIC Multiplier and Reversible Logic Gates

6.  Results and Discussion

The modified 64-bit multiplier using Vedic multiplier and
DKG adder is fast and design of MAC done using Xilinx.
This design is implemented in Verilog code using Xilinx.
The below Figure 6(a) and 6(b) shows the RTL Schematic
of the proposed design.
Figure 6(c) shows 64 X 64-bit MAC unit design using
Vedic Multiplier and DKG gates.
Figure 7 shows comparison between MAC design unit
using different Adders. The number of LUTs and utiliza-
tion of logic blocks in MAC design using CSA, RCA, KSA
will be greater than DKG and speed is also more in MAC
design using DKG. But it will take more area.
Compare to array multipliers, baugh wooley multipli-
ers and booths multipliers Vedic multipliers requires less
area and performs operations at high speed.
Figure 8 shows the statistics results of MAC design
Vedic Multiplier with different adders. In which DKG
Adders has moderate delay. But it consumes very less
power and it can be designed in small area.
Table 1 describes the number of adders and multipli-
ers requires in different approaches.

Table 1.  Comparison of no of additions and

multiplications required in various multipliers

Figure 8.  Delay Analysis report of 64-bit MAC using vedic

multiplier using RCA,DKG and KSA reversible logic gates.

is stored in accumulator.64 X 64 multiplier gives result of

128-bit output. Sometimes if carry generated it will give
129 bit output. So 129-bit accumulator designed to store
result of the multiplier. Figure 9.  Simulation result of Adder.

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 P. SivaNagendra Reddy and M. Saraswathi

8.  References
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