International Journal of Computer Applications (0975 8887)

Volume 120 No.17, June 2015

A Novel Vedic Divider Architecture with Reduced Delay

for VLSI Applications

Siba Kumar Panda Arati Sahu

Assistant Professor, Dept. of ECE M.Tech Scholar, Dept. of ECE
CUTM, SOET CUTM, SOET
Bhubaneswar, Odisha, India Bhubaneswar, Odisha, India

ABSTRACT Indians used these techniques in different fields like medicine,

The ever increasing demand in VLSI architecture to handle science etc. due to which INDIA emerged as the richest
complex systems has resulted for designing of high speed country in the world. They named these systems of calculation
divider architecture. The divider is designed using ever known as VEDIC MATHEMATICS. Vedic mathematics is much
ancient methodology Vedic mathematics. There are several simpler, easily understandable & tricky too.
methods present in Vedic mathematics but here Parvartya Swami Bharati Krishna Tirthaji Maharaj sankaracharya of
sutra is used. It is a general division formula which can be govardhan peath was introduced Vedic mathematics to this
applicable to all cases of division which is an efficient way for world in the form of 16 sutras (formulae) which are very
dividing large numbers with respect to delay and power significant for calculations. Bharati Krishna, who was himself
consumption. Here thirty-two bit divider architecture is a scholar of Sanskrit, Mathematics, History and Philosophy,
implemented using this sutra & synthesized and simulated was able to reconstruct the mathematics of the Vedas. He had
using Xilinx ISE simulator and implemented on virtex4 FPGA explored the mathematical potentials from Vedas and proved
device XC4VLX15.The output parameters such as that the mathematical operations can be carried out to
propagation delay and device utilization are calculated from produce fast answers using the Sutras .As most of the
synthesis results. Our result shows speed improvement as engineering system designs are based on mathematical
compared to other architecture presented in this literature. approach so conventional mathematics become an integral
This architecture can be implemented in many applications part of education. The leading microprocessor manufacturers
such as digital signal processing, cryptography, processor developed their architectures to be suitable for conventional
arithmetic unit design etc. binary arithmetic methods. The need for faster processing
speed drives us for major improvement in processor
General Terms technologies & also search for new methodologies. The Vedic
Algorithms, Sutras mathematics approach is totally different &can be easily
adaptable.
Keywords
Vedic Mathematics, Vedic Divider, Paravartya Sutra, VLSI Vedic Mathematics introduces the wonderful applications
design, Digital Signal Processing to Arithmetical computations, theory of numbers,
compound multiplications, algebraic operations,
1. INTRODUCTION factorizations, simple quadratic and higher order equations,
Now days digitization plays a vital role in the designing of simultaneous quadratic equations, partial fractions, calculus,
processor, ALU unit [1] has greatest importance. In design of squaring, cubing, square root, cube root, coordinate
processor arithmetic units are always based on addition, geometry and wonderful Vedic Numerical code.
substraction, multiplication [2] division operations. Out of all
these operations there are a lot of scientific papers are present Ancient Vedic mathematics mainly deals with sixteen sutras.
based on hardware implementation of addition & Paravartya sutra is one of them which is used for division. A
multiplication operation. But division also has the equal shortcut method for dividing a polynomial [4] by a linear
importance in designing arithmetic unit & has many divisor is one of the forms of general division is considered as
applications in real world systems. But there are few scientific a special case of the paravartya sutra in Vedic mathematics.
papers available on hardware implementation of division The word Vedic is derived from the word Veda which
algorithms. As division is a sequential type of operation its means the store-house of all knowledge. Vedic mathematics is
more costlier in terms of complexity & complex compared mainly based on sixteen sutras & from that paravartya sutra is
with other mathematical operations like multiplication & for division. Sanskrit term PARAYARTYA means all
addition. Division is mainly of two kinds a) slow division b) Transpose and apply.
fast division. Slow division includes several methods like
restoring, non restoring & SRT method. Where one digit of A divider is one of the important hardware block which is
final quotient is produced per iteration. Fast division includes applicable in most of applications such as digital signal
methods like Newton rapshon method & Goldschmidt application, encryption, and decryption algorithms in
method. It gives a close approximated result i.e. twice as cryptography [5] & also in various mathematical
many digit of the final quotient on each iteration. computations. With advances in technology, many
researchers have tried to design dividers which offer either of
Vedic mathematics [3] (Sri Bharati Krishna Tirthatji Maharaja the following- high speed, low power consumption, regularity
1992) is full of magics & mysteries. In ancient days Indians of layout and hence less area or even combination of
were able to understand these mysteries & able to develop them in dividers. From which the Vedic divider is considered
simple keys to solve those mysteries .Thousand years ago best here to satisfy our requirements.

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 International Journal of Computer Applications (0975 8887)
Volume 120 No.17, June 2015

In this paper, we present division operations based on register. This removal decreases the time for the division than
paravartya sutra, and implemented in HDL language. As taken in the current restoring division algorithm considerably.
compared to other methods like restoring division method this
divider provides reduced delay. The paper is organized as A high speed squaring circuit for binary numbers [12] is
follows. In the starting section the background its related work proposed. High speed Vedic multiplier is used for design of
are presented. In the second section Vedic division principle is the proposed squaring circuit. The key to our success is that
described which is based on paravartya sutra. In the third only one Vedic multiplier is used instead of four multipliers
section the proposed divider is described. Fourth section deal reported in the literature. In addition, one squaring circuit is
with the design of the architecture of the divider in BCD used twice. Our proposed Squaring Circuit seems to have
format. Fifth section summarizes the experimental result better performance in terms of speed.
obtained & the final section presents the conclusion and future This paper bring out a 32X32 bit reversible Vedic multiplier
work of the literature. [13] using "Urdhva Tiryakabhayam" sutra meaning Vertical
and crosswise, is designed using reversible logic gates, which
2. BACKGRUND AND RELATED WRK is the first of its kind. Also in this paper we propose a new
Dividers are important components in processor design. The reversible unsigned division circuit. This circuit is designed
normal division i.e. restoring division (R.Bhaskar.Ganapathi using reversible components like reversible parallel adder,
Hegde, P.R.Vaya 2011) is described for sixteen bit division & reversible left-shift register, and reversible. multiplexer,
well explained its implementation in RSA [6] encryption reversible n-bit register with parallel load line. The reversible
system. Extensive research work has been published which Vedic multiplier and reversible divider modules have been
implemented Vedic division method / algorithm for written in Verilog HDL and then synthesized and simulated
(Ratiranjan Senapati Bandan Bhoi & Manoranjan Pradhan using Xilinx ISE 9.2i. This reversible Vedic multiplier results
2012) for 8 bit division. But it is implemented for binary shows less delay and less power consumption by comparing
numbers & compared with our Vedic division & shows an with array multiplier.
improved delay result. In this literature we are using the Vedic
mathematics sutra i.e. paravartya sutra for dividing a 32 bit 3. METHODOLOGY FOR VEDIC
number in BCD format. DIVISION
In progress Floating-point divisor architectures[7] have low Researchers have anticipated many algorithms and Procedural
frequency, larger area and high latency in nature. With advent architectures to carry out division in order to ease the
of more graphic, scientific and medical applications, floating computational time and thus enhancing the recital.
point dividers have become crucial and increasingly
1. Restoring Division
important. However, most of these modern applications need
higher frequency or low latency of operations with minimal Restoring division operates on fixed-point fractional
area occupancy. In this work, highly optimized pipelined numbers and depends on the following assumptions: (a) D <
architecture of an IEEE-754 standard double precision N and (b) 0 < N, D < 1.The quotient digits q are formed from
floating point divider is designed in order to achieve high the digit set {0, 1}. The basic algorithm for binary (radix 2)
frequency on FPGAs. By using secondary clock to perform restoring division is:
mantissa division the overall latency of the divisor is reduced
to 30 clock cycles, i.e. 52% less compared to conventional To compute a/b, put a in register A, b in register B
divisors. This design is mapped onto a Virtex-6 FPGA and an and 0 in register P.
operating frequency of 452.69 MHz is achieved. The
proposed design also handles all the IEEE specified four I.Shift the register pair (P, A) one bit left.
rounding modes, overflow, underflow and various exception II.Subtract the content of Register B from register P.
conditions.
R.panda,M.pradhan[8] presents the concepts behind the iii. If the result of step 2 is negative, set the A0 to 0,
"Urdhva Tiryagbhyam Sutra" and "Nikhilam Sutra"
otherwise to 1.
multiplication techniques.It then shows the architecture for a
1616 Vedic multiplier module using Urdhva Tiryagbhyam iv.If the result of step 2 is negative, restore the old value of P
Sutra [9,10].This paper then extends multiplication to 1616 by adding the contents of register B back into P.
Vedic multiplier using "Nikhilam Sutra" technique. The
1616 Vedic multiplier module using Urdhva Tiryagbhyam After repeating the algorithm, n times, register A will
Sutra uses four 88 Vedic multiplier modules; one 16 bit have quotient and register P with reminder.
carry save adders, and two 17 bit full adder stages. The carry
save adder in the multiplier architecture increases the speed of 2. Non-Restoring Division
addition of partial products. The 1616 Vedic multiplier is
Non-restoring division uses the digit set {1, 1} for the
coded in VHDL, synthesized and simulated using Xilinx ISE
quotient digits instead of {0, 1}. The basic algorithm for
10.1 software. This multiplier is implemented on Spartan 2
binary (radix 2) non-restoring division is:
FPGA device XC2S30-5pq208. The performance evaluation
results in terms of speed and device utilization are compared If P is negative,
with earlier multiplier architecture.
1a. Shift (P,A) one bit left.
An improvement in the current restoring computer division
algorithm [11] which minimizes the number of restorations 2a. Add the content of register B to P.
performed by the computer. Currently, restoration is checked else
after each shifting of the register but deprived Restoring
Division Algorithm checks restoration only when it is needed. 1b. Shift (P,A) one bit left.
The needless restorations are removed by the use of an extra 2b. Subtract the contents of register B from P.

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 International Journal of Computer Applications (0975 8887)
Volume 120 No.17, June 2015

3. If P is negative, set the low-order bit of A to 0, For the base method we use the powers of ten as the base i.e.
for a digit 898 the base number will be 1000 giving a positive
Otherwise set it to 1. difference of 102.Then the difference between the base
Repeat the above procedure n times. After n cycles, number and divisor is calculated. The difference will further
acts as the divisor which is a positive number. Then division
Register A will have the quotient and if P is positive, it is the by paravartya method. But when the divisor is greater than the
remainder, otherwise it has to be restored (add base number we get the difference a negative number i.e. for a
B to it) to get the remainder. digit 1222 the base will be 1000 giving a difference of - (222).
The number of digits of the difference is exactly will be the
3. SRT Division number of digits of the reminder. So before division we have
Named for its creators (Sweeney, Robertson, and to give a demarcation line for the quotient & reminder. But in
Tocher), SRT division is a popular method for division in this literature we specially discussed for the small digits
many microprocessor implementations. SRT division is which gives negative difference which are well explained in
similar to non-restoring division, but it uses a lookup table the later section.
based on the dividend and the divisor to determine each
quotient digit. The basic algorithm for binary (radix 2) non- 3.1 Format for Paravartya Method
restoring division is:
1. Load a and b into A and B registers (Figure A.2)
2. If B has k leading zero, shift B and (P,A) left k bits
3. For l=0, n-1,
a) If top 3 bits of P are equal, set qi=0 and
shift (P,A) one bit left.
b) If top 3 bits of P are not equal and P is negative, set qi=-1
(write as ) shift (P,A) one bit left, add B.
c) Otherwise, set qi=1, shift (P,A) one bit left, sub B.
Fig 1:Format for Paravartya Method
4. If final remainder is negative, correct the remainder by
adding B; correct the quotient by subtracting 1 from q0. 3.2 Steps of Division by using Paravartya
5. Shift remainder k bits right. Sutra
1. We have the dividend & divisor given. Check whether the
divisor is greater than the base number or smaller. If
grater we will have a positive difference else a negative
4. Vedic Architecture: Nikhilam Sutra
difference. which will act as the new divisor for further
Vedic Sutra, Nikhilam can be further extended to steps.
carry out Binary Division as an alternative to conventional
2. Bring down the very 1st digit of the dividend. Then
algorithm. Assume that, A and B are dividend and divisor
multiply it with the difference. Now write down the
respectively. Dividend is n-bits wide. The flowchart diagram
result in the next line of the dividend shifting one bit
can be executed as follows:
right.
a)Initialize the incrementer with 0.
3. Perform addition to get the 2nd bit and put it down. Same
b) Determine the complement B with respect to 2n assume the operation should be performed till the last digit of the
complemented result is equal to B. dividend.
c) Add B with A. If the carry is 1, then feed the result to the 4. In this manner finally the quotient & reminder can be
adder. obtained.
d) Increment the content of the incrementer by one.
e) Repeat step-3 until the result is less than B.
f) The final result of the incrementer is the quotient and result
from the adder is the remainder.
In this paper we presented the BCD (binary coded decimal)
division of thirty two bit divider architecture based on
paravartya sutra. Its an optimized method which led to
reduction in several steps. So by using paravartya sutra we
can reduce several steps as compared to other methods there
by reducing the hardware complexity & latency of the circuit.
Basically the division is mainly based on two factors Fig 2: Division of two decimal numbers with positive
(a) Divisor greater than the base number (for digits like 8, quotient & reminder
9, 7 used in the divisor)
(b) Divisor smaller than the base number (for digits like
1,2,3,4 used in the divisor)

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 International Journal of Computer Applications (0975 8887)
Volume 120 No.17, June 2015

Here S0 S7 represents the entire 32 bit no each having 4

digits & B0 B3 denotes the 16 bit divisor and A2, A1, A0
denotes the 2s complement of B2, B1,B0. In the last row Q4
Q0 represents the quotient & R1 R0 the reminder.

4. FLOW CHART OF BCD DIVIDER

Fig 3:Division of two decimal number with positive quotient

& reminder
If we are getting positive value of quotient & reminder then
that will be the direct answer but we get negative quotient
then we have to check the places of the digit & according to
that we can be able to find the result. As in the above example
by the places we can calculate it as (100 -20 +4) = 85, so the
quotient can be found in this way& reminder is 035.

Fig 4: Division of two decimal numbers with positive

quotient & negative reminder
The reminder is found by subtracting it from the divisor as
(111-20-1) = 90, So the quotient is 131 & reminder is 90.

3.3 Extension of Paravartya Sutra Using Fig.6. Flowchart for BCD divider
BCD Code
4.1 Algorithm for Implemented BCD
Divider
1. The dividend & divisor are given in decimal number
system. Write down the dividend & divisors BCD
equivalents just below the digits. Give a demarcation line
for quotient & reminder.
2. Take the difference between the base number & divisor
resulting a negative number which will be acting as new
divisor for further steps. Number of digits in new divisor
is equal in number with the number of digits in reminder.
3. As the resulted divisor is a negative number & we are
implementing in BCD format we have to take the 2s
complement of the resulted divisor.
4. Now bring down the 1st digit of the dividend (1st four bits
as in BCD format) & multiplication of the digit with the
2s complemented result of the divisor which is written
just shifting one digit right of the dividend.
Fig 5: Paravartya Sutra for BCD Code

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 International Journal of Computer Applications (0975 8887)
Volume 120 No.17, June 2015

5. Then addition of the 2nd digit of the dividend with the 9. Same process should be used until the last digit of the
multiplied value, if carry occurs only last four digits dividend; finally we have the quotient as0001 0010 0001
should be taken & carry should be discarded. (The 0010 0011 & reminder 0110 1001 1000.
addition should be bit by bit).
10. So the quotient is 1 2 -1 2 -3 & reminder is 698.
6. Repeat step 4 & 5 till the end of the digits of dividend
bits. 11. Now again the result should not be in 2s complement
form so the final quotient can be calculated as 10000 +
7. The resulted bits after addition gives us the quotient & 2000 100 + 20 3 = 11917 & reminder 698.
reminder but the values must not exceed the value 9
(1001) as its in BCD format, so the values greater than 5. RESULT ANALYSIS
1001 should be complemented. The design of the divider using paravartya sutra of Vedic
mathematics consists of several steps like design entry,
8. The obtained result which are in 2s complemented form synthesis, simulation & implementation. In the very first step
i.e. either the quotient & reminder digits can be i.e. design entry we have written the verilog HDL code for the
calculated as explained in the above examples. proposed paravartya divider. In the next step the code is
checked for errors & when no error found, and then the code
4.2 32Bit Divided By 16Bit is synthesized using XILINX9.2 software synthesis tool.We
have simulated the proposed divider by creating a test bench
file by taking two set of combination of dividend & divisor
operands. XILINX 9.2 ISE simulation tool is used to simulate
the created test bench file. By Xilinx implementation tool a
user constraint file is created in virtex4 FPGA device
XC4VLX15 with package SF363 of speed -12 for the
implementation of the proposed divider. As there are no
scientific papers available for hardware implementation of 32
bit divider architecture, so to compare our result we
implemented restoring division method (R.Bhaskar.Ganapathi
Hegde, P.R.Vaya 2011) in VHDL and synthesized using
XILINX 9.2. and compared our result with this result. We
implemented parvartya sutra in BCD format because 8 bit
binary division discussed (Ratiranjan Bandan & Pradhan
2012) shows a delay of 19.9ns & our proposed divider which
performs 32bit division shows a delay of 18.67ns.Oviously
the hardware complexity is more in case of binary divider .
Fig.7. Division of 32 bit number with 16 bit number in
BCD format Table 1. Comparison of synthesis result of restoring
division to paravartya division (32 bit)
4.3 Description Of Paravartya Sutra For
BCD Format
1. The dividend is 14563272, divisor 1222 is taken &
whose BCD equivalent is written.
2. Here the difference we found is -2 -2 -2 so in BCD
format we have to take its 2s complement. We will get it
as 1100 1100 1100.
3. Then bring down the 1st place digits of the
dividend.(0001)
4. Multiply of the 2s complemented result 1110 1110 1110
with 0001 & the result is 1110.
5. Multiplied result should be written below the 2nd place From the table we are very clear about the result of device
digits(0100) & addition should done (if carry occurs utilization and delay as the restoring division method shows a
neglect & only last 4 digits should be taken). larger delay as compared to the proposed divider & the
percentage of device utilization in restoring division method is
6. Now the 2nd column result is 0010 and will be quite high from Vedic divider
multiplied with 1110 1110 1110,result will be written in
starting place of (2nd row) / under 3rd place digits. 6. CONCLUSION
7. In the very next step we have to perform addition This literature presents a novel design & an algorithm to
operation, but that should be added bit by bit means 0101 construct a new high speed thirty two bit divider .It also
+ 1110 = 1,0011 here the 1 should be discarded & now discusses example to how the method is implemented &
0011 is added with the next value i.e. 0011 + 1100 = which is evaluated in terms of the path delay & device
1111. utilization. Our synthesis result shows better result i.e.
improved delay & better device utilization. It is seen that the
8. But as its a BCD format 1111,1101 are not allowed .So speed of the proposed divider is higher than that of the
in above example whatever values we are getting more restoring division method i.e. the delay has been drastically
than 0 - 9 all those values are again 2s complemented reduced. This divider can be used in applications such as
digital signal processing, cryptography & processor ALU

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 International Journal of Computer Applications (0975 8887)
Volume 120 No.17, June 2015

design. Further the above thesis work modified for optimized [10] Siba Ku Panda, Ritisnigdha Das et al. VLSI
delay, less power consumption, less area and also FPGA Implementation of Vedic Multiplier Using Urdhva-
implementation will done as future work. Tiryakbhyam Sutra in VHDL Environment: A Novelty,
IOSR, Vol.5, February 2015.
7. REFERENCES
[1] Abhishek Gupta Arithmetic Unit Implementation Using [11] Nitish Aggarwal, Kartik Asooja, Saurabh Shekhar
Delay Optimized Vedic Multiplier with BIST Verma, Sapna Negi An Improvement in the Restoring
Capability International Journal of Engineering and Division Algorithm 2009 IEEE.
Innovative Technology (IJEIT) Volume 1, Issue 5, May [12] K.sethi & R.panda An improved squaring circuit for
2012. binary numbers, International Journal of Advanced
[2] Manoranjan Pradhan and Rutuparna Panda High speed Computer Science and Applications, page111116 ,
multiplier using Nikhilam Sutra algorithm of Vedic 2012.
mathematicsOn: 12 April 2013, International Journal of [13] Srikanth G, Nasam Sai Kumar Design of High speed
Electronics. Low Power Reversible Vedic multiplier and Reversible
[3] Jagadguru Swami Sri Bharati Krishna Tirthatji DividerIJERAISSN : 2248-9622, Vol. 4, Issue 9(
Maharaja, Vedic Mathematics, Motilal Banarsidass Version 5), September 2014, pp.70-74
Publication, 1992.
8. AUTHORS PROFILE
[4] Ashish Joglekar , Shaunak Vaidya , Ajinkya Kale, A Mr.Siba Kumar Panda was born on November 09,1989.He
Novel Binary Division Algorithm based on Vedic received the B.Tech degree in Electronics & Communication
Mathematics and Applications to Polynomial Division Engineering from Biju Patnaik University of
2007. Technology,odisha in 2012 and M.Tech degree in VLSI Signal
Processing Specialization from Veer Surendra Sai University
[5] R.Bhaskar.Ganapathi Hegde, P.R.VayaAn efficient Of Technology,odisha in 2014.
hardware model for RSA Encryption system using Vedic
mathematics. International Conference on Currently he is working as an Assistant Professor at Centurion
Communication Technology and System Design 2011. University of Technology and Management, Bhubaneswar;
Odisha.He also awarded the University Silvermedal for best
[6] Ming Der Shieh,jun Hong Chen, A new modular Electronics & Telecommunication Engineering Post Graduate
exponentiation architecture for efficient design of RSA for the academic year 2012-2014 at VSSUT, Odisha..
Cryptosystem,IEEE transactions on VLSI
systems,Sept.2008. His research area of interest includes Ultra-wideband (UWB)
device design, RF circuit design using CMOS
[7] Purna Ramesh Addanki, Venkata Nagaratna Tilak Technique,VLSI implementation of Vedic mathematics,VLSI
Alapati and Mallikarjuna Prasad Avana Floating Point Signal Processing.
Double Precision Divisor Using Verilog International
Journal of Advanced Science and Technology Vol. 48, Mrs Arati Sahu was born in Rourkela , Odisha , India, in
November, 2012. 1991. She has completed B.Tech in Electronics and
Communication Engineering,from Sundargarh Engineering
[8] Rutuparna panda,M.pradhan, Speed comparision of Collage,Sundargarh.Currently pursuing her M.tech degree in
16*16 vedic multipliers IJCA,vol-21,may-2011 VLSI from ECE , Centurion University of Technology and
[9] Arati Sahu, Siba kumar Panda et al. HDL Management, Bhubaneswar, Odisha 751020 ,India, in the
Implementation and Performance Comparison of an academic period of 2013-2015.
Optimized High Speed Multiplier, International
Organization Of Scientific Research (IOSR), Issue 2,
vol.5, April 2015.

IJCATM : www.ijcaonline.org
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