DLD - Lec 2
DLD - Lec 2
DLD - Lec 2
d. xyz' + x'yz + xyz + x'yz' = xy(z + z') + x'y(z + z') = xy + x'y = y(x + x’)
=y
(a) F1=x’yz’+ x’y’z by taking their dual and complementing each literal.
The dual of F1 is (x’+y+z’)(x’+y’+z)
Complement each literal: (x+y’+z)(x+y+z’)=F1’
(b) F2= x(yz + yz) by taking their dual and complementing each literal.
The dual of F2 is x + (y + z)(y + z).
Complement each literal: x + (y + z)(y + z) = F2’
• TTL: transister-transister logic: has been used for a long time and is
considered as standard; but is declining in use.
• Fan out specifies the number of standard loads that the output of a
typical gate can drive without impairing its normal operation.