Si4800BDY

Vishay Siliconix

N-Channel Reduced Qg, Fast Switching MOSFET

PRODUCT SUMMARY FEATURES

VDS (V) RDS(on) (Ω) ID (A) • Halogen-free According to IEC 61249-2-21
Available
0.0185 at VGS = 10 V 9
30 • TrenchFET® Power MOSFET
0.030 at VGS = 4.5 V 7
• High-Efficient PWM Optimized
• 100 % UIS and Rg Tested

SO-8
D
S 1 8 D
S 2 7 D

S 3 6 D
G 4 5 D
G

Top View

S
Ordering Information: Si4800BDY-T1-E3 (Lead (Pb)-free)
Si4800BDY-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter Symbol 10 s Steady State Unit
Drain-Source Voltage VDS 30
V
Gate-Source Voltage VGS ± 25
TA = 25 °C 9 6.5
Continuous Drain Current (TJ = 150 °C)a, b ID
TA = 70 °C 7.0 5.0
Pulsed Drain Current (10 µs Pulse Width) IDM 40 A
Continuous Source Current (Diode Conduction)a, b IS 2.3
Avalanche Current IAS 15
L = 0.1 mH
Single-Pulse Avalanche Energy EAS 11.25 mJ
TA = 25 °C 2.5 1.3
Maximum Power Dissipationa, b PD W
TA = 70 °C 1.6 0.8
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C

THERMAL RESISTANCE RATINGS

Limits
Parameter Symbol Typ. Max. Unit
t ≤ 10 s 40 50
Maximum Junction-to-Ambienta RthJA
Steady State 70 95 °C/W
Maximum Junction-to-Foot (Drain) Steady State RthJF 24 30
Notes:
a. Surface Mounted on FR4 board.
b. t ≤ 10 s.

Document Number: 72124 www.vishay.com

S-83039-Rev. H, 29-Dec-08 1
Si4800BDY
Vishay Siliconix

MOSFET SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 0.8 1.8 V
Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA
VDS = 30 V, VGS = 0 V 1
Zero Gate Voltage Drain Current IDSS µA
VDS = 30 V, VGS = 0 V, TJ = 55 °C 5
On-State Drain Currenta ID(on) VDS ≥ 5 V, VGS = 10 V 30 A
VGS = 10 V, ID = 9 A 0.0155 0.0185
Drain-Source On-State Resistancea RDS(on) Ω
VGS = 4.5 V, ID = 7 A 0.023 0.030
Forward Transconductancea gfs VDS = 15 V, ID = 9 A 16 S
a VSD IS = 2.3 A, VGS = 0 V 0.75 1.2 V
Diode Forward Voltage
Dynamicb
Total Gate Charge Qg 8.7 13
Gate-Source Charge Qgs VDS = 15 V, VGS = 5.0 V, ID = 9 A 1.5 nC
Gate-Drain Charge Qgd 3.5
Gate Resistance Rg 0.5 1.4 2.2 Ω
Turn-On Delay Time td(on) 7 15
Rise Time tr VDD = 15 V, RL = 15 Ω 12 20
Turn-Off Delay Time td(off) ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω 32 50 ns
Fall Time tf 14 25
Source-Drain Reverse Recovery Time trr IF = 2.3 A, dI/dt = 100 A/µs 30 60
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

www.vishay.com Document Number: 72124

2 S-83039-Rev. H, 29-Dec-08
 Si4800BDY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

40 40
VGS = 10 thru 5 V 4V
TC = - 55 °C
35 35
25 °C
30 30

I D - Drain Current (A)

I D - Drain Current (A)

25 25
125 °C
20 20
3V
15 15

10 10

5 5

0 0
0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V)

Output Characteristics Transfer Characteristics

0.040 1200

1000
0.032
R DS(on) - On-Resistance (Ω)

C - Capacitance (pF)

Ciss
VGS = 4.5 V 800
0.024
600
VGS = 10 V
0.016
400
Coss
0.008 200
Crss

0.000 0
0 5 10 15 20 25 30 0 4 8 12 16 20

ID - Drain Current (A) VDS - Drain-to-Source Voltage (V)

On-Resistance vs. Drain Current Capacitance

6 1.8

VDS = 15 V VGS = 10 V
ID = 9 A
V GS - Gate-to-Source Voltage (V)

ID = 9 A 1.6
5
RDS(on) - On-Resistance

4 1.4
(Normalized)

3 1.2

2 1.0

1 0.8

0 0.6
0 2 4 6 8 10 - 50 - 25 0 25 50 75 100 125 150

Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C)

Gate Charge On-Resistance vs. Junction Temperature

Document Number: 72124 www.vishay.com

S-83039-Rev. H, 29-Dec-08 3
Si4800BDY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

0.06
50

0.05

r DS(on) - On-Resistance (Ω)

I S - Source Current (A)

TJ = 150 °C 0.04

10 ID = 9 A
0.03

0.02

0.01
TJ = 25 °C
0.00
1
0 2 4 6 8 10
0.0 0.2 0.4 0.6 0.8 1.0 1.2
VGS - Gate-to-Source Voltage (V)
VSD - Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage

0.4
150

0.2
120
ID = 250 µA
V GS(th) Variance (V)

0.0
90
Power (W)

- 0.2

60
- 0.4

- 0.6 30

- 0.8
0
- 50 - 25 0 25 50 75 100 125 150
10-3 10-2 10-1 1 10
TJ - Temperature (°C) Time (s)
Threshold Voltage Single Pulse Power, Junction-to-Ambient

100
Limited
by R DS(on)*

10
I D - Drain Current (A)

1 ms

1
10 ms

100 ms
1s
0.1
TC = 25 °C 10 s
Single Pulse
DC

0.01
0.1 1 10 100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum V GS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient

www.vishay.com Document Number: 72124

4 S-83039-Rev. H, 29-Dec-08
 Si4800BDY
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

1
Normalized Effective Transient

Duty Cycle = 0.5

Thermal Impedance

0.2
Notes:
0.1
0.1 PDM
0.05
t1
t2
t1
0.02 1. Duty Cycle, D =
t2
2. Per Unit Base = R thJA = 70 °C/W
3. T JM - TA = PDMZthJA(t)
Single Pulse 4. Surface Mounted
0.01
10-4 10-3 10-2 10-1 1 10 100 600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient

1
Normalized Effective Transient

Duty Cycle = 0.5

Thermal Impedance

0.2

0.1
0.1
0.05

0.02

Single Pulse
0.01
10-4 10-3 10-2 10-1 1 10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?72124.

Document Number: 72124 www.vishay.com

S-83039-Rev. H, 29-Dec-08 5
 Package Information
Vishay Siliconix

SOIC (NARROW): 8-LEAD

JEDEC Part Number: MS-012

8 7 6 5

E H

1 2 3 4

D h x 45
C
0.25 mm (Gage Plane)
A
All Leads

q 0.101 mm
e B A1 L
0.004"

MILLIMETERS INCHES
DIM Min Max Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.20 0.004 0.008
B 0.35 0.51 0.014 0.020
C 0.19 0.25 0.0075 0.010
D 4.80 5.00 0.189 0.196
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.50 0.93 0.020 0.037
q 0° 8° 0° 8°
S 0.44 0.64 0.018 0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498

Document Number: 71192 www.vishay.com

11-Sep-06 1
 VISHAY SILICONIX

TrenchFET® Power MOSFETs Application Note 808

Mounting LITTLE FOOT®, SO-8 Power MOSFETs

Wharton McDaniel
0.288
7.3
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
0.050 0.088
been been modified to provide the heat transfer capabilities 1.27 2.25
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains 0.088
0.027 2.25
the same. 0.69

See Application Note 826, Recommended Minimum Pad 0.078 0.2

1.98 5.07
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the Figure 2. Dual MOSFET SO-8 Pad Pattern
basis of the pad design for a LITTLE FOOT SO-8 power With Copper Spreading
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make The minimum recommended pad patterns for the
two connections: an electrical connection and a thermal
single-MOSFET SO-8 with copper spreading (Figure 1) and
connection, to draw heat away from the package.
dual-MOSFET SO-8 with copper spreading (Figure 2) show
In the case of the SO-8 package, the thermal connections the starting point for utilizing the board area available for the
are very simple. Pins 5, 6, 7, and 8 are the drain of the heat-spreading copper. To create this pattern, a plane of
MOSFET for a single MOSFET package and are connected copper overlies the drain pins. The copper plane connects
together. In a dual package, pins 5 and 6 are one drain, and the drain pins electrically, but more importantly provides
pins 7 and 8 are the other drain. For a small-signal device or planar copper to draw heat from the drain leads and start the
integrated circuit, typical connections would be made with process of spreading the heat so it can be dissipated into the
traces that are 0.020 inches wide. Since the drain pins serve
ambient air. These patterns use all the available area
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The underneath the body for this purpose.
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a Since surface-mounted packages are small, and reflow
large thermal impedance. Also, heat spreads in a circular soldering is the most common way in which these are
fashion from the heat source. In this case the drain pins are affixed to the PC board, “thermal” connections from the
the heat sources when looking at heat spread on the PC planar copper to the pads have not been used. Even if
board. additional planar copper area is used, there should be no
APPLICATION NOTE

problems in the soldering process. The actual solder

0.288
7.3
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
0.050
drain pins, the solder mask generation occurs automatically.
1.27
0.196
5.0
A final item to keep in mind is the width of the power traces.
0.027
The absolute minimum power trace width must be
0.69 determined by the amount of current it has to carry. For
0.078 0.2
thermal reasons, this minimum width should be at least
1.98 5.07 0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
Figure 1. Single MOSFET SO-8 Pad
from the device.
Pattern With Copper Spreading

Document Number: 70740 www.vishay.com

Revision: 18-Jun-07 1
 Application Note 826
Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR SO-8

0.172
(4.369)
0.028
(0.711)
(6.248)

(3.861)
0.246

0.152
(1.194)
0.047

0.022 0.050
(0.559) (1.270)

Recommended Minimum Pads

Dimensions in Inches/(mm)

Return to Index
Return to Index
APPLICATION NOTE

www.vishay.com Document Number: 72606

22 Revision: 21-Jan-08
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Revision: 02-Oct-12 1 Document Number: 91000