CHAPTER 3

Memory and basic IO interface

CONTENTS

 Memory interface

 I/O interface
 Peripheral I/O
 Interfacing output devices

 Interfacing input devices

 Memory –Mapped I/O

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WHAT IS AN INTERFACE

 An interface is a concept that refers to a point of

interaction between components, and is applicable
at the level of both hardware and software.

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INTERFACING EXAMPLE BLOCK DIAGRAM

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MEMORY INTERFACE

 Memory in a microprocessor system is where

information (data and instructions) is kept.

 It can be classified into two main types:

 Main memory (RAM and ROM)

 Storage memory (Disks , CD ROMs, etc.)

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8085 INTERFACING PINS

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MEMORY INTERFACE
 Memory pin

Vcc

D7-D0
A10-0
RAM

/CS
/RD
/WR

Gnd 7
MEMORY INTERFACE

 Memory requirement

 Address lines to identify memory register

 Chip select (/CS) signal to enable the chip

 Control signal /RD or /WR enable

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MEMORY INTERFACE

 Accessing Memory
 For the microprocessor to access (Read or Write)
information in memory (RAM or ROM), it needs to do
the following:
 Select the right memory chip (using part of the address bus).

 Identify the memory location (using the rest of the address

bus).

 Access the data (using the data bus)

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MEMORY INTERFACE

 The steps of writing into Memory

 The microprocessor would turn on the WR control
(WR = 0) and turn off the RD control (RD = 1).

 The address is applied to the address decoder which

generates a single Enable signal to turn on only
one of the memory registers.

 The data is then applied on the data lines and it is

stored into the enabled register.
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MEMORY INTERFACE

 The 8085 has 16 address lines.

 That means it can address 216 = 64K memory
locations.
 1 memory chip with 64 k locations, or

 2 chips with 32 K in each, or

 4 chips with 16 K each or

 16 of the 4 K chips, etc.

 How would we use these address lines to control

the multiple chips? 11
MEMORY INTERFACE
 The 8085 and Address Ranges
 If we use memory chips with 1K locations each, then
we will need 64 such chips.
 The 1K memory chip needs 10 address lines to
uniquely identify the 1K locations.
 (log21024 = 10)

 That leaves 6 address lines which is the exact

number needed for selecting between the 64
different chips
 (log264 = 6) 12
MEMORY INTERFACE
 The 8085 and Address Ranges
 Now, we can break up the 16-bit address of the 8085
into two pieces:

Chip select bits Location select bits

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

 Depending on the combination on the address lines

A15 - A10 , the address range of the specified chip is
determined.
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MEMORY INTERFACE DECODING
 Address decoding methods
 Using a NAND gate

 Using a 3-to-8 decoding

000 to 111= eight possible
output

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MEMORY INTERFACE EXAMPLE

 Interface 2kB RAM with microprocessor 8085.

You can assign the address range of your choice
to the 2kB RAM.

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MEMORY INTERFACE EXAMPLE
Understand the pin for the memory
 Data pins: D0-D7 connected to the memory
chip.
 Address pins: a memory of size 2kB x 8
will have 211 different memory locations.
 11 address lines A0 to A10.
 /CS pin: chip select
 /OE pin: active-low  enable output pin
/WR pin: active-low  data written on the
memory 16
MEMORY INTERFACE EXAMPLE

 Data Bus interfacing

 There are eight lines comprising the data bus of both

8085 and the memory chips

 We just connect corresponding lines (D0-D7 from

8085) to the corresponding pins (D0-D7 of the

memory chip).
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MEMORY INTERFACE EXAMPLE
 Address bus Interfacing
 We have a 2kB RAM with 11 address lines.

 So, the first 11 lines of the address bus of 8085 will be

connected to the corresponding address lines of the
2kB RAM.

 The remaining address lines will be used to generate

the chip select (CS) signal.

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 MEMORY INTERFACE EXAMPLE
 Connecting Control Signals
 OE (Output Enable) and WR (Memory Write)

 Use control signals generated using a 3 to 8

decoder

 Our control signals are generated when we

input the WR, RD and IO/M signals from the
8085 to the 3:8 decoder

 Since we are dealing with memory, we will

just need MEMR and MEMW signals.

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MEMORY INTERFACE EXAMPLE
 Generating the chip select(/CS) signal
 Use address A11 to A15

 Use NAND gate

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COMPLETE INTERFACE

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EXERCISE

 Design an 8085 based system for the following

specification
 CPU working at 3MHz

 8KB of EPROM using 4KB Device

 4K RAM using 2kb device

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CONTENTS

 Memory interface

 I/O interface
 Peripheral I/O
 Interfacing output devices

 Interfacing input devices

 Memory –Mapped I/O

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INTERFACING INPUT OUTPUT DEVICES
 I/O device
 Are communicating channel for
microprocessor to outside world
 Keyboards and display units

 Mode of interfacing
 Parallel I/O: Eight bit data transferred at a time

 Serial I/O: only single bit transferred at a time

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PARALLEL I/O

 Types of Parallel Interface

 Peripheral I/O-

 I/O device mapped I/O ports

 Memory mapped I/O

 It considers them like any other memory

location.

 memory location mapped to I/O ports

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PARALLEL I/O

 Devices are identified by 8-bit address called Port

 Data transfer method

 Place address on address bus

 Send control signals

 Enable interfacing device

 Transfer data

 Instructions
 IN and OUT 26
PERIPHERAL I/O INSTRUCTIONS
 Instruction
 IN / OUT

 IN 8-bit port address

 IN 01H
 Copy from port 01h to Accumulator

 OUT 8-bit port address

 OUT 02H
 Copy content from Accumulator to port 02h output
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device
PERIPHERAL I/O- INTERFACING
 Decode address bus(A7-0) to generate device address
(/IOADR)
 Combine device address with control signal (/IOR or
/IOW) to generate device select signal
 Use device select signal to activate the interfacing device

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PERIPHERAL I/O- INTERFACING LED OUTPUT
 Peripheral I/O interface for LED output

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PERIPHERAL I/O- INTERFACING LED OUTPUT

 Figure above shows one of the way to decode address lines

to obtain output address 01H.

 The line address A7-A0 is connected to eight NAND gates

function as decoder.

 The line A0 is connected directly, A7-A1 are connected

through inverter gates.

 The G2 gate is combined with gate G1 and IO/W control

signal to generate select signal I/O whenever both signals
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are active low.
PERIPHERAL I/O- INTERFACING INPUT
 Peripheral I/O interface for Dip-switch input

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CONTENTS

 Memory interface

 I/O interface
 Peripheral I/O
 Interfacing output devices

 Interfacing input devices

 Memory –Mapped I/O

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MEMORY MAPPED I/O
 I/O devices are addressed with address from
memory

 Device identified using 16-bit address

 Device are enabled by memory related control signal.

 Data transfer
 LDA, STA

 Control signal
 /MEMR and /MEMW
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MEMORY MAPPED I/O

 Device selection and data transfer steps

 Decode address bus to generate device address pulse

 Combine device address with control signal to

generate device select signal

 Use device select signal to activate the interfacing

device
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MEMORY MAPPED I/O
 Memory–mapped vs. peripheral I/O
Characteristic Memory-mapped I/O Peripheral I/O

Address 16-bit 8-bit

Control signal /MEMW, /MEMR /IOR, /IOW

Instructions LDA, STA, LDAX, STAX, MOV IN, OUT

M,R, ADD M, SUB M, ANA M…

Data transfer Between any reg. and I/O Between I/O and A

Number of <64K 256 for IN

possible I/O 256 for OUT
interface
Decoders More complex decoder to decode Less complex decoder to
16-bit address decode 8-bit address
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Operation Arithmetic and logic operation Not available

MEMORY INTERFACE
 Instruction cycle
 Time required to execute single instruction

 Include one to six machine or operation cycle

 Machine cycle
 Time required to complete one operation

 Accessing memory , I/O or acknowledge external request

 Include three to six T-state

 T-state
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 Subdivision of operation performed in one clock period
MEMORY INTERFACE
 Consider MVI A, 32H
 Consists of 2 byte (Instruction MVI A and Data 32H)
 It needs two machine cycle(Opcode Fetch and memory
read)
 Needs Seven T-State ( 4 fetch and 3 memory read)
 Clock frequency f=2MHz
 T-state = clock period(1/f)= 0.5µs
 Execution time for Op-code Fetch: (4T)*0.5=2µs
 Execution time for memory read: (3T)*0.5=1.5µs
 Execution time for Instruction: (7T)*0.5=3.5µs 37
MEMORY INTERFACE

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CONTENTS

 Memory interface

 I/O interface
 Peripheral I/O
 Interfacing output devices

 Interfacing input devices

 Memory –Mapped I/O

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