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Advanced UVM: Understanding The Factory and Configuration

This document discusses two customization mechanisms in UVM - the factory and configuration. The factory allows overriding the type of components created, while configuration allows setting properties of child components. It provides examples of using the factory to change component types both globally and for specific instances. Parameterized types can also be overridden. Tests are created from the factory like other UVM components.

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0% found this document useful (0 votes)
320 views

Advanced UVM: Understanding The Factory and Configuration

This document discusses two customization mechanisms in UVM - the factory and configuration. The factory allows overriding the type of components created, while configuration allows setting properties of child components. It provides examples of using the factory to change component types both globally and for specific instances. Parameterized types can also be overridden. Tests are created from the factory like other UVM components.

Uploaded by

manchurico
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Advanced UVM

Understanding the Factory


and Configuration
Tom Fitzpatrick
Strategic Verification Architect
Two Customization Mechanisms
Factory
• Allows test to change the type of a desired component or object
• Typically set up at start of simulation
Configuration
• Allows parents to define properties for children
• Static (build-time) – Highest parent “wins”
• Dynamic (run_time) – Last set “wins”
• All UVM components get their own configuration
• Optionally use to configure their children

Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021


Create() vs. New()
class my_env extends uvm_env; new() hard-codes the type
virtual function void build_phase(uvm_phase phase);
comp1 = new(“comp1”, this); …without
comp2 = my_comp::type_id::create(“comp2”, this); modifying the
endfunction instantiating
code!
class my_comp extends uvm_component;
`uvm_component_utils(my_comp) create() returns a
… constructed instance
endclass comp1 from the factory
class my_Xcomp
my_comp extends
extendsuvm_component;
my_comp; Factory lets you change
`uvm_component_utils(my_comp)
`uvm_component_utils(my_Xcomp) the type of the created
… comp2 component…
endclass

Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021


Registering with the Factory
Objects are registered with the factory via macros
• `uvm_object_utils(<type>)
• `uvm_component_utils(<type>) ‘type_id’ is a wrapper
created by the macro

class my_env extends uvm_env;


virtual function void build_phase(uvm_phase phase);
comp2 = my_comp::type_id::create(“comp2”, this);
endfunction class my_comp extends uvm_component;
`uvm_component_utils(my_comp) No “;”
No ‘;’

comp2
endclass

Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021


Registering with the Factory
Static methods in wrapper Override type
returned by factory
class test extends uvm_test;
get_type() returns
function void build_phase(uvm_phase phase);
my_env e = new(“e”); the type “handle”
my_comp::type_id::set_type_override(my_Xcomp::get_type());
class my_env extends uvm_env;
virtual function void build_phase(uvm_phase phase);
comp2 = my_comp::type_id::create(“comp2”, this);
endfunction class my_Xcomp extends my_comp;
returns a constructed `uvm_component_utils(my_Xcomp)
instance … comp2
(no $cast needed) endclass

set_inst_override(<type>, “<instance>”); // too


Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Overriding a Type
class test extends uvm_test;
function void build_phase(uvm_phase phase); Environments are
e = my_env::type_id::create(“e”, this); components

endfunction class my_env extends uvm_env;


U1 U2
endclass `uvm_component_utils(my_env)
shape u1,u2;// default square

function void build_phase(uvm_phase phase);


u1 = shape::type_id::create(“u1”,this);
u2 = shape::type_id::create(“u2”,this);


endfunction
Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Overriding a Type
class test extends uvm_test;
New Desired
function void build_phase(uvm_phase phase);
type
e = my_env::type_id::create(“e”, this); All Instances
shape::type_id::set_type_override( circle::get_type() ); Overridden

endfunction class my_env extends uvm_env;


U1 U2
endclass `uvm_component_utils(my_env)
shape u1,u2;// default square

function void build_phase(uvm_phase phase);


u1 = shape::type_id::create(“u1”,this);
u2 = shape::type_id::create(“u2”,this);


endfunction
Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Overriding an Instance
class test extends uvm_test; New Desired type
function void build_phase(uvm_phase phase);
Instance Name
e = my_env::type_id::create(“e”, this);
shape::type_id::set_type_override( circle::get_type() ); Instance
shape::type_id::set_inst_override( triangle::get_type(), “e.u2”, this ); Changed

endfunction class my_env extends uvm_env;


U1 U2
endclass `uvm_component_utils(my_env) U2
shape u1,u2;// default square

function void build_phase(uvm_phase phase);


u1 = shape::type_id::create(“u1”,this);
u2 = shape::type_id::create(“u2”,this);


endfunction
Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Using Parameterized Types
class test extends uvm_test; class red #(int SIDES=3)
function void build_phase(uvm_phase phase); extends uvm_component;
e = my_env::type_id::create(“e”, this); `uvm_component_param_utils(red#(SIDES))
shape::type_id::set_type_override( circle::get_type() );
shape::type_id::set_inst_override( triangle::get_type(), “e.u2”, this );

endfunction class my_env extends uvm_env;


U1 U3
endclass `uvm_component_utils(my_env) U2
shape u1,u2;// default square
red #(4) u3;
function void build_phase(uvm_phase phase); Parameterized
u1 = shape::type_id::create(“u1”,this); type
u2 = shape::type_id::create(“u2”,this);
u3 = red#(4)::type_id::create(“u3”,this);

endfunction
Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Using Parameterized Types
class test extends uvm_test;
function void build_phase(uvm_phase phase);
e = my_env::type_id::create(“e”, this);
shape::type_id::set_type_override( circle::get_type() );
shape::type_id::set_inst_override( triangle::get_type(), “e.u2”, this );
red#(4)::type_id::set_type_override( blue#(4)::get_type() );
endfunction class my_env extends uvm_env;
U1
endclass `uvm_component_utils(my_env) U2
shape u1,u2;// default square
red #(4) u3;
function void build_phase(uvm_phase phase);
u1 = shape::type_id::create(“u1”,this);
u2 = shape::type_id::create(“u2”,this);
u3 = red#(4)::type_id::create(“u3”,this);

endfunction
Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Tests are Components, too!
run_test() creates the test from the factory

class test extends uvm_test;


module top; `uvm_component_utils(test)
... …
endclass
Register the test
initial with the factory
begin: blk
...
run_test();
end

endmodule: top
Command line: vsim +UVM_TESTNAME=test
Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Tests are Components, too!
Always call run_test() with null argument

class test extends uvm_test;


module top; `uvm_component_utils(test)
... …
endclass class test2 extends uvm_test;
`uvm_component_utils(test2)
initial …
begin: blk endclass
...
run_test(“test”);
run_test();
end

endmodule: top
Command line: vsim +UVM_TESTNAME=test2
Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Use the Factory for Objects, too
class test extends uvm_test;
`uvm_component_utils(test)

virtual function void build_phase(phase);
e = my_env::type_id::create(“env”, this);
my_seq::type_id::set_type_override(my_seq2::get_type());
endfunction
endclass class my_env extends uvm_env;
virtual function void run_phase(uvm_phase phase);
rseq = my_seq::type_id::create(“rseq”);
endfunction
class my_seq2 extends my_seq;
`uvm_object_utils(my_seq2)

endclass

Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021


UVM Configuration Database
Explicitly typed Usually, a component will get
its configuration and use that to
Tied to hierarchical scopes configure its children

test
test set e.y = 4
set e.a.d.x = 4 Path Value
env
env {test .e.a.d.x} 4
get y;
set a.d.x = 3 {test.e .a.d.x} 3 set a.y = y
agent {test.e.a .d.x} 2 agent
set d.x = 2; get y;
{test.e.a.d .x} 1
set d.y = y;
driver Highest Write
get x = 2
1
4
3 Wins driver
get y = 4
Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
uvm_config_db
Uses a set/get() API
• No casting on get()
• Linked to component hierarchy

uvm_config_db #(<type>)::set(this, “<inst>”,“<field>”,


value );
uvm_config_db #(<type>)::get(this, “<inst>”,“<field>”,
value );
top.env.agent
set(this,”drv”,”vif”,vif); top.env.agent.drv
top.env.agent.drv top.env.agent.drv
get(this,””,”vif”,vif);
Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
UVM Features – uvm_config_db
For passing into Test:
ahb_if AHB(); // AHB Interface
initial begin
uvm_config_db #(virtual ahb_if)::set(null, “uvm_test_top”, “AHB”, AHB);

For passing inside UVM:


ahb_agent_config ahb_cfg;
env_config env_cfg;
function void build_phase(uvm_phase);
ahb_cfg = ahb_agent_config::type_id::create(“ahb_cfg”);
if(!uvm_config_db #(virtual ahb_if)::get(this, “”, “AHB”, ahb_cfg.AHB))
begin `uvm_error(…) end
env_cfg = env_config::type_id::create(“env_cfg”);
env_cfg.ahb_cfg = ahb_cfg;
uvm_config_db #(env_config)::set(this, “*”,
“env”, “config”,
“config”, env_cfg);
env_cfg);

Supports pattern matching
glob-style or regular expressions
Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021
Summary
Use `uvm_object/component_utils macro to register with the factory
Always call <type>::type_id::create()
Register tests with the factory
Call run_test() with null argument
• Specify which test via the command line
Use Config DB at build-time
• Components get their config before configuring children
• Highest set wins
Use Config DB at run_time
• Last set wins
• Up to the “getter” to decide when it’s legal

Unrestricted | © Siemens | Verification Academy: Advanced UVM | March 2021


Advanced UVM
Understanding the Factory
and Configuration
Tom Fitzpatrick
Strategic Verification Architect

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