@shraddha_pawankar date : 2/8/23

uvm_config_db

1) UVM_CONFIGURATION is an important feature of UVM_METHODOLOGY.

2) Supports sharing of configuration and parameters across different testbench

component.

3) It provides facility to user to customize their TB and reuse without making changes in
source code.

4) A centralized database called configuration database and it is used to store

configuration information.

5) the UVM Config DB is a powerful and flexible tool, but it should be used with care to
ensure easy maintainability and readability of your testbench code.

There are two methods in UVM_CONFIGURATION

Parameterized with set and get method

SYNTAX:

Config_db#(datatype) :: set(contx,instance name,string_field_name,value)

Config_db#(datatype) :: get(contx,instance name,string_field_name,value)

Where,
Contx: Hierarchy point
Instance_name : Hierarchy path;
String_field_name : Act like pointer for the database what we are setting value

SET METHOD :
i) Set method used in top level
ii) Set method provide visibility to lower level components
iii) Set method returns void type

GET METHOD:
@shraddha_pawankar date : 2/8/23

i) Get method used in lower level component

ii) Get method is used to access the database which was set area

iii) Get method returns bit type i.e 0 & 1.

Note :

 Execution is failed when if there is a mismatch between strings that are

setting and getting.
 Or visibility for the component is not set properly

Que 1) What is the purpose of the UVM Config DB?

We can customize the behavior of components without modifying source code.

Que 2) Can you set configuration parameters for a specific instance of a component?

Yes we can set

Ex: uvm_config_db#(virtual intf) :: set(this,”uvm_test_top_agent”,”intf”,vif)

uvm_config_db#(virtual intf) :: get(this,”uvm_test_top_agent”,”intf”,vif)

Que 3) How do you handle situations where multiple components want to set the same
configuration parameter?

Uvm_config_db follow priority based scheme

Que 4) Can you use the UVM Config DB to set configuration parameters for sequence
items and sequences?

Yes, the UVM Config DB can be used to set configuration parameters for sequence items and
sequences as well.

Que 5) Is the UVM Config DB only for setting integer parameters?

No, uvm config db is used for wide range of datatype including string,integer,Boolean,user
defined datatypes.

It automatically handles data type conversions when setting or getting configuration

parameters.

Que 6) Can you set configuration parameters for different phases in the UVM
testbench?

Yes we use different phases such as build phase or run phase

Que 7) How do you initialize the UVM Config DB before using it in a testbench?

We don’t need to define explicitely.it is automatically present in uvm library.

Que 8) Can you use the UVM Config DB outside of UVM components?
@shraddha_pawankar date : 2/8/23

No we cannot use the uvm config db outside of uvm components

It used within uvm component.

Que 9) How do you debug issues related to the UVM Config DB?

We can debug message or print statement

Que 10) Can you change configuration parameters at runtime during simulation?

Yes we can change,we can modify the behavior of components during run time.

Que 11) Can configuration parameters be overridden by command-line arguments?

Yes, we can override configuration parameters using command-line arguments when

invoking the simulator.

Que 12) Is it possible to define default configuration values for components?

Yes, we can set default values for configuration parameters in the components themselves.

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Que 13) Can configuration parameters be set during the elaboration phase of the
testbench?

No it is used in Run phase

Que 14) How do you handle situations where a configuration parameter needs to be
set differently for different test scenarios or use cases?

We can use `uvm_config_db#(T)::set method

Que 15) Can you set configuration parameters for a specific instance and its
descendants in one call?

We can use ‘*’

Example:

Uvm_config_db#(virtual intf)::get(this,”*”,”intf”,vif);

Que 16) How can you ensure that configuration parameters are set before components
start using them during simulation?

configuration parameters should be set in the test's run_phase or pre_run_phase .

Components can access their configuration parameters during the build_phase , which occurs
before the run_phase .

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Que 17) Can you set configuration parameters for virtual interfaces and channels using
the UVM Config DB?

Yes, the UVM Config DB can be used to set configuration parameters for virtual interfaces
@shraddha_pawankar date : 2/8/23

In order to share the data between multiple classes,uvm_config_db(uvm configuration

database).

//**********SET METHOD***********//
uvm_config_db#(int)::set(null, ”*” ,”k”,10);
int = datatype
null = uvm_root
“*” = visibility to allow lower level component
“k” = key(use same key while get else will fail
10 = value(which we are setting)

Set method is not returning anything i.e void function

//*******GET METHOD***********//
uvm_config_db#(int)::get(null,” ”, ”k” ,i)

int = datatype
null = uvm root
“ ” = for component class for object class ,get_full_name()
“k” = use same while get else will fail
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Base classes for set and get method

Static function void set (uvm_component contxt,

String inst_name,
String field_name,
T value);
@shraddha_pawankar date : 2/8/23

Static function bit get (uvm_component contxt,

String inst_name,

String field_name,
inout T value);

Example
`include "uvm_macros.svh" //access all uvm macros

import uvm_pkg::*; //access of uvm classes

///////////////////////////env class///////////////////////////////
Lower level component (where we are getting value)

class env extends uvm_env;

`uvm_component_utils(env)

int i;
function new(string name="",uvm_component parent);

super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);

if(!uvm_config_db#(int)::get(null,"","k",i))
`uvm_error(get_type_name(),$sformatf("getting value of i=%0d",i),UVM_NONE)
else

`uvm_info(get_type_name(),$sformatf("getting value of i=%0d",i),UVM_NONE)

endfunction
endclass
@shraddha_pawankar date : 2/8/23

////////////////////////TEST CLASS/////////////////////////
Higher level component,whivh we are setting value

class test extends uvm_test;

`uvm_component_utils(test)
env e;
function new(string name="",uvm_component parent);
super.new(name,parent);

endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);

uvm_config_db#(int)::set(null,"*","k",10); //value we are providing is 10

endfunction
endclass

/////////TOP//////////

module top;
initial
begin
run_test("test");//run all the phases

end
endmodule

Output : # KERNEL: UVM_INFO /home/runner/testbench.sv(20) @ 0:

uvm_test_top.e [env] getting value of i=10

https://www.edaplayground.com/x/8ZFz
@shraddha_pawankar date : 2/8/23

Example 2)
`include "uvm_macros.svh" //access all uvm macros
import uvm_pkg::*; //access of uvm classes

///////env class/////////

class env extends uvm_env;

`uvm_component_utils(env)

string s;
function new(string name="",uvm_component parent);
super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);

if(!uvm_config_db#(string)::get(null,"","k",s))

`uvm_error(get_type_name(),$sformatf("getting value of s=%0s",s),UVM_NONE)

else
`uvm_info(get_type_name(),$sformatf("getting value of s=%0s",s),UVM_NONE)
endfunction
endclass

//////test class//////

class test extends uvm_test;

`uvm_component_utils(test)
env e;
function new(string name="",uvm_component parent);
@shraddha_pawankar date : 2/8/23

super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
e=env::type_id::create("e",this);
uvm_config_db#(string)::set(null,"*","k","uvm"); //value we are providing is 10
endfunction

endclass
/////////TOP//////////

module top;
initial

begin
run_test("test");//run all the phases
end
endmodule

Output : # KERNEL: UVM_INFO /home/runner/testbench.sv(20) @ 0:

uvm_test_top.e [env] getting value of s=uvm
https://www.edaplayground.com/x/pSKm
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Example : 3

`include "uvm_macros.svh"
import uvm_pkg::*;

class test extends uvm_test;

`uvm_component_utils(test)
@shraddha_pawankar date : 2/8/23

int data;
function new(string name="",uvm_component parent);
super.new(name,parent);

endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
if(!uvm_config_db#(int)::get(this,"","data",data))

`uvm_info("TEST","Unable to read db",UVM_NONE)

endfunction

task run_phase(uvm_phase phase);

`uvm_info("TEST",$sformatf("value read : %0d",data),UVM_NONE)

endtask
endclass

module tb();

test t;

initial
begin
t=new("TEST",null);

uvm_config_db#(int)::set(null,"*","data",12);
run_test();
end
endmodule

output : # KERNEL: UVM_INFO /home/runner/testbench.sv(19) @ 0: TEST [TEST] value

read : 12
@shraddha_pawankar date : 2/8/23

https://www.edaplayground.com/x/nX_K
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