DataSheeT – enpirion® power solutions

EN5335QI 3A PowerSoC
Step-Down DC-DC Switching Converter with Integrated Inductor

DESCRIPTION FEATURES
The EN5335QI is an Intel® Enpirion® Power System on • Integrated INDUCTOR, MOSFETS, Controller
a Chip (PowerSoC) DC-DC converter. It is specifically
• Footprint 1/3rd that of competing solutions
designed to meet the precise voltage and fast
• Low Part Count: only 3 MLC Capacitors
transient requirements of present and future high-
performance, low-power processor, DSP, FPGA, • Up to 10W continuous output power
memory boards and system level applications in a • 5MHz operating frequency
distributed power architecture. • High efficiency, up to 93%
Advanced circuit techniques, ultra high switching • VOUT accuracy 3% over line, load and temp
frequency, and very advanced, high-density, • Wide input voltage range of 2.375V to 6.6V
integrated circuit and proprietary inductor • 3-pin VID output voltage select to choose one of
technology deliver high-quality, ultra compact, non-
7 pre-programmed voltage levels
isolated DC-DC conversion. Operating this converter
requires as few as three external components that • Output enable pin and Power OK signal
include small value input and output ceramic • Programmable soft-start time
capacitors and a soft-start capacitor. • Programmable over-current protection
The Intel Enpirion solution significantly helps in • Thermal shutdown, short circuit, and UVLO
system design and productivity by offering greatly • Output over-voltage protection
simplified board design, layout and manufacturing • RoHS compliant, MSL level 3, 260C reflow
requirements. In addition, a reduction in the number
of vendors required for the complete power solution
helps to enable an overall system cost savings. APPLICATIONS
All Intel Enpirion products are RoHS compliant and • Point of load regulation for low-power processors,
lead-free manufacturing environment compatible. network processors, DSPs, FPGAs, and ASICs
• Notebook computers, servers, workstations

VIN PVIN VS0

• Broadband, networking, LAN/WAN, optical
VID Output
AVIN
VS1
Voltage Select
• Low voltage, distributed power architectures with
22µF VS2
2.5V, 3.3V or 5V rails
POK
VSENSE
• DSL, STB, DVR, DTV, iPC
SS VOUT VOUT
• Ripple sensitive application
15nF 47µF
AGND PGND

Figure 1: Simplified Applications Circuit

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ORDERING INFORMATION
Part Number Package Markings TJ Rating Package Description
EN5335QI EN5335QI -40°C to +125°C 44-pin (7.5mm x 10mm x 1.85mm) QFN
EN5335QI-E EN5335QI QFN Evaluation Board

Packing and Marking Information: https://www.intel.com/support/quality-and-reliability/packing.html

PIN FUNCTIONS

Figure 2: Pin Diagram (Top View)

NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground or voltage. However,
they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.

NOTE B: White ‘dot’ on top left is pin 1 indicator on top of the device package.

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PIN DESCRIPTIONS
PIN NAME TYPE FUNCTION
1-3, 7,
16, 25-
NO CONNECT – Do not electrically connect these pins to each other or to
26, 30- NC -
PCB.
31, 42-
44
No Connect. These pins are internally connected to the switch node of
4-6, 15 N(SW) - the internal MOSFETs. NC(SW) pins are not to be electrically connected to
any external signal, ground, or voltage.
Regulated converter output. Connect these pins to the load and place
8-14 VOUT Power
output capacitor from these pins the PGND pins 17-18
Output power ground. Connect these pins to the ground electrode of the
17-20 PGND Power
output filter capacitors. Refer to layout guideline section.
Input power supply. Connect to input power supply. Decouple with input
21-24 PVIN Power
capacitor to PGND (pins 19-20).
This is the external feedback input pin. A resistor divider connects from
the output to AGND. The mid-point of the resistor divider is connected to
25-26 VFB Analog VFB. A feed-forward capacitor is required parallel to the upper feedback
resistor (RA). The output voltage regulation is based on the VFB node
voltage equal to 0.600V.
Optional Over Current Protection adjust pin. Place ROCP resistor
27 ROCP Analog between this pin and AGND (pin 40) to increase the over current trip point
by 50%.
Analog voltage input for the controller circuits. Connect this pin to the
28 AVIN Power
input power supply.
29 AGND Power Analog ground for the controller circuits.
32 VS2 Digital Voltage select line 2 input. See Table 1.
33 VS1 Power Voltage select line 1 input. See Table 1.
34 VS0 Ground Voltage select line 0 input. See Table 1.
Power OK is an open drain transistor for power system state indication.
35 POK Analog
POK is a logic high when VOUT is with -10% to +20% of VOUT nominal.
Remote voltage sense input. Connect this pin to the load voltage at the
36 VSENSE Analog
point to be regulated.
Soft-Start node. The soft-start capacitor is connected between this pin
37 SS Analog
and AGND. The value of this resistor determines the startup timing.
Optional Error Amplifier input. Allows for customization of the control
38 EAIN Analog
loop.
Optional Error Amplifier output. Allows for customization of the control
39 EAOUT Analog
loop.

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PIN NAME TYPE FUNCTION

Optional Error Amplifier Buffer output. Allows for customization of the
40 COMP Analog
control loop.
Input Enable. Applying a logic high, enables the output and initiates a
41 ENABLE Analog
soft-start. Applying a logic low disables the output.

ABSOLUTE MAXIMUM RATINGS

CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended
operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device
life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

Absolute Maximum Pin Ratings

PARAMETER SYMBOL MIN MAX UNITS
VIN, VOUT -0.3 7.0 V
ENABLE, VSENSE -0.3 VIN+0.3 V
VS0-VS2(1) -0.3 2.7 V

Absolute Maximum Thermal Ratings

PARAMETER CONDITION MIN MAX UNITS
Maximum Operating Junction
+150 °C
Temperature
Storage Temperature Range -65 +150 °C
Ambient Temperature Range -40 +85 °C
Reflow Peak Body Temperature (10 Sec) MSL3 JEDEC J-STD-020A +260 °C

Absolute Maximum ESD Ratings

PARAMETER CONDITION MIN MAX UNITS
HBM (Human Body Model) ±2000 V
CDM (Charged Device Model) ±500 V

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL MIN MAX UNITS
Input Voltage Range (for output voltages < 1.2V) VIN 2.375 5.5 V
Input Voltage Range (for output voltages ≥ 1.2V) VIN 2.375 6.6 V
Output Current Range IOUT 3 A
Operating Ambient Temperature Range TA -40 +85 °C
Operating Junction Temperature TJ -40 +125 °C

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THERMAL CHARACTERISTICS
PARAMETER SYMBOL TYPICAL UNITS
Thermal Shutdown TSD 150 °C
Thermal Shutdown Hysteresis TSDHYS 15 °C
Thermal Resistance: Junction to Ambient (0 LFM) θJA 25 °C/W
Thermal Resistance: Junction to Case (0 LFM) θJC 3 °C/W

ELECTRICAL CHARACTERISTICS
NOTE: VIN = 5V, Minimum and Maximum values are over operating ambient temperature range unless
otherwise noted. Typical values are at TA = 25°C.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Operating Input Voltage
(for output voltages < VIN 2.375 5.5 V
1.2V)
Operating Input Voltage
(for output voltages ≥ VIN 2.375 6.6 V
1.2V)

TA = 25C, VIN = 5.0V, ILOAD =

VOUT Initial Accuracy ∆VOUT_INIT 0A; %
-2 +2
• All VID Settings except 0.8V
• 0.8V -3 +2

Drop out voltage VIN - VOUT Drop out voltage at full load 600 mV
Shut-Down Supply
IS ENABLE=0V 100 µA
Current
Switching Frequency FOSC 5 MHz

Over line, load and

temperature

Output Voltage VID Output Voltage Setting

VOUT
Regulation (V): %
1.2, 1.25, 1.5, 1.8, 2.5, 3.3 -3.0 3.0
-4.0 4.0
0.8V
Over Current Trip Piont IOCP 4.5 A

VDISABLE Max voltage to ensure the 0.8 V

Disable Threshold
converter is disabled

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PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

2.375V ≤ VIN ≤ 5.5V 1.8

Enable Threshold VENABLE V
5.5V < VIN 2.0

Enable Pin Current IENABLE VIN = 5.5V 50 µA

VSX Logic Low Threshold voltage for Logic

VSX-Low 0.8 V
Threshold Low

Threshold voltage for Logic

High
VSX Logic High
VSX-High 1.8 VIN V
Threshold (internally pulled high; can be
left floating to achieve logic
high)

(VIN = 5.5V)
VSx = GND 50
VSX Pin Current IVSX µA
VSx = VIN 0
VSx = Open 0
POK low voltage VPOK IPOK = 4mA (sink current) 0.4 V

Max POK Voltage VPOK VIN V

(1) VS0-VS2 pins have an internal pull-up resistor, only ground potentials should be placed on them as required.

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TYPICAL PERFORMANCE CURVES

Efficiency versus Load, VIN = 5.0V Efficiency versus Load, VIN = 3.3V

Top to Bottom: VOUT = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V Top to Bottom: VOUT = 2.5V, 1.8V, 1.5V, 1.2V, 0.8V

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TYPICAL PERFORMANCE CHARACTERISTICS

Load transient, 0 – 3A, VIN/VOUT = 5.5V/1.2V Load transient, 0 – 3A, VIN/VOUT = 5.5V/3.3V

Start-up waveform, VIN/VOUT = 5.5V/1.2V Shut-down waveform, VIN/VOUT = 5.5V/1.2V

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FUNCTIONAL BLOCK DIAGRAM

POK PVIN

UVLO power
Good
Logic
Thermal Limit

ROCP Current Limit

Over
VOUT
Voltage

Over Voltage

P-Drive
VOUT

(-)
PWM N-Drive
Comp PGND
(+)

Compensation
Sawtooth Network
VSENSE
Generator

Voltage
(-)
Selector
Error
Amp VS0
(+) VS1
ENABLE VS2

Reference
SS Soft Start Voltage
selector

Bandgap
Reference

EAOUT EAIN COMP

Figure 3: Functional Block Diagram

FUNCTIONAL DESCRIPTION
Synchronous DC-DC Step-Down PowerSoC
The EN5335QI is a synchronous, pin programmable power supply with integrated power MOSFET switches
and integrated inductor. The nominal input voltage range is 2.4-5.0V. The output can be set to common pre-
set voltages by connecting appropriate combinations of 3 voltage selection pins to ground. The feedback
control loop is a type III voltage-mode and the part uses a low-noise PWM topology. Up to 3A of output current
can be drawn from this converter. The 5MHz operating frequency enables the use of small-size output
capacitors.

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The power supply has the following protection features:

• Over-current protection (to protect the IC from excessive load current)
• Thermal shutdown with hysteresis
• Over-voltage protection
• Under-voltage lockout circuit to disable the converter output when the input voltage is less than
approximately 2.2V
Additional features include:
• Soft-start circuit, limiting the in-rush current when the converter is powered up
• Power good circuit indicating whether the output voltage is within 90% - 120% of the programmed
voltage.

Output Voltage Programming

The EN5335QI output voltage is programmed using a 3-pin voltage-ID or VID selector. Three binary VID pins
allow the user to choose one of seven pre-set voltages. Refer to Table 1 for the proper VID pin settings to
choose VOUT.
The voltage select pins, VS0, VS1, and VS2, are pulled-up internally and so will default to a logic high, or “1”,
if left “open”. Connecting the voltage select pin to ground will result in a logic “0”.
Table 1: Output Voltage Select Table

VS2* VS1* VS0* Output Voltage

0 0 0 3.3V

0 0 1 2.5V

0 1 0 1.8V

0 1 1 1.5V

1 0 0 1.25V

1 0 1 1.2V

1 1 0 0.8V

1 1 1 Reserved

Input Capacitor Selection

The EN5335QI requires about 20μF of input capacitance. Low-cost, low-ESR ceramic capacitors should be
used as input capacitors for this converter. The dielectric must be X5R or X7R rated. In some applications,
lower value capacitors are needed in parallel with the larger, capacitors in order to provide high frequency
decoupling. It is recommended to use 10V rated MLCC capacitors.

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Table 2: Recommended input capacitors

Description MFG P/N

10μF, 10V, 10%, X7R, 1206 Murata GRM31CR71A106KA01L

(2 capacitors needed) Taiyo Yuden LMK316B7106KL-T

22μF, 10V, 10%, X7R, 1210 Murata GRM32ER71A226KE20L

(1 capacitor needed) Taiyo Yuden LMK325B7226KM-T

Output Capacitor Selection

The EN5335QI has been optimized for use with approximately 50μF of output capacitance. Low ESR ceramic
capacitors are required with X5R or X7R rated dielectric formulation. Y5V or equivalent dielectric formulations
must not be used as these lose capacitance with frequency, temperature and bias voltage.
Output ripple voltage is determined by the aggregate output capacitor impedance. Output impedance,
denoted as Z, is comprised of effective series resistance, ESR, and effective series inductance, ESL:
Z = ESR + ESL
Placing output capacitors in parallel reduces the impedance and will hence result in lower ripple voltage.
1 1 1 1
= + + ... +
Z Total Z1 Z 2 Zn
Table 3: Typical ripple versus capacitance is given below

Output Capacitor Typical Output Ripple (mVp-p) (as

Configuration measured on EN5335QI Evaluation Board)

1 x 47 μF 30

3 x 22 μF 15

Table 4: Recommended output capacitors

Description MFG P/N

22μF, 6.3V, 10%, X5R, 1206 Murata GRM31CR60J226KE19L

(3 capacitors needed) Taiyo Yuden JMK316BJ226KL-T

47μF, 10V, 10%, X5R, 1210 Murata GRM32ER61A476KE20L

47μF, 6.3V, 10%, X5R, 1210 AVX 12106D476KAT2A

(1 capacitor needed)

Enable Operation
The ENABLE pin provides a means to shut down the device, or enable normal operation. A logic high will enable
the converter into normal operation. When the ENABLE pin is asserted, the device will undergo a normal soft
start. A logic low will disable the converter and cause it to shut down. When Enable goes low, circuitry internal
to the device continue to operate to ensure the output voltage is gradually returned to zero and the circuits
turn off subsequently. A short low going pulse on Enable is ignored.

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Soft-Start Operation
Soft start is a method to reduce in-rush current when the device is enabled. The output voltage is ramped up
slowly upon start-up. The output rise time is controlled by choice of a soft-start capacitor, which is placed
between the SS pin (pin 37) and the AGND pin (pin 29).
Rise Time: TR = Css* 75KΩ
During start-up of the converter, the reference voltage to the error amplifier is gradually increased from zero
to its final level by an internal current source of typically 10uA. Typical soft-start rise time is 1mS to 3mS. The
rise time is measured from the time when AVIN > VUVLO and the Enable signal crosses its logic high threshold.
Typical SS capacitor values are in the range of 15nF to 50 nF.

Power-Up/Down Sequencing
During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before
AVIN. The PVIN should never be powered when AVIN is off. During power down, the AVIN should
not be powered down before the PVIN. Tying PVIN and AVIN or all three pins (AVIN, PVIN, ENABLE)
together during power up or power down meets these requirements.

Pre-Bias Start-up
The EN5335QI does not support startup into a pre-biased condition. Be sure the output capacitors are not
charged or the output of the EN5335QI is not pre-biased when the EN5335QI is first enabled.

POK Operation
The POK signal is an open drain signal from the converter indicating the output voltage is within the specified
range. The POK signal will be a logic high when the output voltage is within 90% - 120% of the programmed
output voltage. If the output voltage goes outside of this range, the POK signal will be a logic low until the
output voltage has returned to within this range. In the event of an over-voltage condition the POK signal will
go low and will remain in this condition until the output voltage has dropped to 95% of the programmed
output voltage before returning to the high state (see also: Over-Voltage Protection).

Over-Current Protection
The current limit function is achieved by sensing the current flowing through the sense P-MOSFET. When the
sensed current exceeds the current limit, both NFET and PFET switches are turned off. If the over-current
condition is removed, the over-current protection circuit will enable the PWM operation. This circuit is
designed to provide high noise immunity.
The nominal over current trip point is set to 4.5A. It is possible to increase the over-current set point by about
50% by connecting a 7.5kΩ resistor between ROCP (pin 27) and GND. The typical voltage at the ROCP pin is
0.75V.
In some cases, such as the start-up of FPGA devices, it is desirable to blank the over-current protection feature.
In order to disable over-current protection, the ROCP pin should be tied to any voltage between 2.5V and
PVIN.

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Over-Voltage Protection
When the output voltage exceeds 120% of the programmed output voltage, the PWM operation stops, the
lower N-MOSFET is turned on and the POK signal goes low. When the output voltage drops below 95% of the
programmed output voltage, normal PWM operation resumes and POK returns to its high state.

Thermal Overload Protection

Thermal shutdown will disable operation once the Junction temperature exceeds approximately 150ºC. Once
the junction temperature drops by approx 25ºC, the converter will re-start with a normal soft-start.

Input Under-voltage Lock-out

Circuitry is provided to ensure that when the input voltage is below the specified voltage range, the converter
will not start-up. Circuits for hysteresis, input de-glitch and output leading edge blanking are included to
ensure high noise immunity and prevent false tripping.

Compensation
The EN5335QI is internally compensated through the use of a type 3 compensation network and is optimized
for use with about 50μF of output capacitance and will provide excellent loop bandwidth and transient
performance for most applications. (See the section on Capacitor Selection for details on recommended
capacitor types.) Voltage mode operation provides high noise immunity at light load.
In some cases modifications to the compensation may be required. For more information, contact Intel Power
Applications support.

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LAYOUT RECOMMENDATIONS
Figure 4 shows critical components and layer 1 traces of a recommended minimum footprint EN5335QI layout.
Alternate ENABLE configurations and other small signal pins need to be connected and routed according to
specific customer application. Please see the Gerber files on the Intel website www.intel.com/enpirion for exact
dimensions and other layers. Please refer to Figure 4 while reading the layout recommendations in this section.

Figure 4: Optimized Layout Recommendations

Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as
close to the EN5335QI package as possible. They should be connected to the device with very short and wide
traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The
+V and GND traces between the capacitors and the EN5335QI should be as close to each other as possible so
that the gap between the two nodes is minimized, even under the capacitors.
Recommendation 2: Two PGND pins are dedicated to the input circuit, and two to the output circuit. The slit
in Figure 4 separating the input and output GND circuits helps minimize noise coupling between the converter
input and output switching loops.
Recommendation 3: The system ground plane should be the first layer immediately below the surface layer.
This ground plane should be continuous and un-interrupted below the converter and the input/output
capacitors. Please see the Gerber files on the Intel website www.intel.com/enpirion.
Recommendation 4: The large thermal pad underneath the component must be connected to the system
ground plane through as many vias as possible. The drill diameter of the vias should be 0.33mm, and the vias
must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm.
Do not use thermal reliefs or spokes to connect the vias to the ground plane. This connection provides the
path for heat dissipation from the converter. Please see Figures: 5, 6, and 7.
Recommendation 5: Multiple small vias (the same size as the thermal vias discussed in recommendation 4
should be used to connect ground terminal of the input capacitor and output capacitors to the system ground
plane. It is preferred to put these vias under the capacitors along the edge of the GND copper closest to the
+V copper. Please see Figure 4. These vias connect the input/output filter capacitors to the GND plane, and
help reduce parasitic inductances in the input and output current loops. If the vias cannot be placed under CIN
and COUT, then put them just outside the capacitors along the GND slit separating the two components. Do not
use thermal reliefs or spokes to connect these vias to the ground plane.

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Recommendation 6: AVIN is the power supply for the internal small-signal control circuits. It should be
connected to the input voltage at a quiet point. In Figure 4 this connection is made at the input capacitor close
to the VIN connection.
Recommendation 7: The layer 1 metal under the device must not be more than shown in Figure 4. See the
section regarding exposed metal on bottom of package. As with any switch-mode DC-DC converter, try not to
run sensitive signal or control lines underneath the converter package on other layers.
Recommendation 8: The VSENSE point should be just after the last output filter capacitor. Keep the sense
trace as short as possible in order to avoid noise coupling into the control loop.

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DESIGN CONSIDERATIONS FOR LEAD-FRAME BASED MODULES

Exposed Metal on Bottom of Package
Lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special considerations.
In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame
cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several
small pads being exposed on the bottom of the package.
Only the large thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC
board. The PCB top layer under the EN5335QI should be clear of any metal except for the large thermal pad.
The “grayed-out” area in Figure 5 represents the area that should be clear of any metal (traces, vias, or planes),
on the top layer of the PCB. Figure 6 shows the recommended PCB footprint for this device.

Figure 5. Lead-Frame exposed metal. Grey area highlights exposed metal that is not to be mechanically or
electrically connected to the PCB.

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RECOMMENDED PCB FOOTPRINT

Figure 6: EN5335QI PCB Footprint (Top View)

The solder stencil aperture for the thermal pad is shown in blue and is based on Enpirion power product manufacturing
specifications.

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PACKAGE DIMENSIONS

Figure 7: EN5335QI Package Dimensions (Bottom View)

Packing and Marking Information: https://www.intel.com/support/quality-and-reliability/packing.html

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REVISION HISTORY
Rev Date Change(s)
K Feb, 2019 Changed datasheet into Intel format.

WHERE TO GET MORE INFORMATION

For more information about Intel® and Enpirion® PowerSoCs, visit:
www.intel.com/enpirion

© 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel
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* Other marks and brands may be claimed as the property of others.

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