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12/22/2020 https://sppu.wheebox.com/WAC-3/allqusdownloadhtml.ils?testNo=5702&code=1052000&showTest=320&actForm=edit&set=1
Seat No -
Total number of questions : 60
1001147_T1 MICROPROCESSOR
Time : 1hr
Max Marks : 50
N.B
1) All questions are Multiple Choice Questions having single correct option.
2) Attempt any 50 questions out of 60.
3) Use of calculator is allowed.
4) Each question carries 1 Mark.
5) Specially abled students are allowed 20 minutes extra for examination.
6) Do not use pencils to darken answer.
7) Use only black/blue ball point pen to darken the appropriate circle.
8) No change will be allowed once the answer is marked on OMR Sheet.
9) Rough work shall not be done on OMR sheet or on question paper.
10) Darken ONLY ONE CIRCLE for each answer.
Q.no 1. The limit field of the descriptor is of
A:8
B : 16
C : 10
D : 20
Q.no 2. ESP Register is used to access ------ segment
A : Extra
B : Stack
C : Code
D : Data
Q.no 3. An interrupt breaks the execution of instructions and diverts its execution to
A : Interrupt service routine

https://sppu.wheebox.com/WAC-3/allqusdownloadhtml.ils?testNo=5702&code=1052000&showTest=320&actForm=edit&set=1 1/13
B : Counter word register
C : Execution unit
D : control unit
Q.no 4. What is stored in Task Register
A : Selector to TSS descriptor of currently executing task
B : Base address of GDT
C : Limit of GDT
D : All of the above.
Q.no 5. Segmentation Unit translates ------------------- When paging is diabled .
A : logical address to physical address
B : linear address to physical address
C : logical address to linear address
D : logical address to absolute address
Q.no 6. In I/O addressing if value in DX type is used the port range is upto ________.
A : 255
B : 256
C : 65535
D : 65536
Q.no 7. A near pointer is an offset ----- a segment
A : Outside
B : Within
C : None
D : Both
Q.no 8. In the executable segment descriptor the conforming bit comes under ___________.
A : Limit
B : Type
C : Base
D : Offset
Q.no 9. Interrupt 4 represents following exception
A : Overflow exception
B : Bounds Check exception
C : Interrupt exception
D : Divide error
Q.no 10. For a single task in protected mode, the 80386 can address the virtual memory of
A : 32 GB
B : 64 MB
C : 32 TB
D : 64TB
Q.no 11. What does segment register in 80386 hold in protected mode?
A : Segment base
B : Segment Descriptor
C : Segment selector
D : Segment Limit
Q.no 12. Which is the highest and most secure privilege level in 80386 ?
A : PL0
B : PL1
C : PL2
D : PL3
Q.no 13. Which IOPL value has highest priority?
A:0
B:1
C:2
D:3
Q.no 14. When carry flag is set?
A : If carry generated out of MSB
B : If carry generated out of D15 bit
C : If carry generated out of D3 bit
D : All of above
Q.no 15. How many descriptors can be stored in LDT at the most?
A : 8192
B : 4096
C : 1024
D : 2048
Q.no 16. The linear address is calculated by
A : effective address + segment base address
B : effective address –segment base address
C : effective address + physical address
D : effective address –physical address
Q.no 17. If CPL=0 then the processor is executing at _______________.
A : User level
B : Supervised level
C : US level
D : None of these
Q.no 18. Which bit in segment descriptor decides whether it is system or nonsystem segment?
A : S bit
B : W bit
C : G bit
D : A bit
Q.no 19. Interrupts give using INT instruction are called
A : Hardware interrupts
B : Software interrupts
C : Procedures
D : Macros
Q.no 20. In segmentation process when TI = 1 , the selector’s Index part points to the -----
A : Target segment descriptor.
B : Interrupt gate descriptor
C : LDT descriptors.
D : None of the above.
Q.no 21. Type 2 system descriptor is -----------------.
A : an LDT descriptor
B : a TSS descriptor
C : a Call gate Descriptor
D : None of given.
Q.no 22. Stack operations implicitly address operands via
A : SS:ESP
B : SS:EIP
C : GS:ESP
D : GS:EIP
Q.no 23. The privilege level of the code segment determines the
A : RPL
B : DPL
C : CPL
D : IOPL
Q.no 24. The sign bit is located in ----- in a byte.

A : bit 1
B : bit 5
C : bit 7
D : bit 4
Q.no 25. Interrupt that vectors through Trap gate
A : sets IF
B : resets IF
C : sets IOPL
D : non of above
Q.no 26. Register Names beginning with E indicates ------- bit register width
A:8
B : 16
C : 32
D : 64
Q.no 27. If the Default operation size bit, D=1, the code segment operation size selected is
A : 8 bit
B : 16 bit
C : 32 bit
D : 64 bit
Q.no 28. At the end of ISR, the instruction should be
A : END
B : ENDS
C : IRET
D : INTR
Q.no 29. The ability for tasks to have ____________ is an important aspect of 80386 protection.
A : same address spaces

B : contiguous address spaces
C : distinct address spaces
D : external address spaces
Q.no 30. In segmentation process when TI = 0 , then destination segment descriptor is fetched
from ---------------
A : GDT
B : LDT
C : IDT
D : None of above
Q.no 31. SLDT instruction is used for _________
A : Storing Local Descriptor Table
B : Storing Local Descriptor Table Register
C : Storing Local Data Table Register
D : None of above
Q.no 32. The bit that indicates whether the segment has been accessed by the CPU or not is
A : base address
B : attribute bit
C : present bit
D : granular bit
Q.no 33. The 80386 consists of
A : on-chip address translation cache
B : instruction set of predecessors with upward compatibility
C : virtual memory space of 64TB
D : all of the mentioned
Q.no 34. The NT flag indicates whether the __________ field is valid.
A : front-link
B : back-link
C : next-link
D : previous-link
Q.no 35. Paging can be speed up using --------
A : Translation look aside buffer
B : Tables
C : Memory
D : None of the above
Q.no 36. How many GDT’s are required in protected mode of 80386?
A : Minimum one
B : Only one, mandatory
C : One per task
D : None of above
Q.no 37. The INTR interrupt may be masked using the flag
A : direction flag
B : overflow flag
C : interrupt flag
D : sign flag
Q.no 38. The stack pointer (ESP) register is used to point ---------
A : Top of the stack
B : Bottom of stack
C : Middle of stack
D : None
Q.no 39. The program can reference data only within a segment in which
A : DPL <= CPL
B : DPL>=CPL
C : DPL=CPL
D : RPL=DPL
Q.no 40. Task Register contains
C : Limit of GDT
Q.no 41. The data segments defined in GDT (global descriptor table) and the LDT (local
descriptor table) can be accessed by a task with
A : privilege level 0
B : privilege level 1
C : privilege level 2
D : privilege level 3
Q.no 42. The total descriptors that the 80386 can handle is
A : 2K
B : 8K
C : 4K
D : 16K
Q.no 43. The control register that stores the 32-bit linear address, at which the previous page
fault is detected is
A : CR0
B : CR1
C : CR2
D : CR3
Q.no 44. What fields are checked by Privilege check unit of CPU ?
A : CPL
B : RPL
C : DPL
D : All of the above
Q.no 45. The TSS with a selector that has TI = 1 ________________ results in an exception.
A : Indicating the current LDT
B : Indicating the current IDT
C : Indicating the current GDT
D : Indicating the current IVT
Q.no 46. Interrupt 0 is used for following exception.
A : Divide Error
B : Debug Exception
C : Overflow exception
Q.no 47. In TSS of 80386 the field PDBR is associate with ______________.
A : static
B : dynamic
C : reserved
D : bank
Q.no 48. When hardware is accessed by reading and writing to the specific memory locations,
then it is called
A : port-mapped I/O
B : controller-mapped I/O
C : bus-mapped I/O
D : none of the mentioned
Q.no 49. The bit that is used for providing protection is
A : User/Supervisor bit
B : Read Bit
C : Write Bit
Q.no 50. which are register I/O instructions
A : IN/OUT
B : INS/OUTS
C : INSB/OUTSB
D : INC/DEC
Q.no 51. The task state segment descriptor the ‘B’ bit having bit number ___.
A:7
B:8
C:9
D : 10
Q.no 52. Once the CPL is selected, it can be changed by
A : hold
B : transferring control using system descriptors
C : transferring control using gate descriptors
D : transferring control using interrupt descriptors
A:7
B:8
C:9
D : 10
Q.no 54. The new task releases control by executing ___________.
A : IRET instruction
B : LAR instruction
C : LSL instruction
D : VERW instruction
Q.no 55. The task privilege level at the instant of execution is called
A : Descriptor privilege level (DPL)
B : Current privilege level (CPL)
C : Effective privilege level (EPL)
D : None of the mentioned
Q.no 56. I/O instructions can be executed when
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL
Q.no 57. The bits of CR3, that are always zero are
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits
Q.no 58. If the segment descriptor bit, S=0, then the descriptor is
A : data segment descriptor
B : code segment descriptor
C : system descriptor
Q.no 59. The SELECTOR field of a task gate must refer to a -----------
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor
Q.no 60. The selector RPL that uses a less trusted privilege than the current privilege level for
further use is known as
A : Least task privilege level
B : Descriptor privilege level
C : Effective privilege level
12/22/2020 https://sppu.wheebox.com/WAC-3/openanswers.obj
Answer for Question No 1. is d
Answer for Question No 2. is b
Answer for Question No 3. is a
Answer for Question No 6. is c
https://sppu.wheebox.com/WAC-3/openanswers.obj 1/4

Seat No -
Time : 1hr
Max Marks : 50
N.B
A : 32 GB
B : 64 MB
C : 32 TB
D : 64TB
Q.no 3. In instruction NOP requires ______ number of operands
A : Four
B : Two
C : Zero
D : One
A : Segment base
D : Segment Limit
Q.no 5. If ____mechanism is not enabled, then linear address is similar to physical
A : Segmentation
B : Paging
C : Both A and B
D : None of above
Q.no 6. The Interrupt handler routine returns with
A : RET instruction
B : IRET instruction
C : CALL instruction
D : JMP instruction
C : Procedures
D : Macros
A : 8 bit
B : 16 bit
C : 32 bit
D : 64 bit
A : sets IF
B : resets IF
C : sets IOPL
D : non of above
Q.no 10. The input and output operations are respectively similar to the operations,
A : read, read
B : write, write
C : read, write
D : write, read
C : Execution unit
D : control unit
A:0
B:1
C:2
D:3
D : Divide error
Q.no 14. Size of IDTR is --------- bits
A : 16
B : 32
C : 48
D : 64
Q.no 16. If the INT3 instruction is executed then which type of exception is executed?
A : Fault
B : Trigger
C : Abort
D : None of these
Q.no 17. Interrupt 1 is used for following exception
A : Divide Error
B : Debug Exception
D : None of given.
A : SS:ESP
B : SS:EIP
C : GS:ESP
D : GS:EIP
Q.no 20. When IF(Interrupt Flag) is disabled following is true
A : Procedures are disabled
B : Multitasking is disabled
C : INTR interrupts are disabled
D : . Macros are disabled
A:8
B : 16
C : 32
D : 64
A : S bit
B : W bit
C : G bit
D : A bit
Q.no 23. What is the size of segment descriptor?
A : 4 bytes
B : 2 bytes
C : 8 bytes
D : 1 byte
Q.no 24. The size of segment registers are -----------

A : 32
B:8
C : 16
D : 64
Q.no 25. Protection provided by ---------- unit can further be increased by --------- unit.
A : Segmentation, Paging
B : Paging, Segmentation
C : Segmentation, Control
D : Decode, Execution
Q.no 26. The 80386 processor can address up to -------------- memory
A : 64 KB.
B : 4 GB.
C : 1 MB
D : none of above.
A : User level
C : US level
D : None of these
Q.no 28. The IDT is a direct replacement of which table used in 8086 sys.
A : IVT
B : LDT
C : GDT
D : none of this
A:8
B : 16
C : 10
D : 20
Q.no 30. 80386DX is available in a grid array package of
A : 64 pin
B : 128 pin
C : 132 pin
D : 142 pin
A : static
B : dynamic
C : reserved
D : bank
A : Minimum one
C : One per task
D : None of above
B : Tables
C : Memory
Q.no 34. Maskable interrupts are signalled via
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
B : Read Bit
C : Write Bit
A : IN/OUT
B : INS/OUTS
C : INSB/OUTSB
D : INC/DEC
Q.no 37. When a JUMP instruction references a Task State Segment(TSS) descriptor, then DPL
must be
A : equally privileged as CPL
B : greater or equally privileged than CPL
C : less or equally privileged than CPL
D : less privileged than CPL
B : Bottom of stack
C : Middle of stack
D : None
C : Limit of GDT
A : base address
B : attribute bit
C : present bit
D : granular bit
A : CR0
B : CR1
C : CR2
D : CR3
A : direction flag
B : overflow flag
C : interrupt flag
D : sign flag
Q.no 45. Task Gate , Interrupt Gate , Trap Gate descriptors all are located in
A : IDT (Interrupt Descriptor Table)
B : GDT (Global Descriptor Table)
C : LDT (Local Descriptor Table)
D : Task Register
A : 2K
B : 8K
C : 4K
D : 16K
then it is called
A : port-mapped I/O
C : bus-mapped I/O
Q.no 49. Which of the following instruction/s is/are used for verification of pointer parameters?
A : ARPL
B : LLDT
C : LTR
D : All of above
A : Divide Error
B : Debug Exception
A : hold
A:7
B:8
C:9
D : 10
B : LAR instruction
C : LSL instruction
A:7
B:8
C:9
D : 10
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor

Seat No -
Time : 1hr
Max Marks : 50
N.B
A : read, read
B : write, write
C : read, write
D : write, read

from ---------------
A : GDT
B : LDT
C : IDT
D : None of above
Q.no 4. Length of the GDT is ------------.
A : fixed
B : 64 KB
C : between 8 bytes to 64 Kbytes
D : 8KB
A : Outside
B : Within
C : None
D : Both
A : Extra
B : Stack
C : Code
D : Data
Q.no 7. PG bit is present in -------
A : CR0
B : CR1
C : CR2
D : CR3
A : sets IF
B : resets IF
C : sets IOPL
D : non of above
A : IVT
B : LDT
C : GDT
D : none of this
A : RET instruction
D : JMP instruction
A : Limit
B : Type
C : Base
D : Offset
D : None of given.
A : Divide Error
B : Debug Exception
A : 8192
B : 4096
C : 1024
D : 2048
A : 4 bytes
B : 2 bytes
C : 8 bytes
D : 1 byte
A : Segmentation
B : Paging
C : Both A and B
D : None of above
Q.no 19. Which of the following is not a scale factor of addressing modes of 80386?
A:2
B:4
C:6
D:8
C : Procedures
D : Macros
Q.no 21. Which of the following is a special purpose reg. in 80386 ?
A : EIP
B : ESP
C : EFLAGS
D : ALL
A : 8 bit
B : 16 bit
C : 32 bit
D : 64 bit
A:8
B : 16
C : 32
D : 64
A : bit 1
B : bit 5
C : bit 7
D : bit 4
A : User level
C : US level
D : None of these
Q.no 26. Faults are
A : maskable interrupts
B : Non maskable interrupts
C : exceptions
D : traps
A : Fault
B : Trigger
C : Abort
D : None of these
A : PL0
B : PL1
C : PL2
D : PL3
A : RPL
B : DPL
C : CPL
D : IOPL
D : None of above
B : Tables
C : Memory
A : DPL <= CPL
B : DPL>=CPL
C : DPL=CPL
D : RPL=DPL
A : direction flag
B : overflow flag
C : interrupt flag
D : sign flag
B : Bottom of stack
C : Middle of stack
D : None
A : 2K
B : 8K
C : 4K
D : 16K
C : Limit of GDT
A : Minimum one
C : One per task
D : None of above

D : Task Register
A : static
B : dynamic
C : reserved
D : bank
B : Read Bit
C : Write Bit
A : front-link
B : back-link
C : next-link
D : previous-link
A : Divide Error
B : Debug Exception
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
A : IN/OUT
B : INS/OUTS
C : INSB/OUTSB
D : INC/DEC
then it is called
A : port-mapped I/O
C : bus-mapped I/O
A : CR0
B : CR1
C : CR2
D : CR3
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL
A : hold
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits
A:7
B:8
C:9
D : 10
B : LAR instruction
C : LSL instruction
A:7
B:8
C:9
D : 10

Seat No -
Time : 1hr
Max Marks : 50
N.B
Q.no 1. The prefetch unit permits 80386DX to prefetch upto …………….. bytes of instruction
code.
A:6
B:8
C : 16
D : 20
A : Divide Error
B : Debug Exception
A : 16
B : 32
C : 48
D : 64
A : User level
C : US level
D : None of these
A : RPL
B : DPL
C : CPL
D : IOPL
A : Fault
B : Trigger
C : Abort
D : None of these
A : S bit
B : W bit
C : G bit
D : A bit
A : 64 pin
B : 128 pin
C : 132 pin
D : 142 pin
A:8
B : 16
C : 32
D : 64
A : 32
B:8
C : 16
D : 64
A : sets IF
B : resets IF
C : sets IOPL
D : non of above

A:0
B:1
C:2
D:3
A : 8 bit
B : 16 bit
C : 32 bit
D : 64 bit
Q.no 16. What is stored in Task State Segment
A : General purpose registers
B : Segment registers
C : Flag registers
A : bit 1
B : bit 5
C : bit 7
D : bit 4
A : END
B : ENDS
C : IRET
D : INTR
A : PL0
B : PL1
C : PL2
D : PL3
A : 32 GB
B : 64 MB
C : 32 TB
D : 64TB
A : fixed
B : 64 KB
D : 8KB
C : Limit of GDT

A : Outside
B : Within
C : None
D : Both
Q.no 25. The Applications are related with __________ privilege level
A : Level 0
B : Level 1
C : Level 2
D : Level 3
A : 64 KB.
B : 4 GB.
C : 1 MB
D : none of above.
D : All of above
A : Limit
B : Type
C : Base
D : Offset

D : None of given.
A : 4 bytes
B : 2 bytes
C : 8 bytes
D : 1 byte
then it is called
A : port-mapped I/O
C : bus-mapped I/O
A : CR0
B : CR1
C : CR2
D : CR3
A : direction flag
B : overflow flag
C : interrupt flag
D : sign flag
D : None of above
B : Read Bit
C : Write Bit
C : Limit of GDT
must be
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
A : IN/OUT
B : INS/OUTS
C : INSB/OUTSB
D : INC/DEC
A : ARPL
B : LLDT
C : LTR
D : All of above
A : Divide Error
B : Debug Exception
B : Bottom of stack
C : Middle of stack
D : None
A : static
B : dynamic
C : reserved
D : bank
A : base address
B : attribute bit
C : present bit
D : granular bit
D : Task Register
A : 2K
B : 8K
C : 4K
D : 16K
B : Tables
C : Memory
A:7
B:8
C:9
D : 10
A : hold
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor
B : LAR instruction
C : LSL instruction
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL
A:7
B:8
C:9
D : 10
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits

Seat No -
Time : 1hr
Max Marks : 50
N.B
A : 32 GB
B : 64 MB
C : 32 TB
D : 64TB
A : fixed
B : 64 KB
D : 8KB

A : PL0
B : PL1
C : PL2
D : PL3
A : Four
B : Two
C : Zero
D : One
Q.no 6. Following are components of Memory Management unit.
A : Decode and Execute
B : Segmentation and Paging
C : Fetch and Control
D : All of above
Q.no 7. Faults are
C : exceptions
D : traps

A : S bit
B : W bit
C : G bit
D : A bit
A : Segment base
D : Segment Limit
A : RPL
B : DPL
C : CPL
D : IOPL
Q.no 12. If DF= -------- ,string instruction will automatically increment Pointers.
A:1
B:2
C:3
D:0
A : EIP
B : ESP
C : EFLAGS
D : ALL
A : 64 KB.
B : 4 GB.
C : 1 MB
D : none of above.
A : Outside
B : Within
C : None
D : Both
A : Divide Error
B : Debug Exception
A:8
B : 16
C : 32
D : 64

A : 8 bit
B : 16 bit
C : 32 bit
D : 64 bit
A : 255
B : 256
C : 65535
D : 65536
A : bit 1
B : bit 5
C : bit 7
D : bit 4
A : IVT
B : LDT
C : GDT
D : none of this
A:0
B:1
C:2
D:3

C : Procedures
D : Macros
D : Divide error
A : 4 bytes
B : 2 bytes
C : 8 bytes
D : 1 byte
A : 16
B : 32
C : 48
D : 64
A : CR0
B : CR1
C : CR2
D : CR3
A : read, read
B : write, write
C : read, write
D : write, read
A : DPL <= CPL
B : DPL>=CPL
C : DPL=CPL
D : RPL=DPL
then it is called
A : port-mapped I/O
C : bus-mapped I/O
A : Divide Error
B : Debug Exception
B : Tables
C : Memory
B : Bottom of stack
C : Middle of stack
D : None
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
A : base address
B : attribute bit
C : present bit
D : granular bit
must be
D : Task Register
A : front-link
B : back-link
C : next-link
D : previous-link
A : ARPL
B : LLDT
C : LTR
D : All of above
D : None of above
C : Limit of GDT
A : CR0
B : CR1
C : CR2
D : CR3
A : static
B : dynamic
C : reserved
D : bank
A : direction flag
B : overflow flag
C : interrupt flag
D : sign flag
A : 2K
B : 8K
C : 4K
D : 16K
A : CPL
B : RPL
C : DPL
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL
A : hold
A:7
B:8
C:9
D : 10
B : LAR instruction
C : LSL instruction
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor

A:7
B:8
C:9
D : 10

Seat No -
Time : 1hr
Max Marks : 50
N.B

from ---------------
A : GDT
B : LDT
C : IDT
D : None of above
A : Divide Error
B : Debug Exception
A : Four
B : Two
C : Zero
D : One
C : Limit of GDT
A : RET instruction
D : JMP instruction
A : 32
B:8
C : 16
D : 64
A : 64 KB.
B : 4 GB.
C : 1 MB
D : none of above.
A : 16
B : 32
C : 48
D : 64
A : Segment base
D : Segment Limit
D : All of above
A : bit 1
B : bit 5
C : bit 7
D : bit 4
A : 32 GB
B : 64 MB
C : 32 TB
D : 64TB

D : All of above
A:8
B : 16
C : 32
D : 64
A : END
B : ENDS
C : IRET
D : INTR
A : Outside
B : Within
C : None
D : Both
A : PL0
B : PL1
C : PL2
D : PL3
C : Procedures
D : Macros
A : 4 bytes
B : 2 bytes
C : 8 bytes
D : 1 byte
A : User level
C : US level
D : None of these
A : 255
B : 256
C : 65535
D : 65536
A : Level 0
B : Level 1
C : Level 2
D : Level 3
A : fixed
B : 64 KB
D : 8KB
D : None of given.
A:1
B:2
C:3
D:0
Q.no 27. Faults are
C : exceptions
D : traps
A : RPL
B : DPL
C : CPL
D : IOPL

A : SS:ESP
B : SS:EIP
C : GS:ESP
D : GS:EIP
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
A : IN/OUT
B : INS/OUTS
C : INSB/OUTSB
D : INC/DEC
A : CPL
B : RPL
C : DPL

B : Bottom of stack
C : Middle of stack
D : None
A : DPL <= CPL
B : DPL>=CPL
C : DPL=CPL
D : RPL=DPL
A : Minimum one
C : One per task
D : None of above
then it is called
A : port-mapped I/O
C : bus-mapped I/O
B : Tables
C : Memory
A : Divide Error
B : Debug Exception
A : base address
B : attribute bit
C : present bit
D : granular bit
A : front-link
B : back-link
C : next-link
D : previous-link
must be
A : direction flag
B : overflow flag
C : interrupt flag
D : sign flag
C : Limit of GDT
A : static
B : dynamic
C : reserved
D : bank
A : CR0
B : CR1
C : CR2
D : CR3
A : ARPL
B : LLDT
C : LTR
D : All of above
B : Read Bit
C : Write Bit
A:7
B:8
C:9
D : 10
A : hold
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits
A:7
B:8
C:9
D : 10
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL
B : LAR instruction
C : LSL instruction

Seat No -
Time : 1hr
Max Marks : 50
N.B
A : RET instruction
D : JMP instruction
A : fixed
B : 64 KB
D : 8KB
A : Divide Error
B : Debug Exception
A : 4 bytes
B : 2 bytes
C : 8 bytes
D : 1 byte
A : RPL
B : DPL
C : CPL
D : IOPL
C : Procedures
D : Macros
A : 8192
B : 4096
C : 1024
D : 2048
A:1
B:2
C:3
D:0
A : CR0
B : CR1
C : CR2
D : CR3
A : 64 KB.
B : 4 GB.
C : 1 MB
D : none of above.
A : Segmentation
B : Paging
C : Both A and B
D : None of above
A : Extra
B : Stack
C : Code
D : Data
Q.no 14. Faults are
C : exceptions
D : traps
C : Flag registers
A : Outside
B : Within
C : None
D : Both
A : END
B : ENDS
C : IRET
D : INTR
A : 16
B : 32
C : 48
D : 64
A : 32
B:8
C : 16
D : 64
A : sets IF
B : resets IF
C : sets IOPL
D : non of above
D : All of above
A : 8 bit
B : 16 bit
C : 32 bit
D : 64 bit

A : EIP
B : ESP
C : EFLAGS
D : ALL
A:8
B : 16
C : 10
D : 20
from ---------------
A : GDT
B : LDT
C : IDT
D : None of above
A : Four
B : Two
C : Zero
D : One
A : 255
B : 256
C : 65535
D : 65536
A : IVT
B : LDT
C : GDT
D : none of this
D : Divide error
A : IN/OUT
B : INS/OUTS
C : INSB/OUTSB
D : INC/DEC
A : 2K
B : 8K
C : 4K
D : 16K
D : None of above

A : ARPL
B : LLDT
C : LTR
D : All of above
A : base address
B : attribute bit
C : present bit
D : granular bit
then it is called
A : port-mapped I/O
C : bus-mapped I/O
A : DPL <= CPL
B : DPL>=CPL
C : DPL=CPL
D : RPL=DPL
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
B : Bottom of stack
C : Middle of stack
D : None
C : Limit of GDT
A : static
B : dynamic
C : reserved
D : bank
A : Divide Error
B : Debug Exception
B : Read Bit
C : Write Bit
B : Tables
C : Memory
A : front-link
B : back-link
C : next-link
D : previous-link
A : direction flag
B : overflow flag
C : interrupt flag
D : sign flag
A : CPL
B : RPL
C : DPL
A:7
B:8
C:9
D : 10
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor
A:7
B:8
C:9
D : 10
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits
B : LAR instruction
C : LSL instruction
A : hold

Seat No -
Time : 1hr
Max Marks : 50
N.B
A:2
B:4
C:6
D:8
A : 16
B : 32
C : 48
D : 64
A : 64 KB.
B : 4 GB.
C : 1 MB
D : none of above.
A : RET instruction
D : JMP instruction
A : sets IF
B : resets IF
C : sets IOPL
D : non of above
A : Fault
B : Trigger
C : Abort
D : None of these
A:8
B : 16
C : 10
D : 20
A : 4 bytes
B : 2 bytes
C : 8 bytes
D : 1 byte
D : None of given.
A : Outside
B : Within
C : None
D : Both
A : Segment base
D : Segment Limit
from ---------------
A : GDT
B : LDT
C : IDT
D : None of above
A : SS:ESP
B : SS:EIP
C : GS:ESP
D : GS:EIP
A : 255
B : 256
C : 65535
D : 65536
A : Extra
B : Stack
C : Code
D : Data
C : Procedures
D : Macros
A : 32
B:8
C : 16
D : 64
A : CR0
B : CR1
C : CR2
D : CR3
C : Limit of GDT
D : All of above
D : Divide error
A:1
B:2
C:3
D:0
A : PL0
B : PL1
C : PL2
D : PL3
A : 8 bit
B : 16 bit
C : 32 bit
D : 64 bit
code.
A:6
B:8
C : 16
D : 20
A:8
B : 16
C : 32
D : 64
A : Segmentation
B : Paging
C : Both A and B
D : None of above
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
B : Read Bit
C : Write Bit
A : 2K
B : 8K
C : 4K
D : 16K
A : base address
B : attribute bit
C : present bit
D : granular bit
A : ARPL
B : LLDT
C : LTR
D : All of above
A : direction flag
B : overflow flag
C : interrupt flag
D : sign flag
A : IN/OUT
B : INS/OUTS
C : INSB/OUTSB
D : INC/DEC
A : Minimum one
C : One per task
D : None of above
must be
A : CPL
B : RPL
C : DPL
A : CR0
B : CR1
C : CR2
D : CR3
D : None of above
C : Limit of GDT
A : DPL <= CPL
B : DPL>=CPL
C : DPL=CPL
D : RPL=DPL
B : Bottom of stack
C : Middle of stack
D : None

B : Tables
C : Memory
A : front-link
B : back-link
C : next-link
D : previous-link
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor
A:7
B:8
C:9
D : 10
A:7
B:8
C:9
D : 10
B : LAR instruction
C : LSL instruction
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL
A : hold


Seat No -
Time : 1hr
Max Marks : 50
N.B
A:1
B:2
C:3
D:0
A : Segmentation
B : Paging
C : Both A and B
D : None of above

C : Flag registers
A:2
B:4
C:6
D:8
A : Segment base
D : Segment Limit
C : Procedures
D : Macros
A : Limit
B : Type
C : Base
D : Offset
D : All of above
A : Extra
B : Stack
C : Code
D : Data
A : 32 GB
B : 64 MB
C : 32 TB
D : 64TB

A : RPL
B : DPL
C : CPL
D : IOPL
A : read, read
B : write, write
C : read, write
D : write, read
C : Execution unit
D : control unit
A : Divide Error
B : Debug Exception

A:8
B : 16
C : 32
D : 64
A : 64 KB.
B : 4 GB.
C : 1 MB
D : none of above.
A : S bit
B : W bit
C : G bit
D : A bit
code.
A:6
B:8
C : 16
D : 20
A : SS:ESP
B : SS:EIP
C : GS:ESP
D : GS:EIP
A : Level 0
B : Level 1
C : Level 2
D : Level 3
A : CR0
B : CR1
C : CR2
D : CR3
A:0
B:1
C:2
D:3

A : Four
B : Two
C : Zero
D : One
A : RET instruction
D : JMP instruction
A : IN/OUT
B : INS/OUTS
C : INSB/OUTSB
D : INC/DEC
B : Bottom of stack
C : Middle of stack
D : None
A : base address
B : attribute bit
C : present bit
D : granular bit
A : CR0
B : CR1
C : CR2
D : CR3
B : Read Bit
C : Write Bit
D : None of above
A : ARPL
B : LLDT
C : LTR
D : All of above
must be
then it is called
A : port-mapped I/O
C : bus-mapped I/O
B : Tables
C : Memory
A : static
B : dynamic
C : reserved
D : bank
A : front-link
B : back-link
C : next-link
D : previous-link
A : DPL <= CPL
B : DPL>=CPL
C : DPL=CPL
D : RPL=DPL
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
A : Minimum one
C : One per task
D : None of above
C : Limit of GDT
A : CPL
B : RPL
C : DPL
D : Task Register
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor
A:7
B:8
C:9
D : 10
A : hold

A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits
B : LAR instruction
C : LSL instruction
A:7
B:8
C:9
D : 10
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL

Seat No -
Time : 1hr
Max Marks : 50
N.B
code.
A:6
B:8
C : 16
D : 20
A : Outside
B : Within
C : None
D : Both
A : 64 pin
B : 128 pin
C : 132 pin
D : 142 pin
A : EIP
B : ESP
C : EFLAGS
D : ALL
C : Procedures
D : Macros
A : Limit
B : Type
C : Base
D : Offset
D : Divide error

D : All of above
A : 32 GB
B : 64 MB
C : 32 TB
D : 64TB
A : Level 0
B : Level 1
C : Level 2
D : Level 3
A:1
B:2
C:3
D:0
A : read, read
B : write, write
C : read, write
D : write, read
A:8
B : 16
C : 32
D : 64
A : S bit
B : W bit
C : G bit
D : A bit
A : Four
B : Two
C : Zero
D : One
A : CR0
B : CR1
C : CR2
D : CR3

A : fixed
B : 64 KB
D : 8KB
A : RPL
B : DPL
C : CPL
D : IOPL
D : All of above
A : END
B : ENDS
C : IRET
D : INTR
D : None of given.
A : IVT
B : LDT
C : GDT
D : none of this
A : 64 KB.
B : 4 GB.
C : 1 MB
D : none of above.
C : Execution unit
D : control unit
A : bit 1
B : bit 5
C : bit 7
D : bit 4
A:2
B:4
C:6
D:8
A : Divide Error
B : Debug Exception
C : Limit of GDT
A : 2K
B : 8K
C : 4K
D : 16K
A : DPL <= CPL

B : DPL>=CPL
C : DPL=CPL
D : RPL=DPL
A : CPL
B : RPL
C : DPL
A : IN/OUT
B : INS/OUTS
C : INSB/OUTSB
D : INC/DEC
A : static
B : dynamic
C : reserved
D : bank
A : Minimum one
C : One per task
D : None of above
then it is called
A : port-mapped I/O
C : bus-mapped I/O
A : direction flag
B : overflow flag
C : interrupt flag
D : sign flag
D : Task Register
B : Read Bit
C : Write Bit
A : front-link
B : back-link
C : next-link
D : previous-link
A : ARPL
B : LLDT
C : LTR
D : All of above
A : CR0
B : CR1
C : CR2
D : CR3
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
A : base address
B : attribute bit
C : present bit
D : granular bit
B : Bottom of stack
C : Middle of stack
D : None
D : None of above
B : LAR instruction
C : LSL instruction
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL
A:7
B:8
C:9
D : 10

A : hold
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor
A:7
B:8
C:9
D : 10


Seat No -
Time : 1hr
Max Marks : 50
N.B
A : Limit
B : Type
C : Base
D : Offset
A : Divide Error
B : Debug Exception
A:0
B:1
C:2
D:3
A : RPL
B : DPL
C : CPL
D : IOPL
A : 8 bit
B : 16 bit
C : 32 bit
D : 64 bit
A : Fault
B : Trigger
C : Abort
D : None of these

A : IVT
B : LDT
C : GDT
D : none of this
A : END
B : ENDS
C : IRET
D : INTR
A : fixed
B : 64 KB
D : 8KB
A : Outside
B : Within
C : None
D : Both
A : bit 1
B : bit 5
C : bit 7
D : bit 4
A : SS:ESP
B : SS:EIP
C : GS:ESP
D : GS:EIP
A : Extra
B : Stack
C : Code
D : Data
A : Segmentation
B : Paging
C : Both A and B
D : None of above
A : 32 GB
B : 64 MB
C : 32 TB
D : 64TB

Q.no 19. Faults are
C : exceptions
D : traps
D : Divide error
C : Procedures
D : Macros
A : S bit
B : W bit
C : G bit
D : A bit
A : Four
B : Two
C : Zero
D : One
A:8
B : 16
C : 32
D : 64
C : Limit of GDT
code.
A:6
B:8
C : 16
D : 20
A : sets IF
B : resets IF
C : sets IOPL
D : non of above
D : None of given.
A : 64 pin
B : 128 pin
C : 132 pin
D : 142 pin
B : Bottom of stack
C : Middle of stack
D : None
A : CR0
B : CR1
C : CR2
D : CR3
A : direction flag
B : overflow flag
C : interrupt flag
D : sign flag
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
then it is called
A : port-mapped I/O
C : bus-mapped I/O
D : Task Register
A : static
B : dynamic
C : reserved
D : bank
must be
A : CPL
B : RPL
C : DPL
B : Read Bit
C : Write Bit
A : base address
B : attribute bit
C : present bit
D : granular bit
A : Divide Error
B : Debug Exception
A : ARPL
B : LLDT
C : LTR
D : All of above
B : Tables
C : Memory
A : Minimum one
C : One per task
D : None of above
D : None of above
A : DPL <= CPL
B : DPL>=CPL
C : DPL=CPL
D : RPL=DPL
A : 2K
B : 8K
C : 4K
D : 16K
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits

A : hold
A:7
B:8
C:9
D : 10
A:7
B:8
C:9
D : 10
B : LAR instruction
C : LSL instruction

Seat No -
Time : 1hr
Max Marks : 50
N.B
A:0
B:1
C:2
D:3
A : CR0
B : CR1
C : CR2
D : CR3
A : Segment base
D : Segment Limit
A : RET instruction
D : JMP instruction
A : 32 GB
B : 64 MB
C : 32 TB
D : 64TB
A : Outside
B : Within
C : None
D : Both
A : Extra
B : Stack
C : Code
D : Data
A : EIP
B : ESP
C : EFLAGS
D : ALL
A : Fault
B : Trigger
C : Abort
D : None of these
A : User level
C : US level
D : None of these
A : S bit
B : W bit
C : G bit
D : A bit

D : All of above
C : Flag registers
A : read, read
B : write, write
C : read, write
D : write, read
A : fixed
B : 64 KB
D : 8KB
A : END
B : ENDS
C : IRET
D : INTR
A : sets IF
B : resets IF
C : sets IOPL
D : non of above
A:2
B:4
C:6
D:8
A : 64 KB.
B : 4 GB.
C : 1 MB
D : none of above.
A:8
B : 16
C : 32
D : 64
A : IVT
B : LDT
C : GDT
D : none of this
code.
A:6
B:8
C : 16
D : 20
D : All of above
A : 8192
B : 4096
C : 1024
D : 2048
from ---------------
A : GDT
B : LDT
C : IDT
D : None of above
A:8
B : 16
C : 10
D : 20
A : 255
B : 256
C : 65535
D : 65536
A : static
B : dynamic
C : reserved
D : bank
A : direction flag
B : overflow flag
C : interrupt flag
D : sign flag
B : Tables
C : Memory
A : front-link
B : back-link
C : next-link
D : previous-link
A : base address
B : attribute bit
C : present bit
D : granular bit
B : Bottom of stack
C : Middle of stack
D : None
must be
A : CPL
B : RPL
C : DPL
A : 2K
B : 8K
C : 4K
D : 16K
C : Limit of GDT
A : DPL <= CPL
B : DPL>=CPL
C : DPL=CPL
D : RPL=DPL
A : CR0
B : CR1
C : CR2
D : CR3
A : Minimum one
C : One per task
D : None of above
B : Read Bit
C : Write Bit
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
A : IN/OUT
B : INS/OUTS
C : INSB/OUTSB
D : INC/DEC
D : None of above
A:7
B:8
C:9
D : 10
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits

B : LAR instruction
C : LSL instruction
A : hold
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor
A:7
B:8
C:9
D : 10

Seat No -
Time : 1hr
Max Marks : 50
N.B
D : All of above
A : Divide Error
B : Debug Exception
A : Limit
B : Type
C : Base
D : Offset
A : sets IF
B : resets IF
C : sets IOPL
D : non of above
A : 8 bit
B : 16 bit
C : 32 bit
D : 64 bit
A : Extra
B : Stack
C : Code
D : Data
A : Fault
B : Trigger
C : Abort
D : None of these
A : END
B : ENDS
C : IRET
D : INTR
A : Four
B : Two
C : Zero
D : One
Q.no 10. Faults are
C : exceptions
D : traps
C : Limit of GDT
A : Level 0
B : Level 1
C : Level 2
D : Level 3
A:1
B:2
C:3
D:0
A : 32 GB
B : 64 MB
C : 32 TB
D : 64TB
A : 255
B : 256
C : 65535
D : 65536
A : 32
B:8
C : 16
D : 64
A : Segment base
D : Segment Limit
D : Divide error
A : S bit
B : W bit
C : G bit
D : A bit
A : CR0
B : CR1
C : CR2
D : CR3
A:2
B:4
C:6
D:8
A:8
B : 16
C : 32
D : 64
A : Segmentation
B : Paging
C : Both A and B
D : None of above
A:8
B : 16
C : 10
D : 20
code.
A:6
B:8
C : 16
D : 20
A : IVT
B : LDT
C : GDT
D : none of this
A : bit 1
B : bit 5
C : bit 7
D : bit 4
D : None of above
B : Bottom of stack
C : Middle of stack
D : None
A : Minimum one
C : One per task
D : None of above

D : Task Register
must be
A : CR0
B : CR1
C : CR2
D : CR3
A : IN/OUT
B : INS/OUTS
C : INSB/OUTSB
D : INC/DEC
B : Read Bit
C : Write Bit
A : ARPL
B : LLDT
C : LTR
D : All of above
then it is called
A : port-mapped I/O
C : bus-mapped I/O
A : front-link
B : back-link
C : next-link
D : previous-link
C : Limit of GDT
A : CPL
B : RPL
C : DPL
A : base address
B : attribute bit
C : present bit
D : granular bit
A : direction flag
B : overflow flag
C : interrupt flag
D : sign flag
A : static
B : dynamic
C : reserved
D : bank
A : 2K
B : 8K
C : 4K
D : 16K
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits
A:7
B:8
C:9
D : 10
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL
A : hold
B : LAR instruction
C : LSL instruction
A:7
B:8
C:9
D : 10

Seat No -
Time : 1hr
Max Marks : 50
N.B
A:8
B : 16
C : 10
D : 20
A:2
B:4
C:6
D:8
A : User level
C : US level
D : None of these
A : Outside
B : Within
C : None
D : Both
A : 255
B : 256
C : 65535
D : 65536
A : 16
B : 32
C : 48
D : 64
A : fixed
B : 64 KB
D : 8KB
A:1
B:2
C:3
D:0
A : 8 bit
B : 16 bit
C : 32 bit
D : 64 bit
A : RET instruction
D : JMP instruction
A : read, read
B : write, write
C : read, write
D : write, read
A : Extra
B : Stack
C : Code
D : Data
A : sets IF
B : resets IF
C : sets IOPL
D : non of above
A : Segmentation
B : Paging
C : Both A and B
D : None of above
A:8
B : 16
C : 32
D : 64
C : Procedures
D : Macros
A : 4 bytes
B : 2 bytes
C : 8 bytes
D : 1 byte
code.
A:6
B:8
C : 16
D : 20
D : All of above
A : bit 1
B : bit 5
C : bit 7
D : bit 4
A : 64 KB.
B : 4 GB.
C : 1 MB
D : none of above.
A : Fault
B : Trigger
C : Abort
D : None of these
A : 64 pin
B : 128 pin
C : 132 pin
D : 142 pin
A : Four
B : Two
C : Zero
D : One

A:0
B:1
C:2
D:3
A : SS:ESP
B : SS:EIP
C : GS:ESP
D : GS:EIP
A : 2K
B : 8K
C : 4K
D : 16K
A : base address
B : attribute bit
C : present bit
D : granular bit
A : CR0
B : CR1
C : CR2
D : CR3
D : None of above
B : Read Bit
C : Write Bit
A : DPL <= CPL
B : DPL>=CPL
C : DPL=CPL
D : RPL=DPL
B : Bottom of stack
C : Middle of stack
D : None
A : front-link
B : back-link
C : next-link
D : previous-link
A : Divide Error
B : Debug Exception
C : Limit of GDT
B : Tables
C : Memory
A : Minimum one
C : One per task
D : None of above
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
then it is called
A : port-mapped I/O
C : bus-mapped I/O
A : CPL
B : RPL
C : DPL
A : direction flag
B : overflow flag
C : interrupt flag
D : sign flag
D : Task Register
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits
A : hold

A : TSS
B : base address
C : Segment Limit
D : TSS descriptor
B : LAR instruction
C : LSL instruction
A:7
B:8
C:9
D : 10
A:7
B:8
C:9
D : 10

Seat No -
Time : 1hr
Max Marks : 50
N.B
A : bit 1
B : bit 5
C : bit 7
D : bit 4
A : PL0
B : PL1
C : PL2
D : PL3
A : User level
C : US level
D : None of these
A : 8192
B : 4096
C : 1024
D : 2048
A : END
B : ENDS
C : IRET
D : INTR
A : 64 pin
B : 128 pin
C : 132 pin
D : 142 pin
A:2
B:4
C:6
D:8

from ---------------
A : GDT
B : LDT
C : IDT
D : None of above
A : S bit
B : W bit
C : G bit
D : A bit
A : 32
B:8
C : 16
D : 64
A : Segmentation
B : Paging
C : Both A and B
D : None of above
A : RPL
B : DPL
C : CPL
D : IOPL
C : Procedures
D : Macros
A : Fault
B : Trigger
C : Abort
D : None of these
A:8
B : 16
C : 10
D : 20
code.
A:6
B:8
C : 16
D : 20
D : None of given.
D : All of above
A : 8 bit
B : 16 bit
C : 32 bit
D : 64 bit

A:1
B:2
C:3
D:0
A : Segment base
D : Segment Limit
A : Level 0
B : Level 1
C : Level 2
D : Level 3
A:0
B:1
C:2
D:3
A : 255
B : 256
C : 65535
D : 65536
A : Extra
B : Stack
C : Code
D : Data
A : fixed
B : 64 KB
D : 8KB
A : front-link
B : back-link
C : next-link
D : previous-link
A : base address
B : attribute bit
C : present bit
D : granular bit
A : static
B : dynamic
C : reserved
D : bank
A : direction flag
B : overflow flag
C : interrupt flag
D : sign flag
B : Read Bit
C : Write Bit
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
B : Bottom of stack
C : Middle of stack
D : None
A : ARPL
B : LLDT
C : LTR
D : All of above

C : Limit of GDT
then it is called
A : port-mapped I/O
C : bus-mapped I/O
D : None of above
must be
B : Tables
C : Memory
A : Divide Error
B : Debug Exception
A : Minimum one
C : One per task
D : None of above
A : CPL
B : RPL
C : DPL
D : Task Register
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor
A : hold
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits
B : LAR instruction
C : LSL instruction
A:7
B:8
C:9
D : 10
A:7
B:8
C:9
D : 10
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL

Seat No -
Time : 1hr
Max Marks : 50
N.B
A : 64 pin
B : 128 pin
C : 132 pin
D : 142 pin
A:0
B:1
C:2
D:3
A:2
B:4
C:6
D:8
A:8
B : 16
C : 32
D : 64
A : 8 bit
B : 16 bit
C : 32 bit
D : 64 bit
code.
A:6
B:8
C : 16
D : 20
D : All of above
C : Execution unit
D : control unit
C : Limit of GDT
A : Extra
B : Stack
C : Code
D : Data
A : END
B : ENDS
C : IRET
D : INTR
A:1
B:2
C:3
D:0

D : Divide error
A : RET instruction
D : JMP instruction
C : Flag registers
A : 64 KB.
B : 4 GB.
C : 1 MB
D : none of above.
A : CR0
B : CR1
C : CR2
D : CR3
A : 255
B : 256
C : 65535
D : 65536
A : Four
B : Two
C : Zero
D : One
A : Fault
B : Trigger
C : Abort
D : None of these
A : Outside
B : Within
C : None
D : Both
A : Divide Error
B : Debug Exception
A : EIP
B : ESP
C : EFLAGS
D : ALL
A : 32 GB
B : 64 MB
C : 32 TB
D : 64TB
A : SS:ESP
B : SS:EIP
C : GS:ESP
D : GS:EIP
A : Segment base
D : Segment Limit
A : read, read
B : write, write
C : read, write
D : write, read
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
D : Task Register
A : DPL <= CPL
B : DPL>=CPL
C : DPL=CPL
D : RPL=DPL
A : Minimum one
C : One per task
D : None of above
then it is called
A : port-mapped I/O
C : bus-mapped I/O
must be
A : CPL
B : RPL
C : DPL
A : front-link
B : back-link
C : next-link
D : previous-link
A : ARPL
B : LLDT
C : LTR
D : All of above
B : Tables
C : Memory
A : IN/OUT
B : INS/OUTS
C : INSB/OUTSB
D : INC/DEC
A : base address
B : attribute bit
C : present bit
D : granular bit
B : Bottom of stack
C : Middle of stack
D : None
A : 2K
B : 8K
C : 4K
D : 16K
A : static
B : dynamic
C : reserved
D : bank
B : Read Bit
C : Write Bit
A : Divide Error
B : Debug Exception
B : LAR instruction
C : LSL instruction
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor
A : hold

A:7
B:8
C:9
D : 10
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits
A:7
B:8
C:9
D : 10
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL

Seat No -
Time : 1hr
Max Marks : 50
N.B
A : Level 0
B : Level 1
C : Level 2
D : Level 3
A:0
B:1
C:2
D:3
A : Limit
B : Type
C : Base
D : Offset
A:8
B : 16
C : 32
D : 64
A : Divide Error
B : Debug Exception
A : S bit
B : W bit
C : G bit
D : A bit
code.
A:6
B:8
C : 16
D : 20
D : Divide error

from ---------------
A : GDT
B : LDT
C : IDT
D : None of above
A : Outside
B : Within
C : None
D : Both
A : SS:ESP
B : SS:EIP
C : GS:ESP
D : GS:EIP
D : All of above
A : RET instruction
D : JMP instruction
A : 8192
B : 4096
C : 1024
D : 2048
Q.no 15. Faults are
C : exceptions
D : traps
A : read, read
B : write, write
C : read, write
D : write, read

A : Segment base
D : Segment Limit
C : Execution unit
D : control unit
A:8
B : 16
C : 10
D : 20
A : EIP
B : ESP
C : EFLAGS
D : ALL
A : Four
B : Two
C : Zero
D : One
A : 32
B:8
C : 16
D : 64
A : 32 GB
B : 64 MB
C : 32 TB
D : 64TB
A : RPL
B : DPL
C : CPL
D : IOPL
A : 255
B : 256
C : 65535
D : 65536
A : Fault
B : Trigger
C : Abort
D : None of these
A : User level
C : US level
D : None of these
must be
A : CR0
B : CR1
C : CR2
D : CR3
A : Divide Error
B : Debug Exception
A : ARPL
B : LLDT
C : LTR
D : All of above
A : IN/OUT
B : INS/OUTS
C : INSB/OUTSB
D : INC/DEC
A : front-link
B : back-link
C : next-link
D : previous-link
D : Task Register
then it is called
A : port-mapped I/O
C : bus-mapped I/O
C : Limit of GDT
B : Tables
C : Memory
D : None of above
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
A : static
B : dynamic
C : reserved
D : bank
A : 2K
B : 8K
C : 4K
D : 16K
A : CPL
B : RPL
C : DPL
A : base address
B : attribute bit
C : present bit
D : granular bit
A : Minimum one
C : One per task
D : None of above
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor
A:7
B:8
C:9
D : 10
B : LAR instruction
C : LSL instruction
A:7
B:8
C:9
D : 10
A : hold

A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits

Seat No -
Time : 1hr
Max Marks : 50
N.B
A : 32 GB
B : 64 MB
C : 32 TB
D : 64TB
A:8
B : 16
C : 32
D : 64
A : Extra
B : Stack
C : Code
D : Data
C : Flag registers
A : fixed
B : 64 KB
D : 8KB
A : 8192
B : 4096
C : 1024
D : 2048
A : 255
B : 256
C : 65535
D : 65536
A : RET instruction
D : JMP instruction
A : 8 bit
B : 16 bit
C : 32 bit
D : 64 bit
A : Segmentation
B : Paging
C : Both A and B
D : None of above
A:2
B:4
C:6
D:8
A:8
B : 16
C : 10
D : 20
C : Execution unit
D : control unit
A : CR0
B : CR1
C : CR2
D : CR3
A : S bit
B : W bit
C : G bit
D : A bit
D : All of above
A : END
B : ENDS
C : IRET
D : INTR
A : IVT
B : LDT
C : GDT
D : none of this
Q.no 20. Faults are
C : exceptions
D : traps
A : 16
B : 32
C : 48
D : 64
A : Divide Error
B : Debug Exception
D : All of above

A : 32
B:8
C : 16
D : 64
A : Outside
B : Within
C : None
D : Both
D : None of given.
A : bit 1
B : bit 5
C : bit 7
D : bit 4
A : RPL
B : DPL
C : CPL
D : IOPL
A : Level 0
B : Level 1
C : Level 2
D : Level 3
must be
A : Minimum one
C : One per task
D : None of above
A : static
B : dynamic
C : reserved
D : bank
A : IN/OUT
B : INS/OUTS
C : INSB/OUTSB
D : INC/DEC
B : Bottom of stack
C : Middle of stack
D : None
A : front-link
B : back-link
C : next-link
D : previous-link
B : Tables
C : Memory
then it is called
A : port-mapped I/O
C : bus-mapped I/O
A : base address
B : attribute bit
C : present bit
D : granular bit
A : CR0
B : CR1
C : CR2
D : CR3
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
A : direction flag
B : overflow flag
C : interrupt flag
D : sign flag
A : DPL <= CPL
B : DPL>=CPL
C : DPL=CPL
D : RPL=DPL
A : CPL
B : RPL
C : DPL
D : Task Register
B : Read Bit
C : Write Bit
A : Divide Error
B : Debug Exception
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL
A:7
B:8
C:9
D : 10
B : LAR instruction
C : LSL instruction
A:7
B:8
C:9
D : 10
A : hold
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor

A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits

Seat No -
Time : 1hr
Max Marks : 50
N.B
A : RPL
B : DPL
C : CPL
D : IOPL
A : RET instruction
D : JMP instruction

C : Flag registers
A : read, read
B : write, write
C : read, write
D : write, read
A : PL0
B : PL1
C : PL2
D : PL3
C : Execution unit
D : control unit
A : 16
B : 32
C : 48
D : 64
A : SS:ESP
B : SS:EIP
C : GS:ESP
D : GS:EIP
A:8
B : 16
C : 32
D : 64
D : None of given.
A : 4 bytes
B : 2 bytes
C : 8 bytes
D : 1 byte
A : S bit
B : W bit
C : G bit
D : A bit
A : Four
B : Two
C : Zero
D : One
C : Procedures
D : Macros
from ---------------
A : GDT
B : LDT
C : IDT
D : None of above
A : 8 bit
B : 16 bit
C : 32 bit
D : 64 bit
A:0
B:1
C:2
D:3
A : EIP
B : ESP
C : EFLAGS
D : ALL
A : User level
C : US level
D : None of these
A : bit 1
B : bit 5
C : bit 7
D : bit 4
A : Divide Error
B : Debug Exception

A : Level 0
B : Level 1
C : Level 2
D : Level 3
code.
A:6
B:8
C : 16
D : 20
A : fixed
B : 64 KB
D : 8KB
A : CR0
B : CR1
C : CR2
D : CR3
D : Divide error
A : DPL <= CPL
B : DPL>=CPL
C : DPL=CPL
D : RPL=DPL
then it is called
A : port-mapped I/O
C : bus-mapped I/O
A : Divide Error
B : Debug Exception
A : Minimum one
C : One per task
D : None of above
A : base address
B : attribute bit
C : present bit
D : granular bit
must be
D : Task Register
B : Read Bit
C : Write Bit
B : Tables
C : Memory
A : 2K
B : 8K
C : 4K
D : 16K
B : Bottom of stack
C : Middle of stack
D : None
A : direction flag
B : overflow flag
C : interrupt flag
D : sign flag
D : None of above
A : CPL
B : RPL
C : DPL
A : front-link
B : back-link
C : next-link
D : previous-link
A : ARPL
B : LLDT
C : LTR
D : All of above
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits
A : hold
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor
A:7
B:8
C:9
D : 10
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL
B : LAR instruction
C : LSL instruction
A:7
B:8
C:9
D : 10

Seat No -
Time : 1hr
Max Marks : 50
N.B
A:8
B : 16
C : 32
D : 64
A : S bit
B : W bit
C : G bit
D : A bit
A:2
B:4
C:6
D:8
D : All of above
A : 8 bit
B : 16 bit
C : 32 bit
D : 64 bit
A : 64 KB.
B : 4 GB.
C : 1 MB
D : none of above.
A : bit 1
B : bit 5
C : bit 7
D : bit 4
D : All of above
A : IVT
B : LDT
C : GDT
D : none of this
A : 8192
B : 4096
C : 1024
D : 2048

D : None of given.
A:1
B:2
C:3
D:0
Q.no 15. Faults are
C : exceptions
D : traps
D : Divide error
A : 32
B:8
C : 16
D : 64
C : Flag registers
A : Outside
B : Within
C : None
D : Both
A : 255
B : 256
C : 65535
D : 65536
A : Four
B : Two
C : Zero
D : One
A : Extra
B : Stack
C : Code
D : Data

A : sets IF
B : resets IF
C : sets IOPL
D : non of above
A : Level 0
B : Level 1
C : Level 2
D : Level 3
C : Execution unit
D : control unit
A : EIP
B : ESP
C : EFLAGS
D : ALL
A:8
B : 16
C : 10
D : 20

A : PL0
B : PL1
C : PL2
D : PL3
A : Minimum one
C : One per task
D : None of above
A : CPL
B : RPL
C : DPL
A : static
B : dynamic
C : reserved
D : bank
B : Read Bit
C : Write Bit
A : ARPL
B : LLDT
C : LTR
D : All of above
then it is called
A : port-mapped I/O
C : bus-mapped I/O
A : Divide Error
B : Debug Exception
A : 2K
B : 8K
C : 4K
D : 16K
A : front-link
B : back-link
C : next-link
D : previous-link
A : INTR pin
B : INT pin
C : NMI pin
D : BUSY pin
A : IN/OUT
B : INS/OUTS
C : INSB/OUTSB
D : INC/DEC
must be
A : base address
B : attribute bit
C : present bit
D : granular bit
A : CR0
B : CR1
C : CR2
D : CR3
D : Task Register
A : direction flag
B : overflow flag
C : interrupt flag
D : sign flag
A : DPL <= CPL
B : DPL>=CPL
C : DPL=CPL
D : RPL=DPL
A:7
B:8
C:9
D : 10
A : CPL< IOPL
B : CPL<= IOPL
C : CPL>IOPL
D : CPL>= IOPL
A : TSS
B : base address
C : Segment Limit
D : TSS descriptor
B : LAR instruction
C : LSL instruction
A : hold
A:7
B:8
C:9
D : 10
A : higher 4 bits
B : lower 8 bits
C : higher 10 bits
D : lower 12 bits

Seat No -
PWD12242_MICROCONTROLLERS
Time : 1hr
Max Marks : 50
N.B
Q.no 1. ____ register is used to read input from the port
A : TRIS
B : LAT
C : READ
D : PORT
Q.no 2. The low Priority interrupt vector has address of
A : 0000h
B : 001Bh
C : 000008h
D : 000018h
Q.no 3. PIC 18f452 is ________Microcontroller

A:8
B : 16
C : 32
D : 64
Q.no 4. A stepper motor may be considered as a ____________ converter
A : Dc to dc
B : Ac to ac
C : Dc to ac
D : Digital-to-analogue
Q.no 5. On power up, the 8051 uses which RAM locations for register R0- R7
A : 00-2F
B : 00-0F
C : 00-7F
D : 00-07
Q.no 6. How many Control lines are used by LCD
A:3
B:5
C:2
D:1
Q.no 7. Which of the ports act as the 16 bit address lines for transferring data
through it?
A : PORT 0 and PORT 1
B : PORT 0 and PORT 2
C : PORT 1 and PORT 2
D : PORT 1 and PORT 3
Q.no 8. The speed of the DC motor depends on

A : Voltage and current
B : Voltage and Load
C : Voltage, Current and Load
Q.no 9. How many SFRS are available in 8051
A : 20
B:8
C : 21
D : 34
Q.no 10. How many banks are available in PIC 18F452
A : 12
B : 16
C : 10
D : 14
Q.no 11. What is role of ALE in ADC
A : Data latch
B : Address latch
C : Signal latch
D : control latch
Q.no 12. what is PIC
A : Peripheral interrupt Controller,
B : Peripheral Interface Controller,
C : Programmable interface Controller,
D : Port interface Controller
Q.no 13. The E pin requires an ___ pulse to latch infromation at the data pins of
the LCD
A : H - to - L
B : L - to - H
C : always H
D : always L
Q.no 14. What is ROM and RAM of 8051
A : 2K,256 bytes
B : 4K, 256 bytes
C : 4K,128 bytes
D : 2K,128 bytes
Q.no 15. A microcontroller at-least should consist of
A : RAM, ROM, I/O ports and timers
B : CPU, RAM, I/O ports and timers
C : CPU, RAM, ROM, I/O ports and timers
D : CPU, ROM, I/O ports and timers
Q.no 16. What is the use of ADCON1 register in PIC 4550
A : Select refernce Voltage
B : Select Channel
C : Slect Clock
D : Chaanel and Clock
Q.no 17. What are optoisolators
A : Driver
B : Isolater
C : Latch
D : Buffer
Q.no 18. In unsigned number addition, the status of which bit is important?
A : OV
B : PSW
C : AC
D : CY
Q.no 19. What is the name of first block of logic analyser
A : Adjustable threshold Amplifier
B : Adjustable threshold Inverter
C : Adjustable threshold comparator
D : Threshold analyser
Q.no 20. How many lines are used by SPI protocol
A:2
B:3
C:4
D:1
Q.no 21. What is count require to rotate the stepper motor in 90 degree if it
complete 1 revolution in 200 steps
A : 40
B : 50
C : 60
D : 70
Q.no 22. Capture/Compare mode uses
A : Timer 0
B : Timer 0 or Timer 3
C : Timer 0 and Timer 3
D : Timer 2
Q.no 23. Operating Frequency of PIC 18F452 is

A : Dc-20 MHz
B : Dc-48MHz
C : Dc-40 MHz
D : Dc-60 MHz
Q.no 24. Serial port interrupt is generated, if ____ bits are set
A : IE
B : RI
C : TI
D : RI,TI
Q.no 25. Timer 2 module of PIC 18F4550 uses ______
A : 8-bit/16-bit timer/counter with 8-bit programmable prescaler
B : 16-bit timer/counter
C : 8-bit timer/counter with 8-bit period register
D : 8-bit timer/counter
Q.no 26. o display ‘A’ using common cathode seven-segment display, the code
required is
A : 7FH
B : 77H
C : 79H
D : 80H
Q.no 27. Which Pins ar eused for Tx and Rx in UART
A : RC6 and RC7
B : RC2 and RC3
C : RC7 and RC6
D : RB2 and RB1
Q.no 28. How many are the vectored interrupts in 8051

A:3
B:6
C:4
D:5
Q.no 29. How many data lines are essential in addition to RS , EN and RW control
lines for interfacing LCD with PIC microcontroller?
A:3
B:5
C:8
D : 10
Q.no 30. If LED is connected with Anode to port what is its status on power on
reset
A : OFF
B : undefined
C : ON
D : Tristate
Q.no 31. In compare mode, when a match occurs, the CCPx pin can be
A : driven high
B : driven low
C : toggled
D : all the above
Q.no 32. How can we control the speed of a stepper motor?
A : By controlling its switching rate
B : By controlling its torque
C : By controlling its wave drive 4 step sequence
D : Cant be controlled
Q.no 33. SSPADD register in MSSP I2C is used
A : To hold master address
B : To hold master and slave address
C : To hold slave address
D : To hold Slave and Master Address
Q.no 34. What is program memory size of PIC
A : 2K
B : 8k
C : 2MB
D : 64KB
Q.no 35. T0CON Register of Timer is __________
A : TIMER0 CONTINUOUS REGISTER
B : TIMER0 CONSTANT REGISTER
C : TIMER0 CONTROL REGISTER
D : TIMER0 CONFIG. REGISTER
Q.no 36. Name of Addressing Modes in PIC18F4550 are ______
A : Immediate, Register and Indirect
B : Immediate, Direct and Offset
C : Immediate, Direct and Index
D : Immediate, Direct and Indirect
Q.no 37. Speed of ADC depends on,
A : Resolution of ADC
B : Conversion Time
C : Number of bits
D : Step Size
Q.no 38. What is STOP Condition in I2C
A : SDA High and SCL low
B : SDA High and SCL High
C : SDA low and SCL High
D : SDA low and SCL Low
Q.no 39. The PWM period will be set in ____ Register
A : CCPCON
B : CCPR1L
C : PR2
D : T2CON
Q.no 40. What is the role of LED
A : Status indication
B : Display of Char
C : Display of Number
D : Display of Text
Q.no 41. in which direction stepper motor will rotate for sequence of 09,0C, 06,03
A : Clockwise
B : Both clockwise and anticlockwise
C : Anticlockwise
D : Reverse
Q.no 42. What is role of CCPXCON register
A : Mode Set and duty cycle
B : Set mode and interrupt
C : only for Mode set
D : only Duty cycle Set

Q.no 43. In MSSP SPI bus data is Send out by and taken in By using
A : Port C lines
B : Port D lines
C : Port B lines
D : Port E lines
Q.no 44. To generate a square wave of 50 Hz frequency continuously using Timer0,

16-bit, No prescaler, XTAL = 10 MHz, What value should be loaded into TMR0L and
TMR0H
A : TMR0L= 59 H, TMR0H= 9E H
B : TMR0L= 58 H, TMR0H= 9E H
C : TMR0L= 57 H, TMR0H= 9E H
D : none of the above
Q.no 45. Which instruction is used to check the status of a single bit?
A : MOV A,P0
B : ADD A,05H
C : JNB P0.0, label
D : CLR P0.05H
Q.no 46. Find out the roll over value for the timer in Mode 0, Mode 1 and Mode 2?
A : 1FFFH,FFFFH,00FFH
B : 1FFFH,0FFFH,FFFFH
C : 00FFH,0FFFH,FFFFH
D : 1FFFH,00FFH,FFFFH
Q.no 47. What is the limiting condition of battery for swiching in RTC
A : 1.3x Vbat
B : 1.25x Vcc
C : 1.25x Vbat
D : 1.3x Vcc
Q.no 48. What is the value to be loaded in SPBRG if BR=1200 and BRGH=0
A : 130
B : 129
C : 131
D : 132
Q.no 49. How many Bits are used by Asynchronus Communication in Serial mode
A : 11
B:8
C:7
D:9
Q.no 50. How many rows and columns are present in a 16*2 alphanumeric LCD?
A : rows=2, columns=32
B : rows=16, columns=2
C : rows=16, columns=16
D : rows=2, columns=16
Q.no 51. List out the correct sequence when the following embedded C code is
executed?
If (TMR0IF == 1)
{
TMR0ON = 0;
TMR0IF = 0;
TMR0H = 0xED;
TMR0L = 0xAF;
TMR0ON = 1;
}
A : If timer0 is ON, the timer interrupt will be off, interrupt flag is set, Timer register
loaded with count value, Timer is set
B : If timer0 interrupt flag is ON, the timer0 will be off, interrupt flag is cleared, Timer
register loaded with count value, Timer is ON
C : If timer0 interrupt flag is OFF, the timer0 will be off, interrupt flag is cleared, Timer
D : If timer0 is ON, the timer0 interrupt will be off, interrupt flag is set, Timer register
Q.no 52. What is the correct order of priority that is set after a controller gets
reset?
A : TxD/RxD, T1 ,T0 ,EX1 , EX0
B : T1, TxD/RxD,T0 ,EX1 , EX0
C : TxD/RxD,EX1 , EX0,T0,T1
D : EX0 , To,EX1,T1,TxD/RxD
Q.no 53. TMR0H and TMR0L registers of PIC 18F4550 are used ____
A : to control On and OFF of TIMER0
B : to set bits of Timer Control Register
C : to store the Hex values to generate delay of specific time
D : to initialize the Timer settings
Q.no 54. Why do we need a ULN2803 in driving a relay?
A : For switching a motor
B : For increasing the power
C : For increasing the current limit in the relays
D : For decreasing the current limit in the relays
Q.no 55. How may steps are required to rotate stepper motor 90 degree clokwise if
step anle is 1.8 degree
A : 90
B : 32
C : 60
D : 50
Q.no 56. The instruction of DECFSZ F,d,a means :

A : Decrement F and go to the next instruction if F=0
B : Decrement F and skip the next instruction if F is not Zero
C : Decrement F and skip the next instruction if F=0
D : Decrement S and skip the next instruction if F=0
Q.no 57. The instruction "MOVLW 8- bits" of PIC18F4550 signifies :
A : Load an 8 bit address into WREG
B : Load an 8 bit literal into WREG
C : Move an 8 bit literal into WREG
D : Move an 8 bit literal into any register
Q.no 58. The instruction SLEEP in PIC 18F4550 :
A : Keeps Oscillator for peripherals OFF
B : Keeps Microcontroller in standby mode
C : Resets all the registers
D : Set all registers
Q.no 59. What is the value to be loadeed in THx and TLx for for delay of 1msec
using mode0
A : 55,2A
B : 1C,67
C : 3A,22
D : 69,1C
Q.no 60.
A : CY=0,AC=0,P=0
B : CY=0,AC=1,P=0
C : CY=1,AC=1,P=1
D : CY=1,AC=1,P=0
Q.no 1. PORT names of PIC18F452 are
A : 0,1
B : 0,1,2,3,4
C : A,B,C,D,E
D : A,B,C
Q.no 2. CCP feature in PIC18 is
A : Control, capture, Pulse width Modulation
B : Capture, Compare, Pulse Width Modulation
C : Compare, Control, pulse generator
D : Capture, Control, Pulse generator
Q.no 3. PIC18F542 has ____program counter
A : 8-bit
B : 16-bit
C : 20-bit
D : 21-bit
Q.no 4. The number of ports in PIC18F458 are
A : 4
B:5
C:6
D:8
Q.no 5. Which component is replaced by an in-circuit emulator on the

development board for testing purposes?
A : RAM
B : I/O Ports
C : Peripharals
D : Micro-controller IC
Q.no 6. What is Significance of EA pin
A : Repreaentes Internalmemory access
B : Repreaentes external memory access
C : Repreaentes SFR memory access
D : Repreaentes Program memory access
Q.no 7. Which Protocol is used by RTC and EPROM
A : I2C
B : SPI and RS232protocol
C : SPI
D : I2C and SPI
Q.no 8. What is the mode of Communication in RS232
A : Aynchronous
B : Synchronous and Asynchronous
C : Synchronous
D : Isochornous
Q.no 9. The display operations in LCD are undertaken on EN line with ______
A : H to L transitions
B : L to H transitions
C : logic high
D : logic low
Q.no 10. What is the difference between UART and USART communication?
A : Synchronous
C : Asynchronous
D : Isochornous
Q.no 11. Which are the registers associated with LCD
A : INTR
B : Data
C : Data and Command
D : BUFFER
Q.no 12. PIC18F452 has total _____ pins .
A : 40
B : 20
C : 16
D:8
Q.no 13. ADDWFC, SUBWF are
A : Arithmatic Instructions
B : Move and Load instructions
C : Branch instructions
D : Logical instructions
Q.no 14. In 4-bit mode LCD, the data lines used are
A : D7-D0
B : D3-D0
C : D4-D1
D : D7-D4
Q.no 15. Abbreviate CISC and RISC
A : Complete Instruction Set Computer, Reduced Instruction Set Computer
B : Complex Instruction Set Computer, Reduced Instruction Set Computer
C : Complex Instruction Set Computer, Reliable Instruction Set Computer

D : Complete Instruction Set Computer, Reliable Instruction Set Computer
Q.no 16. What is IoL of microcontroller
A : 1.6 ma
B : 60 MA
C : 50 Ma
D : 20 Ma
Q.no 17. Which of the following signal control the flow of data?
A : DTR
B : RTS & DTR
C : RTS and CTS
D : CTS
Q.no 18. If we say microcontroller is 8-bit then here 8-bit denotes size of
A : Data Bus
B : ALU
C : Control Bus
D : Address Bus
Q.no 19. The total addressible external code memory of 8051 is
A : 64 KB
B : 16KB
C : 128KB
D : 256KB
Q.no 20. Which pin provides a reset option in 8051?
A : pin1
B : pin4
C : pin9
D : pin20
Q.no 21. _____ instruction is used to set the port A upper nibble as input
A : TRISA = 0XF0;
B : TRISA = 0X0F;
C : TRISAbits.TRISA0 = 1;
D : TRISAbits.TRISA0 = 0;
Q.no 22. MSSP module of PIC18F452 has
A : ADC and PWM
B : SPI and I2C
C : USART and CCP
D : I2C and PWM
Q.no 24. What is the maximum value of PR2 register
A : 100
B : 149
C : 200
D : 255
Q.no 25. Which development tool can facilitate the creation and modification of
source programs in addition to assembly and higher -level languages?
A : High-level language Compiler
B : Assembler
C : Debugger
D : Editor
Q.no 26. What is the data rate used by I2C
A : 2.5 Mbits
B : 2 Mbits
C : 250 kbits
D : 1 Mbits
Q.no 27. Find value of PR2 for Fosc=20MHz, N=4 and period of wave is 200
microsecond
A : 250
B : 249
C : 255
D : 149
Q.no 28. Interrupts are used bt port
A : PORTD
B : PORTC
C : PORT A
D : Port B
Q.no 29. What value of 'B' should be loaded in the TRISB register if the lines RB7 :
RB4 and RB3:RB0 are supposed to be inputs and outputs respectively after the
PORT B initialization?
A : 1.10001E7
B : 1.1110011E7
C : 1.111E7
D : 1.1110001E7
Q.no 30. How many address lines are used by ADC0809 for transfre of data from
channel 7
A:2
B:4
C:1
D:3
Q.no 31. What is the status of BRGH register for low Speed
A : BRGH=1
B : BRGH= undefined
C : BRGH = 0and 1
D : BRGH=0
Q.no 32. Which is not Stepper motor specification
A : Steps/revolution
B : Torque
C : Current rating
D : Pressure
Q.no 33. The instruction RESET in PIC 18F4550 :
A : Resets the Microcontroller
B : Resets all the registers and flags
C : Resets all the flags
D : Resets all the registers
Q.no 34. In 4 bit mode of LCD Which Data lines are used
A : D7-D1
B : D7-D0
C : D3-D0
D : D7-D4
Q.no 35. The SP is of ___ wide register. And this may be defined anywhere in the
______.
A : 8 byte, on-chip 128 byte RAM

B : 8 bit, on chip 256 byte RAM.
C : 16 bit, on-chip 128 byte ROM
D : 8 bit, on chip 128 byte RAM.
Q.no 36. If a hybrid stepper motor has a rotor pitch of 36º and a step angle of 9º,
the number of its phases must be
A:4
B:2
C:3
D:6
Q.no 37. Circuit used for initialization of all values to default is named as
A : Power-On Reset Circuit
B : Brown Out Detection Circuit
C : Power ON/OFF circuit
D : WDT circuit
Q.no 38. Logic analyser is used for testing of _________ Signals
A : Analog
B : Digital
C : Digital and Logic
D : descrite
Q.no 39. What is the value of C and R used for reset operation
A : 1.5 microfarad and 10Kohms
B : 0.5 microfarad and 10Kohms
C : 0.1 microfarad and 20Kohms
D : 1.5 microfarad and 20Kohms
Q.no 40. In LCD,_____ command is used For Cursor blink
A : 0X0F
B : 0X08
C : 0x04
D : 0X0E
Q.no 41.
A : Sowtooth
B : Square
C : Ramp
D : Sine
Q.no 42. What is the Address (SFR) for TCON, SCON, SBUF, PCON and PSW
A : 88H, 98H, 99H, 87H, 0D0H
B : 98H, 99H, 87H, 88H, 0D0H
C : 0D0H, 87H, 88H, 99H, 98H
D : 87H, 88H, 0D0H, 98H, 99H
Q.no 43. How many Channels ADC 0809 has with Converstion time of __
A : 8, 20 micro second
B : 10, 20 micro second

C : 10,100 micro second
D : 8, 100 micro second
Q.no 44. What is use of Bit D7 In LCD
A : Busy flag
B : Status flag
C : Driver flag
D : mode flag
Q.no 45. SPI Is
A : 3 wire , half duplex, symchrous data transfer bus
B : 3 wire , Full duplex, Asymchrous data transfer bus
C : 3 wire , half duplex, Asymchrous data transfer bus
D : 3 wire , Full fuplex, symchrous data transfer bus
Q.no 46. Which of the following is TRUE for PIC18F4550 Timer modules
A : Timer1 , Timer3 for PWN mode and Timer2 for Capture or Compare modes.
B : Timer1 , Timer3 for Capture or Compare modes and Timer2 for PWM mode.
C : Timer1 , Timer2 for Capture or Compare modes and Time3 for PWM mode.
D : Timer1 ,Timer2 and Timer3 for Capture or Compare and PWM mode.
Q.no 47. What is data transmission speeed of RS 485 for 10 mtrs and 1200mtrs
A : 10Mbits/s and 35 Mbits/s
B : 35Mbits/s and 100 Kbits/s
C : 100Kbits/s and 25 Mbits/s
D : 100 kbits/s and 35 Mbits/s
Q.no 48. What is the difference between LM 34 and LM 35 sensors
A : one is a sensor and the other is a transducer
B : one is of low precision and the other is of higher precision

C : one’s output voltage corresponds to the Fahrenheit temperature and the other
corresponds to the Celsius temperature
D : one requires external calibration and the other doesn’t require it
Q.no 49. "INTCONbits.TMR0IF = 0" statement for PIC 18F4550 :
A : Clears Timer0 overflow flag
B : Clear Timer0 Interrupt enable flag
C : Clear Timer0
D : Overflow detect
Q.no 50. If PR2 = 50, for 20% duty cycle the value loaded in CCPR1L is
A : 20
B : 50
C : 15
D : 10
Q.no 51. From ADC chip Step size is selected by which two bits?
A : Vref/2& Vin
B : Vin
C : Vref/2
D : Vin/2
Q.no 52. How the offset level in DAC is adjusted using
A : Hardware only
B : hardware or software
C : Software only
D : Iref only
Q.no 53. LCALL instruction takes
A : 2 bytes
B : 4 bytes
C : 3 bytes
D : 1 byte
Q.no 54. Which timer is used in PWM mode
A : Timer1
B : TIMER2
C : TIMER3
D : TIMER4
Q.no 55. What is the meaning of the instruction MOV A,05H?
A : data 05H is stored in the accumulator
B : fifth bit of accumulator is set to one
C : address 05H is stored in the accumulator
D : byte 05H is stored in the accumulator
Q.no 56. Which Decoder is used in interfacing of 7 segment display
A : 3-8 line decoder
B : 2-4 linr decoder
C : 1-2 line decoder
D : 4-16 line decoder
Q.no 57. To make port 1 bit 0 high , which instruction is used
A : SETB P1.0
B : SETB P 0.0
C : SETB P1.1
D : SETB P0.1
Q.no 58. Whow do you define the start condition in I2C protocol

Q.no 59. In T1CON register , BIT 0 is _____and BIT1 is _______
A : T1CKPS1,T1CKPS0
B : TMR1CS,TMR1ON
C : T1CKPS0,T1CKPS1
D : TMR1ON,TMR1CS
Q.no 60. Logic Analyser has number of maximum channels
A : 36
B : 136
C : 248
D : 120
Q.no 1. What is the clock rate of EEPROM AT 24C04A
A : 400kHz
B : 300KHZ
C : 250 KHz
D : 1KHz
through it?
Q.no 3. What is the significance of "d=0" bit in ADDWF F D a
A : Undefined
B : Result saved in F
C : Results saved in F and W
D : Ressult Saaved in W
Q.no 4. Optoisolator protect the 8051 from
A : freuency
B : Current
C : EMI
D : voltage
Q.no 5. PIC18F452 has _____ ADC
A : 8 bit
B : 10 bit
C : 12 bit
D : 14 bit
Q.no 6. What is Significance of BF bit
A : Buffer Full
B : Buffer empty
C : Baud rate full
D : Buffer
Q.no 7. Which Line Carries the Data in I2C protocol
A : DTR
B : DTS
C : SCL
D : SDA
Q.no 8. Main block of frequency counter other than 8051 is
A : adder
B : subtrcter
C : memory
D : counter
Q.no 9. How will you configure the port as output in PIC
A : LATx=0x00h
B : PORT=0xFFH
C : TRISx=0x00h
D : TRISx=0xFFH
Q.no 10. A stepping motor is a ____________ device
A : Incremental
B : Analogue
C : Electrical
D : Mechanical
Q.no 11. Timer 0 is a ________ bit register.
A : 4 bit
B : 8 bit
C : 11 bit
D : 16 bit
Q.no 12. The SFRs associated with interrupts are
A : INTCON,IPR
B : PIR
C : TCON,RCON
D : TCON
Q.no 13. What is the time duration of key debounce circuit for open or closure
with frequency of 50Hz
A : 30 msec
B : 25 msec
C : 40 msec
D : 20 msec
Q.no 14. Whay is the role of key , it is
A : Used for status indication
B : Used for display
C : Used for graphics
D : used for control action
Q.no 15. TF1, TR1, TF0, TR0 bits are of which register?
A : TCON
B : SCON
C : TMOD
D : SMOD
Q.no 16. In SPI Data is Shifted in and Out using
A : MOSI and MISO
B : only MISO
C : MISO and MOSI
D : Only MOSI
Q.no 17. ____ bit makes the job of Enabling/ disabling all the interrupts
A : GIE
B : PEIE
C : IE
D : INTIE
Q.no 18. BOD' stands for
A : Brown OR Reset Detection
B : Brown out Reset Detection

C : Brown out Reset Debug
D : Board on Reset Detection
Q.no 19. What is the command of LCD used to clear the content
A : 01H
B : 06H
C : 38H
D : OFEH
Q.no 20. Seven Segmant display is used to display
A : Only Graphics
B : Only numbers
C : Text and Numbers
D : only text
Q.no 21. EEPROM Data Memory of PIC 18F4550 is
A : 128 Bytes
B : 256 Bytes
C : 1KByte
D : 128 Kbytes
Q.no 22. A relay is used to
A : Break the fault current
B : Sense the fault
C : Sense the fault and direct to trip the circuit breaker
D : Close the operation
Q.no 23. What are the contents of the IE register, when the interrupt of the
memory location 0x00 is caused?
A : 0x00H
B : 0xFFH
C : 0x10H
D : 0xF0H
Q.no 24. PIC18F452 device can be operated in ____ oscillator Configuration modes.
A : 10
B : 12
C : 14
D : 16
Q.no 25. The speed of the DC motor can be varied by
A : Changing the width of the pulse applied to DC motor
B : Changing the voltage applied to the motor
C : Changing Current
D : Changing Power
Q.no 26. What is the time taken by one machine cycle if crystal frequency is
20MHz?
A : 1.085 micro seconds
B : 0.75 micro seconds
C : 0.60 micro seconds
D : 1 micro seconds
Q.no 27. How long the the RS232 transmitt data
A : 5 feet
B : 25 feet
C : 10 feet
D : 2 mtrs
reset
A : OFF
B : undefined
C : ON
D : Tristate
Q.no 29. Three types of memory in PIC18 enhanced microcontroller are _____
A : Program Memory, Data RAM, Data ROM
B : Program Memory, Data ROM, Data EEPROM
C : Program Memory, Data RAM, Data EEPROM
D : Program ROM, Data RAM, Data EEPROM
Q.no 30. The following instruction will make

TRISB = 0x00;
LATB = 0xFF;
A : Port B as input and port B bits as 1
B : Port B as output and Port B bits as 1
C : Port B as input and port B bits as 0
D : Port B as output and port B bits as 0
Q.no 31. What is the max ref current of DAC 0808
A : 1.5mA
B : 2 mA
C : 3 mA
D : 1 mA
Q.no 32. If PR2 = 150 and duty cycle is 20%, the value to be loaded in DC1B2:DC1B1
is
A:0
B:1
C : 10
D : 11

Q.no 34. What is Role of RS pin in LCD
A : Select data and Command Register
B : Select Address and Command Register
C : Select Address and Data Register
D : Select Address and Command Register with flag
Q.no 35. The command codes for line 1, first character, and line 2 , first character
in LCD are
A : 01H and F0H
B : E0H and 80H
C : E0H and C0H
D : 80H and C0H
A : Dc-20 MHz
B : Dc-48MHz
C : Dc-40 MHz
D : Dc-60 MHz
Q.no 38. Which regidter is used by MSSP-SPI bus oto selsct the clock Frequency
A : SSPCON1
B : SSPSTAT
C : SSPCON1 and SSPSTAT
D : SSPBUF
Q.no 39. ECCP peropheral module of PIC 18F4550 has
A : Enhanced Capture/Control/PWM
B : Enhanced Capture/Compare/Power
C : Enhanced Control/Compare/PWM
D : Enhanced Capture/Compare/PWM
Q.no 40. What is the file extension that is loaded in a microcontroller for
executing any instruction?
A : .hex
B : .c
C : .txt
D : .doc
executed?
If (TMR0IF == 1)
{
TMR0ON = 0;
TMR0IF = 0;
TMR0H = 0xED;
TMR0L = 0xAF;
TMR0ON = 1;
}
Q.no 42.
A : Yes
B : No
C : Undefined
D : Can not determine
reset?
A : Clockwise
C : Anticlockwise
D : Reverse
using mode0
A : 55,2A
B : 1C,67
C : 3A,22
D : 69,1C

TMR0H
Q.no 48. If RB7-RB4 = 0111is the data read from the columns starting with RB4
which column does the key pressed key belong to
A : column 0
B : column 1
C : column 2
D : column 3
Q.no 50. What is the sequence of LCD codes with their associated functions,
function Set, no blinking, Curser shift from left to right, clear screen
A : 38h,0Eh,06h,01h
B : 38h,0Fh,06h,10h
C : 3Eh,0Eh,06h,01h
D : 38h,0Eh,08h,01h
Q.no 51. By default LCD operates in
A : 4 bit mode
B : 8 bit mode
C : 12 bit mode
D : 16 bit mode
A : 90
B : 32
C : 60
D : 50
Q.no 53. What is the count to be loaded for BCD and Hex Counter
A : 0Fh and 09h
B : 09H and 0FH
C : 08 and 0EH
D : 09 and 0F
A : Port C lines
B : Port D lines
C : Port B lines
D : Port E lines
A : 1.3x Vbat
B : 1.25x Vcc
C : 1.25x Vbat
D : 1.3x Vcc
Q.no 60.
A : CY=0,AC=0,P=0
B : CY=0,AC=1,P=0
C : CY=1,AC=1,P=1
D : CY=1,AC=1,P=0
Q.no 1. Clock frequency of PIC is
A : DC to 20MHZ
B : AC to 20MHZ
C : 1 to 20MHZ
D : DC to 25MHZ
Q.no 2. DAS system multiple i/p are acess using
A : DEMUX
B : MUX
C : DEMUX and MUX both
D : Decoder
A : 20
B:8
C : 21
D : 34
Q.no 4. How many number of data can be transmitted between starts stop
condition in I2c
A : N+1
B:N
C : N-1
D : N+2
Q.no 5. What is MSSP
A : Master Synchronous serial port

B : Master serial port
C : Master serial Asynchronous port
D : Master serial Synchronous port
A : 64 KB
B : 16KB
C : 128KB
D : 256KB
Q.no 7. _____ register is used to set the direction of the port
A : LAT
B : PORT
C : TRIS
D : DIR
Q.no 8. In DC motor, ____the duty cycle of PWM signal, ______ is the speed of DC
motor
A : higher, lower
B : lower, higher
C : higher,higher
Q.no 9. What is the start lineaddress of 16x2 LCD
A : FFH
B : C0H
C : 80H
D : 90H
A : INTR
B : Data
D : BUFFER
Q.no 11. PIC 18f452 Microcontroller has _____ Timer modules
A:1
B:2
C:3
D:4
Q.no 12. What is Significance of WCOL bit in SSPCON1 register
A : Write Collision Detect bit
B : Read Collision Detect bit
C : Read and write Collision bit
D : Write and read Collision detect bit
Q.no 13. LM35 has how many pins?
A:2
B:1
C:3
D:5
Q.no 15. PIC18F 4552 has MSSP (_____________)module.
A : Master Synchronous Serial Peripheral

B : Master Synchronous slave Port
C : Master Synchronous Serial Port
D : Master Slave Serial Port
Q.no 16. Which diodes are employed in the electromechanical relays since the
inductor current cannot be reduced to zero
A : Tunnel Diode
B : Shockley Diode
C : Freewheeling Diode
D : Zener Diode
A : Dc to dc
B : Ac to ac
C : Dc to ac
Q.no 18. upon reset all the interrupts in PIC18 are
A : Enabled
B : Disabled
C : Undefined
D : Initialized to some value
Q.no 20. What is the resolution of ADC used in PIC 18F4550
A : 10 bits
B : 12 bits
C : 11 bits
D : 8 bits
Q.no 21. PIR sensor O/P is in __form
A : Analog
B : Digital
C : Analog and digital
D : Descrite
Q.no 22. USART means :
A : Univeral Synchrnous Asynchronous Register Transmit
B : Univeral Synchrnous Asymmatric Receive Transmit
C : Univeral Synchrnous Asynchronous Receive Transmit
D : Univeral Serial Asynchronous Receive Transmit
Q.no 23. input DAC has ________
A : 8 discrete voltage levels
B : 64 discrete voltage levels
C : 256 discrete voltage levels
D : 124 discrete voltage levels
Q.no 24. What is the data rate of SPI
A : 2 Mbits/s
B : 1 Mbits/s
C : 3 Mbits/s
D : 5 Mbits/s
Q.no 25. What is the vector address for TF0 flag
A : 0x0003h
B : 0x000Bh
C : 0x0023h
D : 0x0013h
Q.no 26. What is the maximum delay that can be generated with the crystal
frequency of 22MHz?
A : 2978.9 sec
B : 0.011 msec
C : 11.63 sec
D : 2.97 msec
Q.no 27. Which register is used to make the pulse a level or an edge triggered
pulse?
A : TCON
B : IE
C : IPR
D : SCON
Q.no 28. DAS system having important block
A : Adder
B : Shift Register
C : ADC
D : Counter
Q.no 29. What is the maximum data rate of RS232
A : 20Kbps
B : 21 Mbps
C : 4kbps
D : 19.2 kbps
Q.no 30. What is the Ammount of Non volatile RAM in RTC

A : 25 bytes
B : 30 bytes
C : 58 bytes
D : 56 bytes
Q.no 31. What is the value of baud rate if TH1 is loaded with -3
A : 4800
B : 9600
C : 1200
D : 2400
Q.no 32. Which ports of the PIC18 are bit addressable?
A : Only port A
B : All the ports
C : Port B and D
D : Port A and E
A:3
B:5
C:8
D : 10
Q.no 34. All the Timer module Registers of PIC 18F 4550 are
A : 64 bit
B : 16 bit
C : 32 bit
D : 8 bit

Q.no 36. What is the status of bit for Right justified result
A : ADFM=0
B : ADFM=xx
C : ADFM= 1
D : ADFM=00
A : 1.10001E7
B : 1.1110011E7
C : 1.111E7
D : 1.1110001E7
Q.no 38. DJNZ R0, label is ________ byte instruction.
A:2
B:3
C:1
D:4
Q.no 39. If 41 ASCII code is transferred to LCD , Which letter is Displayed
A:B
B:A
C:a
D:b
Q.no 40. How many bytes of bit addressable memory is present in 8051 based
microcontrollers?
A : 8 bytes
B : 16 bytes
C : 32bytes
D : 128 bytes
Q.no 42. What is the internal organization of 4K memory
A : 256x8
B : 128x8
C : 128x4
D : 512x8
A : T1CKPS1,T1CKPS0
B : TMR1CS,TMR1ON
C : T1CKPS0,T1CKPS1
D : TMR1ON,TMR1CS
A : 11
B:8
C:7
D:9
A : 20
B : 50
C : 15
D : 10
A : 130
B : 129
C : 131
D : 132
A : Busy flag
B : Status flag
C : Driver flag
D : mode flag
A : MOV A,P0
B : ADD A,05H
C : JNB P0.0, label
D : CLR P0.05H
A : 2 bytes
B : 4 bytes
C : 3 bytes
D : 1 byte
A : SETB P1.0
B : SETB P 0.0
C : SETB P1.1
D : SETB P0.1
Q.no 55. SPI Is
Q.no 56. CONFIG2L is used for
A : Frequency Selection
B : Background debugger
C : Watch dog timer
D : Reset voltage
A : 36
B : 136
C : 248
D : 120
A : Hardware only
C : Software only
D : Iref only
A : Timer1
B : TIMER2
C : TIMER3
D : TIMER4
Q.no 1. What is the time duration of key debounce circuit for open or closure with
frequency of 50Hz
A : 30 msec
B : 25 msec
C : 40 msec
D : 20 msec
A : 400kHz
B : 300KHZ
C : 250 KHz
D : 1KHz
Q.no 3. Which registers of bank are used for indirect adressing
A : R1, R2
B : R0,R1
C : R3,R0
D : R0,R2
A : Incremental
B : Analogue
C : Electrical
D : Mechanical
A : 4 bit
B : 8 bit
C : 11 bit
D : 16 bit
Q.no 6. Each instruction has two parts __________
A : Opcode and Register
B : Opcode and Operand
C : Operand and Register
D : Opcode and Pointer value
Q.no 7. Which devices are specifically being used for converting serial to parallel
and from parallel to serial respectively?
A : Registers
B : Counters
C : Timers
D : Serial communication
Q.no 8. What is the principle on which electromagnetic relays operate?
A : Electromagnetic induction
B : Motor control
C : Switching
D : Breaker
Q.no 9. How cammand register is enabled in LCD
A : RS=0, Rw=1
B : RS=0, EN=0
C : RS=0,RW=0
D : RW=0
Q.no 10. How many port lines are required to interface DAC 0808 with
microcontroller
A:2
B:4
C:8
D : 12
Q.no 11. FLASH Program Memory of PIC18F452 is _______
A : 128K
B : 64K
C : 32K
D : 16K
A : MOSI and MISO
B : only MISO
C : MISO and MOSI
D : Only MOSI
A : freuency
B : Current
C : EMI
D : voltage
A : Buffer Full
B : Buffer empty
C : Baud rate full

D : Buffer
A : Driver
B : Isolater
C : Latch
D : Buffer
A : 01H
B : 06H
C : 38H
D : OFEH
Q.no 17. RESET uses ________ Machine cycles.
A:2
B:3
C:4
D:1
A : 0000h
B : 001Bh
C : 000008h
D : 000018h
Q.no 19. Control lines used in LCD
A : EN, RW,RS
B : EN, INTR, RW
C : RS, RW, IE
D : EN and RW
Q.no 20. PIC 18f452 Miceocontroller has ______
A : High performance RISC CPU
B : High performance CISC CPU
C : Combination of both RISC and CISC CPU
D : Advanced RISC CPU
Q.no 21. What is the memory used by AT24C04 EEPROM
A : 2048 bits
B : 4096 bits
C : 1024 bits
D : 512 bits
Q.no 22. Which of the following is the logic level understood by the micro-
controller/micro-processor?
A : TTL logic level
B : RS232 logic level
C : TTL & RS232 logic level
D : RS 485
Q.no 23. Find the time delay for one machine cycle for 8051
A : 90.42 microseconds
B : 361.68 microseconds
C : 1.085 microseconds
D : 150.145 microseconds
Q.no 24. In DAS A/D converter is used for __________
A : Converting analog to digital
B : Converting digital to analog
C : Converting digital to mixed signal mode

D : Converting analog to mixed signal mode
Q.no 25. The operation of the oscillator in PIC18F4550 is controlled through two
Configuration registers as ________
A : OSCCONFIG1 and OSCCONFIG2
B : CONFIG2 and CONFIG2
C : CONFIG1L and CONFIG1H
A : CCPCON
B : CCPR1L
C : PR2
D : T2CON
Q.no 27. What the function set register in LCD represents
A : Mode, no. of lines , dot pattern
B : Mode, no. of lines , dot pattern, blibking
C : Mode, no. of lines , dot pattern, L to R shiftblibking
D : Mode, no. of lines , dot pattern, L to R shift
A : 2.5 Mbits
B : 2 Mbits
C : 250 kbits
D : 1 Mbits
A : 40
B : 50
C : 60
D : 70
Q.no 30. In Capture mode RC2 is configured as
A : Input
B : output
C : tristate
D : input and output
Q.no 31. MSSP is used by
A : Rs232 and RS485
C : I2C and RS232protocol
D : I2C and SPI protocol
A : 100
B : 149
C : 200
D : 255
A : .hex
B : .c
C : .txt
D : .doc
in LCD are
A : 01H and F0H
B : E0H and 80H
C : E0H and C0H
D : 80H and C0H
A : D7-D1
B : D7-D0
C : D3-D0
D : D7-D4
Q.no 37. For PIC18F458 , what pins are assigned to INT0-INT2?
A : RA0,RA1 and RA2
B : RB5,RB6 and RB7
C : RC0,RC1 and RC2
D : RB1, RB2 and RB3
Q.no 38. PIC18F452 has power down modes as _____
A : idle and sleep
B : deep power down and idle
C : sleep and deep sleep
D : deep sleep and deep power down
Q.no 40. 8051 series has how many 16 bit registers?
A:1
B:2
C:3
D:4
A : Vref/2& Vin
B : Vin
C : Vref/2
D : Vin/2

A : 0Fh and 09h
B : 09H and 0FH
C : 08 and 0EH
D : 09 and 0F
A : 1.3x Vbat
B : 1.25x Vcc
C : 1.25x Vbat
D : 1.3x Vcc
A : 90
B : 32
C : 60
D : 50
Q.no 48.
A : CY=0,AC=0,P=0
B : CY=0,AC=1,P=0
C : CY=1,AC=1,P=1
D : CY=1,AC=1,P=0
reset?
executed?
If (TMR0IF == 1)
{
TMR0ON = 0;
TMR0IF = 0;
TMR0H = 0xED;
TMR0L = 0xAF;
TMR0ON = 1;
}
A : Clockwise

C : Anticlockwise
D : Reverse
A : column 0
B : column 1
C : column 2
D : column 3
A : Port C lines
B : Port D lines
C : Port B lines
D : Port E lines
A : 38h,0Eh,06h,01h
B : 38h,0Fh,06h,10h
C : 3Eh,0Eh,06h,01h
D : 38h,0Eh,08h,01h
Q.no 57.
A : Yes
B : No
C : Undefined
Q.no 59. What is the value to be loaded in TH1 for baud rate of 4800 with SMOD=0
A : 0xFCH
B : 0xFAH
C : 0xFBH
D : 0xFEH
A : 88H, 98H, 99H, 87H, 0D0H
B : 98H, 99H, 87H, 88H, 0D0H
C : 0D0H, 87H, 88H, 99H, 98H
D : 87H, 88H, 0D0H, 98H, 99H
Q.no 1. How many Channels are available in PIC 18F452
A : 10
B : 11
C : 12
D:8

A : I2C
C : SPI
D : I2C and SPI
Q.no 3. In reading the columns of a matrix, if no key is pressed we should get all
in binary notation
A:0
B:1
C:F
D:7
A : 20
B:8
C : 21
D : 34
through it?
A : Data latch
B : Address latch
C : Signal latch
D : control latch
Q.no 7. Which register is used in ADC for Converstion
A : Data
B : Command
C : R -2R ladder
D : SAR
A : OV
B : PSW
C : AC
D : CY
Q.no 9. What is use of SSPBUF register
A : Read the data
B : Transmitt the data
C : Hold the data
D : Detect the data
A : DC to 20MHZ
B : AC to 20MHZ
C : 1 to 20MHZ
D : DC to 25MHZ
A : Dc to dc
B : Ac to ac
C : Dc to ac
Q.no 12. Full form for PIR sensor is
A : Passive infrared sensor
B : Port infrared sensor
C : Parent infrared sensor
A : Aynchronous
C : Synchronous
D : Isochornous
A : Data Bus
B : ALU
C : Control Bus
D : Address Bus
Q.no 15. In Common Cathode mode of LED, all LEDs are Connected to
A : Vcc
B : GND
C : VCC and GND
D : VDD
B : Select Channel
C : Slect Clock

Q.no 18. Flag 'N' in Status register of PIC18F452 denotes
A : Zero Flag
B : Negative Flag
C : Overflow Flag
D : Carry Flag
Q.no 19. Which registers are used to check the status of receiver and transmitter
in UART
A : RCSTA and TXSTA
B : TXSTA only
C : RCSTA only
D : TXSTA and RCSTA
A : LAT
B : PORT
C : TRIS
D : DIR
Q.no 21. What is the value of baud rate if TH1 is loaded with -3
A : 4800
B : 9600
C : 1200
D : 2400
A : Adder
B : Shift Register
C : ADC
D : Counter
A : 0x0003h
B : 0x000Bh
C : 0x0023h
D : 0x0013h
A : ADC and PWM
B : SPI and I2C
C : USART and CCP
D : I2C and PWM
Q.no 25. What is the role of EOC
A : Start of Converstion
B : output enable
C : End of Conversion
D : Buffer the data
A : 1.5mA
B : 2 mA
C : 3 mA
D : 1 mA
Q.no 27. Which Bit is used to Start and Stop the ADC Conversion
A : ADON
B : GO/ DOWN
C : VCF
D : ADFM
A : 128 Bytes
B : 256 Bytes
C : 1KByte
D : 128 Kbytes
A : Analog
B : Digital
D : descrite
Q.no 32. What the output of LM 35 for every degree change in temp
A : 20 mV
B : 15mV
C:5mV
D : 10mV
Q.no 33. In Immediate (Literal) addressing mode The operand is _____ that follows
the opcode
A : a register
B : a number
C : a pointer
D : an address
A:3
B:6
C:4
D:5
Q.no 35. PIC 18F4550 has ____ External Interrupts
A : Five
B : Four
C : Six
D : Two
A : 1.10001E7
B : 1.1110011E7
C : 1.111E7
D : 1.1110001E7
A : driven high
B : driven low
C : toggled
D : all the above
Q.no 38. Which instruction enables INT1
A : BSF INTCON3, INT1IE
B : BSF INTCON2, INT1IE
C : BSF INTCON1, INT1IE
D : BCF INTCON2, INT1IE
A : Timer 0
D : Timer 2
Q.no 40. What is the important signal requerd for functioning of ADC
A : PSEN
B : EA
C : clock
D : address

A : 36
B : 136
C : 248
D : 120

TMR0H
A : 4 bit mode
B : 8 bit mode
C : 12 bit mode
D : 16 bit mode

A : SETB P1.0
B : SETB P 0.0
C : SETB P1.1
D : SETB P0.1
A : MOV A,P0
B : ADD A,05H
C : JNB P0.0, label
D : CLR P0.05H
A : Timer1
B : TIMER2
C : TIMER3
D : TIMER4
A : 256x8
B : 128x8
C : 128x4
D : 512x8
C : Clear Timer0
using mode0
A : 55,2A
B : 1C,67
C : 3A,22
D : 69,1C
Q.no 55. SPI Is

Q.no 56.
A : Sowtooth
B : Square
C : Ramp
D : Sine
C : Watch dog timer
D : Reset voltage
executed?
If (TMR0IF == 1)
{
TMR0ON = 0;
TMR0IF = 0;
TMR0H = 0xED;
TMR0L = 0xAF;
TMR0ON = 1;
}
A : 130
B : 129
C : 131
D : 132
A : 0Fh and 09h
B : 09H and 0FH
C : 08 and 0EH
D : 09 and 0F
A : TRIS
B : LAT
C : READ
D : PORT
A : DEMUX
B : MUX

D : Decoder
A : INTCON,IPR
B : PIR
C : TCON,RCON
D : TCON
A:1
B:2
C:3
D:4
Q.no 5. BNZ n : Instruction of PIC 18F452
A : Branch if Z flag = 1
B : Branch if Z flag = 0
C : Branch if Z Accumulator is 0
Q.no 7. Which Circuit is used at the output of DAC to get analog signal
A : Buffer circuit
B : I- V Convertor
C : V-I Convertor
D : V-F Convertor
Q.no 8. The group of memory locations set aside to hold the address of ISRs is
called as
A : Interrupt
B : Interrupt vector table
C : Interrupt service routine
D : Polling
A:3
B:5
C:2
D:1
A:8
B : 16
C : 32
D : 64
Q.no 12. Instruction set of PIC18F452 has _________instructions
A : 33
B : 35
C : 40
D : 75
A : Buffer Full
B : Buffer empty
C : Baud rate full
D : Buffer
motor
A : higher, lower
B : lower, higher
C : higher,higher
A : 1.6 ma
B : 60 MA
C : 50 Ma
D : 20 Ma
A : DTR
B : DTS
C : SCL
D : SDA
A : Only Graphics
B : Only numbers

D : only text
A : 40
B : 20
C : 16
D:8
A : 2K,256 bytes
B : 4K, 256 bytes
C : 4K,128 bytes
D : 2K,128 bytes
Q.no 20. What is the function of the SCON register?
A : To control SBUF and SMOD registers
B : To program the start bit, stop bit, and data bits of framing
C : To control SMOD registers
D : To set baud rate
Q.no 21. The _____ pins of PORTB can cause an interrupt when any changes are
detected on any one of them
A : RB0-RB7
B : RB0-RB3
C : RB4-RB7
D : PORTB pins cannot cause interrupt

A : 20Kbps
B : 21 Mbps
C : 4kbps
D : 19.2 kbps
Q.no 25. What is Significance of mov p0, #0FFH
A : Port P0 is configured as Tristate
B : Port p1 Configured as Output
C : Port P0 is configured as output
D : Port P0 is configured as Input
B : Display of Char
D : Display of Text

reset
A : OFF
B : undefined
C : ON
D : Tristate
A : 0x00H
B : 0xFFH
C : 0x10H
D : 0xF0H
Q.no 31. What is he maximum bus length of I2C
A : 4mtrs
B : 6 mtrs
C : 5 mtrs
D : 1 mtrs
microcontrollers?
A : 8 bytes
B : 16 bytes
C : 32bytes
D : 128 bytes
A : Rs232 and RS485
A : PORTD
B : PORTC
C : PORT A
D : Port B
A : 25 bytes
B : 30 bytes
C : 58 bytes
D : 56 bytes
Q.no 37. Which Methode is used to generate sine wave using DAC
A : Look up table
B : Bubble sort
C : Initilaisation
D : Rotation
B : Conversion Time
C : Number of bits
D : Step Size
A : 2K
B : 8k
C : 2MB
D : 64KB
A : 38h,0Eh,06h,01h
B : 38h,0Fh,06h,10h
C : 3Eh,0Eh,06h,01h
D : 38h,0Eh,08h,01h
A : Vref/2& Vin
B : Vin
C : Vref/2
D : Vin/2
A : T1CKPS1,T1CKPS0
B : TMR1CS,TMR1ON
C : T1CKPS0,T1CKPS1
D : TMR1ON,TMR1CS
A : Clockwise
C : Anticlockwise
D : Reverse
A : 11
B:8
C:7
D:9
A : 0xFCH
B : 0xFAH
C : 0xFBH
D : 0xFEH
A : 2 bytes
B : 4 bytes
C : 3 bytes
D : 1 byte
A : 20
B : 50
C : 15
D : 10
Q.no 53.
A : Yes
B : No
C : Undefined
A : Port C lines
B : Port D lines
C : Port B lines
D : Port E lines
A : 90
B : 32
C : 60
D : 50

A : column 0
B : column 1
C : column 2
D : column 3
A : Hardware only
C : Software only
D : Iref only
Q.no 1. In MSSP I2C bus data is Send out by and taken in By using
A : Port C lines
B : Port B lines
C : Port D lines
D : Port E lines

A : 4
B:5
C:6
D:8
A : Enabled
B : Disabled
C : Undefined
Q.no 5. WDT stands for ________
A : Watch Down Timer
B : Watch Dog Timer
C : Width Delay Timer
D : Watch Delay Timer
A : 128K
B : 64K
C : 32K
D : 16K

A : 400kHz
B : 300KHZ
C : 250 KHz
D : 1KHz
A : DTR
B : RTS & DTR
C : RTS and CTS
D : CTS
A : 12
B : 16
C : 10
D : 14
the LCD
A : H - to - L
B : L - to - H
C : always H
D : always L
A : D7-D0
B : D3-D0
C : D4-D1
D : D7-D4
A : Data latch
B : Address latch
C : Signal latch
D : control latch
A : GIE
B : PEIE
C : IE
D : INTIE
A : INTR
B : Data
D : BUFFER

A : 10
B : 11
C : 12
D:8
A : MOSI and MISO
B : only MISO
C : MISO and MOSI
D : Only MOSI
Q.no 20. PIC18F452 has power down modes :
A : sleep, idle
B : sleep, deep sleep
C : idle, deep sleep
D : deep sleep, deep power down
A : 0X0F
B : 0X08
C : 0x04
D : 0X0E
microsecond
A : 250
B : 249
C : 255
D : 149
Q.no 23. SSPSR is
A : Directly read write
B : Not Directly read write
C : Read only
D : Write only
A : Adder
B : Shift Register
C : ADC
D : Counter
required is
A : 7FH
B : 77H
C : 79H
D : 80H
Q.no 27. What are the Square wave frequencies if SQW/Out=1
A : 1 Hz, 4 KHz,8 KHz,32 KHz
B : 4 Hz, 1 KHz,8 KHz,32 KHz
C : 8 Hz, 1 KHz,4 KHz,32 KHz
D : 8 Hz, 32 KHz,4 KHz,1 KHz
A : RC6 and RC7
B : RC2 and RC3
C : RC7 and RC6
D : RB2 and RB1
B : Torque
C : Current rating
D : Pressure
A : .hex
B : .c
C : .txt
D : .doc
B : Assembler
C : Debugger
D : Editor
Q.no 32. Which register is used to check the flags in PIC
A : PIR1
B : IPR
C : PIR2
D : INTCON2
B : output enable
D : Buffer the data
channel 7
A:2
B:4
C:1
D:3
A : 2048 bits
B : 4096 bits
C : 1024 bits
D : 512 bits
A : TRISA = 0XF0;
B : TRISA = 0X0F;
A : 40
B : 50
C : 60
D : 70
A : ADFM=0
B : ADFM=xx
C : ADFM= 1
D : ADFM=00
A : 1.3x Vbat
B : 1.25x Vcc
C : 1.25x Vbat
D : 1.3x Vcc
A : Busy flag
B : Status flag
C : Driver flag
D : mode flag
A : 88H, 98H, 99H, 87H, 0D0H
B : 98H, 99H, 87H, 88H, 0D0H
C : 0D0H, 87H, 88H, 99H, 98H
D : 87H, 88H, 0D0H, 98H, 99H
reset?
A : SETB P1.0
B : SETB P 0.0
C : SETB P1.1
D : SETB P0.1
A : 130
B : 129
C : 131
D : 132
Q.no 50. SPI Is

executed?
If (TMR0IF == 1)
{
TMR0ON = 0;
TMR0IF = 0;
TMR0H = 0xED;
TMR0L = 0xAF;
TMR0ON = 1;
}
using mode0
A : 55,2A
B : 1C,67
C : 3A,22
D : 69,1C
A : 256x8
B : 128x8
C : 128x4
D : 512x8
Q.no 55.
A : CY=0,AC=0,P=0
B : CY=0,AC=1,P=0
C : CY=1,AC=1,P=1
D : CY=1,AC=1,P=0
A : 36
B : 136
C : 248
D : 120
A : Timer1
B : TIMER2
C : TIMER3
D : TIMER4
Q.no 58.
A : Sowtooth
B : Square
C : Ramp
D : Sine

A : Data
B : Command
C : R -2R ladder
D : SAR
A : Incremental
B : Analogue
C : Electrical
D : Mechanical
A : DEMUX
B : MUX
D : Decoder
A : pin1
B : pin4
C : pin9
D : pin20

A : adder
B : subtrcter
C : memory
D : counter
A : 00-2F
B : 00-0F
C : 00-7F
D : 00-07
A : Vcc
B : GND
C : VCC and GND
D : VDD
A : 0000h
B : 001Bh
C : 000008h
D : 000018h
C : logic high
D : logic low
A : Buffer circuit
B : I- V Convertor
C : V-I Convertor
D : V-F Convertor
in binary notation
A:0
B:1
C:F
D:7
A : Synchronous
C : Asynchronous
D : Isochornous
A : Read the data
C : Hold the data
D : Detect the data

A : Tunnel Diode
B : Shockley Diode
D : Zener Diode
A : Dc to dc
B : Ac to ac
C : Dc to ac
A : 30 msec
B : 25 msec
C : 40 msec
D : 20 msec
A : RA0,RA1 and RA2
B : RB5,RB6 and RB7
C : RC0,RC1 and RC2
A : 1.5mA
B : 2 mA
C : 3 mA
D : 1 mA
20MHz?
D : 1 micro seconds
D : WDT circuit
A : 2 Mbits/s
B : 1 Mbits/s
C : 3 Mbits/s
D : 5 Mbits/s
frequency of 22MHz?
A : 2978.9 sec
B : 0.011 msec
C : 11.63 sec
D : 2.97 msec
A : 1.10001E7
B : 1.1110011E7
C : 1.111E7
D : 1.1110001E7
A : Analog
B : Digital

D : descrite
A : idle and sleep
D : Changing Power
the opcode
A : a register
B : a number
C : a pointer
D : an address
A : driven high
B : driven low
C : toggled
D : all the above
A : IE
B : RI
C : TI
D : RI,TI
______.
A : 0x0003h
B : 0x000Bh
C : 0x0023h
D : 0x0013h
A : 2.5 Mbits
B : 2 Mbits
C : 250 kbits
D : 1 Mbits

A : 11
B:8
C:7
D:9
A : Vref/2& Vin
B : Vin
C : Vref/2
D : Vin/2
C : Clear Timer0
Q.no 46.
A : Yes
B : No
C : Undefined
A : 90
B : 32
C : 60
D : 50
A : Clockwise
C : Anticlockwise
D : Reverse
A : T1CKPS1,T1CKPS0
B : TMR1CS,TMR1ON
C : T1CKPS0,T1CKPS1
D : TMR1ON,TMR1CS
A : 4 bit mode
B : 8 bit mode
C : 12 bit mode
D : 16 bit mode
A : column 0
B : column 1
C : column 2
D : column 3
A : 0xFCH
B : 0xFAH
C : 0xFBH
D : 0xFEH
A : 2 bytes
B : 4 bytes
C : 3 bytes
D : 1 byte
A : MOV A,P0
B : ADD A,05H
C : JNB P0.0, label
D : CLR P0.05H
C : Watch dog timer
D : Reset voltage

Q.no 1. PIC18 uses _____ Timer for PWM
A : Timer 0
B : Timer 1
C : Timer 2
D : Timer 3
A : Buffer Full
B : Buffer empty
C : Baud rate full
D : Buffer
B : Motor control
C : Switching
D : Breaker
A : D7-D0
B : D3-D0
C : D4-D1
D : D7-D4
A : DC to 20MHZ
B : AC to 20MHZ
C : 1 to 20MHZ
D : DC to 25MHZ
A : R1, R2
B : R0,R1
C : R3,R0
D : R0,R2
A : 33
B : 35
C : 40
D : 75
B : Watch Dog Timer
A:1
B:2
C:3
D:4
B : Select Channel
C : Slect Clock
A : DTR
B : DTS
C : SCL
D : SDA
A : 400kHz
B : 300KHZ
C : 250 KHz
D : 1KHz
A : 4
B:5
C:6
D:8
A:2
B:1
C:3
D:5
A : sleep, idle
A : FFH
B : C0H
C : 80H
D : 90H
A : 8 bit
B : 10 bit
C : 12 bit
D : 14 bit
A : 4 bit
B : 8 bit
C : 11 bit
D : 16 bit
A:3
B:5
C:8
D : 10
A : 4mtrs
B : 6 mtrs
C : 5 mtrs
D : 1 mtrs
A : 2K
B : 8k
C : 2MB
D : 64KB
A : TTL logic level
D : RS 485

A:2
B:3
C:1
D:4
A : 2048 bits
B : 4096 bits
C : 1024 bits
D : 512 bits
A : D7-D1
B : D7-D0
C : D3-D0
D : D7-D4

microsecond
A : 250
B : 249
C : 255
D : 149
A : Look up table
B : Bubble sort
C : Initilaisation
D : Rotation
B : Conversion Time
C : Number of bits
D : Step Size
A : PORTD
B : PORTC
C : PORT A
D : Port B
Q.no 35. SSPSR is

C : Read only
D : Write only
A : 100
B : 149
C : 200
D : 255
A : 10
B : 12
C : 14
D : 16

B : Display of Char
D : Display of Text
A : 256x8
B : 128x8
C : 128x4
D : 512x8
A : Timer1
B : TIMER2
C : TIMER3
D : TIMER4
A : 38h,0Eh,06h,01h
B : 38h,0Fh,06h,10h
C : 3Eh,0Eh,06h,01h
D : 38h,0Eh,08h,01h

A : 36
B : 136
C : 248
D : 120
reset?

TMR0H
A : Port C lines
B : Port D lines
C : Port B lines
D : Port E lines
A : 20
B : 50
C : 15
D : 10
Q.no 51.
A : Sowtooth
B : Square
C : Ramp
D : Sine

A : Hardware only
C : Software only
D : Iref only
using mode0
A : 55,2A
B : 1C,67
C : 3A,22
D : 69,1C
A : 0xFCH
B : 0xFAH
C : 0xFBH
D : 0xFEH

executed?
If (TMR0IF == 1)
{
TMR0ON = 0;
TMR0IF = 0;
TMR0H = 0xED;
TMR0L = 0xAF;
TMR0ON = 1;
}
A : 0Fh and 09h
B : 09H and 0FH
C : 08 and 0EH
D : 09 and 0F
Q.no 60. SPI Is
A:2
B:3
C:4
D:1

A : RAM
B : I/O Ports
C : Peripharals
A : Registers
B : Counters
C : Timers
Q.no 5. what is PIC

A : Only Graphics
B : Only numbers
D : only text
A : DTR
B : RTS & DTR

C : RTS and CTS
D : CTS
A : 12
B : 16
C : 10
D : 14
A : TCON
B : SCON
C : TMOD
D : SMOD
A : 0,1
B : 0,1,2,3,4
C : A,B,C,D,E
D : A,B,C
in UART
A : RCSTA and TXSTA
B : TXSTA only
C : RCSTA only
D : TXSTA and RCSTA
A : RS=0, Rw=1
B : RS=0, EN=0
C : RS=0,RW=0
D : RW=0
Q.no 18. What is the frequency of Clock used in RTC
A : 33 MHZ
B : 40 MHz
C : 32.786 MHz
D : 32 MHz
A : I2C
C : SPI
D : I2C and SPI
A : 25 bytes
B : 30 bytes
C : 58 bytes
D : 56 bytes
A : BRGH=1
C : BRGH = 0and 1
D : BRGH=0
A : RC6 and RC7
B : RC2 and RC3
C : RC7 and RC6
D : RB2 and RB1
A : driven high
B : driven low
C : toggled
D : all the above
A : CCPCON
B : CCPR1L
C : PR2
D : T2CON
A : 128 Bytes
B : 256 Bytes
C : 1KByte
D : 128 Kbytes

B : Torque
C : Current rating
D : Pressure
A : SSPCON1
B : SSPSTAT
D : SSPBUF
channel 7
A:2
B:4
C:1
D:3
A : ADC and PWM
B : SPI and I2C
C : USART and CCP
D : I2C and PWM
A : idle and sleep

Q.no 37. How are the bits of the register PSW affected if we select Bank2 of 8051?
A : PSW.5=0 and PSW.4=1
B : PSW.2=0 and PSW.3=1
C : PSW.3=0 and PSW.4=1
D : PSW.3=1 and PSW.4=1
A:1
B:2
C:3
D:4
A : MOV A,P0
B : ADD A,05H
C : JNB P0.0, label
D : CLR P0.05H
Q.no 42.
A : Yes
B : No
C : Undefined
A : 88H, 98H, 99H, 87H, 0D0H
B : 98H, 99H, 87H, 88H, 0D0H
C : 0D0H, 87H, 88H, 99H, 98H
D : 87H, 88H, 0D0H, 98H, 99H
A : Vref/2& Vin
B : Vin
C : Vref/2
D : Vin/2
A : 1.3x Vbat
B : 1.25x Vcc
C : 1.25x Vbat
D : 1.3x Vcc

Q.no 51.
A : CY=0,AC=0,P=0
B : CY=0,AC=1,P=0
C : CY=1,AC=1,P=1
D : CY=1,AC=1,P=0
A : T1CKPS1,T1CKPS0
B : TMR1CS,TMR1ON
C : T1CKPS0,T1CKPS1
D : TMR1ON,TMR1CS
C : Clear Timer0
A : 130
B : 129
C : 131
D : 132
A : 11
B:8
C:7
D:9
A : column 0
B : column 1
C : column 2
D : column 3
A : SETB P1.0
B : SETB P 0.0
C : SETB P1.1
D : SETB P0.1

A : DEMUX
B : MUX
D : Decoder
A : Incremental
B : Analogue
C : Electrical
D : Mechanical
A : pin1
B : pin4
C : pin9
D : pin20
A : Timer 0
B : Timer 1
C : Timer 2
D : Timer 3
A : Zero Flag
B : Negative Flag
C : Overflow Flag
D : Carry Flag
A : DTR
B : DTS
C : SCL
D : SDA
A : Aynchronous
C : Synchronous
D : Isochornous
A : Buffer Full
B : Buffer empty
C : Baud rate full
D : Buffer
A : Driver
B : Isolater
C : Latch
D : Buffer
A : 01H
B : 06H
C : 38H
D : OFEH
A : FFH
B : C0H
C : 80H
D : 90H
A : 64 KB
B : 16KB
C : 128KB
D : 256KB
A : 1.6 ma
B : 60 MA
C : 50 Ma
D : 20 Ma
A : Data latch
B : Address latch
C : Signal latch
D : control latch
A : Port C lines
B : Port B lines
C : Port D lines
D : Port E lines
A : freuency
B : Current
C : EMI
D : voltage
the LCD
A : H - to - L
B : L - to - H
C : always H
D : always L
A : 0000h
B : 001Bh
C : 000008h
D : 000018h
A : TRIS
B : LAT
C : READ
D : PORT
A:2
B:1
C:3
D:5
A : RB0-RB7
B : RB0-RB3
C : RB4-RB7
A : PIR1
B : IPR
C : PIR2
D : INTCON2
A : .hex
B : .c
C : .txt
D : .doc
A : TTL logic level
D : RS 485
A : 40
B : 50
C : 60
D : 70
A : 2.5 Mbits
B : 2 Mbits
C : 250 kbits
D : 1 Mbits
A : 64 bit
B : 16 bit
C : 32 bit
D : 8 bit
B : output enable
D : Buffer the data
20MHz?
D : 1 micro seconds
the opcode
A : a register
B : a number
C : a pointer
D : an address
A : PSEN
B : EA
C : clock
D : address
D : Changing Power

TRISB = 0x00;
LATB = 0xFF;
A : Analog
B : Digital
D : descrite
A : 4mtrs
B : 6 mtrs
C : 5 mtrs
D : 1 mtrs
A : TRISA = 0XF0;
B : TRISA = 0X0F;
A : Port C lines
B : Port D lines
C : Port B lines
D : Port E lines
A : 36
B : 136
C : 248
D : 120
A : 20
B : 50
C : 15
D : 10
A : 0xFCH
B : 0xFAH
C : 0xFBH
D : 0xFEH
reset?
A : 4 bit mode
B : 8 bit mode
C : 12 bit mode
D : 16 bit mode
executed?
If (TMR0IF == 1)
{
TMR0ON = 0;
TMR0IF = 0;
TMR0H = 0xED;
TMR0L = 0xAF;
TMR0ON = 1;
}
A : Busy flag
B : Status flag
C : Driver flag
D : mode flag
A : Timer1
B : TIMER2
C : TIMER3
D : TIMER4

TMR0H
using mode0
A : 55,2A
B : 1C,67
C : 3A,22
D : 69,1C
A : 90
B : 32
C : 60
D : 50
A : 38h,0Eh,06h,01h
B : 38h,0Fh,06h,10h
C : 3Eh,0Eh,06h,01h
D : 38h,0Eh,08h,01h
A : 2 bytes
B : 4 bytes
C : 3 bytes
D : 1 byte
A : Clockwise
C : Anticlockwise
D : Reverse
B : Motor control
C : Switching
D : Breaker
Q.no 4. Which registers are used to check the status of receiver and transmitter in
UART
A : RCSTA and TXSTA
B : TXSTA only
C : RCSTA only
D : TXSTA and RCSTA
A : GIE
B : PEIE
C : IE
D : INTIE
through it?
A : 40
B : 20
C : 16
D:8
A : 10 bits
B : 12 bits
C : 11 bits
D : 8 bits
A : sleep, idle
A : D7-D0
B : D3-D0
C : D4-D1
D : D7-D4
A : MOSI and MISO
B : only MISO
C : MISO and MOSI
D : Only MOSI

A:8
B : 16
C : 32
D : 64
A : 8-bit
B : 16-bit
C : 20-bit
D : 21-bit
A : 12
B : 16
C : 10
D : 14
A : 0,1
B : 0,1,2,3,4
C : A,B,C,D,E
D : A,B,C
A : 400kHz
B : 300KHZ
C : 250 KHz
D : 1KHz
A : Data Bus
B : ALU
C : Control Bus
D : Address Bus
A : 00-2F
B : 00-0F
C : 00-7F
D : 00-07
A:3
B:5
C:8
D : 10

A:1
B:2
C:3
D:4
A:4
B:2
C:3
D:6
A : 1.5mA
B : 2 mA
C : 3 mA
D : 1 mA
A : 0x00H
B : 0xFFH
C : 0x10H
D : 0xF0H
A : BRGH=1
C : BRGH = 0and 1
D : BRGH=0
A : Analog
B : Digital
D : Descrite
A : Look up table
B : Bubble sort
C : Initilaisation
D : Rotation
B : Assembler
C : Debugger
D : Editor
A : 5 feet
B : 25 feet
C : 10 feet
D : 2 mtrs
A : 100
B : 149
C : 200
D : 255
A:B
B:A
C:a
D:b
A : Input
B : output
C : tristate
A : IE
B : RI
C : TI
D : RI,TI
Q.no 38. Which ports of the PIC18 are bit addressable?
A : Only port A
B : All the ports
C : Port B and D
D : Port A and E
A : 10
B : 12
C : 14
D : 16
A : 88H, 98H, 99H, 87H, 0D0H
B : 98H, 99H, 87H, 88H, 0D0H

C : 0D0H, 87H, 88H, 99H, 98H
D : 87H, 88H, 0D0H, 98H, 99H
Q.no 43. SPI Is
A : Vref/2& Vin
B : Vin
C : Vref/2
D : Vin/2
A : 1.3x Vbat
B : 1.25x Vcc
C : 1.25x Vbat
D : 1.3x Vcc
A : column 0
B : column 1
C : column 2
D : column 3
Q.no 48.
A : Yes
B : No
C : Undefined
A : MOV A,P0
B : ADD A,05H
C : JNB P0.0, label
D : CLR P0.05H
Q.no 52.
A : Sowtooth
B : Square
C : Ramp
D : Sine
A : T1CKPS1,T1CKPS0
B : TMR1CS,TMR1ON
C : T1CKPS0,T1CKPS1
D : TMR1ON,TMR1CS
A : 256x8
B : 128x8
C : 128x4
D : 512x8

A : 130
B : 129
C : 131
D : 132
Q.no 58.
A : CY=0,AC=0,P=0
B : CY=0,AC=1,P=0
C : CY=1,AC=1,P=1
D : CY=1,AC=1,P=0
C : Watch dog timer

D : Reset voltage
A : Hardware only
C : Software only
D : Iref only
A : 4
B:5
C:6
D:8
A : Aynchronous
C : Synchronous
D : Isochornous
A : Undefined
A : Data
B : Command
C : R -2R ladder
D : SAR
A : freuency
B : Current
C : EMI
D : voltage
A:3
B:5
C:2
D:1
A : EN, RW,RS
B : EN, INTR, RW
C : RS, RW, IE
D : EN and RW
A : Only Graphics
B : Only numbers

D : only text
motor
A : higher, lower
B : lower, higher
C : higher,higher
A : 33
B : 35
C : 40
D : 75
A : Enabled
B : Disabled
C : Undefined
A:2
B:3
C:4
D:1

A:1
B:2
C:3
D:4
called as
A : Interrupt
D : Polling
A : INTCON,IPR
B : PIR
C : TCON,RCON
D : TCON

A : RAM
B : I/O Ports
C : Peripharals
A : Buffer Full
B : Buffer empty
C : Baud rate full
D : Buffer
in LCD are
A : 01H and F0H
B : E0H and 80H
C : E0H and C0H
D : 80H and C0H
is
A:0
B:1
C : 10
D : 11
A : Adder
B : Shift Register
C : ADC
D : Counter
required is
A : 7FH
B : 77H
C : 79H
D : 80H
A : RA0,RA1 and RA2
B : RB5,RB6 and RB7
C : RC0,RC1 and RC2
A : 20Kbps
B : 21 Mbps
C : 4kbps
D : 19.2 kbps

B : Sense the fault
D : WDT circuit
A : ADON
B : GO/ DOWN
C : VCF
D : ADFM
______.
A : CCPCON
B : CCPR1L
C : PR2
D : T2CON
Q.no 36. SSPSR is
C : Read only
D : Write only
A : D7-D1
B : D7-D0
C : D3-D0
D : D7-D4
B : Torque
C : Current rating
D : Pressure
pulse?
A : TCON
B : IE
C : IPR
D : SCON
A : 36
B : 136
C : 248
D : 120

TMR0H

A : 0xFCH
B : 0xFAH
C : 0xFBH
D : 0xFEH
C : Clear Timer0
executed?
If (TMR0IF == 1)
{
TMR0ON = 0;
TMR0IF = 0;
TMR0H = 0xED;
TMR0L = 0xAF;
TMR0ON = 1;
}
using mode0
A : 55,2A
B : 1C,67
C : 3A,22
D : 69,1C
A : Port C lines
B : Port D lines
C : Port B lines
D : Port E lines
A : Timer1
B : TIMER2
C : TIMER3
D : TIMER4

reset?
A : 11
B:8
C:7
D:9
A : SETB P1.0
B : SETB P 0.0
C : SETB P1.1
D : SETB P0.1
A : 0Fh and 09h
B : 09H and 0FH
C : 08 and 0EH
D : 09 and 0F
A : Clockwise
C : Anticlockwise
D : Reverse
A : 20
B : 50
C : 15
D : 10
A : 40
B : 20
C : 16
D:8
A : 8 bit
B : 10 bit
C : 12 bit
D : 14 bit
A : 2K,256 bytes
B : 4K, 256 bytes
C : 4K,128 bytes
D : 2K,128 bytes
A : 01H
B : 06H
C : 38H
D : OFEH
A : Incremental
B : Analogue
C : Electrical
D : Mechanical
A : 64 KB
B : 16KB
C : 128KB
D : 256KB
A : DTR
B : DTS
C : SCL
D : SDA
A : 0,1
B : 0,1,2,3,4
C : A,B,C,D,E
D : A,B,C

A : R1, R2
B : R0,R1
C : R3,R0
D : R0,R2
in binary notation
A:0
B:1
C:F
D:7
A : TRIS
B : LAT
C : READ
D : PORT
A : LATx=0x00h
B : PORT=0xFFH
C : TRISx=0x00h
D : TRISx=0xFFH
A : 30 msec
B : 25 msec
C : 40 msec
D : 20 msec
A : Dc to dc
B : Ac to ac
C : Dc to ac

A : ADC and PWM
B : SPI and I2C
C : USART and CCP
D : I2C and PWM
Q.no 24. RS 485 uses principle of
A : Single drop
B : Multiplexing
C : Multidrop
D : single and multi drop
A : driven high
B : driven low
C : toggled
D : all the above
microsecond
A : 250
B : 249
C : 255
D : 149
A : 1.10001E7
B : 1.1110011E7
C : 1.111E7
D : 1.1110001E7
A:3
B:6
C:4
D:5
A : 2 Mbits/s
B : 1 Mbits/s
C : 3 Mbits/s
D : 5 Mbits/s
A : PSEN
B : EA
C : clock
D : address
A : ADFM=0
B : ADFM=xx
C : ADFM= 1
D : ADFM=00
A : SSPCON1
B : SSPSTAT
D : SSPBUF
A : 25 bytes
B : 30 bytes
C : 58 bytes
D : 56 bytes

reset
A : OFF
B : undefined
C : ON
D : Tristate
channel 7
A:2
B:4
C:1
D:3

TRISB = 0x00;
LATB = 0xFF;

A : 130
B : 129
C : 131
D : 132
C : Watch dog timer
D : Reset voltage
A : 90
B : 32
C : 60
D : 50
A : 38h,0Eh,06h,01h
B : 38h,0Fh,06h,10h
C : 3Eh,0Eh,06h,01h
D : 38h,0Eh,08h,01h
A : 256x8
B : 128x8
C : 128x4
D : 512x8
A : T1CKPS1,T1CKPS0
B : TMR1CS,TMR1ON
C : T1CKPS0,T1CKPS1
D : TMR1ON,TMR1CS
A : column 0
B : column 1
C : column 2
D : column 3
Q.no 52. SPI Is

A : Busy flag
B : Status flag
C : Driver flag
D : mode flag
Q.no 55.
A : Sowtooth
B : Square
C : Ramp
D : Sine
A : Hardware only
C : Software only
D : Iref only
A : 1.3x Vbat
B : 1.25x Vcc
C : 1.25x Vbat
D : 1.3x Vcc

C : logic high
D : logic low
A : 10
B : 11
C : 12
D:8
B : Select Channel
C : Slect Clock
A : 400kHz
B : 300KHZ
C : 250 KHz
D : 1KHz
A : 33
B : 35
C : 40
D : 75
A : RS=0, Rw=1
B : RS=0, EN=0
C : RS=0,RW=0
D : RW=0
microcontroller
A:2
B:4
C:8
D : 12
A : Read the data
C : Hold the data
D : Detect the data
A : INTR
B : Data
D : BUFFER
A : Only Graphics
B : Only numbers
D : only text
A : 10 bits
B : 12 bits
C : 11 bits
D : 8 bits
A : 128K
B : 64K
C : 32K
D : 16K
A : 4 bit
B : 8 bit
C : 11 bit
D : 16 bit
the LCD
A : H - to - L
B : L - to - H
C : always H
D : always L
A : Zero Flag
B : Negative Flag
C : Overflow Flag
D : Carry Flag
A : Tunnel Diode
B : Shockley Diode
D : Zener Diode
A : DC to 20MHZ
B : AC to 20MHZ
C : 1 to 20MHZ
D : DC to 25MHZ
A:2
B:1
C:3
D:5
A : TCON
B : SCON
C : TMOD
D : SMOD
A : 0x00H
B : 0xFFH
C : 0x10H
D : 0xF0H
B : Torque
C : Current rating
D : Pressure
A : .hex
B : .c
C : .txt
D : .doc

A : 128 Bytes
B : 256 Bytes
C : 1KByte
D : 128 Kbytes
A:B
B:A
C:a
D:b
A : RC6 and RC7
B : RC2 and RC3
C : RC7 and RC6
D : RB2 and RB1
required is
A : 7FH
B : 77H
C : 79H
D : 80H
microcontrollers?
A : 8 bytes
B : 16 bytes
C : 32bytes
D : 128 bytes
B : Display of Char
D : Display of Text
A : Look up table
B : Bubble sort
C : Initilaisation
D : Rotation
A : 4mtrs
B : 6 mtrs
C : 5 mtrs
D : 1 mtrs
A : Timer 0
D : Timer 2
A : Analog
B : Digital
D : descrite
A : TRISA = 0XF0;
B : TRISA = 0X0F;
A : Analog
B : Digital
D : Descrite
A : 5 feet
B : 25 feet
C : 10 feet
D : 2 mtrs
reset?

TMR0H
A : 2 bytes
B : 4 bytes
C : 3 bytes
D : 1 byte
A : Vref/2& Vin
B : Vin
C : Vref/2
D : Vin/2
executed?
If (TMR0IF == 1)
{
TMR0ON = 0;
TMR0IF = 0;
TMR0H = 0xED;
TMR0L = 0xAF;
TMR0ON = 1;
}
C : Clear Timer0
A : 0xFCH
B : 0xFAH
C : 0xFBH
D : 0xFEH
A : Port C lines
B : Port D lines
C : Port B lines
D : Port E lines
A : 88H, 98H, 99H, 87H, 0D0H
B : 98H, 99H, 87H, 88H, 0D0H
C : 0D0H, 87H, 88H, 99H, 98H
D : 87H, 88H, 0D0H, 98H, 99H
A : 36
B : 136
C : 248
D : 120
A : 4 bit mode
B : 8 bit mode
C : 12 bit mode
D : 16 bit mode
A : 11
B:8
C:7
D:9
A : MOV A,P0
B : ADD A,05H
C : JNB P0.0, label
D : CLR P0.05H

A : Timer1
B : TIMER2
C : TIMER3
D : TIMER4
A : 20
B : 50
C : 15
D : 10
condition in I2c
A : N+1
B:N
C : N-1
D : N+2
A : Dc to dc
B : Ac to ac
C : Dc to ac
A : sleep, idle

A : Data latch
B : Address latch
C : Signal latch
D : control latch
called as
A : Interrupt
D : Polling

A : RAM
B : I/O Ports
C : Peripharals
motor
A : higher, lower
B : lower, higher
C : higher,higher
Q.no 8. Which registers are used to check the status of receiver and transmitter in
UART
A : RCSTA and TXSTA
B : TXSTA only
C : RCSTA only
D : TXSTA and RCSTA
A : Enabled
B : Disabled
C : Undefined

A : 4
B:5
C:6
D:8
A : OV
B : PSW
C : AC
D : CY
A:2
B:3
C:4
D:1
A : 00-2F
B : 00-0F
C : 00-7F
D : 00-07

A : Undefined
A : 0000h
B : 001Bh
C : 000008h
D : 000018h
A : ADC and PWM
B : SPI and I2C
C : USART and CCP
D : I2C and PWM

B : output enable
D : Buffer the data
A : 64 bit
B : 16 bit
C : 32 bit
D : 8 bit
A : IE
B : RI
C : TI
D : RI,TI
TRISB = 0x00;
LATB = 0xFF;
A : 2K
B : 8k
C : 2MB
D : 64KB
A:1
B:2
C:3
D:4
B : Conversion Time
C : Number of bits
D : Step Size
A : 1.10001E7
B : 1.1110011E7
C : 1.111E7
D : 1.1110001E7
A : Rs232 and RS485
channel 7
A:2
B:4
C:1
D:3
A : 2 Mbits/s
B : 1 Mbits/s
C : 3 Mbits/s
D : 5 Mbits/s
A:4
B:2
C:3
D:6
Q.no 41.
A : Sowtooth
B : Square
C : Ramp
D : Sine
A : 1.3x Vbat
B : 1.25x Vcc
C : 1.25x Vbat
D : 1.3x Vcc
A : 130
B : 129
C : 131
D : 132
A : Clockwise
C : Anticlockwise
D : Reverse
Q.no 46. SPI Is
Q.no 47.
A : CY=0,AC=0,P=0
B : CY=0,AC=1,P=0
C : CY=1,AC=1,P=1
D : CY=1,AC=1,P=0

A : 256x8
B : 128x8
C : 128x4
D : 512x8
A : 38h,0Eh,06h,01h
B : 38h,0Fh,06h,10h
C : 3Eh,0Eh,06h,01h
D : 38h,0Eh,08h,01h
A : 0Fh and 09h
B : 09H and 0FH
C : 08 and 0EH
D : 09 and 0F
A : 90
B : 32
C : 60
D : 50
Q.no 53.
A : Yes
B : No
C : Undefined
A : T1CKPS1,T1CKPS0
B : TMR1CS,TMR1ON
C : T1CKPS0,T1CKPS1
D : TMR1ON,TMR1CS
A : column 0
B : column 1
C : column 2
D : column 3

C : Watch dog timer
D : Reset voltage
A : INTCON,IPR
B : PIR
C : TCON,RCON
D : TCON
A : 400kHz
B : 300KHZ
C : 250 KHz
D : 1KHz
A : Data Bus
B : ALU
C : Control Bus
D : Address Bus
A : Driver
B : Isolater
C : Latch
D : Buffer
A:8
B : 16
C : 32
D : 64
A : Incremental
B : Analogue
C : Electrical
D : Mechanical

A : DEMUX
B : MUX
D : Decoder
A : 8-bit
B : 16-bit
C : 20-bit
D : 21-bit
A : DTR
B : RTS & DTR
C : RTS and CTS
D : CTS
A : 30 msec
B : 25 msec
C : 40 msec
D : 20 msec
A : adder
B : subtrcter
C : memory
D : counter
microcontroller
A:2
B:4
C:8
D : 12
A : D7-D0
B : D3-D0
C : D4-D1
D : D7-D4
A : 128K
B : 64K
C : 32K
D : 16K
A : Vcc
B : GND
C : VCC and GND
D : VDD
A : RB0-RB7
B : RB0-RB3
C : RB4-RB7
B : Sense the fault

A : 20Kbps
B : 21 Mbps
C : 4kbps
D : 19.2 kbps
A : PORTD
B : PORTC
C : PORT A
D : Port B
pulse?
A : TCON
B : IE
C : IPR
D : SCON
A:B
B:A
C:a
D:b
B : Assembler
C : Debugger
D : Editor
Q.no 28. What the output of LM 35 for every degree change in temp
A : 20 mV
B : 15mV
C:5mV
D : 10mV
A : driven high
B : driven low
C : toggled
D : all the above
A : Adder
B : Shift Register
C : ADC
D : Counter
A : Input
B : output
C : tristate
A : 1.5mA
B : 2 mA
C : 3 mA
D : 1 mA
reset
A : OFF
B : undefined
C : ON
D : Tristate
in LCD are
A : 01H and F0H
B : E0H and 80H
C : E0H and C0H
D : 80H and C0H
A : Look up table
B : Bubble sort
C : Initilaisation
D : Rotation

A : TTL logic level
D : RS 485
B : Display of Char
D : Display of Text
A : ADON
B : GO/ DOWN
C : VCF
D : ADFM
A : 36
B : 136
C : 248
D : 120

TMR0H
A : SETB P1.0
B : SETB P 0.0
C : SETB P1.1
D : SETB P0.1
A : 88H, 98H, 99H, 87H, 0D0H
B : 98H, 99H, 87H, 88H, 0D0H
C : 0D0H, 87H, 88H, 99H, 98H
D : 87H, 88H, 0D0H, 98H, 99H
A : Timer1
B : TIMER2
C : TIMER3
D : TIMER4
A : MOV A,P0
B : ADD A,05H
C : JNB P0.0, label
D : CLR P0.05H

A : 2 bytes
B : 4 bytes
C : 3 bytes
D : 1 byte
using mode0
A : 55,2A
B : 1C,67
C : 3A,22
D : 69,1C
A : Hardware only
C : Software only
D : Iref only
A : 4 bit mode
B : 8 bit mode
C : 12 bit mode
D : 16 bit mode
executed?
If (TMR0IF == 1)
{
TMR0ON = 0;
TMR0IF = 0;
TMR0H = 0xED;
TMR0L = 0xAF;
TMR0ON = 1;
}

C : Clear Timer0
A : 0xFCH
B : 0xFAH
C : 0xFBH
D : 0xFEH
A : 20
B : 50
C : 15
D : 10

A : RAM
B : I/O Ports
C : Peripharals
A : 1.6 ma
B : 60 MA
C : 50 Ma
D : 20 Ma
A:2
B:1
C:3
D:5
A : LATx=0x00h
B : PORT=0xFFH
C : TRISx=0x00h
D : TRISx=0xFFH
A : 2K,256 bytes
B : 4K, 256 bytes
C : 4K,128 bytes
D : 2K,128 bytes
A : Read the data

C : Hold the data
D : Detect the data
A : Buffer circuit
B : I- V Convertor
C : V-I Convertor
D : V-F Convertor
A : Enabled
B : Disabled
C : Undefined
A : DTR
B : DTS
C : SCL
D : SDA
A : Registers
B : Counters
C : Timers
A : Undefined
A : Data latch
B : Address latch
C : Signal latch
D : control latch
A : 8 bit
B : 10 bit
C : 12 bit
D : 14 bit
A : Tunnel Diode
B : Shockley Diode
D : Zener Diode
A : 10
B : 11
C : 12
D:8
A : DC to 20MHZ
B : AC to 20MHZ
C : 1 to 20MHZ
D : DC to 25MHZ
Q.no 19. What is the frequency of Clock used in RTC
A : 33 MHZ
B : 40 MHz
C : 32.786 MHz
D : 32 MHz
A : 12
B : 16
C : 10
D : 14

A : TRISA = 0XF0;
B : TRISA = 0X0F;
the opcode
A : a register
B : a number
C : a pointer
D : an address
A : RA0,RA1 and RA2

B : RB5,RB6 and RB7
C : RC0,RC1 and RC2
A : idle and sleep
Q.no 29. SSPSR is
C : Read only
D : Write only
A:2
B:3
C:1
D:4

D : WDT circuit
A : 40
B : 50
C : 60
D : 70
B : Conversion Time
C : Number of bits
D : Step Size
A:1
B:2
C:3
D:4
frequency of 22MHz?
A : 2978.9 sec
B : 0.011 msec
C : 11.63 sec
D : 2.97 msec
A : 128 Bytes
B : 256 Bytes
C : 1KByte
D : 128 Kbytes
A : Timer 0
D : Timer 2
A : 0Fh and 09h

B : 09H and 0FH
C : 08 and 0EH
D : 09 and 0F
A : Port C lines
B : Port D lines
C : Port B lines
D : Port E lines
A : 38h,0Eh,06h,01h
B : 38h,0Fh,06h,10h
C : 3Eh,0Eh,06h,01h
D : 38h,0Eh,08h,01h
reset?
A : 11
B:8
C:7
D:9
Q.no 47. SPI Is

Q.no 50.
A : Sowtooth
B : Square
C : Ramp
D : Sine
A : Vref/2& Vin
B : Vin
C : Vref/2
D : Vin/2
A : 256x8
B : 128x8
C : 128x4
D : 512x8
A : Clockwise
C : Anticlockwise
D : Reverse
A : T1CKPS1,T1CKPS0
B : TMR1CS,TMR1ON
C : T1CKPS0,T1CKPS1
D : TMR1ON,TMR1CS

A : 4 bit mode
B : 8 bit mode
C : 12 bit mode
D : 16 bit mode
A : 0xFCH
B : 0xFAH
C : 0xFBH
D : 0xFEH
A : I2C
C : SPI
D : I2C and SPI
A : RS=0, Rw=1
B : RS=0, EN=0
C : RS=0,RW=0
D : RW=0

A : pin1
B : pin4
C : pin9
D : pin20
A : OV
B : PSW
C : AC
D : CY
A : Aynchronous
C : Synchronous
D : Isochornous

B : Watch Dog Timer
motor
A : higher, lower
B : lower, higher
C : higher,higher
A : 64 KB
B : 16KB
C : 128KB
D : 256KB
A : Timer 0
B : Timer 1
C : Timer 2
D : Timer 3
A : 33
B : 35
C : 40
D : 75
A : 00-2F
B : 00-0F
C : 00-7F
D : 00-07
A : Synchronous
C : Asynchronous
D : Isochornous
A : sleep, idle
A : INTR
B : Data
D : BUFFER
in binary notation
A:0
B:1
C:F
D:7
A : EN, RW,RS
B : EN, INTR, RW
C : RS, RW, IE
D : EN and RW
A : 0,1
B : 0,1,2,3,4
C : A,B,C,D,E
D : A,B,C
A : Look up table
B : Bubble sort
C : Initilaisation
D : Rotation
A : Adder
B : Shift Register
C : ADC
D : Counter

A : PIR1
B : IPR
C : PIR2
D : INTCON2
A : 2.5 Mbits
B : 2 Mbits
C : 250 kbits
D : 1 Mbits
A : D7-D1
B : D7-D0
C : D3-D0
D : D7-D4
A : RB0-RB7
B : RB0-RB3
C : RB4-RB7

A : 0X0F
B : 0X08
C : 0x04
D : 0X0E

TRISB = 0x00;
LATB = 0xFF;
A : CCPCON
B : CCPR1L
C : PR2
D : T2CON
B : Sense the fault

B : Display of Char
D : Display of Text
______.
A : ADFM=0
B : ADFM=xx
C : ADFM= 1
D : ADFM=00

A : 100
B : 149
C : 200
D : 255
A : 20Kbps
B : 21 Mbps
C : 4kbps
D : 19.2 kbps
microcontrollers?
A : 8 bytes
B : 16 bytes
C : 32bytes
D : 128 bytes
A : SETB P1.0
B : SETB P 0.0
C : SETB P1.1
D : SETB P0.1
A : 88H, 98H, 99H, 87H, 0D0H
B : 98H, 99H, 87H, 88H, 0D0H
C : 0D0H, 87H, 88H, 99H, 98H
D : 87H, 88H, 0D0H, 98H, 99H

A : 90
B : 32
C : 60
D : 50
executed?
If (TMR0IF == 1)
{
TMR0ON = 0;
TMR0IF = 0;
TMR0H = 0xED;
TMR0L = 0xAF;
TMR0ON = 1;
}
A : 20
B : 50
C : 15
D : 10
A : Hardware only
C : Software only
D : Iref only
A : 2 bytes
B : 4 bytes
C : 3 bytes
D : 1 byte
C : Clear Timer0
Q.no 49.
A : Yes
B : No
C : Undefined

A : 36
B : 136
C : 248
D : 120

C : Watch dog timer
D : Reset voltage
A : 0Fh and 09h
B : 09H and 0FH
C : 08 and 0EH
D : 09 and 0F
A : column 0
B : column 1
C : column 2
D : column 3
A : MOV A,P0
B : ADD A,05H
C : JNB P0.0, label
D : CLR P0.05H

condition in I2c
A : N+1
B:N
C : N-1
D : N+2
microcontroller
A:2
B:4
C:8
D : 12
through it?

A:2
B:3
C:4
D:1
A : DEMUX
B : MUX
D : Decoder
A : INTCON,IPR
B : PIR
C : TCON,RCON
D : TCON
Q.no 9. what is PIC

the LCD
A : H - to - L
B : L - to - H
C : always H
D : always L
A : Undefined
in UART
A : RCSTA and TXSTA
B : TXSTA only
C : RCSTA only
D : TXSTA and RCSTA
A : 8-bit
B : 16-bit
C : 20-bit
D : 21-bit

A : 128K
B : 64K
C : 32K
D : 16K
B : Select Channel
C : Slect Clock
A : TCON
B : SCON
C : TMOD
D : SMOD
A : adder
B : subtrcter
C : memory
D : counter
A:2
B:3
C:4
D:1
20MHz?
D : 1 micro seconds
B : Conversion Time
C : Number of bits
D : Step Size

A : 1.10001E7
B : 1.1110011E7
C : 1.111E7
D : 1.1110001E7
A : SSPCON1
B : SSPSTAT
D : SSPBUF
A : IE
B : RI
C : TI
D : RI,TI
A : PORTD
B : PORTC
C : PORT A
D : Port B
A : TRISA = 0XF0;
B : TRISA = 0X0F;
channel 7
A:2
B:4
C:1
D:3
A : PSEN
B : EA
C : clock
D : address
A : 0x0003h
B : 0x000Bh
C : 0x0023h
D : 0x0013h
B : Assembler
C : Debugger
D : Editor
microsecond
A : 250
B : 249
C : 255
D : 149
pulse?
A : TCON
B : IE
C : IPR
D : SCON
A:4
B:2
C:3
D:6
A:3
B:5
C:8
D : 10
Q.no 42.
A : CY=0,AC=0,P=0
B : CY=0,AC=1,P=0
C : CY=1,AC=1,P=1
D : CY=1,AC=1,P=0
A : Busy flag
B : Status flag
C : Driver flag
D : mode flag
A : Port C lines
B : Port D lines
C : Port B lines
D : Port E lines
A : Timer1
B : TIMER2
C : TIMER3
D : TIMER4
A : 4 bit mode
B : 8 bit mode
C : 12 bit mode
D : 16 bit mode
using mode0
A : 55,2A
B : 1C,67
C : 3A,22
D : 69,1C
Q.no 52.
A : Sowtooth
B : Square
C : Ramp
D : Sine
A : 11
B:8
C:7
D:9
A : 0xFCH
B : 0xFAH
C : 0xFBH
D : 0xFEH
A : 38h,0Eh,06h,01h
B : 38h,0Fh,06h,10h
C : 3Eh,0Eh,06h,01h
D : 38h,0Eh,08h,01h

TMR0H
A : 130
B : 129
C : 131
D : 132
A : 1.3x Vbat
B : 1.25x Vcc
C : 1.25x Vbat
D : 1.3x Vcc
A : 256x8
B : 128x8
C : 128x4
D : 512x8
A : GIE
B : PEIE
C : IE
D : INTIE
A : 40
B : 20
C : 16
D:8
C : logic high
D : logic low
A : Data latch
B : Address latch
C : Signal latch
D : control latch
A : R1, R2
B : R0,R1
C : R3,R0
D : R0,R2
A : FFH
B : C0H
C : 80H
D : 90H
A : 10
B : 11
C : 12
D:8
B : Motor control
C : Switching
D : Breaker
A : Vcc
B : GND
C : VCC and GND
D : VDD
A : LATx=0x00h
B : PORT=0xFFH
C : TRISx=0x00h
D : TRISx=0xFFH
A : DTR
B : RTS & DTR
C : RTS and CTS
D : CTS
A : TRIS
B : LAT
C : READ
D : PORT
A:2
B:1
C:3
D:5
A : MOSI and MISO
B : only MISO
C : MISO and MOSI
D : Only MOSI

A : RAM
B : I/O Ports
C : Peripharals
A : Port C lines
B : Port B lines
C : Port D lines
D : Port E lines
A : 0000h
B : 001Bh
C : 000008h
D : 000018h
A : 4mtrs
B : 6 mtrs
C : 5 mtrs
D : 1 mtrs
B : Sense the fault

A : 128 Bytes
B : 256 Bytes
C : 1KByte
D : 128 Kbytes
B : Display of Char
D : Display of Text
A : Timer 0

D : Timer 2
A : RB0-RB7
B : RB0-RB3
C : RB4-RB7
A : BRGH=1
C : BRGH = 0and 1
D : BRGH=0
A : Analog
B : Digital
D : Descrite
A : 64 bit
B : 16 bit
C : 32 bit
D : 8 bit
A : idle and sleep
A : Analog
B : Digital
D : descrite
A : Input
B : output
C : tristate
A : driven high
B : driven low
C : toggled
D : all the above
A : 2048 bits
B : 4096 bits
C : 1024 bits
D : 512 bits
A:3
B:6
C:4
D:5
A : 10
B : 12
C : 14
D : 16
A : Hardware only
C : Software only
D : Iref only
A : 20
B : 50
C : 15
D : 10
A : 36
B : 136
C : 248
D : 120
A : MOV A,P0
B : ADD A,05H
C : JNB P0.0, label
D : CLR P0.05H
A : Clockwise
C : Anticlockwise
D : Reverse
A : 2 bytes
B : 4 bytes
C : 3 bytes
D : 1 byte
C : Clear Timer0
executed?
If (TMR0IF == 1)
{
TMR0ON = 0;
TMR0IF = 0;
TMR0H = 0xED;
TMR0L = 0xAF;
TMR0ON = 1;
}
Q.no 53. SPI Is
A : 0Fh and 09h
B : 09H and 0FH
C : 08 and 0EH
D : 09 and 0F
A : T1CKPS1,T1CKPS0
B : TMR1CS,TMR1ON
C : T1CKPS0,T1CKPS1
D : TMR1ON,TMR1CS
A : Vref/2& Vin
B : Vin
C : Vref/2
D : Vin/2
A : 88H, 98H, 99H, 87H, 0D0H
B : 98H, 99H, 87H, 88H, 0D0H
C : 0D0H, 87H, 88H, 99H, 98H
D : 87H, 88H, 0D0H, 98H, 99H
C : Watch dog timer
D : Reset voltage
A : Undefined
A : EN, RW,RS
B : EN, INTR, RW
C : RS, RW, IE
D : EN and RW
in binary notation
A:0
B:1
C:F
D:7
A : 10 bits
B : 12 bits
C : 11 bits
D : 8 bits
Q.no 6. what is PIC

A : Zero Flag
B : Negative Flag
C : Overflow Flag
D : Carry Flag
A : Only Graphics
B : Only numbers
D : only text
A : Driver
B : Isolater
C : Latch
D : Buffer
A : Data Bus
B : ALU
C : Control Bus
D : Address Bus
A:1
B:2
C:3
D:4
A : I2C
C : SPI
D : I2C and SPI
A : 64 KB
B : 16KB
C : 128KB
D : 256KB
motor
A : higher, lower
B : lower, higher
C : higher,higher
A : DTR
B : DTS
C : SCL
D : SDA
A : adder
B : subtrcter
C : memory
D : counter
A : Timer 0
B : Timer 1
C : Timer 2
D : Timer 3
B : Select Channel
C : Slect Clock
B : Torque
C : Current rating
D : Pressure
A : 5 feet
B : 25 feet
C : 10 feet
D : 2 mtrs
______.
A:1
B:2
C:3
D:4
A : 2K
B : 8k
C : 2MB
D : 64KB
A : Rs232 and RS485
A : 2.5 Mbits
B : 2 Mbits
C : 250 kbits
D : 1 Mbits
A : 25 bytes
B : 30 bytes
C : 58 bytes
D : 56 bytes
is
A:0
B:1
C : 10
D : 11
A : 1.5mA
B : 2 mA
C : 3 mA
D : 1 mA
Q.no 34. RS 485 uses principle of
A : Single drop
B : Multiplexing
C : Multidrop
D : single and multi drop
A : CCPCON
B : CCPR1L
C : PR2
D : T2CON
the opcode
A : a register
B : a number
C : a pointer
D : an address
A:B
B:A
C:a
D:b
Q.no 40. PIC 18F4550 has ____ External Interrupts
A : Five
B : Four
C : Six
D : Two

A : 11
B:8
C:7
D:9
A : 256x8
B : 128x8
C : 128x4
D : 512x8
A : 130
B : 129
C : 131
D : 132
Q.no 47.
A : Sowtooth
B : Square
C : Ramp
D : Sine
A : 90
B : 32
C : 60
D : 50
using mode0
A : 55,2A
B : 1C,67
C : 3A,22
D : 69,1C
A : SETB P1.0
B : SETB P 0.0
C : SETB P1.1
D : SETB P0.1
A : 4 bit mode
B : 8 bit mode
C : 12 bit mode
D : 16 bit mode
reset?


TMR0H
A : 38h,0Eh,06h,01h
B : 38h,0Fh,06h,10h
C : 3Eh,0Eh,06h,01h
D : 38h,0Eh,08h,01h
A : column 0
B : column 1
C : column 2
D : column 3
A : 1.3x Vbat
B : 1.25x Vcc
C : 1.25x Vbat
D : 1.3x Vcc
Q.no 60.
A : Yes
B : No
C : Undefined
A:2
B:1
C:3
D:5
B : Watch Dog Timer
A : 4
B:5
C:6
D:8
A : 33
B : 35
C : 40
D : 75
A : 4 bit
B : 8 bit
C : 11 bit
D : 16 bit
A : D7-D0
B : D3-D0
C : D4-D1
D : D7-D4
A : Buffer circuit
B : I- V Convertor
C : V-I Convertor
D : V-F Convertor
A : 00-2F
B : 00-0F
C : 00-7F
D : 00-07
A : pin1
B : pin4
C : pin9
D : pin20
A : Synchronous
C : Asynchronous
D : Isochornous
A : Data
B : Command
C : R -2R ladder
D : SAR
A : LATx=0x00h
B : PORT=0xFFH
C : TRISx=0x00h
D : TRISx=0xFFH
A : 01H
B : 06H
C : 38H
D : OFEH
A : 10
B : 11
C : 12
D:8

A : RAM
B : I/O Ports
C : Peripharals
A : Dc to dc
B : Ac to ac
C : Dc to ac
C : logic high
D : logic low
A : 30 msec
B : 25 msec
C : 40 msec
D : 20 msec
A : IE
B : RI
C : TI
D : RI,TI
A : driven high
B : driven low
C : toggled
D : all the above
A : 0x00H
B : 0xFFH
C : 0x10H
D : 0xF0H
A : Look up table
B : Bubble sort
C : Initilaisation
D : Rotation

A : .hex
B : .c
C : .txt
D : .doc
A : D7-D1
B : D7-D0
C : D3-D0
D : D7-D4
A : 100
B : 149
C : 200
D : 255

A : Dc-20 MHz
B : Dc-48MHz
C : Dc-40 MHz
D : Dc-60 MHz
A : TRISA = 0XF0;
B : TRISA = 0X0F;
D : Changing Power
A : 2 Mbits/s
B : 1 Mbits/s
C : 3 Mbits/s
D : 5 Mbits/s
A : 128 Bytes
B : 256 Bytes
C : 1KByte
D : 128 Kbytes
A : PIR1
B : IPR
C : PIR2
D : INTCON2
C : Watch dog timer
D : Reset voltage
A : 0Fh and 09h
B : 09H and 0FH
C : 08 and 0EH
D : 09 and 0F
A : Timer1
B : TIMER2
C : TIMER3
D : TIMER4
A : T1CKPS1,T1CKPS0
B : TMR1CS,TMR1ON
C : T1CKPS0,T1CKPS1
D : TMR1ON,TMR1CS
A : 88H, 98H, 99H, 87H, 0D0H
B : 98H, 99H, 87H, 88H, 0D0H
C : 0D0H, 87H, 88H, 99H, 98H
D : 87H, 88H, 0D0H, 98H, 99H
C : Clear Timer0
A : 0xFCH
B : 0xFAH
C : 0xFBH
D : 0xFEH
A : 2 bytes
B : 4 bytes
C : 3 bytes
D : 1 byte
Q.no 52.
A : CY=0,AC=0,P=0
B : CY=0,AC=1,P=0
C : CY=1,AC=1,P=1
D : CY=1,AC=1,P=0
A : 36
B : 136
C : 248
D : 120
A : MOV A,P0
B : ADD A,05H
C : JNB P0.0, label
D : CLR P0.05H
A : Hardware only
C : Software only
D : Iref only
A : Port C lines
B : Port D lines
C : Port B lines
D : Port E lines
Q.no 60. SPI Is
A : DTR
B : DTS
C : SCL
D : SDA
A : LAT
B : PORT
C : TRIS
D : DIR
A:3
B:5
C:2
D:1
A : EN, RW,RS
B : EN, INTR, RW
C : RS, RW, IE
D : EN and RW
A : 20
B:8
C : 21
D : 34
A : Enabled
B : Disabled
C : Undefined
A : R1, R2
B : R0,R1
C : R3,R0
D : R0,R2
A : freuency
B : Current
C : EMI
D : voltage
called as
A : Interrupt
D : Polling
B : Select Channel
C : Slect Clock
A : Timer 0
B : Timer 1
C : Timer 2
D : Timer 3
A : Registers
B : Counters
C : Timers
A : 8-bit
B : 16-bit
C : 20-bit
D : 21-bit
A : RS=0, Rw=1
B : RS=0, EN=0
C : RS=0,RW=0
D : RW=0
A : 12
B : 16
C : 10
D : 14
A : 0,1
B : 0,1,2,3,4
C : A,B,C,D,E
D : A,B,C
A : TTL logic level

D : RS 485
A : RA0,RA1 and RA2
B : RB5,RB6 and RB7
C : RC0,RC1 and RC2
A : 1.10001E7
B : 1.1110011E7
C : 1.111E7
D : 1.1110001E7
the opcode
A : a register
B : a number
C : a pointer
D : an address

20MHz?
D : 1 micro seconds
B : Assembler
C : Debugger
D : Editor
A : PORTD
B : PORTC
C : PORT A
D : Port B
A : RC6 and RC7
B : RC2 and RC3
C : RC7 and RC6
D : RB2 and RB1
in LCD are
A : 01H and F0H
B : E0H and 80H
C : E0H and C0H
D : 80H and C0H
channel 7
A:2
B:4
C:1
D:3
B : Conversion Time
C : Number of bits
D : Step Size
A : 4mtrs
B : 6 mtrs
C : 5 mtrs
D : 1 mtrs
A : 1.5mA
B : 2 mA
C : 3 mA
D : 1 mA
A : 130
B : 129
C : 131
D : 132

A : 1.3x Vbat
B : 1.25x Vcc
C : 1.25x Vbat
D : 1.3x Vcc
A : Busy flag
B : Status flag
C : Driver flag
D : mode flag
A : 256x8
B : 128x8
C : 128x4
D : 512x8
A : column 0
B : column 1
C : column 2
D : column 3

TMR0H
A : SETB P1.0
B : SETB P 0.0
C : SETB P1.1
D : SETB P0.1

A : 11
B:8
C:7
D:9
reset?
executed?
If (TMR0IF == 1)
{
TMR0ON = 0;
TMR0IF = 0;
TMR0H = 0xED;
TMR0L = 0xAF;
TMR0ON = 1;
}
A : 4 bit mode
B : 8 bit mode
C : 12 bit mode
D : 16 bit mode
A : Clockwise
C : Anticlockwise
D : Reverse
A : Vref/2& Vin
B : Vin
C : Vref/2
D : Vin/2
1. What is size of Register? (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP, GDTR, LDTR, IDTR, TR,
MSW)
2. Explain Control Register?
3. Explain Test Register?
4. Explain Debug Register?
5. Explain Flag Register? (Status, Control, System) (Specific each Flag)
6. Explain Architecture of 80386?
7. Explain Pin Diagram of 80386? (Any 5 pin)
8. What is Protected mode?
9. What is Real Mode?
10. What is Virtual Mode?
11. Difference of Real, Virtual, Protected Mode?
12. How many descriptors in GDT, IDT, LDT?
13. Explain any five instructions from Application Instruction set? (Application Instruction set:
Arithmetic, logical, control transfer, Data movement, Decimal Arithmetic Instruction, String
& Character transfer, Instruction for Block Structured language, Flag control, Coprocessor
interface instruction, segment register instruction, Miscellaneous instruction)
14. What are the different section in Assembly program?
15. What is the use of data section?
16. What is the use of text section?
17. What is the use of bss section?
18. Full form of bss?
19. Logic of Add & shift Multiplication?
20. Logic of multiplication using Successive addition method?
21. What is Microprocessor?
22. What is Assembly?
23. What is Assembly Language?
24. What is Assembly Language Program?
25. What is Register?
26. What is DATA or CODE or STACK segment Register?
27. What is Load Effective Address?
28. What is int 0x80 in the program?
29. What is DW, DB in the program?
30. What is DD, DQ in the program?
31. What is CX register in the program of the loops?
32. Explain use of Macro?
33. Explain difference between overlap and non-overlap program logic?
34. What is CLC in the program?
35. What is INC? (With example)
36. What is ADC? (With example)
37. What is SBB? (With example)
38. What is CMP? (With example)
39. What is JC? (With example)
40. What is XCHG? (With example)
41. What is DEC? (With example)
42. What is JNZ? (With example)
Note: like other Instructions which are use in Program.

43. what is the difference between RET and IRET?
44. What is register?
45. What is the use of BT and how it used?
46. How can we display output from system to Monitor? (Procedure)

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All Course MCQ

आमचा हे तू फक्त तु मच्या ज्ञानात भर दे ण्याचा आहे . तु म्हाला Exam मधी

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2) Attempt any 50 questions out of 60.

3) Use of calculator is allowed.

4) Each question carries 1 Mark.

5) Specially abled students are allowed 20 minutes extra for examination.

6) Do not use pencils to darken answer.

8) No change will be allowed once the answer is marked on OMR Sheet.

9) Rough work shall not be done on OMR sheet or on question paper.

10) Darken ONLY ONE CIRCLE for each answer.

Q.no 1. The limit field of the descriptor is of

Q.no 2. ESP Register is used to access ------ segment

A : Interrupt service routine

B : Counter word register

Q.no 4. What is stored in Task Register

A : Selector to TSS descriptor of currently executing task

B : Base address of GDT

D : All of the above.

Q.no 5. Segmentation Unit translates ------------------- When paging is diabled .

A : logical address to physical address

B : linear address to physical address

C : logical address to linear address

D : logical address to absolute address

Q.no 7. A near pointer is an offset ----- a segment

Q.no 9. Interrupt 4 represents following exception

B : Bounds Check exception

Q.no 13. Which IOPL value has highest priority?

Q.no 14. When carry flag is set?

A : If carry generated out of MSB

B : If carry generated out of D15 bit

C : If carry generated out of D3 bit

Q.no 16. The linear address is calculated by

A : effective address + segment base address

B : effective address –segment base address

C : effective address + physical address

D : effective address –physical address

Q.no 17. If CPL=0 then the processor is executing at _______________.

Q.no 19. Interrupts give using INT instruction are called

A : Target segment descriptor.

B : Interrupt gate descriptor

D : None of the above.

Q.no 21. Type 2 system descriptor is -----------------.

C : a Call gate Descriptor

Q.no 22. Stack operations implicitly address operands via

Q.no 24. The sign bit is located in ----- in a byte.

Q.no 25. Interrupt that vectors through Trap gate

Q.no 28. At the end of ISR, the instruction should be

A : same address spaces

B : contiguous address spaces

C : distinct address spaces

D : external address spaces

Q.no 31. SLDT instruction is used for _________

A : Storing Local Descriptor Table

B : Storing Local Descriptor Table Register

A : DPL <= CPL