CS8491 COMPUTER ARCHITECTURE

UNIT - 1
1. The ______ format is usually used to store data.
a) BCD
b) Decimal
c) Hexadecimal
d) Octal
Answer: a
Explanation: The data usually used by computers have to be stored and represented in a
particular format for ease of use.
2. The 8-bit encoding format used to store data in a computer is ______
a) ASCII
b) EBCDIC
c) ANCI
d) USCII
Answer: b
Explanation: The data to be stored in the computers have to be encoded in a particular way
so as to provide secure processing of the data.
3. A source program is usually in _______
a) Assembly language
b) Machine level language
c) High-level language
d) Natural language
Answer: c
Explanation: The program written and before being compiled or assembled is called as a
source program.
4. Which memory device is generally made of semiconductors?
a) RAM
b) Hard-disk
c) Floppy disk
d) Cd disk
Answer: a
Explanation: Memory devices are usually made of semiconductors for faster manipulation of
the contents.
5. The small extremely fast, RAM’s are called as _______
a) Cache
b) Heaps
c) Accumulators
d) Stacks
Answer: a
Explanation: These small and fast memory devices are compared to RAM because they
optimize the performance of the system and they only keep files which are required by the
current process in them
6. The ALU makes use of _______ to store the intermediate results.
a) Accumulators
b) Registers
c) Heap
d) Stack
Answer: a
Explanation: The ALU is the computational center of the CPU. It performs all mathematical
and logical operations. In order to perform better, it uses some internal memory spaces to
store immediate results.
7. The control unit controls other units by generating ___________
a) Control signals
b) Timing signals
c) Transfer signals
d) Command Signals
Answer: b
Explanation: This unit is used to control and coordinate between the various parts and
components of the CPU.
8. ______ are numbers and encoded characters, generally used as operands.
a) Input
b) Data
c) Information
d) Stored Values
Answer: b
Explanation: None.
9. The Input devices can send information to the processor.
a) When the SIN status flag is set
b) When the data arrives regardless of the SIN flag
c) Neither of the cases
d) Either of the cases
Answer: a
Explanation: The input devices use buffers to store the data received and when the buffer
has some data it sends it to the processor.
10. ______ bus structure is usually used to connect I/O devices.
a) Single bus
b) Multiple bus
c) Star bus
d) Rambus
Answer: a
Explanation: BUS is a bunch of wires which carry address, control signals and data. It is
used to connect various components of the computer.
11. The I/O interface required to connect the I/O device to the bus consists of ______
a) Address decoder and registers
b) Control circuits
c) Address decoder, registers and Control circuits
d) Only Control circuits
Answer: c
Explanation: The I/O devices are connected to the CPU via BUS and to interact with the
BUS they have an interface.
12. To reduce the memory access time we generally make use of ______
a) Heaps
b) Higher capacity RAM’s
c) SDRAM’s
d) Cache’s
Answer: d
Explanation: The time required to access a part of the memory for data retrieval.
13. ______ is generally used to increase the apparent size of physical memory.
a) Secondary memory
b) Virtual memory
c) Hard-disk
d) Disks
Answer: b
Explanation: Virtual memory is like an extension to the existing memory.
14. MFC stands for ___________
a) Memory Format Caches
b) Memory Function Complete
c) Memory Find Command
d) Mass Format Command
Answer: b
Explanation: This is a system command enabled when a memory function is completed by a
process.
15. The time delay between two successive initiations of memory operation _______
a) Memory access time
b) Memory search time
c) Memory cycle time
d) Instruction delay
Answer: c
Explanation: The time is taken to finish one task and to start another.
16. The decoded instruction is stored in ______
a) IR
b) PC
c) Registers
d) MDR
Answer: a
Explanation: The instruction after obtained from the PC, is decoded and operands are
fetched and stored in the IR.
17. The instruction -> Add LOCA, R0 does _______
a) Adds the value of LOCA to R0 and stores in the temp register
b) Adds the value of R0 to the address of LOCA
c) Adds the values of both LOCA and R0 and stores it in R0
d) Adds the value of LOCA with a value in accumulator and stores it in R0
Answer: c
Explanation: None.
18. Which registers can interact with the secondary storage?
a) MAR
b) PC
c) IR
d) R0
Answer: a
Explanation: MAR can interact with secondary storage in order to fetch data from it.
19. During the execution of a program which gets initialized first?
a) MDR
b) IR
c) PC
d) MAR
Answer: c
Explanation: For the execution of a process first the instruction is placed in the PC.
20. Which of the register/s of the processor is/are connected to Memory Bus?
a) PC
b) MAR
c) IR
d) Both PC and MAR
Answer: b
Explanation: MAR is connected to the memory BUS in order to access the memory.
21. ISP stands for _________
a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
d) Interrupt Service Procedure
Answer: a
Explanation: None.
22. The internal components of the processor are connected by _______
a) Processor intra-connectivity circuitry
b) Processor bus
c) Memory bus
d) Rambus
Answer: b
Explanation: The processor BUS is used to connect the various parts in order to provide a
direct connection to the CPU.
23. ______ is used to choose between incrementing the PC or performing ALU operations.
a) Conditional codes
b) Multiplexer
c) Control unit
d) None of the mentioned
Answer: b
Explanation: The multiplexer circuit is used to choose between the two as it can give
different results based on the input.
24. The registers, ALU and the interconnection between them are collectively called as
_____
a) process route
b) information trail
c) information path
d) data path
Answer: d
Explanation: The Operational and processing part of the CPU are collectively called as a
data path.
25. _______ is used to store data in registers.
a) D flip flop
b) JK flip flop
c) RS flip flop
d) None of the mentioned
Answer: a
26. The main virtue for using single Bus structure is ____________
a) Fast data transfers
b) Cost effective connectivity and speed
c) Cost effective connectivity and ease of attaching peripheral devices
d) None of the mentioned
Answer: c
Explanation: By using a single BUS structure we can minimize the amount of hardware
(wire) required and thereby reducing the cost.
27. ______ are used to overcome the difference in data transfer speeds of various devices.
a) Speed enhancing circuitory
b) Bridge circuits
c) Multiple Buses
d) Buffer registers
Answer: d
Explanation: By using Buffer registers, the processor sends the data to the I/O device at the
processor speed and the data gets stored in the buffer. After that the data gets sent to or
from the buffer to the devices at the device speed.
28. To extend the connectivity of the processor bus we use ________
a) PCI bus
b) SCSI bus
c) Controllers
d) Multiple bus
Answer: a
Explanation: PCI BUS is used to connect other peripheral devices that require a direct
connection with the processor.
30. IBM developed a bus standard for their line of computers ‘PC AT’ called _____
a) IB bus
b) M-bus
c) ISA
d) None of the mentioned
Answer: c
Explanation: None.
31. The bus used to connect the monitor to the CPU is ______
a) PCI bus
b) SCSI bus
c) Memory bus
d) Rambus
Answer: b
Explanation: SCSI BUS is usually used to connect video devices to the processor.
32. ANSI stands for __________
a) American National Standards Institute
b) American National Standard Interface
c) American Network Standard Interfacing
d) American Network Security Interrupt
Answer: a
33. _____ register Connected to the Processor bus is a single-way transfer capable.
a) PC
b) IR
c) Temp
d) Z
Answer: d
Explanation: The Z register is a special register which can interact with the processor BUS
only.
34. In multiple Bus organisation, the registers are collectively placed and referred as
______
a) Set registers
b) Register file
c) Register Block
d) Map registers
Answer: b
Explanation: None.
35. The main advantage of multiple bus organisation over a single bus is _____
a) Reduction in the number of cycles for execution
b) Increase in size of the registers
c) Better Connectivity
d) None of the mentioned
Answer: a
Explanation: None.
36. The ISA standard Buses are used to connect ___________
a) RAM and processor
b) GPU and processor
c) Harddisk and Processor
d) CD/DVD drives and Processor
Answer: c
37. During the execution of the instructions, a copy of the instructions is placed in the
______
a) Register
b) RAM
c) System heap
d) Cache
Answer: d
38. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively.
Suppose A can execute an instruction with an average of 3 steps and B can execute with
an average of 5 steps. For the execution of the same instruction which processor is faster?
a) A
b) B
c) Both take the same time
d) Insufficient information
Answer: a
Explanation: The performance of a system can be found out using the Basic performance
formula.
39. A processor performing fetch or decoding of different instruction during the execution of
another instruction is called ______
a) Super-scaling
b) Pipe-lining
c) Parallel Computation
d) None of the mentioned
Answer: b
Explanation: Pipe-lining is the process of improving the performance of the system by
processing different instructions at the same time, with only one instruction performing one
specific operation.
40. For a given FINITE number of instructions to be executed, which architecture of the
processor provides for a faster execution?
a) ISA
b) ANSA
c) Super-scalar
d) All of the mentioned
Answer: c
Explanation: In super-scalar architecture, the instructions are set in groups and they’re
decoded and executed together reducing the amount of time required to process them.
41. The clock rate of the processor can be improved by _________
a) Improving the IC technology of the logic circuits
b) Reducing the amount of processing done in one step
c) By using the overclocking method
d) All of the mentioned
Answer: d
Explanation: The clock rate(frequency of the processor) is the hardware dependent quantity
it is fixed for a given processor.
42. An optimizing Compiler does _________
a) Better compilation of the given piece of code
b) Takes advantage of the type of processor and reduces its process time
c) Does better memory management
d) None of the mentioned
Answer: b
Explanation: An optimizing compiler is a compiler designed for the specific purpose of
increasing the operation speed of the processor by reducing the time taken to compile the
program instructions.
43. The ultimate goal of a compiler is to ________
a) Reduce the clock cycles for a programming task
b) Reduce the size of the object code
c) Be versatile
d) Be able to detect even the smallest of errors
Answer: a

44. SPEC stands for _______

a) Standard Performance Evaluation Code
b) System Processing Enhancing Code
c) System Performance Evaluation Corporation
d) Standard Processing Enhancement Corporation
Answer: c
Explanation: SPEC is a corporation that started to standardize the evaluation method of a
system’s performance.
45. As of 2000, the reference system to find the performance of a system is _____
a) Ultra SPARC 10
b) SUN SPARC
c) SUN II
d) None of the mentioned
Answer: a
Explanation: In SPEC system of measuring a system’s performance, a system is used as a
reference against which other systems are compared and performance is determined.
46. When Performing a looping operation, the instruction gets stored in the ______
a) Registers
b) Cache
c) System Heap
d) System stack
Answer: b
Explanation: When a looping or branching operation is carried out the offset value is stored
in the cache along with the data.
47. The average number of steps taken to execute the set of instructions can be made to be
less than one by following _______
a) ISA
b) Pipe-lining
c) Super-scaling
d) Sequential
Answer: c
Explanation: The number of steps required to execute a given set of instructions is
sufficiently reduced by using super-scaling. In this method, a set of instructions are grouped
together and are processed.
48. If a processor clock is rated as 1250 million cycles per second, then its clock period is
________
a) 1.9 * 10-10 sec
b) 1.6 * 10-9 sec
c) 1.25 * 10-10 sec
d) 8 * 10-10 sec
Answer: d
49. If the instruction, Add R1, R2, R3 is executed in a system that is pipe-lined, then the
value of S is (Where S is a term of the Basic performance equation)?
a) 3
b) ~2
c) ~1
d) 6
Answer: c
Explanation: S is the number of steps required to execute the instructions.
50. CISC stands for _______
a) Complete Instruction Sequential Compilation
b) Computer Integrated Sequential Compiler
c) Complex Instruction Set Computer
d) Complex Instruction Sequential Compilation
Answer: c
Explanation: CISC is a type of system architecture where complex instructions are grouped
together and executed to improve system performance.
51. As of 2000, the reference system to find the SPEC rating are built with _____
Processor.
a) Intel Atom SParc 300Mhz
b) Ultra SPARC -IIi 300MHZ
c) Amd Neutrino series
d) ASUS A series 450 Mhz
Answer: b
52. The instruction, Add #45,R1 does _______
a) Adds the value of 45 to the address of R1 and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in R1
c) Finds the memory location 45 and adds that content to that of R1
d) None of the mentioned
Answer: b
Explanation: The instruction is using immediate addressing mode hence the value is stored
in the location 45 is added.
53. In the case of, Zero-address instruction method the operands are stored in _____
a) Registers
b) Accumulators
c) Push down stack
d) Cache
Answer: c
Explanation: In this case, the operands are implicitly loaded onto the ALU.
54. Add #45, when this instruction is executed the following happen/s _______
a) The processor raises an error and requests for one more operand
b) The value stored in memory location 45 is retrieved and one more operand is requested
c) The value 45 gets added to the value on the stack and is pushed onto the stack
d) None of the mentioned
Answer: b
55. The addressing mode which makes use of in-direction pointers is ______
a) Indirect addressing mode
b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode
Answer: a
Explanation: In this addressing mode, the value of the register serves as another memory
location and hence we use pointers to get the data.
56. In the following indexed addressing mode instruction, MOV 5(R1), LOC the effective
address is ______
a) EA = 5+R1
b) EA = R1
c) EA = [R1]
d) EA = 5+[R1]
Answer: d
Explanation: This instruction is in Base with offset addressing mode.
57. The addressing mode/s, which uses the PC instead of a general purpose register is
______
a) Indexed with offset
b) Relative
c) Direct
d) Both Indexed with offset and direct
Answer: b
Explanation: In this, the contents of the PC are directly incremented.
58. When we use auto increment or auto decrements, which of the following is/are true?
1) In both, the address is used to retrieve the operand and then the address gets altered
2) In auto increment, the operand is retrieved first and then the address altered
3) Both of them can be used on general purpose registers as well as memory locations
a) 1, 2, 3
b) 2
c) 1, 3
d) 2, 3
Answer: d
Explanation: In the case of, auto increment the increment is done afterward and in auto
decrement the decrement is done first.
59. The addressing mode, where you directly specify the operand value is _______
a) Immediate
b) Direct
c) Definite
d) Relative
Answer: a
60. The effective address of the following instruction is MUL 5(R1,R2).
a) 5+R1+R2
b) 5+(R1*R2)
c) 5+[R1]+[R2]
d) 5*([R1]+[R2])
Answer: c
Explanation: The addressing mode used is base with offset and index.
61. _____ addressing mode is most suitable to change the normal sequence of execution of
instructions.
a) Relative
b) Indirect
c) Index with Offset
d) Immediate
Answer: a
Explanation: The relative addressing mode is used for this since it directly updates the PC.
62. ___________ symbol is used to signify write back mode.
a) #
b) ^
c) &
d) !
Answer: d
63. The instructions which are used to load or store multiple operands are called as
__________
a) Banked instructions
b) Lump transfer instructions
c) Block transfer instructions
d) DMA instructions
Answer: c
Explanation: These instructions are generally used to perform memory transfer operations.
64. The Instruction, LDM R10!, {R0,R1,R6,R7} ______
a) Loads the contents of R10 into R1, R0, R6 and R7
b) Creates a copy of the contents of R10 in the other registers except for the above
mentioned ones
c) Loads the contents of the registers R1, R0, R6 and R7 to R10
d) Writes the contents of R10 into the above mentioned registers and clears R10
Answer: a
Explanation: The LDM instruction is used to load data into multiple locations.
65. The instruction, MLA R0,R1,R2,R3 performs _________
a) R0<-[R1]+[R2]+[R3]
b) R3<-[R0]+[R1]+[R2]
c) R0<-[R1]*[R2]+[R3]
d) R3<-[R0]*[R1]+[R2]
Answer: c
Explanation: The MLA instruction is used perform addition and multiplication together.
66. The ability to shift or rotate in the same instruction along with other operation is
performed with the help of _________
a) Switching circuit
b) Barrel switcher circuit
c) Integrated Switching circuit
d) Multiplexer circuit
Answer: b
Explanation: These switching circuits are used to basically switch fast and to perform better.
67. _________ instruction is used to get the 1’s complement of the operand.
a) COMP
b) BIC
c) ~CMP
d) MVN
Answer: d
Explanation: The complement of all the bits of a data is its 1’s compliment.
68. The offset used in the conditional branching is __________ bit.
a) 24
b) 32
c) 16
d) 8
Answer: a
Explanation: The offset is used to get the new branching address of the process.
69. The BEQ instructions is used ____________
a) To check the equality condition between the operands and then branch
b) To check if the Operand is greater than the condition value and then branch
c) To check if the flag Z is set to 1 and then causes branch
d) None of the mentioned
Answer: c
Explanation: This instruction is basically used to check the branch enable bit.
70. The condition to check whether the branch should happen or not is given by
____________
a) The lower order 8 bits of the instruction
b) The higher order 4 bits of the instruction
c) The lower order 4 bits of the instruction
d) The higher order 8 bits of the instruction
Answer: b
Explanation: None.
71. Which of the two instructions sets the condition flag upon execution?
i) ADDS R0,R1,R2
ii) ADD R0,R1,R2
a) i
b) ii
c) Both i and ii
d) Insufficient data
Answer: a
Explanation: This instruction sets the condition flag without considering whether a carry or
overflow has happened or not.
72. __________ directive is used to indicate the beginning of the program instruction or
data.
a) EQU
b) START
c) AREA
d) SPACE
Answer: c
Explanation: None.
73. ___________ directive specifies the start of the execution.
a) START
b) ENTRY
c) MAIN
d) ORIGIN
Answer: b
Explanation: This directive indicates the beginning of the executable part of the program.
74. ___________ directives are used to initialize operands.
a) INT
b) DATAWORD
c) RESERVE
d) DCD
Answer: d
Explanation: These directives are used to initialize the operands to a user defined value or a
default value.
75. ___________ directive is used to name the register used for execution of an instruction.
a) ASSIGN
b) RN
c) NAME
d) DECLARE
76. The pseudo instruction used to load an address into the register is _________
a) LOAD
b) ADR
c) ASSIGN
d) PSLOAD
Answer: b