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    Coprocessor Configurations Closely Coupled Losely Coupled

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    lauro eugin britto
    This document discusses different coprocessor configurations including closely coupled and loosely coupled configurations. It describes how the WAIT and ESC instructions allow the CPU to synchronize with external hardware like a math coprocessor. A closely coupled configuration allows a coprocessor to take direct control of the bus while a loosely coupled configuration uses message passing through shared memory and interrupts. Loosely coupled configurations provide advantages like scalability, modularity, and fault tolerance through distributed processing across independent bus masters.

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    Coprocessor Configurations Closely Coupled Losely Coupled

    Uploaded by

    lauro eugin britto
    153 views9 pages
    This document discusses different coprocessor configurations including closely coupled and loosely coupled configurations. It describes how the WAIT and ESC instructions allow the CPU to synchronize with external hardware like a math coprocessor. A closely coupled configuration allows a coprocessor to take direct control of the bus while a loosely coupled configuration uses message passing through shared memory and interrupts. Loosely coupled configurations provide advantages like scalability, modularity, and fault tolerance through distributed processing across independent bus masters.

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    Coprocessor configurations closely coupled losely coupled

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    This document discusses different coprocessor configurations including closely coupled and loosely coupled configurations. It describes how the WAIT and ESC instructions allow the CPU to synchronize with external hardware like a math coprocessor. A closely coupled configuration allows a coprocessor to take direct control of the bus while a loosely coupled configuration uses message passing through shared memory and interrupts. Loosely coupled configurations provide advantages like scalability, modularity, and fault tolerance through distributed processing across independent bus masters.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    153 views9 pages

    Coprocessor Configurations Closely Coupled Losely Coupled

    Uploaded by

    lauro eugin britto
    This document discusses different coprocessor configurations including closely coupled and loosely coupled configurations. It describes how the WAIT and ESC instructions allow the CPU to synchronize with external hardware like a math coprocessor. A closely coupled configuration allows a coprocessor to take direct control of the bus while a loosely coupled configuration uses message passing through shared memory and interrupts. Loosely coupled configurations provide advantages like scalability, modularity, and fault tolerance through distributed processing across independent bus masters.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 9

    Coprocessor configurations, Closely and Loosely Coupled

    Configuration
    Coprocessor Configuration: WAIT instruction allows the processor to synchronize itself with external
    hardware, eg., waiting for 8087 math co-processor.

    Coprocessor configurations
     
    Coprocessor Configuration:
     
    WAIT instruction allows the processor to synchronize itself with external
    hardware, eg., waiting for 8087 math co-processor.
     
    When the CPU executes WAIT waiting state.
     
    TEST input is asserted (low), the waiting state is completed and execution will
    resume. ESC instruction:
     
    ESC opcode, operand, opcode: immediate value recognizable to a coprocessor as
    an instruction opcode
     
    Operand: name of a register or a memory address (in any mode)
     
    When the CPU executes the ESC instruction, the processor accesses the
    memory operand by placing the address on the address bus.
     
    If a coprocessor is configured to share the system bus, it will recognize the ESC
    instruction and therefore will get the opcode and the operand
      
     Coprocessor cannot take control of the bus, it does everything through the
    CPU

     Closely Coupled processor may take control of the bus independently - 8089
    shares CPU’s clock and bus control logic.
     communication with host CPU is by way of shared memory
     host sets up a message (command) in memory
     independent processor interrupts host on completion
     Two 8086’s cannot be closely coupled

    Closely Coupled Configuration
     
     

    Loosely Coupled Configurations:


    A loosely coupled configuration provides the following advantages:
     
    1. High system throughput can be achieved by having more than one CPU.
     
    2.  The system can be expanded in a modular form. Each bus master module
    is an independent unit and normally resides on a separate PC board.
    Therefore, a bus master module can be added or removed without affecting
    the other modules in the system.
    3.  A failure in one module normally does not cause a breakdown of the
    entire system and the faulty module can be easily detected and replaced.
     
    4. Each bus master may have a local bus to access dedicated memory or I/O
    devices so that a greater degree of parallel processing can be achieved. More
    than one bus master module may have access to the shared system bus
     
    Extra bus control logic must be provided to resolve the bus arbitration
    problem. The extra logic is called bus access logic and it is its responsibility
    to make sure that only one bus master at a time has control of the bus.
    Simultaneous bus requests are resolved on a priority basis: There are three
    schemes for establishing priority:
     
    1. Daisy chaining.
    2. Polling.
    3. Independent requesting
    The daisy-chaining method involves connecting all the devices that can request an interrupt in
    a serial manner. This configuration is governed by the priority of the devices. The device with
    the highest priority is placed first followed by the second highest priority device and so on.

    Polling is the process where the computer or controlling device waits for an external device to
    check for its readiness or state, often with low-level hardware. For example, when a printer is
    connected via a parallel port, the computer waits until the printer has received the next
    character.

    Fixed priority or Independent Request method –


    In this, each master has a separate pair of bus request and bus grant lines and each
    pair has a priority assigned to it. The built-in priority decoder within the controller selects
    the highest priority request and asserts the corresponding bus grant signal. Sep 1, 2020

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