Chapter 5

Chapter5:
1, What are block devices and character devices? Give examples
Block devices: is one that stores information in fixed-size blocks, each one with its
own address. Common block sizes range from 512 to 65,536 bytes. All transfers
are in units of one or more entire (consecutive) blocks. The essential property of a
block device is that it is possible to read or write each block independently of all
the other ones. Hard disks, Blu-ray discs, and USB sticks are common block
devices
Character devices: A character device deliv ers or accepts a stream of characters,
without regard to any block structure. It is not addressable and does not have any
seek operation
Example: . Printers, network interfaces, mice (for pointing), rats (for psychology
lab experiments), and most other devices that are not disk-like can be seen as
character devices
2, How does CPU communicate with control registers and data buffer?
With registers: Each controller has a few registers that are used for
communicating with the CPU. By writing into these registers, the operating system
can command the de vice to deliver data, accept data, switch itself on or off, or
otherwise perform some action. By reading from these registers, the operating
system can learn what the device’s state is, whether it is prepared to accept a new
command, and so on.
With data buffer: In addition to the control registers, many devices have a data
buffer that the op erating system can read and write which is basically just a data
buffer, available for programs or the operating system to write into.
3, What does a DMA contain? How does it work?
DMA contain memory addresses registered, counting bits, one or more controller
registers
When DMA is used, the procedure is different.
Step 1: . First the CPU programs the DMA controller by setting its registers so it
knows what to transfer where. It also issues a command to the disk controller
telling it to read data from the disk into its internal buffer and verify the checksum.
When valid data are in the disk controller’s buffer, DMA can begin.
Step 2: The DMA controller initiates the transfer by issuing a read request over the
bus to the disk controller. This read request looks like any other read request, and
the disk controller does not know (or care) whether it came from the CPU or from
a DMA controller.
Step 3: Typically, the memory address to write to is on the bus’ address lines, so
when the disk controller fetches the next word from its internal buffer, it knows
where to write it. The write to memory is another standard bus cycle
Step 4: When the write is complete, the disk controller sends an acknowl edgement
signal to the DMA controller, also over the bus.
4,a, What is a Program Counter? Explain how it work?

A, The Program Counter (PC) is a special register within the CPU that holds the
memory address of the next instruction to be fetched and executed. It plays a
fundamental role in the instruction execution cycle of a processor.
The interrupt signal causes the CPU to stop what it is doing and start doing
something else. The number on the address lines is used as an index into a table
called the interrupt vector to fetch a new program counter. This program counter
points to the start of the corresponding interrupt-service procedure. Typically
traps and interrupts use the same mechanism from this point on, often sharing the
same interrupt vector. The location of the interrupt vector can be hardwired into
the machine or it can be anywhere in memory, with a CPU register (loaded by
the operating system) pointing to its origin.
b, What are 4 properties of precise interrupt?
B, 4 properties of interrupt:
1, The PC (Program Counter) is saved in a known place.
2. All instructions before the one pointed to by the PC have completed.
3. No instruction beyond the one pointed to by the PC has finished.
4. The execution state of the instruction pointed to by the PC is known
5, Explain how programmed I/O works

Programmed I/O, also known as polling or busy waiting, is a straightforward method for
managing input/output operations in computer systems. It involves the CPU actively checking
the status of a device and performing necessary actions based on that status. Here's how
programmed I/O works based on the provided information:
Requesting Access:
The user process requests access to the printer by making a system call to open it. If the printer is
available, the call succeeds, otherwise, it may block until the printer becomes available.
Copying Data to Kernel Space:
Once access is granted, the user process requests the operating system to print a string on the
printer.
The operating system copies the string from the user buffer to a kernel buffer for easier access.
Checking Printer Status:
The operating system checks if the printer is available. If not, it waits until it becomes available.
When the printer becomes available, the operating system copies the first character from the
kernel buffer to the printer's data register, activating the printer.
Printing Characters:
The operating system continuously checks the status of the printer to see if it's ready to accept
another character.
When the printer is ready, the operating system sends the next character from the kernel buffer to
the printer's data register.
This process repeats until all characters in the string have been printed.
Returning Control:
Once all characters have been printed, control returns to the user process.
Busy Waiting:
During this entire process, the CPU is actively involved in checking the printer status and
sending characters to the printer.
This method ties up the CPU until all I/O operations are complete, making it inefficient in
systems where the CPU has other tasks to perform.
6, What are typical steps after a hardware interrupt complates?(10 Steps)

Step 1: Save any registers (including the PSW) that have not already been saved by
the interrupt hardware.
Step 2: Set up a context for the interrupt-service procedure. Doing this may involve
setting up the TLB, MMU and a page table.
Step 3: Set up a stack for the interrupt service-procedure.
Step 4: Acknowledge the interrupt controller. If there is no centralized inter rupt
controller, reenable interrupts.
Step 5: Copy the registers from where they were saved (possibly some stack) to the
process table.
Step 6: Run the interrupt-service procedure. It will extract information from the
interrupting device controller’s registers.
Step 7: Choose which process to run next. If the interrupt has caused some high-
priority process that was blocked to become ready, it may be chosen to run now.
Step 8: Set up the MMU context for the process to run next. Some TLB set up may
also be needed.
Step 9: Load the new process’ registers, including its PSW.
Step 10: Start running the new process
7, What are the differences between devices drives and devices controller?
Device drivers are software programs that facilitate communication between
the OS and hardware, device controllers are hardware components responsible
for managing specific device operations.
8, Explain buffering issues using fig 5.15 -5.16

In Fig. 5.15:
Different buffering schemes are illustrated, highlighting the trade-offs between efficiency and
complexity.
Unbuffered input (Fig. 5.15(a)) involves waking up the user process for each incoming character,
which is inefficient due to frequent process switching.
User-space buffering (Fig. 5.15(b)) improves efficiency by allowing the user process to provide a
buffer for storing incoming characters.
Kernel-level buffering (Fig. 5.15(c)) involves creating a buffer in the kernel space to store
incoming characters, enhancing efficiency but facing potential issues if data arrives while the
user buffer is being brought in from disk.
Double buffering in the kernel (Fig. 5.15(d)) minimizes the chances of missing incoming data by
using two buffers alternately, thus optimizing efficiency.
In Fig. 5.16:
The illustration demonstrates buffering issues in the context of network communication,
emphasizing the sequential steps involved in transmitting data over a network.
Buffering at different stages, including user space, kernel space, and network controller, is shown
to manage data flow and ensure uniform transmission speed.
However, the sequential copying process involved in buffering can impact transmission speed
due to the multiple steps required.
9, Explain the soven standard configurations of Raid(Fig 5.19 – 5.20)

RAID level 0:
Utilizes striping without parity or redundancy.
Data is divided into strips across multiple disks.
Offers increased performance for reads and writes as data is distributed across disks.
No fault tolerance; if one disk fails, data loss occurs.
RAID level 1:
Involves mirroring or duplication of disks.

Each disk is mirrored with another, creating identical copies.
Provides excellent fault tolerance as data redundancy ensures no data loss if one disk fails.
Read performance can be improved as data can be read from any of the mirrored disks.
RAID level 2:
Operates on a word or byte basis with Hamming code for error correction.
Data is divided into words or bytes and spread across multiple disks.
Requires synchronized drives and works with parity bits.
RAID level 3:
Utilizes striping with a dedicated parity disk.

Data is divided into strips with one parity bit computed for each data word.
Requires synchronized drives and provides fault tolerance through parity data.
RAID level 4:
Similar to RAID level 0 but with dedicated parity disk.

Parity information is stored on a separate disk.
May experience performance bottleneck due to heavy load on the parity disk.
RAID level 5:
Distributes parity bits across all disks.

Parity information is distributed evenly among disks, providing fault tolerance without
sacrificing performance.
Complex reconstruction process in case of drive failure.
RAID level 6:
Similar to RAID level 5 but with additional parity block.

Offers higher reliability compared to RAID level 5.
Requires more computational resources for parity calculations, but no performance penalty for
reads.

Chapter 5

Uploaded by

Copyright:

Available Formats

Chapter 5

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Chapter 5

Uploaded by

Copyright:

Available Formats

Chapter5:

1, What are block devices and character devices? Give examples

4,a, What is a Program Counter? Explain how it work?

5, Explain how programmed I/O works

6, What are typical steps after a hardware interrupt complates?(10 Steps)

8, Explain buffering issues using fig 5.15 -5.16

9, Explain the soven standard configurations of Raid(Fig 5.19 – 5.20)

Involves mirroring or duplication of disks.

Utilizes striping with a dedicated parity disk.

Similar to RAID level 0 but with dedicated parity disk.

Distributes parity bits across all disks.

Similar to RAID level 5 but with additional parity block.

You might also like