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MODULE – 1
DIGITAL FUNDAMENTALS AND LOGIC GATES
MODULE I - CONTENT
Digital fundamentals and logic gates - Introduction-number systems - binary number system –
conversion of decimal to binary and vice versa - arithmetic operations on binary - binary coded
decimal - one’s and two’s complement - use of complements - Hexadecimal number system -
conversion of decimal to hex to binary and vice versa - arithmetic operations on hex – BCD -
Packed and Unpacked BCD Numbers – HEX - ASCII codes - Logic gates-truth tables -
different logic families-Diode Logic-Transistor Logic- Resistor -Transistor- Diode-Transistor
Logic – Transistor - Transistor Logic - Complementary Metal Oxide Semiconductor Logic -
Propagation delay - current sourcing and current sinking - Fan in - Fan out – Power dissipation
- Speed.

1.1 Number Systems

(i) Decimal Number System
The decimal system contains ten unique symbols, 0, l, 2, 3, 4, 5, 6, 7, 8, and 9. Since counting
in decimal involves ten symbols, we say that its base or radix is ten. Each symbol in the number
is called a digit. The left most digit in any number representation, which has the greatest
positional weight out of all the digits present in that number, is called the most significant digit
(MSD) and the right most digit which has the least positional weight out of all the digits present
in that number, is called the least significant digit (LSD).
In general, the value of any mixed decimal number
dn dn-1 dn-2 . . . . d1 d0.d-1 d-2 d-3 . . .d-k
is given by
(dn x 10n)+(dn-1 x 10n-1)+ . . +(d1 x 101)+(d0 x 100)+(d-1 x 10-1)+(d-2 x 10-2) . .
Consider the decimal number 9256.26 using digits 2, 5, 6, 9. This is a mixed number.
Hence,
9256.26 = 9 x 1000 + 2 x 100 + 5 x 10 +6 x 1 + 2 x (1/10) + 6 x (1/100)
= 9 x 103 + 2 x 102 + 5 x 101 + 6 x 100 + 2 x l0-1 + 6 x l0-2
Consider another number 6592.69, using the same digits 2, 5, 6, 9. Here,
6592.69 = 6 x 103 + 5 x 102 + 9 x 101 + 2 x 100 + 6 x l0-1 + 9 x l0-2

(ii) Binary Number System

The base or radix of this number system is 2. The symbols used are 0 and l. A binary digit is
called a bit. A binary number consists of a sequence of bits, each of which is either a 0 or a l.
In general, a binary number with an integer part of (n+1) bits and a fraction part of k bits can
be written as
dn dn-1 dn-2 . . . . d1 d0.d-1 d-2 d-3 . . .d-k
Its decimal equivalent is
(dn x 2n)+(dn-1 x 2n-1)+ . . +(d1 x 21)+(d0 x 20)+(d-1 x 2-1)+(d-2 x 2-2)+ . .

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In general, the decimal equivalent of the number dn dn-1 dn-2 . . . . d1 d0.d-1 d-2 …in any number
system with base b is given by
(dn x bn)+(dn-1 x bn-1)+ . . +(d1 x b1)+(d0 x b0)+(d-1 x b-1)+(d-2 x b-2)+ . .

(iii) Hexadecimal Number System

Binary numbers are long. These numbers are fine for machines but are too lengthy to
be handled by human beings. So, there is a need to represent the binary numbers concisely.
One number system developed with this objective is the hexadecimal number system (or Hex).
The hexadecimal number system is a posiLi0na1gti system. The base or radix of this number
system is 16, that means, it has 16 independent symbols. The symbols used are 0, 1, 2, 3, 4, 5,
6, 7, 8, 9, A, B, C, D, E, and F. Since its base is 16 = 24, every 4 binary digit combination can
be represented by one hexadecimal digit. So, a hexadecimal number is 1/4th the length of the
corresponding binary number, yet it provides the same information as the binary number. A 4-
bit group is called a nibble. Since computer words come in 8 bits, 16 bits, 32 bits and so on,
that is, multiples of 4 bits, they can be easily represented in hexadecimal. The hexadecimal
system is particularly useful for human communications with computers. By far, this is the
most commonly used number system in computer literature. It is used both in large and small
computers.

1.2 Conversion of Number Systems

(i) Decimal to Binary Conversion

Any number consist of integer part and fractional part. The separate conversion steps
are followed for integer and fractional part of decimal number system.
Steps for conversion of decimal integer
Step 1: The given decimal integer is converted to binary by successive division by 2,
till the quotient is zero.
Step 2: The reminders read from bottom to top give the equivalent binary integer
number.
Steps for conversion of decimal fraction
Step 1: The given decimal fraction is successively multiplied by 2, till the fraction
part of the product is 0 or till the desired accuracy is obtained.
Step 2: The integer read from top to bottom give the equivalent binary fraction.

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(ii) Decimal to Hexadecimal Conversion

Steps for conversion of decimal integer
Step 1: The given decimal integer is converted to binary by successive division by
16, till the quotient is zero.
Step 2: The reminders read from bottom to top give the equivalent binary integer
number.
Steps for conversion of decimal fraction
Step 1: The given decimal fraction is successively multiplied by 16, till the fraction
part of the product is 0 or till the desired accuracy is obtained.
Step 2: The integer read from top to bottom give the equivalent binary fraction.

(iii) Binary to Decimal Conversion

Binary numbers may be converted to their decimal equivalents by the positional weights
method.
Step 1: Mark the positional weights for each bit (powers of 2).
Step 2: Multiply the positional weights with the bits and add the products together.
Step 3: Sum obtained from step 2 is the equivalent decimal number.

(iv) Binary to Hexadecimal Conversion

To convert a binary number to a hexadecimal number, starting from the binary point,
make groups of 4 bits each, on either side of the binary point and replace each 4-bit group by
the equivalent hexadecimal digit.

(v) Hexadecimal to Decimal Conversion

Hexadecimal numbers may be converted to their decimal equivalents by the positional weights
method.
Step 1: Mark the positional weights for each bit (powers of 16).
Step 2: Multiply the positional weights with the bits and add the products together.
Step 3: Sum obtained from step 2 is the equivalent decimal number.

(vi) Hexadecimal to Binary Conversion

To convert a hexadecimal number to binary, replace each hex digit by its 4-bit binary group.

1.3 Binary Arithmetic

Binary Addition

The rules for binary addition are the following:

0 + 0 = 0; 0 + 1 = 1; 1 + 0 = 1; 1 + 1 = 10 ie 0 with a carry of 1

Binary Subtraction

The binary subtraction is performed in a manner similar to that in decimal subtraction. The
rules for binary subtraction are:
0 – 0 = 0; 1 – 1 = 0; 1 – 0 = 1; 0 – 1 = 1, with a borrow of 1
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Binary Multiplication

There are two methods of binary multiplication the paper method and the computer
method. Both the methods obey the following multiplication rules:
0 x 0 = 0; l x l = 1; l x 0 = 0; 0x1=0
The paper method is similar to the multiplication of decimal numbers on paper.
Multiply the multiplicand with each bit of the multiplier, and add the partial products. The
partial product is the same as the multiplicand if the multiplier bit is a 1 and is zero if the
multiplier bit is a 0.

Binary Division

Like multiplication, division too can be performed by two methods—the paper

method and the computer method. In the paper method, long-division procedures similar to
those in decimal are used.

1’s Complement of a Number

The 1‘s complement of a number is obtained by simply complementing each bit of

the number, that is, by changing all the 0s to 1s and all the 1s to 0s. We can also say that the
1‘s complement of a number is obtained by subtracting each bit of the number from 1. This
complemented value represents the negative of the original number. This system is very easy
to implement in hardware by simply feeding all bits through inverters. One of the difficulties
of using 1‘s complement is its representation of zero. Both 00000000 and its 1‘s complement
11111111 represent zero. The 00000000 is called positive zero and the 11111111 is called
negative zero.
2’s Complement of a Number
Methods of obtaining the 2's complement of a number
1. By obtaining the 1’s complement of the given number and then adding 1
2. Subtracting the given n-bit number N from 2n.
3. Starting at the LSB, copying down each bit up to and including the first 1 bit
encountered, and complementing the remaining bits.
Characteristics of the 2’s complement numbers
1. There is one unique zero.
2. The 2’s complement of 0 is 0.
3. The leftmost bit is a sign bit. If it is a 1, the number is negative and if it is a 0, the
number is positive.
4. Significant information is contained in the 1s of the positive numbers and 0s of the
negative numbers.
Binary Subtraction using 1’s & 2’s Complements

The 1’s complement subtraction is

Step 1: Determine the 1’s complement of the subtrahend
Step 2: Add this to the minuend
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Step 3: If there is a carry out, bring the carry around and add it to the LSB
Step 4: Look at the sign bit (MSB), if it is 0 result is positive and is in true binary. If
the MSB is a 1 the result is negative and is in its 1’s complement form. Take
its 1’s complement to get the magnitude in binary.
The 2’s complement subtraction is
Step 1: Determine the 2’s complement of the subtrahend
Step 2: Add this to the minuend
Step 3: If there is a carry out, ignore it
Step 4: Look at the sign bit (MSB), if it is 0 result is positive and is in true binary. If
the MSB is a 1 the result is negative and is in its 2’s complement form. Take
its 2’s complement to get the magnitude in binary.

1.4 Binary Coded Decimal (BCD) Codes

The main motivation for binary number system is that there are only two elements in
the binary set, namely 0 and 1. While it is advantageous to perform all computations on
hardware in binary forms, human beings still prefer to work with decimal numbers.
There are ten different symbols in the decimal number system: 0, 1, 2, . . ., 9. As there
are ten symbols we require at least four bits to represent them in the binary form. Such a
representation of decimal numbers is called binary coding of decimal numbers.
In a weighted code the decimal value of a code is the algebraic sum of the weights of
1s appearing in the number. Let (A)10 be a decimal number encoded in the binary form as a3
a2 a1 a0.
Then (A)10 = w3a3 + w2a2 + w1a1 +w0a0
where w3, w2, w1 and w0 are the weights selected for a given code, and a3, a2, a1 and
a0 are either 0s or 1s.
The more popularly used codes have the weights as
w3 w2 w1 w0
8 4 2 1
The decimal numbers in these codes are given below and it is called as natural binary coded
decimal codes (NBCD).

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1.5 Logic Gates

1.6 Logic Families

Since the introduction of integrated circuits (ICs) in 1960s, many logic families were
introduced into the market. The major requirements and the desirable features of a logic
family are:

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 Logic flexibility
 Availability of complex functions
 High noise immunity
 Wide operating temperature range
 Loading
 Speed
 Low power dissipation
 Lack of generated noise
 Input and output structures
 Packaging
 Low cost
ICs are fabricated using various technologies such as TTL, ECL, and IIL which use bipolar
transistors, whereas the MOS and CMOS technologies use unipolar MOSFETs.

Characteristics of Digital ICs

1. Propagation Delay

A pulse through a gate takes a certain amount of time to propagate from input to
output. This interval of time is known as the propagation delay of the gate. It is the average
transition delay time tpd, expressed by

where tPLH is the signal delay time when the output goes from a logic 0 to a logic 1 state and
tPHL is the signal delay time when the output goes from a logic 1 to a logic 0 state.

2. Power Dissipation
Every logic gate draws some current from the supply for its operation. The current
drawn in HIGH state is different from that drawn in LOW state. The power dissipation PD, of
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logic gate is the power required by the gate to operate with 50% duty cycle at a specified
frequency and is expressed in milliwatts. This means that 1 and 0 periods of the output are
equal. The power dissipation of a gate is given by

where VCC is the gate supply voltage, ICC(avg) is the average current drawn from the supply
by the entire IC and n is the number of gates in the IC.

3. Fan – in
The fan – in of a logic gate is defined as the number of inputs that the gate is designed
to handle
4. Fan - out

The fan-out (also called the loading factor) of a logic gate is defined as the maximum
number of standard loads that the output of the gate can drive without impairing its normal
operation. A standard load is usually specified as the amount of current needed by an input of
another gate of the same IC family. If a gate is made to drive more than this number of gate
inputs, the performance of the gate is not guaranteed. The gate may malfunction.
Fan-out may be HIGH state fan-out, i.e. the fan-out of the gate when its output is a
logic l, or it may be LOW state fan-output, i.e. the fan-out of the gate when its output is a logic
0. The smaller of these two numbers is taken as the actual fan-out. The fan-out of a gate affects
the propagation delay time as well as saturation. The driving gate sinks current when it is in
LOW state and sources current when it is in HIGH state.

where IOH(max) is the maximum current that the driver gate can source when it is in a 1 state
and IIH is the current drawn by each driven gate from the driver gate.

where IOL(max) is the maximum current that the driver gate can sink when its output is a logic
0 and IIL is the current drawn from each driven gate by the driver gate.

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5. Speed Power Product

A common means for measuring and comparing the overall performance of an IC

family is the speed power product, which is obtained by multiplying the gate propagation delay
by the gate power dissipation. A low value of speed power product is desirable. The smaller
the product, the better the overall performance. The speed power product has the units of energy
and is expressed in picojoules. It is the figure of merit of an IC family. Suppose an IC family
has an average propagation delay of 10 ns and an average power dissipation of 5 mW, the speed
power product is
10 ns x 5 mW = 50 x 10-12 watt-seconds = 50 picojoules (pJ)

Advantages & Disadvantages of Various Logic Families

1. Transistor Transistor Logic (TTL)

a. Advantages
 It is the fastest logic family. TTL gates are available in form of high
speed, high speed schottky, low power schottky and a variety type
 It has good noise immunity. Typical noise margin is about 0.4 V.
 Power dissipation is in the megawatt range.
 Compatible with other logic families
 Commercial and military versions of TTL gates are available.
 More fan out; can drive upto 10 gates
 Low output impedance for higher/low states
b. Disadvantages
 Noise immunity is not very high.
 Power dissipation is much higher than MOS gates.
 Cost is higher.
 It generates transient voltages at switching instants.
2. Emitter – Coupled Logic (ECL)
a. Advantages
 Since transistor operates in the active region, highest speed among all
logic families.
 Complementary outputs are available
 Parameters do not vary much with temperature.
 Typical supply voltage is -5.2V
b. Disadvantages
 Very low noise margin.
 Highest power dissipation among all logic gates
 Capacity loading limits fan out
 Higher cost
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3. Complementary Metal Oxide Semiconductor Logic (CMOS)

a. Advantages
 Extremely large fan out capability (>50)
 Lowest power dissipation of all gates
 Very high noise immunity and noise margin
 Lower propagation delay than NMOS
 Single power supply required
 Temperature stability is excellent
b. Disadvantages
 Increased cost due to additional processing steps
 Packing density is less than the NMOS
 MOS chips must be protected

Comparison of Various Logic Families

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