VINAYAKA MISSIONS UNIVERSITY, SALEM

VMKV ENGINEERING COLLEGE, SALEM

&
AARUPADAI VEEDU INSTITUTE OF TECHNOLOGY, CHENNAI
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
QUESTION BANK

DEGREE / BRANCH : B.E. - MECHATRONICS

SUBJECT : DIGITAL ELECTRONICS
YEAR & SEMESTER : II / IV
REGULATION : CBCS R 2015

UNIT –I NUMBER SYSTEM

PART-A
1. What is the minimum number of bits required to encode the decimal digits 0 through
9? Justify your answer.
2. Find the decimal equivalent of the binary number (1101101)2
3. What is meant by natural BCD code?
4. Represent the hexadecimal number (B65F)16 in powers of 16 & find its decimal
equivalent.
5. Find the 2’s complement of the binary number (1011001)2.
6. Convert the decimal number 345 to binary number.
7. Find the octal equivalent of the decimal number (0.6875)10.
8. Why binary number system is used in digital systems?
9. Specify the radix and the symbols used in ternary, quinary and hexadecimal number
systems.
10. Find the hexadecimal equivalent of the binary number (10001101011.11110)2
11. What are the methods used to represent negative numbers in digital systems?
12. Which codes are called as self complementing code?
13. Convert the hexadecimal number (A72E)16 into octal number.
14. Define sign-magnitude representation of numbers.
15. Which is the most commonly used code for representing alphanumeric information?
16. What is meant by register?
17. List out the basic rules for binary addition.
18. Why is a hexadecimal number system called as an alphanumeric number system?
19. What is meant by a non-weighted code? Give examples of non-weighted codes.
20. Mention the types and uses of complements in a number system.
 PART-B

1. Convert the following numbers with the indicated bases to decimal number
i) (4310)5 and (198)12
ii) (10110.0101)2 ,(16.5)16 and (26.24)8
2. a) Convert the hexadecimal number 68BE to binary and then from binary convert it to
octal.
b) Convert the following binary numbers to hexadecimal (1.11010), (1110.10),
(010100101011.0101101)
c) Add the binary numbers: i) 1011 and 1100 ii) 0101 and 1111

3. Do the following conversion problems:

a) Convert the decimal number 904.215 to binary, octal and hexadecimal number
system

b) Convert the octal number 621.547 to binary, decimal and hexadecimal number
system.

4. Convert the following numbers with the indicated bases:

a) (10110001101.1111001)2 = ( ? )8 , (173.124)8 = ( ? )2 and (CAD)16 = ( ? )8

b) (10110001101011.1111001)2 = ( ? )16 and (306.D)16 = ( ? )2

5. a) Find the 9’s and the 10’s complement of the following decimal number: i) 98127634

ii) 72049900

b) Obtain the 1’s and 2’s complement of the following binary numbers :i) (11101010)

ii)(01101110) iii)(001000)

c) Encode the following decimal numbers in 8-4-2-1 code: i) 27 ii) 396 iii) 9.25 iv) 4096

6. Explain the different types of binary codes in detail with an example.

7. Describe binary logic with an example.

8. a) With a suitable example explain the signed binary numbers in detail.

b) i)Multiply the binary numbers 1001 by 1101 ii) Subtract the binary number 1011 and

0110

9. Explain the binary storage and register in detail.

10. a).Convert the following binary numbers into gray code: i) 011010111101,

ii) 111010101110 iii) 0110100010101

b).Write the following numbers in excess-3 code: i) 28, ii) 396 iii) 403
 UNIT –II: BOOLEAN ALGEBRA, LOGIC GATES & GATE LEVEL-
MINIMIZATION

PART-A
1. State De Morgan's theorem.
2. Define Logic gate.
3. What are called don’t care conditions?
4. Which gates are called as the universal gates? What are its advantages?
5. List the basic properties of Boolean algebra?
6. State the associative property of Boolean algebra.
7. Reduce A(A + B)
8. Simplify the following expression Y = (A + B)(A + C' )(B' + C' )
9. Convert the given expression in canonical SOP form Y = AC + AB + BC
10. What are the methods adopted to reduce Boolean function?
11. Find the minterms of the logical expression Y = A'B'C' + A'B'C + A'BC + ABC'
12. Write the maxterms corresponding to the logical expression Y = (A + B + C' )
(A + B' + C') (A' + B' + C)
13. State the limitations of karnaugh map.
14. Define Minterms & Maxterms .Give examples.
15. Implement AND gate by using only NOR gates.
16. State the principle of duality property.
17. What is meant by POS? Give examples.
18. Implement OR gate by using only NAND gates.
19. Define integrated circuit.
20. What is meant by HDL?
PART-B
1. Reduce the following function using K map technique and draw the equivalent diagram
for the output function by using logic gates.

i) F(A,B,C,D)= п M (0,3,4,7,8,10,12,14) . d (2, 6)

ii) F(x,y,z)= ∑ (0,2,3,4,6)

2. Simplify the given function by using K- map technique and draw the equivalent diagram
for the output function by using logic gates.

i) F(A,B,C,D) = ∑ m(0,1,2,4,5,6,8,9,12,13,14)

ii) F (A,B,C,D) = BC' D+ A'BCD + B'CD' + A'B'C'D' + AC'D

3. Simplify the following functions using K- map technique and draw the equivalent diagram
for the output function by using logic gates.

i)F(A,B,C,D) = ∑ m (7,8,9) + d ( 10,11,12,13,14,15)

ii)F(A,B,C,D) = п M(1,3,7,11,15) . d(0,2,5)

4. a) Implement the following Boolean function using NOR gates.

F = (AB’+A’B)(C+D)

b) Simplify the following Boolean function in SOP and POS and implement the output
expression by using logic gates:

F(A,B,C,D)= ∑ (0,1,2,5,8,9,10)

5.a) Implement the following Boolean function with NAND gates.

i) F(X, Y, Z) = ∑ m (1, 2, 3, 4, 5, 7)

ii) F = (AB+CD)

b) Express the Boolean function F=A+B’C in a sum of minterms.

6.a)Simplify the Boolean function F(W,X,Y,Z)= ∑ (5,6,9,10) Which has the don’t-care
conditions D(W,X,Y,Z)= ∑ (0,2,11)

b) Implement the exclusive-OR function by using digital logic gates.

7. Prove that NOR gate is an universal gate. Also, prove the same for NAND gate.

8. Explain the digital logic gates in detail.

9. a) Implement the expression F = (BC’ + AC) in a canonical SOP form and canonical POS
form.
b) Write short notes on integrated circuits.
10. Explain the Hardware description language in detail.
 UNIT –III: COMBINATIONAL LOGIC

PART-A

1. What is combinational circuit? Give some examples.

2. Give the expression for borrow and difference in full subtractor.
3. Draw the logical diagram of a half adder.
4. Give the truth table of a full adder.
5. Write the output expressions for half subtractor.
6. Give the logical expression for sum and carry of a half adder.
7. What is meant by binary multiplier?
8. Draw the logic Symbol and construct the truth table for the two input EX – OR gate.
9. What is code converter?
10. Define Encoder.
11. List the applications of multiplexers.
12. Define multiplexer.
13. Mention the difference between a DEMUX and a MUX.
14. What do you meant by comparator?
15. Compare a decoder with a demultiplexer.
16. List the various modelling techniques used in HDL for combinational circuit design.
17. What is meant by priority encoder?
18. Write the data flow description of a 2-to-4-line decoder by using HDL.
19. Define three state gates.
20. Specify the application of combinational circuit.
PART-B

1. a) Design a combinational circuit with three inputs and one output. The output is 1
when the binary value of the input is less than 3. The output is 0 otherwise.
b) Give the design procedure of combinational circuit.
2. Design a code converter circuit, which converts BCD to Excess-3 code.
3. Illustrate the design and functioning of a half adder and full adder combinational
circuit.
4. Design a half and full subtractor circuit with inputs x and y and outputs D and B.
Implement the output expression by using digital logic gates.
5. Describe the Magnitude Comparator in detail.
6. Design a 2-to-4-line and 3-to-8 line Decoder circuits.
7. a)Implement the following functions with an 4:1 multiplexer
F (A, B, C) =∑m (0, 2, 4, 5, 7)
b) Implement the following functions with an 8:1 multiplexer
F(A,B,C,D)=Π m(1,5,8,11,12,15)
c ) Implement the following functions with an 8:1 multiplexer
F(A,B,C,D)=∑m(1,3,5,7,10,11,13,14)+d (0,2)
8. a) With a suitable design, explain the octal to binary encoder circuit.
b) Write a note on BCD adder.
9. Design and explain the working of 4:1 and 8:1Multiplexer with a neat diagram.
10. Explain the gate level modelling technique of HDL in combinational circuits.

UNIT-IV: SYNCHRONOUS SEQUENTIAL LOGIC, REGISTER AND COUNTERS

PART-A

1. What do you meant by sequential logic circuits?

2. List the Types of Flip flop.
3. State the difference between latches and flip-flop.
4. Give the truth table of SR flip flop.
5. List the Application of flip-flop.
6. What is a counter?
7. Define synchronous counter.
8. State the various applications of shift register.
9. Define register.
10. What are the different types of shift register?
11. What is meant by state reduction?
12. Define race around condition.
13. Name the methods of triggering a flip-flop.
14. What is meant by positive edge triggering?
15. Write the characteristic table of JK flip-flop.
16. Define state equation.
17. Mention the 2 kinds of behavioral statements in VHDL for sequential circuit.
18. What is BCD counter?
19. Mention the level of describing register and counter in HDL.
20. Write the characteristic equation of D-flip-flop.
 PART-B
1. With logic circuit & truth table explain the operation of JK flip flop.A
2. Explain in detail about T & D flip flops.
3. Discuss about the State minimization and state assignment in detail.
4. Using JK flip flops, design a synchronous counter which counts in the
sequence,000,001,010,011,100,101,110,111,000
5. Draw and explain the operation of a 4-bit SISO, SIPO, PIPO and PISO shift register.
6. Design and explain the working of a 4-bit ripple counter with a neat diagram.
7. a) With a suitable diagram, explain the operation of SR flip-flop in detail.
b) Write the procedure for designing synchronous sequential circuit.
8. Design a 3 bit binary UP/DOWN counter with a direction control M. Use JK Flip-
Flops.
9. Write the HDL behavioral and structural description of universal shift register in
detail.
10. Discuss in detail about the clocked sequential circuit design and analyze with suitable
example.
UNIT-V: DESIGN AT THE REGISTER TRANSFER LEVEL

PART-A
1. What is meant by RTL?
2. Specify the three components of RTL.
3. Write the VHDL logical operator symbol.
4. Define logic synthesis.
5. What is ASM chart?
6. Specify the basic elements of ASM chart
7. Define control logic.
8. What is meant by behavioural description of multiplier?
9. Explain in words the operation specified by the register transfer notation :R1 R2
10. Define binary multiplier
11. Draw the control state diagram for the binary multiplier.
12. Differentiate continuous and procedural assignment.
13. Mention the type of operations most often encountered in digital system.
14. Write the VHDL operator symbol for shift operations.
15. Define ASM block.
16. Mention the function of algorithmic based behavioural description in HDL.
17. Draw the decision box of ASM chart.
 18. Write the HDL behavioural description of multiplier.
19. Define race condition.
20. What is meant by latch free design?

PART-B

1. Explain register transfer level notation in detail.

2. Describe in detail about register transfer level in HDL.
3. Explain the process of HDL simulation and synthesis.
4. Illustrate ASM with suitable example.
5. Explain the block diagram of a binary multiplier in detail.
6. Explain the HDL description of binary multiplier.
7. With suitable example explain the HDL design with multiplexer.
8. Illustrate race free design.
9. Describe the latch free design in detail.
10. Discuss in detail about the control logic design in sequential circuit.