International Journal of Future Computer and Communication, Vol. 2, No.

6, December 2013

ALL Digital Phase-Locked Loop (ADPLL): A Survey

Kusum Lata and Manoj Kumar

(ADPLL) having a fault detection of the input reference

Abstract—ADPLL is contributing great role in advancement signal was modeled in Verilog hardware descriptive
in control system and digital communication since 1980. Design language (HDL) [7].
of ADPLL with integrated circuit (IC) techniques has made
ADPLL very important component. ADPLL is still continuing
to give better results. Now a days ADPLL has great
contribution in digital communication systems. This paper gives II. ADPLL DESIGN
basic details of an ADPLL. It provides brief summary of the
basic ADPLL principle applicable to control systems and digital A. Block Diagram
communication. It also reports components of ADPLL and It contains digital blocks. It uses negative feedback control
comparison among them. loop. It takes digital signal only. The signal could be single or
combination of parallel digital signals. It consists three
Index Terms—DCO, ADPLL, loop filter, phase detector.
blocks: 1.Phase Detector (PD) 2.Loop Filter (LF) and
3.Digitaly Controlled Oscillator (DCO). Fig. 1 gives basic
structure of an ADPLL.
I. INTRODUCTION
The aim of the ADPLL is to interlace the phase input v1
The PLL is a self-correcting control system in which one and output v2’ and also the frequency. To reduce the
signal chases another signal.PLL has four types 1.linear PLL difference among two signals PD is used. For removing noise
2.digital phase locked loop 3.all digital phase locked loop LF is used.
4.software PLL (SPLL).ADPLL takes input as only digital Finally, the digitally-controlled oscillator (DCO) gets the
signals. Due to digital signal as input signal so many signals from LF and makes closer to the input signal. To
advantage of the ADPLL exists. In this paper different realize an ADPLL, existing elements must be digital circuits.
applications of ADPLL is discussed [1]-[7]. There are some advantages: No off-chip components and
Insensitive to technology.
B. Phase Detector
It is also called phase comparator. It compares between
input and DCO output signal. Output depends upon the phase
error. Output signal contains low frequency and higher
frequency component. Some of the existing phase detectors
are explained below.
Fig. 1. General block diagram of ADPLL 1) EXOR gate phase detector
Beginning of all digital phase-locked loops (ADPLL) It uses an EXOR logic gate. It compares the reference
started in 1980 [8]. In the 21'st century, researchers has and DCO signal.
developed a new digitally controlled oscillator (DCO) to
obtain good phase and frequency error that was not
implemented with 74hc297 IC [1], [8]. In 2005's, a frequency
modulated receiving system based on ADPLL was proposed
[2] .In 2006's double edge triggered D flip-flop as phase
detector was proposed [3] This design reduced 33% of power Fig. 2. XOR gate phase detector
dissipation. In 2008's digital fm demodulator was proposed
Disadvantages of this are it has phase limitation [-90, +90]
[4] It was designed by VHDL. In 2009's frequency
degrees and it does not sense edges signal edges. Fig. 3
modulated modem was implemented on field programmable
shows the “locked” state [8], [11], [13].
array (FPGA) [5] In 2010’s a field programmable array based
linear ADPLL was proposed. This ADDPLL used FPGA for
implementation [6] .Recently an all-digital phase-locked loop

Manuscript received December 13, 2012; revised February 23, 2013. This
work is towards the Master’s thesis of the student Mr. Manoj Kumar at
Indian Institute of Information Technology, Allahabad (IIIT- Allahabad).
This work is completed in the Division of Electronics and Communication Fig. 3. Waveforms of XOR gate phase detector
Engineering, IIIT- Allahabad.
The authors are with the Indian Institute of Information Technology, 2) Edge triggered JK flip-flop phase detector
Allahabad, India (e-mail: kusum@iiita.ac.in, manojnitc@gmail.com).
It contains a JK FF. A phase limitation of this is -180

DOI: 10.7763/IJFCC.2013.V2.225 551

 International Journal of Future Computer and Communication, Vol. 2, No. 6, December 2013

degrees to +180 degrees. Waveform is shown below [8]-[13]. CLK is in, trigger always accepts input signal. Trigger can be
3) Flip-flop counter phase detector changed in both edges of CLK [3].
The phase detector contains a counter and a FF, is shown
in Fig. 6. Flip-flop Counter phase detector compares
reference and the DCO output signal. In this case FF input S
takes input signal and R takes DCO output signal. Output of
FF is high when there is error among S and R inputs. Q
enables the counter. FF input S resets counter. Output of
counter depends upon the phase error. Clock frequency of
counter is very high it is M times multiple of input signal is
large positive integer [8], [11].Waveform of this is shown
below. Fig. 7. Phase frequency detector (PFD) is very important for an ADPLL

Fig. 4. JK flip-flop phase detector

Fig. 8. The Strucure of DETDFF

C. Loop Filter
Fig. 5. Waveforms of JK flip-flop phase detector
It is nothing but an integrator. Examples of loop filters are
discussed below.
1) UP/down counter loop filter
It is simplest loop filter. It is always operate in conjunction
with EXOR or JK FF phase detector. For getting clock and
direction signal a pulse forming circuit is used. Counter is
incremented on each UP pulses and it is decremented on each
(a)
down signals .So counter adds both pulses .So its work like
an integrator [8], [11].

(b) (a)
Fig. 6. Flip-flop counters phase detector (a) and corresponding
waveforms (b).
4) Phase frequency detector
Phase Frequency Detector (PFD) is very important for an
ADPLL .It checks both the signal are in phase .It also checks
frequency. A different type of D FF is used .D input is always
high. Nor gate takes input as D FF outputs. It resets the FF.
For increasing DCO clock signal up signal should high and
for decreasing DCO clock signal down signal should high
[9].(Fig. 7)
5) Double edge triggered D flip-flops (DETDFF)
DETDFF is based on data selectors is shown Fig.8. For
this two FF are used. These two flip-flops are controlled by (b)
same CLK. When CLK has logic high, data selectors MUX Fig. 9. Up/down counter loop filter. (a) Block diagram
output port is put through with flip-latch 2.And when CLK (b) Corresponding waveforms.
has logic low, data selectors MUX output port will is put 2) K counter loop filter
through with flip-latch1. Hence, whatever states the signals K counter loop filter is very important loop filter .It always

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 International Journal of Future Computer and Communication, Vol. 2, No. 6, December 2013

works with JK or EXOR phase detector. It has two Carry is assigned to DECR input and Borrow is assigned to
counters .Both are independent .One is called Up and other is INCR input. ID counter with ÷ N counter for again dividing
Down counter .But both counts in upward direction. Counter the OUT. Clock of increment-decrement counter is 2N times
has modulus k. multiple of center frequency. Fig. 12 gives overall structure
So counter contents has range from 0 to k-1.Couter clock [8], [11], [13].
frequency is M times multiple of center frequency. M has
typical values of 8, 16, 32….Down counter is enabled when
DN/UP has logic high and up counter is enabled when this
logic low value. When contents exceed k-1 both counters
resets. “Carry” is MSB of the Up counter .The “borrow”
signal is MSB of the Down counter. When Up-counter stored
data ≥ k/2 “carry” is high .When down counter stored data≥
k/2 “borrow” is high. Frequency of DCO is controlled by
positive edges of the signal [8], [11], [13].
Fig. 12. Increment-decrement counters

If no Carries and Borrows are present then ID counter

divides OUT by 2 on the positive edges of ID clock. The
logical function for ID counter is given by

(a) ID out = (NOT (1D clock) AND (NOT (togg1e-FF))

If carry is present then half cycle is added and if borrow is

present then half cycle is removed from OUT. Here out is
output of increment-decrement counter. The adjusted
waveform is shown below.

Fig. 13. Waveforms of increment-decrement counter

(b) III. COMPARISION OF BASIC BUILDING BLOCK OF ADPLL

Fig. 10. K Counter Loop Filter. (a)Block Diagram.
(b) Corresponding waveforms. Tabular from is used for comparing the basic building
block of ADPLL. Different implementations of the each
D. Digitally Controlled Oscillators
block of ADPLL is given in the last.
Digitally Controlled oscillators are nothing but a
modified oscillator .Depending upon output of the loop filter A. Phase detector
they change their frequency. Some of DCO are explained Advantage and disadvantage of various phase detectors
below. are given in Table I. Depending upon advantage and
1) Divide by N counter DCO disadvantage of various phase detectors we are selecting our
A simple ÷N counter works as DCO. High frequency loop filters.
signal operates at very high frequency. Divide by N counter
produces N bit parallel output [8], [11]. Drawback of it is we B. Loop Filter
can’t design jitter. Advantage and disavantage of various loop filters are
discussed in the Table II. Depending upon advantage and
disadvantage of loop filters we are selecting our digitaly
control oscliators(DCO).
C. Digital Controled Oscliator
Advantage and disadvantage of various digitaly controled
Fig. 11. ÷N Counter DCO oscliators are discussed in Table III. Depending upon the
2) Increment-decrement counter proper choice of digitaly controled oscliators(DCO) we can
Increment-Decrement Counter consists of two blocks. avoid ripple problem which is most critcal parametrs while
designing the ADPLL .

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TABLE I: TYPES OF PHASE DETECTOR AND ITS ADVANTAGES & DISADVANTAGES

Serial Phase Detector
No.
Types Advantage Disadvantage

1 EXOR It produces error pulse on both the edges. Pull in It is not sensitive to edges.So data might be lost.Phase
process slow[8]. error lies between -90 to +90 degrees. Smaller phase
tracking range[8].

2 JK Flip-Flop It is sensitive to edges.So no chance of data losses[8]. Phase error lies between -180 to +180 degrees.Larger
phase tracking range[8].
3 Flip-Flop Counter N bit output are possible[11]. Circuit is not simple.It requires three frequency
inputs[11].
4 Phase Frequency Larger phase tracking range.Phase error lies between
Detector -360 to 360 degrees. It locks under any condition[8]. Circuit has not simple structure [11].
5 DETDFF Power disspiation is less and it provides high speed at Circuit has not simple structure [3].
which it achives a phase-locked state[3] .

TABLE II: TYPES OF LOOP FILTER AND ITS ADVANTAGES & DISADVANTAGES
Serial Loop Filter
No.
Types Advantage Disadvantage
1. Up/Down Counter It is easily adapted to operate in conjunction with an It is not perfectly works as a integrator[8].
XOR or JK-Flip flop phase detectors and others [11].
2. K Counter It perfectly works as a integrator[8]. It is not operate with others detectors except XOR or
JK-Flip flop[8].

TABLE III: TYPES OF DIGITAL CONTROLLED OSCLLIATOR AND ITS ADVANTAGES & DISADVANTAGES
Serial Digital Controlled Oscillator
No. Types(DCO) Advanatage Disadvantage
1 Divide By N counter It has simple structure [11]. It does not offer jitter design criterion [11].
2 Increment-Decrement Good control over Hold range and lock in range [8]. It is not suitable for software implementations[8].
Counter

possible.
IV. APPLICATIONS OF ADPLL REFERENCES
The use of ADPLL with IC (74HC/HCT297) is developed [1] A. H. Khalil, K. T. Ibrahim, and A. E. Salama, “Digital of ADPLL for
good phase and frequency tracking performance,” in Proc. of the
for digital communications [8], for example, FSK decoder. Nineteenth National Radio Science Conference (NRSC 2002),
For wideband frequency tracking and noise reduction Alexandria, pp. 284 – 290, March 2002.
ADPLL can be used [12]. PLL heating control system is [2] N. Rahmatullah, “Design of All Digital FM Receiver Circuit,” Project
replaced by ADPLL in 2009 [13]. The developed ADPLL report in Institute Technology Bandung, Indonesia, March, 2005.
[3] C. H. Shan, Z. Chen, and Y. Wang, “An All Digital Phase-Locked
provides simple structure. FM demodulaton an ADPLL Loop Based on Double Edge Triggered Flip-flop,” in Proc. of 8th IEEE
circuit was proposed [14]. For mobile phones applications International Conference on Solid-State and Integrated Circuit
ADPLL is developed [15]. ADPLL is used in high-speed Technology, (ICSICT '06), China, pp. 1990-1992, 2006.
[4] M. J. P. Brito and S. Bampi, "Design of a digital FM demodulator based
clock generation [16], [17]. There are many ADPLL on a 2nd-order all digital phase locked loop,” Journal of Analog
developed for frequency synthesizers [17]-[19]. In real Integrated Circuit and Signal Processing, Springer, Netherland, May
communication systems like wireless ADPLL is helpful [20]. 28 2008, Numbers 1-2/November 2008.
[5] I. Hatai and I. Chakrabarti, “FPGA implementation of Digital FM
ADPLL is used in Clock recovery circuit and in frequency Modem,” IEEE International Conference on Information and
synthesizers [21]-[26]. Multimedia Technology, ICIMT’09, India, pp. 475 – 479, 2009.
[6] M. Kumn and H. Klingbeil, “An FPGA-Based Linear All- Digital
Phase-Locked Loop,” IEEE Trans. on circuit and systems, vol. 57, no.
9, September 2010.
V. CONCLUSIONS [7] T. Y. Yau and T. Caohuu, “An Efficient All-Digital Phase-Locked
General block diagram of an ADPLL has been Loop with Input Fault Detection,” in Proc. of IEEE conference,
Information Science and Applications (ICISA), 2011.
discussed.Different types implementations of all the blocks [8] R. E. Best, Phase Locked Loops Design Simulation and Applications,
of ADPLL have been presented. Comparision among all the McGraw-Hill Professional, ch. 6, pp. 205-246, 5th Edition, 2003.
blocks have been reported in detail.Typical applications of [9] A. Babu and B. Daya, “All Digital Phase Locked Loop Design and
Implementation,” Project report, University of Florida, Gainesville, FL,
the ADPLL is reported. ADPLL block implementations have 32608, USA.
been presented. [10] A. Chandra, “Phase Locked Loop,” presentation in ECE Department,
NIT Durgapur, Winter School on VLSI Systems Design, WB, Jan 24,
2009.
ACKNOWLEDGMENT [11] S. Vallabhaneni, S. Attri, N. Krishman, S. Sharma, and R. C. Chauhan.
I would like to take this opportunity to express my Design of an all-Digital PLL core on FPGA. [Online]. Available:
http://klabs.org/mapld04/abstracts/sharma_a.doc
gratitude to the people whose assistance has been invaluable [12] S. C. Hong, “An all digital phase-locked loop system with high
in this paper. I would like to thank the Director of Indian performance on wideband frequency tracking,” IEEE Trans. on Circuit
Institute of Information Technology, Allahabad for providing and Systems, vol. 52, no. 10, 2009.
financial and infrastructure support for making this work

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[13] Q. Zhang, “Research and application of all digital phase locked loop,” [22] Y. R. Shayan and T. L. Ngoc, “All Digital phase-locked loop: concepts,
in Proc. of the Second International Conference on Intelligent design and applications,” Radar and Signal Processing, vol. 136, no. 1,
Networks and Intelligent Systems, USA, pp. 122 – 125, 2009. pp. 53 – 56, Feb. 1989.
[14] J. Pablo, M. Brito, and S. Bampi, “Design of a digital FM Demodulator [23] D. Sheng, C. C. Chung, and C. Y. Lee, “An All-Digital Phase- Locked
based on a 2nd order All-digital Phase Locked Loop,” in Proc. of the Loop with High-Resolution for SOC Applications,” in Proc. of
20th Annual Conference on Integrated Circuits and Systems Design International Symposium on VLSI Design, Automation and Test, 2006,
(SBCCI’07), New York, pp. 137 – 141, 2007. Hsinchu, pp. 1-4, April 2006.
[15] Staszewski, et al., “All-digital PLL and transmitter for mobile phones,” [24] A. Neyer, J. H. Mueller, S. Kaehlert, R. Wunderlich, and S. Heinen, “A
Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2469-2482, Dec. fully integrated all-digital PLL based FM-radio Transmitter in 90 nm
2005. CMOS,” in Proc. of 8th IEEE International NEWCAS Conference
[16] C. C. Chung and C. Y. Lee, “An all-digital phase-locked loop for (NEWCAS), Germany, pp. 225 - 228, June 2010.
high-speed clock generation,” IEEE Journal of Solid-State Circuits, [25] R. B. Staszewski et al., “All-Digital Phase-Domain TX Frequency
vol. 38, no. 2, pp. 347-351, Feb. 2003. Synthesizer for Bluetooth Radios in 0.13um CMOS,” ISSCC Digest
[17] Z. J. Cheng, D. Q. Jin, and T. Kwasniewski, "A 4GHz Low Complexity Technical Papers, pp. 272-273, Feb., 2004.
ADPLL-based Frequency Synthesizer in 90nm CMOS," in Proc. of [26] N. A. Mollen, “All-digital phase-locked loop used in a clock recovery
IEEE Custom Integrated Circuits Conference, CICC '07, Ottawa, pp. algorithm,” in Proc. IEEE Colloquium on Phase Lock Loops: Theory
543-546, 2007. and Practice, pp. 8 – 8, 1999.
[18] R. B. Staszewski, C. M. Hung, K. Maggie, J. Walberg, D. Leipold, and
P. T. Balsara, “All-digital phase-domain TX frequency synthesizer for Kusum Lata is working as a faculty member at Indian
Bluetooth radios in 0.13µm CMOS,” in Proc. of IEEE International Institute of Information Technology, Allahabad
Solid-State Circuits Conference, Digest of Technical Papers, Texas (IIIT-A), INDIA. Prior to IIIT Allahabad, she has
Instruments, Dallas, TX, USA, pp. 272 – 527, Feb. 2004. completed her PhD from Indian Institute of Science,
[19] G. N. Sung, S. C. Liao, J. M. Huang, Y. C. Lu, and C. C. Wang, “All
Bangalore, INDIA. Her research interests include
–Digital frequency synthesizer Using a Flying adder,” IEEE
Device modeling, digital circuit Design, Testing and
Transactions on Circuits and Systems, vol. 57, no. 8, pp. 597 – 601,
Verification of VLSI circuits. Dr. Lata has published
Aug. 2010.
[20] A. R. Qureshi, “Implementation of low power, wide range ADPLL for several research papers in reputed conferences
video applications,” Master Degree Thesis, Linkoping University, proceedings and journals. She is the member of IEEE and ACM
Department of Electrical Engineering, Electronics System. Professional society.
[21] T. Y. Hsu, B. J. Shieh, and C. Y. Lee, “An ADPLL-based Clock
Recovery Circuit,” IEEE Journal of Solid-State Circuits, vol. 34, no. 8, Manoj Kumar has completed his master’s Degree in microelectronics from
pp. 1063-1073, 1999. Indian Institute of Information Technology, Allahabad (IIIT-A), INDIA.

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