Core I7 Lga 2011 Datasheet Vol 1

Intel® Core™ i7 Processor Family for
the LGA-2011 Socket

Datasheet, Volume 1
Supporting Desktop Intel® Core™ i7-3960X and i7-3970X Extreme Edition

Processor for the LGA-2011 Socket
Supporting Desktop Intel® Core™ i7-39xxK and i7-38xx Processor Series
for the LGA-2011 Socket
This is volume 1 of 2.
February 2014
Reference Number: 326196-003

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2 Datasheet, Volume 1
Table of Contents
1 Introduction ..............................................................................................................8
1.1 Processor Feature Details .....................................................................................9
1.1.1 Supported Technologies ............................................................................9
1.2 Interfaces ........................................................................................................ 10
1.2.1 System Memory Support ......................................................................... 10
1.2.2 PCI Express* ......................................................................................... 10
1.2.3 Direct Media Interface Gen 2 (DMI2)......................................................... 12
1.2.4 Platform Environment Control Interface (PECI) ........................................... 12
1.3 Power Management Support ............................................................................... 12
1.3.1 Processor Package and Core States........................................................... 12
1.3.2 System States Support ........................................................................... 12
1.3.3 Memory Controller.................................................................................. 12
1.3.4 PCI Express* ......................................................................................... 12
1.4 Thermal Management Support ............................................................................ 13
1.5 Package Summary............................................................................................. 13
1.6 Terminology ..................................................................................................... 13
1.7 Related Documents............................................................................................ 15
2 Interfaces................................................................................................................ 16
2.1 System Memory Interface................................................................................... 16
2.1.1 System Memory Technology Support ........................................................ 16
2.1.2 System Memory Timing Support ............................................................... 16
2.2 PCI Express* Interface....................................................................................... 16
2.2.1 PCI Express* Architecture ....................................................................... 16
2.2.1.1 Transaction Layer ..................................................................... 17
2.2.1.2 Data Link Layer ........................................................................ 17
2.2.1.3 Physical Layer .......................................................................... 18
2.2.2 PCI Express* Configuration Mechanism ..................................................... 18
2.3 DMI2/PCI Express* Interface .............................................................................. 18
2.3.1 DMI2 Error Flow ..................................................................................... 18
2.3.2 DMI2 Link Down..................................................................................... 19
2.4 Platform Environment Control Interface (PECI) ...................................................... 19
3 Technologies ........................................................................................................... 20
3.1 Intel® Virtualization Technology (Intel® VT).......................................................... 20
3.1.1 Intel® Virtualization Technology (Intel® VT) for Intel® 64
and IA-32 Intel® Architecture (Intel® VT-x) Objectives ............................... 20
and IA-32 Intel® Architecture (Intel® VT-x) Features .................................. 21
3.1.3 Intel® Virtualization Technology (Intel® VT) for
Directed I/O (Intel® VT-d) Objectives ....................................................... 21
3.1.3.1 Intel® Virtualization Technology (Intel® VT) for
Directed I/O (Intel® VT-d) Features Supported ............................. 22
Directed I/O (Intel® VT-d) Processor Feature Additions .................. 22
3.1.4 Intel® Virtualization Technology Processor Extensions ................................. 22
3.2 Security Technologies ........................................................................................ 23
3.2.1 Intel® AES New Instructions (Intel® AES-NI) ............................................. 23
3.2.2 Execute Disable Bit ................................................................................. 23
3.3 Intel® Hyper-Threading Technology (Intel® HT Technology).................................... 23
3.4 Intel® Turbo Boost Technology............................................................................ 24
3.4.1 Intel® Turbo Boost Operating Frequency ................................................... 24
3.5 Enhanced Intel® SpeedStep® Technology ............................................................. 24
3.6 Intel® Advanced Vector Extensions (Intel® AVX) ................................................... 25
Datasheet, Volume 1 3
4 Power Management ................................................................................................ 26
4.1 Advanced Configuration and Power Interface (ACPI) States Supported ..................... 26
4.1.1 System States ....................................................................................... 26
4.1.2 Processor Package and Core States .......................................................... 26
4.1.3 Integrated Memory Controller States ........................................................ 28
4.1.4 DMI2 / PCI Express* Link States .............................................................. 28
4.1.5 G, S, and C State Combinations ............................................................... 29
4.2 Processor Core / Package Power Management ...................................................... 29
4.2.1 Enhanced Intel® SpeedStep® Technology ................................................. 29
4.2.2 Low-Power Idle States ............................................................................ 30
4.2.3 Requesting Low-Power Idle States ........................................................... 31
4.2.4 Core C-states ........................................................................................ 31
4.2.4.1 Core C0 State .......................................................................... 32
4.2.4.2 Core C1/C1E State ................................................................... 32
4.2.4.3 Core C3 State .......................................................................... 32
4.2.4.4 Core C6 State .......................................................................... 32
4.2.4.5 Core C7 State .......................................................................... 32
4.2.4.6 C-State Auto-Demotion ............................................................. 32
4.2.5 Package C-States................................................................................... 33
4.2.5.1 Package C0 ............................................................................. 34
4.2.5.2 Package C1/C1E....................................................................... 34
4.2.5.3 Package C2 State ..................................................................... 35
4.2.5.4 Package C3 State ..................................................................... 35
4.2.5.5 Package C6 State ..................................................................... 35
4.2.6 Package C-State Power Specifications ....................................................... 36
4.3 System Memory Power Management ................................................................... 36
4.3.1 CKE Power-Down ................................................................................... 36
4.3.2 Self Refresh .......................................................................................... 37
4.3.2.1 Self Refresh Entry .................................................................... 37
4.3.2.2 Self Refresh Exit....................................................................... 37
4.3.2.3 DLL and PLL Shutdown.............................................................. 37
4.3.3 DRAM I/O Power Management ................................................................. 38
4.4 DMI2 / PCI Express* Power Management ............................................................. 38
5 Thermal Management Specifications ....................................................................... 39
6 Signal Descriptions ................................................................................................. 40
6.1 System Memory Interface .................................................................................. 40
6.2 PCI Express* Based Interface Signals .................................................................. 41
6.3 DMI2 / PCI Express* Port 0 Signals ..................................................................... 43
6.4 Platform Environment Control Interface (PECI) Signal ............................................ 43
6.5 System Reference Clock Signals.......................................................................... 43
6.6 JTAG and TAP Signals........................................................................................ 44
6.7 Serial VID Interface (SVID) Signals ..................................................................... 44
6.8 Processor Asynchronous Sideband and Miscellaneous Signals.................................. 45
6.9 Processor Power and Ground Supplies ................................................................. 47
7 Electrical Specifications .......................................................................................... 48
7.1 Processor Signaling ........................................................................................... 48
7.1.1 System Memory Interface Signal Groups................................................... 48
7.1.2 PCI Express* Signals.............................................................................. 48
7.1.3 DMI2/PCI Express* Signals ..................................................................... 48
7.1.4 Platform Environmental Control Interface (PECI) ........................................ 48
7.1.4.1 Input Device Hysteresis............................................................. 49
7.1.5 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN) ........................ 49
7.1.5.1 PLL Power Supply ..................................................................... 49
7.1.6 JTAG and Test Access Port (TAP) Signals................................................... 50
7.1.7 Processor Sideband Signals ..................................................................... 50
7.1.8 Power, Ground and Sense Signals ............................................................ 50
7.1.8.1 Power and Ground Lands ........................................................... 50
7.1.8.2 Decoupling Guidelines ............................................................... 51
7.1.8.3 Voltage Identification (VID) ........................................................ 51
7.1.9 Reserved or Unused Signals..................................................................... 56
7.2 Signal Group Summary ...................................................................................... 56
7.3 Power-On Configuration (POC) Options................................................................. 59
7.4 Absolute Maximum and Minimum Ratings ............................................................. 60
7.4.1 Storage Conditions Specifications ............................................................. 60
7.5 DC Specifications .............................................................................................. 61
7.5.1 Voltage and Current Specifications............................................................ 61
7.5.2 Die Voltage Validation ............................................................................. 63
7.5.2.1 VCC Overshoot Specifications ...................................................... 63
7.5.3 Signal DC Specifications .......................................................................... 64
7.5.3.1 PCI Express* DC Specifications ................................................... 69
7.5.3.2 DMI2/PCI Express* DC Specifications .......................................... 69
7.5.3.3 Reset and Miscellaneous Signal DC Specifications .......................... 69
8 Processor Land Listing............................................................................................. 70
9 Package Mechanical Specifications ........................................................................ 117
Figures
1-1 Processor Platform Block Diagram Example.............................................................9
1-2 PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2) .................. 11
2-1 PCI Express* Layering Diagram........................................................................... 17
2-2 Packet Flow through the Layers ........................................................................... 17
4-1 Idle Power Management Breakdown of the Processor Cores..................................... 30
4-2 Thread and Core C-State Entry and Exit ............................................................... 30
4-3 Package C-State Entry and Exit ........................................................................... 34
7-1 Input Device Hysteresis...................................................................................... 49
7-2 VR Power-State Transitions................................................................................. 53
7-3 VCC Overshoot Example Waveform ...................................................................... 63
Tables
1-1 Terminology ..................................................................................................... 13
1-2 Reference Documents ........................................................................................ 15
4-1 System States .................................................................................................. 26
4-2 Package C-State Support.................................................................................... 27
4-3 Core C-State Support......................................................................................... 27
4-4 System Memory Power States ............................................................................. 28
4-5 DMI2/PCI Express* Link States ........................................................................... 28
4-6 G, S, and C State Combinations .......................................................................... 29
4-7 P_LVLx to MWAIT Conversion.............................................................................. 31
4-8 Coordination of Core Power States at the Package Level ......................................... 34
4-9 Package C-State Power Specifications .................................................................. 36
6-1 Memory Channel DDR0, DDR1, DDR2, DDR3......................................................... 40
6-2 Memory Channel Miscellaneous ........................................................................... 41
6-3 PCI Express* Port 1 Signals ................................................................................ 41
6-6 PCI Express* Miscellaneous Signals ..................................................................... 43
6-7 DMI2 to Port 0 Signals....................................................................................... 43
6-8 PECI Signals .................................................................................................... 43
6-9 System Reference Clock (BCLK{0/1}) Signals....................................................... 43
6-10 JTAG and TAP Signals........................................................................................ 44
6-11 SVID Signals .................................................................................................... 44
6-12 Processor Asynchronous Sideband Signals............................................................ 45
6-13 Miscellaneous Signals ........................................................................................ 46
6-14 Power and Ground Signals ................................................................................. 47
7-1 Power and Ground Lands ................................................................................... 51
7-2 SVID Address Usage ......................................................................................... 54
7-3 Voltage Identification Definition .......................................................................... 55
7-4 Signal Description Buffer Types .......................................................................... 56
7-5 Signal Groups................................................................................................... 57
7-6 Signals with On-Die Termination ......................................................................... 59
7-7 Power-On Configuration Option Lands.................................................................. 59
7-8 Processor Absolute Minimum and Maximum Ratings .............................................. 60
7-9 Voltage Specification ......................................................................................... 61
7-10 Current (Icc_Max and Icc_TDC) Specification........................................................ 62
7-11 VCC Overshoot Specifications ............................................................................. 63
7-12 DDR3 Signal DC Specifications............................................................................ 64
7-13 PECI DC Specifications ...................................................................................... 65
7-14 System Reference Clock (BCLK{0/1}) DC Specifications......................................... 66
7-15 SMBus DC Specifications.................................................................................... 66
7-16 JTAG and TAP Signals DC Specifications ............................................................... 67
7-17 Serial VID Interface (SVID) DC Specifications ....................................................... 67
7-18 Processor Asynchronous Sideband DC Specifications.............................................. 68
7-19 Miscellaneous Signals DC Specifications ............................................................... 69
8-1 Land Name ...................................................................................................... 71
8-2 Land Number ................................................................................................... 94
Revision History
Revision
Description Revision Date
Number
001 • Initial Release November 2011

• Updated to clarify references to PCI Express*
002 November 2012
• Added Intel® Core™ i7-3970X Extreme Edition processor
003 • Updated Table 4-9, “Package C-State Power Specifications” February 2014
Introduction
1 Introduction
The Intel® Core™ i7 processor family for the LGA-2011 socket is the next generation of
64-bit, multi-core desktop processor built on 32-nanometer process technology. Based
on the low-power/high performance Intel® Core™ i7 processor microarchitecture, the
processor is designed for a two-chip platform as opposed to the traditional three-chip
platforms (processor, MCH, and ICH). The two-chip platform consists of a processor
and the Platform Controller Hub (PCH) and enables higher performance, easier
validation, and improved x-y footprint. Refer to Figure 1-1 for a block diagram of the
processor platform.
The processor features up to 40 lanes of PCI Express* links capable of up to 8.0 GT/s,
and 4 lanes of DMI2/PCI Express* 2.0 interface with a peak transfer rate of 5.0 GT/s.
The processor supports up to 46 bits of physical address space and 48 bits of virtual
address space.
Included in this family of processors is an integrated memory controller (IMC) and

integrated I/O (IIO) (such as PCI Express* and DMI2) on a single silicon die. This single
die solution is known as a monolithic processor.
This document is Volume 1 of the datasheet for the Intel® Core™ i7 processor family
for the LGA-2011 socket. The complete datasheet consists of two volumes. This
document provides DC electrical specifications, land and signal definitions, interface
functional descriptions, power management descriptions, and additional feature
information pertinent to the implementation and operation of the processor on its
platform. Volume 2 provides register information. Refer to Section 1.7, “Related
Documents” for access to Volume 2.
Note: Throughout this document, the Intel® Core™ i7 processor family for the LGA-2011
socket may be referred to as “processor”.
Note: Throughout this document, the Desktop Intel® Core™ i7-39xxK processor series for the
LGA-2011 socket refers to the i7-3930K.
Note: Throughout this document, the Desktop Intel® Core™ i7-38xx processor series for the
LGA-2011 socket refers to the i7-3820.
Note: Throughout this document, the Intel® X79 Chipset Platform Controller Hub may be
referred to as “PCH”.
Introduction
Figure 1-1. Processor Platform Block Diagram Example
1.1 Processor Feature Details

• Up to 6 Execution Cores
• Each core supports two threads (Intel® Hyper-Threading Technology) for up to
12 threads
• A 32-KB instruction and 32-KB data first-level cache (L1) for each core
• A 256-KB shared instruction/data mid-level (L2) cache for each core
• Up to 15 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level
cache (LLC), shared among all cores
1.1.1 Supported Technologies

• Intel® Virtualization Technology (Intel® VT)
• Intel® Virtualization Technology for Directed I/O (Intel® VT-d)
• Intel® Virtualization Technology Intel® Core™ i7 processor family for the LGA-2011
socket Extensions
• Intel® 64 Architecture
• Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1)
• Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
• Intel® Advanced Vector Extensions (Intel® AVX)
• Intel® Hyper-Threading Technology (Intel® HT Technology)
• Execute Disable Bit
• Intel® Turbo Boost Technology
• Enhanced Intel® SpeedStep® Technology
Introduction
1.2 Interfaces
1.2.1 System Memory Support
• The processor supports 4 DDR3 channels with 1 unbuffered DIMM per channel
• Unbuffered DDR3 DIMMs supported
• Data burst length of eight cycles for all memory organization modes
• Memory DDR3 data transfer rates of 1066, 1333, and 1600 MT/s
• DDR3 UDIMM standard I/O Voltage of 1.5 V
• 1-Gb, 2-Gb, and 4-Gb DDR3 DRAM technologies supported for these devices:
— UDIMMs x8, x16
• Up to 2 ranks supported per memory channel, 1 or 2 ranks per DIMM
• Open with adaptive idle page close timer or closed page policy
• Command launch modes of 1n/2n
• Improved Thermal Throttling with dynamic CLTT
• Memory thermal monitoring support for DIMM temperature using two memory
signals, MEM_HOT
1.2.2 PCI Express*

• Support for PCI Express* 2.0 (5.0 GT/s), PCI Express* (2.5 GT/s), and capable of
up to PCI Express* 8.0 GT/s.
• Up to 40 lanes of PCI Express* interconnect for general purpose PCI Express
devices capable of up to 8.0 GT/s speeds that are configurable for up to 10
independent ports.
• Negotiating down to narrower widths is supported, see Figure 1-2
— x16 port (Port 2 & Port 3) may negotiate down to x8, x4, x2, or x1
— x8 port (Port 1) may negotiate down to x4, x2, or x1
— x4 port (Port 0) may negotiate down to x2, or x1
— When negotiating down to narrower widths, there are caveats as to how lane
reversal is supported
• Address Translation Services (ATS) 1.0 support
• Hierarchical PCI-compliant configuration mechanism for downstream devices
• Traditional PCI style traffic (asynchronous snooped, PCI ordering)
• PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express* Enhanced Access Mechanism. Accessing the device configuration
space in a flat memory mapped fashion.
Introduction
• Supports receiving and decoding 64 bits of address from PCI Express*

— Memory transactions received from PCI Express* that go above the top of
physical address space (when Intel VT-d is enabled, the check would be against
the translated HPA (Host Physical Address) address) are reported as errors by
the processor.
— Outbound access to PCI Express* will always have address bits 63 to 46 cleared
• Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status
• Power Management Event (PME) functions
• Message Signaled Interrupt (MSI and MSI-X) messages
• Degraded Mode support and Lane Reversal support
• Static lane numbering reversal and polarity inversion support
Figure 1-2. PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2)
Introduction
1.2.3 Direct Media Interface Gen 2 (DMI2)

• Serves as the chip-to-chip interface to the PCH
• The DMI2 port supports x4 link width and only operates in a x4 mode when in DMI2
• Operates at PCIe2 or PCIe1 speeds
• Transparent to software
• Processor and peer-to-peer writes and reads with 64-bit address support
• APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined “End of
Interrupt” broadcast message when initiated by the processor.
• System Management Interrupt (SMI), SCI, and SERR error indication
• Static lane numbering reversal support
• Supports DMI2 virtual channels VC0, VC1, VCm, and VCp
1.2.4 Platform Environment Control Interface (PECI)

The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master (the PCH). Refer to the processor
Thermal Mechanical Specification and Design Guide (see Section 1.7, “Related
Documents”) for additional details on PECI services available in the processor.
• Supports operation at up to 2 Mbps data transfers
• Link layer improvements to support additional services and higher efficiency over
PECI 2.0 generation
• Services include processor thermal and estimated power information, control
functions for power limiting, P-state and T-state control, and access for Machine
Check Architecture registers and PCI configuration space (both within the processor
package and downstream devices)
• Single domain (Domain 0) is supported
1.3 Power Management Support

1.3.1 Processor Package and Core States
• ACPI C-states as implemented by the following processor C-states
— Package: PC0, PC1/PC1E, PC2, PC3, PC6 (Package C7 is not supported)
— Core: CC0, CC1, CC1E, CC3, CC6, CC7
• Enhanced Intel SpeedStep® Technology
1.3.2 System States Support

• S0, S1, S3, S4, S5
1.3.3 Memory Controller

• Multiple CKE power down modes
• Multiple self-refresh modes
• Memory thermal monitoring using MEM_HOT_C01_N and MEM_HOT_C23_N Signals
1.3.4 PCI Express*

• L0s and L1 ASPM power management capability
Introduction
1.4 Thermal Management Support

• Adaptive Thermal Monitor
• THERMTRIP_N and PROCHOT_N signal support
• On-Demand mode clock modulation
• Open Loop Thermal Throttling and Hybrid OLTT/CLTT support for system memory
• Fan speed control with DTS
• Two integrated SMBus masters for accessing thermal data from DIMMs
• New Memory Thermal Throttling features using MEM_HOT signals
1.5 Package Summary

The processor socket type is noted as LGA2011. The processor package is a 52.5 x
45 mm FC-LGA package (LGA2011). Refer to the processor Thermal Mechanical
Specification and Design Guide (see Section 1.7, “Related Documents”) for the package
mechanical specifications.
1.6 Terminology
Table 1-1. Terminology (Sheet 1 of 3)

Term Description
ASPM Active State Power Management
Cbo Cache and Core Box. It is a term used for internal logic providing ring interface to
LLC and Core.
Third generation Double Data Rate SDRAM memory technology that is the successor to
DDR3
DDR2 SDRAM
DMA Direct Memory Access
DMI Direct Media Interface
DMI2 Direct Media Interface Gen 2
DTS Digital Thermal Sensor
ECC Error Correction Code
Enhanced Intel® Allows the operating system to reduce power consumption when performance is not
SpeedStep® Technology needed.
The Execute Disable bit allows memory to be marked as executable or non-executable,
when combined with a supporting operating system. If code attempts to run in non-
executable memory the processor raises an error to the operating system. This feature
Execute Disable Bit
can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities
and can thus help improve the overall security of the system. See the Intel® 64 and IA-32
Architectures Software Developer's Manuals for more detailed information.
Refers to the normal operating conditions in which all processor specifications, including
Functional Operation
DC, AC, system bus, signal quality, mechanical, and thermal, are satisfied.
Integrated Memory A Memory Controller that is integrated in the processor die.
Controller (IMC)
Integrated I/O An I/O controller that is integrated in the processor die.
Controller (IIO)
64-bit memory extensions to the IA-32 architecture. Further details on Intel 64
Intel® 64 Technology architecture and programming model can be found at
http://developer.intel.com/technology/intel64/.
Intel® Turbo Boost Technology is a way to automatically run the processor core faster
Intel® Turbo Boost than the marked frequency if the part is operating under power, temperature, and current
Technology specifications limits of the Thermal Design Power (TDP). This results in increased
performance of both single and multi-threaded applications.
Introduction

Term Description
Processor virtualization which when used in conjunction with Virtual Machine Monitor
Intel® Virtualization
software enables multiple, robust independent software environments inside a single
Technology (Intel® VT)
platform.
Intel® Virtualization Technology (Intel® VT) for Directed I/O. Intel VT-d is a hardware
® assist, under system software (Virtual Machine Manager or OS) control, for enabling I/O
Intel VT-d
device virtualization. Intel VT-d also brings robust security by providing protection from
errant DMAs by using DMA remapping, a key feature of Intel VT-d.
Integrated Heat A component of the processor package used to enhance the thermal performance of the
Spreader (IHS) package. Component thermal solutions interface with the processor at the IHS surface.
Jitter Any timing variation of a transition edge or edges from the defined Unit Interval (UI).
IOV I/O Virtualization
The 2011-land FC-LGA package mates with the system board through this surface mount,
LGA2011 Socket
2011-contact socket.
LLC Last Level Cache
ME Management Engine
Non-Critical to Function: NCTF locations are typically redundant ground or non-critical
NCTF reserved, so the loss of the solder joint continuity at end of life conditions will not affect
the overall product functionality.
Intel® Core™ i7 Intel’s 32-nm processor design, follow-on to the 32-nm 2nd Generation Intel® Core™
processor family for the processor family desktop design.
LGA-2011 socket
Platform Controller Hub. The next generation chipset with centralized platform capabilities
PCH including the main I/O interfaces along with display connectivity, audio features, power
management, manageability, security and storage features.
PCU Power Control Unit.
PCIe* PCI Express*
PECI Platform Environment Control Interface
Processor The 64-bit, single-core or multi-core component (package)
The term “processor core” refers to Si die itself which can contain multiple execution
cores. Each execution core has an instruction cache, data cache, and 256-KB L2 cache. All
Processor Core
execution cores share the L3 cache. All DC and AC timing and signal integrity
specifications are measured at the processor die (pads), unless otherwise noted.
PCU Uncore Power Manager
A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. These
Rank
devices are usually, but not always, mounted on a single side of a DDR3 DIMM.
SCI System Control Interrupt. Used in ACPI protocol.
SSE Intel® Streaming SIMD Extensions (Intel® SSE)
A processor Stock Keeping Unit (SKU) to be installed in the platform. Electrical, power and
SKU
thermal specifications for these SKU’s are based on specific use condition assumptions.
System Management Bus. A two-wire interface through which simple system and power
SMBus management related devices can communicate with the rest of the system. It is based on
the principals of the operation of the I2C* two-wire serial bus from Philips Semiconductor.
A non-operational state. The processor may be installed in a platform, in a tray, or loose.
Processors may be sealed in packaging or exposed to free air. Under these conditions,
processor landings should not be connected to any supply voltages, have any I/Os biased
Storage Conditions
or receive any clocks. Upon exposure to “free air” (that is, unsealed packaging or a device
removed from packaging material) the processor must be handled in accordance with
moisture sensitivity labeling (MSL) as indicated on the packaging material.
TAC Thermal Averaging Constant
TDP Thermal Design Power
TSOD Thermal Sensor on DIMM
UDIMM Unbuffered Dual In-line Module
Introduction

Term Description
Signaling convention that is binary and unidirectional. In this binary signaling, one bit is
sent for every edge of the forwarded clock, whether it be a rising edge or a falling edge. If
Unit Interval a number of edges are collected at instances t1, t2, tn,...., tk then the UI at instance “n” is
defined as:
UI n = t n – t n – 1
VCC Processor core power supply
VSS Processor ground
Power supply for the processor system memory interface. VCCD is the generic term for
VCCD_01, VCCD_23
VCCD_01, VCCD_23.
x1 Refers to a Link or Port with one Physical Lane
x4 Refers to a Link or Port with four Physical Lanes
x8 Refers to a Link or Port with eight Physical Lanes
x16 Refers to a Link or Port with sixteen Physical Lanes
1.7 Related Documents

Refer to the following documents for additional information.
Table 1-2. Reference Documents

Document Number/
Document
Location
Intel® Core™ i7 Processor Family for the LGA-2011 Socket Datasheet, Volume 2 326197
Intel® Core™ i7 Processor Family for the LGA-2011 Socket Specification Update 326198
Desktop Intel®
Core™ i7 Processor Family for the LGA-2011 Socket Thermal
326199
Mechanical Specifications and Design Guide
®
Intel C600 Series Chipset and Intel® X79 Express Chipset Datasheet 326514
Intel® C600 Series Chipset and Intel® X79 Express Chipset Specification Update 326515
Intel ®
X79 Express Chipset Thermal Mechanical Specifications and Design Guide 326202
Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info
PCI Local Bus Specification http://www.pcisig.com/

specifications
PCI Express* Base Specification http://www.pcisig.com
System Management Bus (SMBus) Specification http://smbus.org/
DDR3 SDRAM Specification http://www.jedec.org
Intel® 64 and IA-32 Architectures Software Developer's Manuals

• Volume 1: Basic Architecture http://www.intel.com/p
roducts/processor/man
• Volume 2A: Instruction Set Reference, A-M
uals/index.htm
• Volume 2B: Instruction Set Reference, N-Z
• Volume 3A: System Programming Guide
• Volume 3B: System Programming Guide
Intel® 64 and IA-32 Architectures Optimization Reference Manual
Intel® Virtualization Technology Specification for Directed I/O Architecture http://download.intel.co

Specification m/technology/computin
g/vptech/Intel(r)_VT_fo
r_Direct_IO.pdf
Interfaces
2 Interfaces
This chapter describes the functional behaviors supported by the processor.
2.1 System Memory Interface

2.1.1 System Memory Technology Support
The Integrated Memory Controller (IMC) supports DDR3 protocols with four
independent 64-bit memory channels and supports 1 unbuffered DIMM per channel.
2.1.2 System Memory Timing Support

The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
• tCL = CAS Latency
• tRCD = Activate Command to READ or WRITE Command delay
• tRP = PRECHARGE Command Period
• CWL = CAS Write Latency
• Command Signal modes = 1n indicates a new command may be issued every clock
and 2n indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer rate and memory configuration.
2.2 PCI Express* Interface

This section describes the PCI Express* interface capabilities of the processor. See the
PCI Express* Base Specification for details of PCI Express*.
Note: The processor is capable of up to 8.0 GT/s speeds.
2.2.1 PCI Express* Architecture

Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged. The PCI Express configuration uses
standard mechanisms as defined in the PCI Plug-and-Play specification.
The PCI Express architecture is specified in three layers — Transaction Layer, Data Link
Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries. Refer to Figure 2-1 for the PCI Express Layering Diagram.
Interfaces
Figure 2-1. PCI Express* Layering Diagram
PCI Express uses packets to communicate information between components. Packets

are formed in the Transaction and Data Link Layers to carry the information from the
transmitting component to the receiving component. As the transmitted packets flow
through the other layers, they are extended with additional information necessary to
handle packets at those layers. At the receiving side, the reverse process occurs and
packets get transformed from their Physical Layer representation to the Data Link
Layer representation and finally (for Transaction Layer Packets) to the form that can be
processed by the Transaction Layer of the receiving device.
Figure 2-2. Packet Flow through the Layers
2.2.1.1 Transaction Layer

The upper layer of the PCI Express architecture is the Transaction Layer. The
Transaction Layer's primary responsibility is the assembly and disassembly of
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as
read and write, as well as certain types of events. The Transaction Layer also manages
flow control of TLPs.
2.2.1.2 Data Link Layer

The middle layer in the PCI Express stack, the Data Link Layer, serves as an
intermediate stage between the Transaction Layer and the Physical Layer.
Responsibilities of Data Link Layer include link management, error detection, and error
correction.
Interfaces
The transmission side of the Data Link Layer accepts TLPs assembled by the
Transaction Layer, calculates and applies data protection code and TLP sequence
number, and submits them to Physical Layer for transmission across the Link. The
receiving Data Link Layer is responsible for checking the integrity of received TLPs and
for submitting them to the Transaction Layer for further processing. On detection of TLP
error(s), this layer is responsible for requesting retransmission of TLPs until information
is correctly received, or the Link is determined to have failed. The Data Link Layer also
generates and consumes packets which are used for Link management functions.
2.2.1.3 Physical Layer

The Physical Layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance
matching circuitry. It also includes logical functions related to interface initialization and
maintenance. The Physical Layer exchanges data with the Data Link Layer in an
implementation-specific format, and is responsible for converting this to an appropriate
serialized format and transmitting it across the PCI Express Link at a frequency and
width compatible with the remote device.
2.2.2 PCI Express* Configuration Mechanism

The PCI Express link is mapped through a PCI-to-PCI bridge structure.
PCI Express extends the configuration space to 4096 bytes per-device/function, as

compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express
configuration space is divided into a PCI-compatible region (which consists of the first
256 bytes of a logical device's configuration space) and an extended PCI Express region
(which consists of the remaining configuration space). The PCI-compatible region can
be accessed using either the mechanisms defined in the PCI specification or using the
enhanced PCI Express configuration access mechanism described in the PCI Express
Enhanced Configuration Mechanism section.
The PCI Express Host Bridge is required to translate the memory-mapped PCI Express
configuration space accesses from the host processor to PCI Express configuration
cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is
recommended that system software access the enhanced configuration space using
32-bit operations (32-bit aligned) only.
See the PCI Express* Base Specification for details of both the PCI-compatible and PCI
Express Enhanced configuration mechanisms and transaction rules.
2.3 DMI2/PCI Express* Interface

Direct Media Interface 2 (DMI2) connects the processor to the Platform Controller Hub
(PCH). DMI2 is similar to a four-lane PCI Express supporting a speed of 5 GT/s per
lane. Refer to Section 6.3, “DMI2 / PCI Express* Port 0 Signals” for additional details.
Note: Only DMI2 x4 configuration is supported.
2.3.1 DMI2 Error Flow

DMI2 can only generate SERR in response to errors; never SCI, SMI, MSI, PCI INT, or
GPE. Any DMI2 related SERR activity is associated with Device 0.
Interfaces
2.3.2 DMI2 Link Down

The DMI2 link going down is a fatal, unrecoverable error. If the DMI2 data link goes to
data link down, after the link was up, then the DMI2 link hangs the system by not
allowing the link to retrain to prevent data corruption. This is controlled by the PCH.
Downstream transactions that had been successfully transmitted across the link prior
to the link going down may be processed as normal. No completions from downstream,
non-posted transactions are returned upstream over the DMI2 link after a link down
event.
2.4 Platform Environment Control Interface (PECI)

The Platform Environment Control Interface (PECI) uses a single wire for self-clocking
and data transfer. The bus requires no additional control lines. The physical layer is a
self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle
level near zero volts. The duration of the signal driven high depends on whether the bit
value is a logic ‘0’ or logic ‘1’. PECI also includes variable data transfer rate established
with every message. In this way, it is highly flexible even though underlying logic is
simple.
The interface design was optimized for interfacing to Intel processor and chipset
components in both single processor and multiple processor environments. The single
wire interface provides low board routing overhead for the multiple load connections in
the congested routing area near the processor and chipset components. Bus speed,
error checking, and low protocol overhead provides adequate link bandwidth and
reliability to transfer critical device operating conditions and configuration information.
Refer to the processor Thermal Mechanical Specification and Design Guide (see
Section 1.7, “Related Documents”) for additional details regarding PECI and for a list of
supported PECI commands.
Technologies
3 Technologies
3.1 Intel® Virtualization Technology (Intel® VT)

Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple
independent systems to software. This allows multiple, independent operating systems
to run simultaneously on a single system. Intel VT comprises technology components
to support virtualization of platforms based on Intel architecture microprocessors and
chipsets.
• Intel® Virtualization Technology (Intel® VT) for Intel® 64 and IA-32 Intel®
Architecture (Intel® VT-x) adds hardware support in the processor to improve
the virtualization performance and robustness. Intel VT-x specifications and
functional descriptions are included in the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3B and is available at http://www.intel.com/
products/processor/manuals/index.htm
• Intel® Virtualization Technology (Intel® VT) for Directed I/O
(Intel® VT-d) adds processor and uncore hardware implementations to support
and improve I/O virtualization performance and robustness. The Intel VT-d
specification and other Intel VT documents can be referenced at
http://www.intel.com/technology/virtualization/index.htm

and IA-32 Intel® Architecture (Intel® VT-x) Objectives
Intel VT-x provides hardware acceleration for virtualization of IA platforms. Virtual
Machine Monitor (VMM) can use Intel VT-x features to provide improved reliable
virtualized platform. By using Intel VT-x, a VMM is:
• Robust: VMMs no longer need to use para-virtualization or binary translation. This
means that they will be able to run off-the-shelf operating systems and applications
without any special steps.
• Enhanced: Intel VT enables VMMs to run 64-bit guest operating systems on IA x86
processors.
• More reliable: Due to the hardware support, VMMs can now be smaller, less
complex, and more efficient. This improves reliability and availability and reduces
the potential for software conflicts.
• More secure: The use of hardware transitions in the VMM strengthens the isolation
of VMs and further prevents corruption of one VM from affecting others on the
same system.
Technologies

and IA-32 Intel® Architecture (Intel® VT-x) Features
The processor core supports the following Intel VT-x features:
• Extended Page Tables (EPT)
— hardware assisted page table virtualization
— eliminates VM exits from guest OS to the VMM for shadow page-table
maintenance
• Virtual Processor IDs (VPID)
— Ability to assign a VM ID to tag processor core hardware structures (such as,
TLBs)
— This avoids flushes on VM transitions to give a lower-cost VM transition time
and an overall reduction in virtualization overhead.
• Guest Preemption Timer
— Mechanism for a VMM to preempt the execution of a guest OS after an amount
of time specified by the VMM. The VMM sets a timer value before entering a
guest
— The feature aids VMM developers in flexibility and Quality of Service (QoS)
guarantees
• Descriptor-Table Exiting
— Descriptor-table exiting allows a VMM to protect a guest OS from internal
(malicious software based) attack by preventing relocation of key system data
structures like IDT (interrupt descriptor table), GDT (global descriptor table),
LDT (local descriptor table), and TSS (task segment selector).
— A VMM using this feature can intercept (by a VM exit) attempts to relocate
these data structures and prevent them from being tampered by malicious
software.
3.1.3 Intel® Virtualization Technology (Intel® VT) for

Directed I/O (Intel® VT-d) Objectives
The key Intel VT-d objectives are abstraction and robustness. Hardware abstraction has
two key benefits. First is partitioning hardware into configurable isolated environments
called domains to which a subset of host physical memory is allocated. Second is
greater flexibility in modifying hardware capability without direct operating system
interference. Virtualization allows for the creation of one or more partitions on a single
system. This could be multiple partitions in the same operating system, or there can be
multiple operating system instances running on the same system. The VT-d
architecture provides the flexibility to support multiple usage models and in turn
complement Intel VT-x capability. This offers benefits such as system consolidation,
legacy migration, activity partitioning, or security. The second objective is robustness.
VT-d enables protected access to I/O devices from a given virtual machine so that it
does not interfere with a different virtual machine on the same platform. Any errors or
permission violation are trapped and hence the system is more robust.
Technologies

Directed I/O (Intel® VT-d) Features Supported
The processor supports the following Intel VT-d features:
• Root entry, context entry, and default context
• Support for 4-K page sizes only
• Support for register-based fault recording only (for single entry only) and support
for MSI interrupts for faults
— Support for fault collapsing based on Requester ID
• Support for both leaf and non-leaf caching
• Support for boot protection of default page table
— Support for non-caching of invalid page table entries
• Support for hardware based flushing of translated but pending writes and pending
reads upon IOTLB invalidation
• Support for page-selective IOTLB invalidation
• Support for ARI (Alternative Requester ID – a PCI SIG ECR for increasing the
function number count in a PCIe device) to support IOV devices

Directed I/O (Intel® VT-d) Processor Feature Additions
The following are new features supported in Intel VT-d on the processor:
• Improved invalidation architecture
• End point caching support (Address Translation Services)
• Interrupt remapping
• 2M/1G/512G super page support
3.1.4 Intel® Virtualization Technology Processor Extensions

The processor supports the following Intel VT Intel® Core™ i7 processor family for the
LGA-2011 socket Extensions features:
• Large Intel VT-d Pages
— Adds 2 MB and 1 GB page sizes to Intel VT-d implementations
— Matches current support for Extended Page Tables (EPT)
— Ability to share CPU's EPT page-table (with super-pages) with Intel VT-d
— Benefits:
• Less memory foot-print for I/O page-tables when using super-pages
• Potential for improved performance – Due to shorter page-walks, allows
hardware optimization for IOTLB
• Transition latency reductions expected to improve virtualization performance
without the need for VMM enabling. This reduces the VMM overheads further and
increase virtualization performance.
Technologies
3.2 Security Technologies

3.2.1 Intel® AES New Instructions (Intel® AES-NI)
These instructions enable fast and secure data encryption and decryption using the
Advanced Encryption Standard (AES), which is defined by FIPS Publication number
197. Since AES is the dominant block cipher, and it is deployed in various protocols, the
new instructions will be valuable for a wide range of applications.
The architecture consists of six instructions that offer full hardware support for AES.
Four instructions support the AES encryption and decryption, and the other two
instructions support the AES key expansion. Together, they offer a significant increase
in performance compared to pure software implementations.
The AES instructions have the flexibility to support all three standard AES key lengths,
all standard modes of operation, and even some nonstandard or future variants.
Beyond improving performance, the AES instructions provide important security

benefits. Since the instructions run in data-independent time and do not use lookup
tables, they help in eliminating the major timing and cache-based attacks that threaten
table-based software implementations of AES. In addition, these instructions make AES
simple to implement, with reduced code size. This helps reducing the risk of
inadvertent introduction of security flaws, such as difficult-to-detect side channel leaks.
3.2.2 Execute Disable Bit

Intel's Execute Disable Bit functionality can help prevent certain classes of malicious
buffer overflow attacks when combined with a supporting operating system:
• Allows the processor to classify areas in memory by where application code can
execute and where it cannot.
• When a malicious worm attempts to insert code in the buffer, the processor
disables code execution, preventing damage and worm propagation.
3.3 Intel® Hyper-Threading Technology (Intel® HT

Technology)
The processor supports Intel® Hyper-Threading Technology (Intel® HT Technology)
that allows an execution core to function as two logical processors. While some
execution resources such as caches, execution units, and buses are shared, each
logical processor has its own architectural state with its own set of general-purpose
registers and control registers. This feature must be enabled using the BIOS and
requires operating system support.
For more information on Intel Hyper-Threading Technology, see http://www.intel.com/

technology/platform-technology/hyper-threading/.
Technologies
3.4 Intel® Turbo Boost Technology

Intel Turbo Boost Technology is a feature that allows the processor to opportunistically
and automatically run faster than its rated operating frequency if it is operating below
power, temperature, and current limits. The result is increased performance in multi-
threaded and single threaded workloads. It should be enabled in the BIOS for the
processor to operate with maximum performance.
3.4.1 Intel® Turbo Boost Operating Frequency

The processor’s rated frequency assumes that all execution cores are running an
application at the thermal design power (TDP). However, under typical operation, not
all cores are active. Therefore, most applications are consuming less than the TDP at
the rated frequency. To take advantage of the available TDP headroom, the active cores
can increase their operating frequency.
To determine the highest performance frequency amongst active cores, the processor
takes the following into consideration:
• The number of cores operating in the C0 state.
• The estimated current consumption.
• The estimated power consumption.
• The temperature.
Any of these factors can affect the maximum frequency for a given workload. If the
power, current, or thermal limit is reached, the processor will automatically reduce the
frequency to stay with its TDP limit.
Note: Intel Turbo Boost Technology is only active if the operating system is requesting the P0
state. For more information on P-states and C-states, refer to Chapter 4, "Power
Management".
3.5 Enhanced Intel® SpeedStep® Technology

The processor supports Enhanced Intel SpeedStep Technology (EIST) as an advanced
means of enabling very high performance while also meeting the power-conservation
needs of the platform.
Enhanced Intel SpeedStep Technology builds upon that architecture using design
strategies that include the following:
• Separation between Voltage and Frequency Changes. By stepping voltage up
and down in small increments separately from frequency changes, the processor
can reduce periods of system unavailability (which occur during frequency change).
Thus, the system can transition between voltage and frequency states more often,
providing improved power/performance balance.
• Clock Partitioning and Recovery. The bus clock continues running during state
transition, even when the core clock and Phase-Locked Loop are stopped, which
allows logic to remain active. The core clock can also restart more quickly under
Enhanced Intel SpeedStep Technology.
For additional information on Enhanced Intel SpeedStep Technology, see Section 4.2.1.
Technologies
3.6 Intel® Advanced Vector Extensions (Intel® AVX)

Intel® Advanced Vector Extensions (Intel® AVX) is a new 256-bit vector SIMD
extension of Intel Architecture. The introduction of Intel AVX starts with the 2nd
Generation Intel® Core™ Processor Family Desktop. Intel AVX accelerates the trend of
parallel computation in general purpose applications like image, video, and audio
processing, engineering applications such as 3D modeling and analysis, scientific
simulation, and financial analysts.
Intel AVX is a comprehensive ISA extension of the Intel 64 Architecture. The main
elements of Intel AVX are:
• Support for wider vector data (up to 256-bit) for floating-point computation
• Efficient instruction encoding scheme that supports 3 operand syntax and
headroom for future extensions
• Flexibility in programming environment, ranging from branch handling to relaxed
memory alignment requirements
• New data manipulation and arithmetic compute primitives, including broadcast,
permute, fused-multiply-add, etc
The key advantages of Intel AVX are:

• Performance – Intel AVX can accelerate application performance using data
parallelism and scalable hardware infrastructure across existing and new
application domains:
— 256-bit vector data sets can be processed up to twice the throughput of 128-bit
data sets
— Application performance can scale up with number of hardware threads and
number of cores
• Power Efficiency – Intel AVX is extremely power efficient. Incremental power is
insignificant when the instructions are unused or scarcely used. Combined with the
high performance that it can deliver, applications that lend themselves heavily to
using Intel AVX can be much more energy efficient and realize a higher
performance-per-watt.
• Extensibility – Intel AVX has built-in extensibility for the future vector extensions:
— OS context management for vector-widths beyond 256 bits is streamlined
— Efficient instruction encoding allows unlimited functional enhancements:
• Vector width support beyond 256 bits
• 256-bit Vector Integer processing
• Additional computational and/or data manipulation primitives.
• Compatibility – Intel AVX is backward compatible with previous ISA extensions
including Intel SSE4:
— Existing Intel SSE applications/library can:
• Run unmodified and benefit from processor enhancements
• Recompile existing Intel SSE intrinsic using compilers that generate Intel
AVX code
• Inter-operate with library ported to Intel AVX
— Applications compiled with Intel AVX can inter-operate with existing Intel SSE
libraries
§
Power Management
4 Power Management
This chapter provides information on the following power management topics:

• Advanced Configuration and Power Interface (ACPI) States
• System States
• Processor Core/Package States
• Integrated Memory Controller (IMC) and System Memory States
• Direct Media Interface Gen 2 (DMI2)/PCI Express* Link States
4.1 Advanced Configuration and Power Interface

(ACPI) States Supported
The ACPI states supported by the processor are described in this section.
4.1.1 System States
Table 4-1. System States

State Description
G0/S0 Full On
Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the

G1/S3-Cold
processor).
G1/S4 Suspend-to-Disk (STD). All power lost (except wakeup on PCH).
G2/S5 Soft off. All power lost (except wakeup on PCH). Total reboot.
G3 Mechanical off. All power removed from system.
4.1.2 Processor Package and Core States

Table 4-2 lists the package C-state support as:
• the shallowest core C-state that allows entry into the package C-state
• the additional factors that will restrict the state from going any deeper
• the actions taken with respect to the Ring Vcc, PLL state, and LLC.
Power Management
Table 4-3 lists the processor core C-states support.
Table 4-2. Package C-State Support

LLC
Core Retention and
Package C-State Limiting Factors Fully Notes1
States PLL-Off
Flushed
PC0 – Active CC0 N/A No No 2
• PCIe/PCH and Remote Socket

Snoops
• PCIe/PCH and Remote Socket
Accesses VccMin
PC2 – Snoopable
CC3–CC7 Freq = MinFreq No 2
Idle • Interrupt response time
requirement PLL = ON
• DMI Sidebands
• Configuration Constraints
• Core C-state
PC3 – Light at least • Snoop Response Time Vcc = retention
one Core No 2,3,4
Retention in C3 • Interrupt Response Time PLL = OFF
• Non Snoop Response Time
• LLC ways open

PC6 – Deeper • Snoop Response Time Vcc = retention
CC6–CC7 No 2,3,4
Retention • Non Snoop Response Time PLL = OFF
• Interrupt Response Time
Notes:
1. Package C7 is not supported.
2. All package states are defined to be "E" states – such that they always exit back into the LFM point upon
execution resume.
3. The mapping of actions for PC3, and PC6 are suggestions – microcode will dynamically determine which
actions should be taken based on the desired exit latency parameters.
4. CC3/CC6 will all use a voltage below the VccMin operational point. The exact voltage selected will be a
function of the snoop and interrupt response time requirements made by the devices (PCIe* and DMI) and
the operating system.
Table 4-3. Core C-State Support

Core C-State Global Clock PLL L1/L2 Cache Core VCC Context
CC0 Running On Coherent Active Maintained
CC1 Stopped On Coherent Active Maintained
CC1E Stopped On Coherent Request LFM Maintained
CC3 Stopped On Flushed to LLC Request Retention Maintained

CC6 Stopped On Flushed to LLC Power Gate Flushed to LLC
CC7 Stopped Off Flushed to LLC Power Gate Flushed to LLC
Power Management
4.1.3 Integrated Memory Controller States
Table 4-4. System Memory Power States

State Description
Power Up/Normal Operation CKE asserted. Active Mode, highest power consumption.
Opportunistic, per rank control after idle time:

• Active Power Down (APD) (default mode)
— CKE de-asserted. Power savings in this mode, relative to active idle
state is about 55% of the memory power. Exiting this mode takes
3–5 DCLK cycles.
• Pre-charge Power Down Fast Exit (PPDF)
— CKE de-asserted. DLL-On. Also known as Fast CKE. Power savings in
this mode, relative to active idle state, is about 60% of the memory
power. Exiting this mode takes 3–5 DCLK cycles.
CKE Power Down • Pre-charge Power Down Slow Exit (PPDS)
— CKE de-asserted. DLL-Off. Also known as Slow CKE. Power savings in
this mode, relative to active idle state, is about 87% of the memory
power. Exiting this mode takes 3–5 DCLK cycles until the first
command is allowed and 16 cycles until first data is allowed.
• Register CKE Power Down
— IBT-ON mode: Both CKE’s are de-asserted, the Input Buffer
Terminators (IBTs) are left “on”.
— IBT-OFF mode: Both CKE’s are de-asserted, the Input Buffer
Terminators (IBTs) are turned “off”.
CKE de-asserted. In this mode, no transactions are executed and the system
memory consumes the minimum possible power. Self refresh modes apply to
all memory channels for the processor.
• IO-MDLL Off: Option that sets the IO master DLL off when self refresh
occurs.
• PLL Off: Option that sets the PLL off when self refresh occurs.
Self-Refresh
In addition, the register component found on registered DIMMs (RDIMMs) is

complemented with the following power down states:
• Self Refresh
— Clock Stopped Power Down with IBT-On
— Clock Stopped Power Down with IBT-Off
4.1.4 DMI2 / PCI Express* Link States
Table 4-5. DMI2/PCI Express* Link States

State Description
L0 Full on – Active transfer state.

L11 Lowest Active State Power Management (ASPM) - Longer exit latency.
Notes:
1. L1 is only supported when the DMI2/PCI Express port is operating as a PCI Express port.
Power Management
4.1.5 G, S, and C State Combinations
Table 4-6. G, S, and C State Combinations

Processor
Global (G) Sleep Processor System
Core Description
State (S) State State Clocks
(C) State
G0 S0 C0 Full On On Full On
G0 S0 C1/C1E Auto-Halt On Auto-Halt
G0 S0 C3 Deep Sleep On Deep Sleep
Deep Power Deep Power Down

G0 S0 C6/C7 On
Down
G1 S3 Power off — Off, except RTC Suspend to RAM
G1 S4 Power off — Off, except RTC Suspend to Disk
G2 S5 Power off — Off, except RTC Soft Off

G3 NA Power off — Power off Hard off
4.2 Processor Core / Package Power Management

While executing code, Enhanced Intel SpeedStep® Technology optimizes the
processor’s frequency and core voltage based on workload. Each frequency and voltage
operating point is defined by ACPI as a P-state. When the processor is not executing
code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower
power C-states have longer entry and exit latencies.
4.2.1 Enhanced Intel® SpeedStep® Technology

The following are the key features of Enhanced Intel SpeedStep® Technology:
• Multiple frequency and voltage points for optimal performance and power
efficiency. These operating points are known as P-states.
• Frequency selection is software controlled by writing to processor MSRs. The
voltage is optimized based on temperature, leakage, power delivery loadline, and
dynamic capacitance.
— If the target frequency is higher than the current frequency, VCC is ramped up
to an optimized voltage. This voltage is signaled by the SVID Bus to the voltage
regulator. Once the voltage is established, the PLL locks on to the target
frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
target frequency, then transitions to a lower voltage by signaling the target
voltage on the SVID Bus.
— All active processor cores share the same frequency and voltage. In a multi-
core processor, the highest frequency P-state requested amongst all active
cores is selected.
— Software-requested transitions are accepted at any time. The processor has a
new capability from the previous processor generation, it can preempt the
previous transition and complete the new request without waiting for this
request to complete.
• The processor controls voltage ramp rates internally to ensure glitch-free
transitions.
• Because there is low transition latency between P-states, a significant number of
transitions per-second are possible.
Power Management
4.2.2 Low-Power Idle States

When the processor is idle, low-power idle states (C-states) are used to save power.
More power savings actions are taken for numerically higher C-states. However, higher
C-states have longer exit and entry latencies. Resolution of C-states occur at the
thread, processor core, and processor package level. Thread level C-states are
available if Hyper-Threading Technology is enabled. Entry and exit of the C-States at
the thread and core level are shown in Figure 4-2.
Figure 4-1. Idle Power Management Breakdown of the Processor Cores
Figure 4-2. Thread and Core C-State Entry and Exit
While individual threads can request low power C-states, power saving actions only
take place once the core C-state is resolved. Core C-states are automatically resolved
by the processor. For thread and core C-states, a transition to and from C0 is required
before entering any other C-state.
Power Management
4.2.3 Requesting Low-Power Idle States

If enabled, the core C-state will be C1E if all actives cores have also resolved a core C1
state or higher.
The primary software interfaces for requesting low power idle states are through the
MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).
However, software may make C-state requests using the legacy method of I/O reads
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This
method of requesting C-states provides legacy support for operating systems that
initiate C-state transitions using I/O reads.
For legacy operating systems, P_LVLx I/O reads are converted within the processor to
the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in
I/O reads to the system. The feature, known as I/O MWAIT redirection, must be
enabled in the BIOS.
Note: The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read
interface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as shown in
Table 4-7.
Table 4-7. P_LVLx to MWAIT Conversion
P_LVLx MWAIT(Cx) Notes
P_LVL2 MWAIT(C3)
P_LVL3 MWAIT(C6) C6. No sub-states allowed.
P_LVL4 MWAIT(C7) C7. No sub-states allowed.
The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict
the range of I/O addresses that are trapped and emulate MWAIT like functionality. Any
P_LVLx reads outside of this range do not cause an I/O redirection to MWAIT(Cx) like
request. They fall through like a normal I/O instruction.
Note: When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. The
MWAIT substate is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O
redirections enable the MWAIT 'break on EFLAGS.IF’ feature that triggers a wakeup on
an interrupt, even if interrupts are masked by EFLAGS.IF.
4.2.4 Core C-states

The following are general rules for all core C-states, unless specified otherwise:
• A core C-State is determined by the lowest numerical thread state (such as, Thread
0 requests C1E while Thread 1 requests C3, resulting in a core C1E state). See
Table 4-6.
• A core transitions to C0 state when:
— an interrupt occurs.
— there is an access to the monitored address if the state was entered using an
MWAIT instruction.
• For core C1/C1E, and core C3, an interrupt directed toward a single thread wakes
only that thread. However, since both threads are no longer at the same core C-
state, the core resolves to C0.
• An interrupt only wakes the target thread for both C3 and C6 states. Any interrupt
coming into the processor package may wake any core.
Power Management
4.2.4.1 Core C0 State

The normal operating state of a core where code is being executed.
4.2.4.2 Core C1/C1E State

C1/C1E is a low power state entered when all threads within a core execute a HLT or
MWAIT(C1/C1E) instruction.
A System Management Interrupt (SMI) handler returns execution to either Normal

state or the C1/C1E state. See the Intel® 64 and IA-32 Architecture Software
Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.
While a core is in C1/C1E state, it processes bus snoops and snoops from other
threads. For more information on C1E, see Section 4.2.5.2, “Package C1/C1E”.

Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to
the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its
L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while
maintaining its architectural state. All core clocks are stopped at this point. Because the
core’s caches are flushed, the processor does not wake any core that is in the C3 state
when either a snoop is detected or when another core accesses cacheable memory.

Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an
MWAIT(C6) instruction. Before entering core C6, the core will save its architectural
state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero
volts. During exit, the core is powered on and its architectural state is restored. In
addition to flushing core caches core architecture state is saved to the uncore. Once the
core state save is completed, core voltage is reduced to zero.

Individual threads of a core can enter the C7 state by initiating a P_LVL4 I/O read to
the P_BLK or by an MWAIT(C7) instruction. Core C7 and core C7 substate are the same
as Core C6. The processor does not support LLC flush under any condition.
4.2.4.6 C-State Auto-Demotion

In general, deeper C-states such as C6 or C7 have long latencies and have higher
energy entry/exit costs. The resulting performance and energy penalties become
significant when the entry/exit frequency of a deeper C-state is high. To increase
residency in deeper C-states, the processor supports C-state auto-demotion.
There are two C-State auto-demotion options:

• C6/C7 to C3
• C7/C6/C3 To C1
The decision to demote a core from C6/C7 to C3 or C3/C6/C7 to C1 is based on each

core’s immediate residency history. Upon each core C6/C7 request, the core C-state is
demoted to C3 or C1 until a sufficient amount of residency has been established. At
that point, a core is allowed to go into C3/C6 or C7. Each option can be run
concurrently or individually.
Power Management
This feature is disabled by default. BIOS must enable it in the

PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by
this register.
4.2.5 Package C-States

The processor supports C0, C1/C1E, C2, C3, and C6 power states. The following is a
summary of the general rules for package C-state entry. These apply to all package
C-states unless specified otherwise:
• A package C-state request is determined by the lowest numerical core C-state
amongst all cores.
• A package C-state is automatically resolved by the processor depending on the
core idle power states and the status of the platform components.
— Each core can be at a lower idle power state than the package if the platform
does not grant the processor permission to enter a requested package C-state.
— The platform may allow additional power savings to be realized in the
processor.
• For package C-states, the processor is not required to enter C0 before entering any
other C-state.
The processor exits a package C-state when a break event is detected. Depending on
the type of break event, the processor does the following:
• If a core break event is received, the target core is activated and the break event
message is forwarded to the target core.
— If the break event is not masked, the target core enters the core C0 state and
the processor enters package C0.
— If the break event is masked, the processor attempts to re-enter its previous
package state.
• If the break event was due to a memory access or snoop request.
— But the platform did not request to keep the processor in a higher package C-
state, the package returns to its previous C-state.
— And the platform requests a higher power C-state, the memory access or snoop
request is serviced and the package remains in the higher power C-state.
The package C-states fall into two categories – uncoordinated and coordinated. C0/C1/
C1E are uncoordinated, while C2/C3/C6 are coordinated.
Starting with the 2nd Generation Intel® Core™ Processor Family Desktop, package C-
states are based on exit latency requirements which are accumulated from the PCIe*
devices, PCH, and software sources. The level of power savings that can be achieved is
a function of the exit latency requirement from the platform. As a result, there is no
fixed relationship between the coordinated C-state of a package, and the power savings
that will be obtained from the state. Coordinated package C-states offer a range of
power savings which is a function of the ensured exit latency requirement from the
platform.
There is also a concept of Execution Allowed (EA) – when EA status is 0, the cores in a
socket are in C3 or a deeper state, a socket initiates a request to enter a coordinated
package C-state. The coordination is across all sockets and the PCH.
Table 4-8 shows an example of a dual-core processor package C-state resolution.

Figure 4-3 summarizes package C-state transitions with package C2 as the interim
between PC0 and PC1 prior to PC3 and PC6.
Power Management
Table 4-8. Coordination of Core Power States at the Package Level

Core 1
Package C-State
C0 C1 C3 C6
C0 C0 C0 C0 C0
C1 C0 C11 C11 C11

Core 0
C3 C0 C11 C3 C3
C6 C0 C11 C3 C6
Notes:
1. If enabled, the package C-state will be C1E if all actives cores have resolved a core C1 state or higher.
Figure 4-3. Package C-State Entry and Exit
4.2.5.1 Package C0
The normal operating state for the processor. The processor remains in the normal
state when at least one of its cores is in the C0 or C1 state or when the platform has
not granted permission to the processor to go into a low power state. Individual cores
may be in lower power idle states while the package is in C0.
4.2.5.2 Package C1/C1E

No additional power reduction actions are taken in the package C1 state. However, if
the C1E sub-state is enabled, the processor automatically transitions to the lowest
supported core clock frequency, followed by a reduction in voltage. Autonomous power
reduction actions that are based on idle timers can trigger depending on the activity in
the system.
The package enters the C1 low power state when:

• At least one core is in the C1 state
• The other cores are in a C1 or lower power state
Power Management
The package enters the C1E state when:

• All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint
• All cores are in a power state lower that C1/C1E but the package low power state is
limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR
• All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is
enabled in IA32_MISC_ENABLES
No notification to the system occurs upon entry to C1/C1E.
4.2.5.3 Package C2 State

The Package C2 state is an intermediate state that represents the point at which the
system level coordination is in progress. The package cannot reach this state unless all
cores are in at least C3.
The package will remain in C2 when:

• it is awaiting for a coordinated response
• the coordinated exit latency requirements are too stringent for the package to take
any power saving actions
If the exit latency requirements are high enough, the package will transition to C3 or
C6 depending on the state of the cores.

A processor enters the package C3 low power state when:
• The other cores are in a C3 or lower power state, and the processor has been
granted permission by the platform
• L3 shared cache retains context and becomes inaccessible in this state
• Additional power savings actions, as allowed by the exit latency requirements,
include putting PCIe* links in L1, the uncore is not available, further voltage
reduction can be taken
• In package C3, the ring will be off and as a result no accesses to the LLC are
possible. The content of the LLC is preserved

A processor enters the package C6 low power state when:
• The other cores are in a C6 or lower power state, and the processor has been
granted permission by the platform
• L3 shared cache retains context and becomes inaccessible in this state
• Additional power savings actions, as allowed by the exit latency requirements,
include putting PCIe* links in L1, the uncore is not available, further voltage
reduction can be taken
In package C6 state, all cores have saved their architectural state and have had their
core voltages reduced to zero volts. The LLC retains context, but no accesses can be
made to the LLC in this state, the cores must break out to the internal state package C2
for snoops to occur.
Power Management
4.2.6 Package C-State Power Specifications

Table 4-9 lists the processor package C-state power specifications for various processor
SKUs.
The C-state power specification is based on post-silicon validation results. The

processor case temperature is assumed at 50 °C for all C-states.
Table 4-9. Package C-State Power Specifications
TDP SKUs C1E (W) C3 (W) C6 (W)
6-Core
Intel® Core™ 3970X processor

Extreme Edition 58 27 15
150 W (6-core)
Intel® Core™ 3960X processor
130 W (6-core)
Intel® Core™ 3930K processor
130 W (6-core)
4-Core
Intel® Core™ 3820K processor

130 W (4-core)
4.3 System Memory Power Management

The DDR3 power states can be summarized as the following:
• Normal operation (highest power consumption)
• CKE Power-Down: Opportunistic, per rank control after idle time. There may be
different levels.
— Active Power-Down
— Precharge Power-Down with Fast Exit
— Precharge power Down with Slow Exit
• Self Refresh: In this mode no transaction is executed. The DDR consumes the
minimum possible power.
4.3.1 CKE Power-Down

The CKE input land is used to enter and exit different power-down modes. The memory
controller has a configurable activity timeout for each rank. When no reads are present
to a given rank for the configured interval, the memory controller will transition the
rank to power-down mode.
The memory controller transitions the DRAM to power-down by de-asserting CKE and
driving a NOP command. The memory controller will tri-state all DDR interface lands
except CKE (de-asserted) and ODT while in power-down. The memory controller will
transition the DRAM out of power-down state by synchronously asserting CKE and
driving a NOP command.
When CKE is off, the internal DDR clock is disabled and the DDR power is significantly
reduced.
Power Management
The DDR defines three levels of power-down:

• Active power-down: This mode is entered if there are open pages when CKE is de-
asserted. In this mode the open pages are retained. Existing this mode is 3–5 DCLK
cycles.
• Precharge power-down fast exit: This mode is entered if all banks in DDR are
precharged when de-asserting CKE. Existing this mode is 3–5 DCLK cycles. The
difference from the active power-down mode is that when waking up, all page-
buffers are empty.
• Precharge power-down slow exit: In this mode the data-in DLLs on DDR are off.
Existing this mode is 3–5 DCLK cycles until the first command is allowed, but about
16 cycles until first data is allowed.
4.3.2 Self Refresh

The Uncore Power Manager (PCU) may request the memory controller to place the
DRAMs in self refresh state. Self refresh per channel is supported. The BIOS can put
the channel in self refresh if software remaps memory to use a subset of all channels.
Also processor channels can enter self refresh autonomously without PCU instruction
when the package is in a package C0 state.
4.3.2.1 Self Refresh Entry

Self refresh entrance can be either disabled or triggered by an idle counter. Idle counter
always clears with any access to the memory controller and remains clear as long as
the memory controller is not drained. As soon as the memory controller is drained, the
counter starts counting, and when it reaches the idle-count, the memory controller will
place the DRAMs in self refresh state.
Power may be removed from the memory controller core at this point, but the VCCD
supply (1.5 V) to the DDR I/O must be maintained.
4.3.2.2 Self Refresh Exit

Self refresh exit can be either a message from an external unit (PCU in most cases, but
also possibly from any message-channel master) or as reaction for an incoming
transaction.
The proper actions on self refresh exit are:
• CK is enabled, and four CK cycles driven
• When proper skew between Address/Command and CK are established, assert CKE
• Issue NOPs for tXSRD cycles
• Issue ZQCL to each rank
• The global scheduler will be enabled to issue commands
4.3.2.3 DLL and PLL Shutdown

Self refresh, according to configuration, may be a trigger for master DLL shut-down
and PLL shut-down. The master DLL shut-down is issued by the memory controller
after the DRAMs have entered self refresh.
The PLL shut-down and wake-up is issued by the PCU. The memory controller gets a
signal from PLL indicating that the memory controller can start working again.
Power Management
4.3.3 DRAM I/O Power Management

Unused signals are tristated to save power. This includes all signals associated with an
unused memory channel.
The I/O buffer for an unused signal should be tristated (output driver disabled), the
input receiver (differential sense-amp) should be disabled. The input path must be
gated to prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).
4.4 DMI2 / PCI Express* Power Management

Active State Power Management (ASPM) support using the L1 state.
Thermal Management Specifications
5 Thermal Management
Specifications
For thermal specifications and design guidelines, refer to the processor Thermal
Mechanical Specification and Design Guide (see Section 1.7, “Related Documents”).
§§
Signal Descriptions
6 Signal Descriptions
This chapter describes the processor signals. They are arranged in functional groups
according to their associated interface or category.
6.1 System Memory Interface
Table 6-1. Memory Channel DDR0, DDR1, DDR2, DDR3

Signal Name Description
Bank Address. Defines the bank which is the destination for the
DDR{0/1/2/3}_BA[2:0] current Activate, Read, Write, or Precharge command.
DDR{0/1/2/3}_CAS_N Column Address Strobe.
DDR{0/1/2/3}_CKE[3:0] Clock Enable.
DDR{0/1/2/3}_CLK_DN[3:0] Differential clocks to the DIMM. All command and control signals are
valid on the rising edge of clock.
DDR{0/1/2/3}_CLK_DP[3:0]
DDR{0/1/2/3}_CS_N[1:0] Chip Select. Each signal selects one rank as the target of the
DDR{0/1/2/3}_CS_N[5:4] command and address.
DDR{0/1/2/3}_DQ[63:00] Data Bus. DDR3 Data bits.
DDR{0/1/2/3}_DQS_DP[08:00] Data strobes. Differential pair, Data Strobe. Differential strobes latch
data for each DRAM. Driven with edges in center of data, receive
DDR{0/1/2/3}_DQS_DN[08:00] edges are aligned with data edges.
Check bits. An error correction code is driven along with data on these
lines for DIMMs that support that capability.
DDR{0/1/2/3}_ECC[7:0] Note: ECC DIMMs are not supported on the processor; thus, these
signals are not used.
Memory Address. Selects the Row address for Reads and writes, and
DDR{0/1/2/3}_MA[15:00] the column address for activates. Also used to set values for DRAM
configuration registers.
On Die Termination. Enables DRAM on die termination during Data
DDR{0/1/2/3}_ODT[3:0] Write or Data Read transactions.
DDR{0/1/2/3}_RAS_N Row Address Strobe.
DDR{0/1/2/3}_WE_N Write Enable.
Signal Descriptions
Table 6-2. Memory Channel Miscellaneous

DDR_RESET_C01_N System memory reset: Reset signal from processor to DRAM devices on the
DIMMs. DDR_RESET_C01_N is used for memory channels 0 and 1 while
DDR_RESET_C23_N DDR_RESET_C23_N is used for memory channels 2 and 3.
SMBus clock for the dedicated interface to the serial presence detect (SPD)
DDR_SCL_C01 and thermal sensors (TSoD) on the DIMMs. DDR_SCL_C01 is used for
DDR_SCL_C23 memory channels 0 and 1 while DDR_SCL_C23 is used for memory channels
2 and 3.
SMBus data for the dedicated interface to the serial presence detect (SPD)
DDR_SDA_C01 and thermal sensors (TSoD) on the DIMMs. DDR_SDA_C1 is used for
DDR_SDA_C23 memory channels 0 and 1 while DDR_SDA_C23 is used for memory channels
2 and 3.
DDR_VREFDQRX_C01 Voltage reference for system memory reads. DDR_VREFDQRX_C01 is used

for memory channels 0 and 1 while DDR_VREFDQRX_C23 is used for memory
DDR_VREFDQRX_C23 channels 2 and 3.
Voltage reference for system memory writes. DDR_VREFDQTX_C01 is used
DDR_VREFDQTX_C01 for memory channels 0 and 1 while DDR_VREFDQTX_C23 is used for memory
DDR_VREFDQTX_C23 channels 2 and 3.
Note: Future implementation option, not included in first silicon.
DDR{01/ System memory impedance compensation. Impedance compensation must

23}_RCOMP[2:0] be terminated on the system board using a precision resistor.
DRAM_PWR_OK_C01 Power good input signal used to indicate that the VCCD power supply is
stable for memory channels 0 & 1 and channels 2 & 3.
DRAM_PWR_OK_C23
6.2 PCI Express* Based Interface Signals

Note: PCI Express* Ports 1, 2, and 3 Signals are receive and transmit differential pairs.
Table 6-3. PCI Express* Port 1 Signals

PE1A_RX_DN[3:0] PCIe Receive Data Input

PE1A_RX_DP[3:0]
PE1B_RX_DN[7:4] PCIe Receive Data Input
PE1B_RX_DP[7:4]
PE1A_TX_DN[3:0] PCIe Transmit Data Output
PE1A_TX_DP[3:0]
PE1B_TX_DN[7:4] PCIe Transmit Data Output
PE1B_TX_DP[7:4]
Signal Descriptions


PE2A_RX_DP[3:0]
PE2B_RX_DP[7:4]
PE2C_RX_DN[11:8] PCIe Receive Data Input
PE2C_RX_DP[11:8]
PE2D_RX_DN[15:12] PCIe Receive Data Input
PE2D_RX_DP[15:12]
PE2A_TX_DP[3:0]
PE2B_TX_DP[7:4]
PE2C_TX_DN[11:8] PCIe Transmit Data Output
PE2C_TX_DP[11:8]
PE2D_TX_DN[15:12] PCIe Transmit Data Output
PE2D_TX_DP[15:12]


PE3A_RX_DP[3:0]
PE3B_RX_DP[7:4]
PE3C_RX_DN[11:8] PCIe Receive Data Input
PE3C_RX_DP[11:8]
PE3D_RX_DN[15:12] PCIe Receive Data Input
PE3D_RX_DP[15:12]
PE3A_TX_DP[3:0]
PE3B_TX_DP[7:4]
PE3C_TX_DN[11:8] PCIe Transmit Data Output
PE3C_TX_DP[11:8]
PE3D_TX_DN[15:12] PCIe Transmit Data Output
PE3D_TX_DP[15:12]
Signal Descriptions
Table 6-6. PCI Express* Miscellaneous Signals

This input is used to control PCI Express* bias currents. A 50 ohm 1%

tolerance resistor must be connected from this land to VSS by the platform.
PE_RBIAS PE_RBIAS is required to be connected as if the link is being used even when
PCIe* is not used.
Provides dedicated bias resistor sensing to minimize the voltage drop caused
PE_RBIAS_SENSE by packaging and platform effects. PE_RBIAS_SENSE is required to be
connected as if the link is being used even when PCIe* is not used.
PCI Express* voltage reference used to measure the actual output voltage
PE_VREF_CAP and comparing it to the assumed voltage. A 0.01 uF capacitor must be
connected from this land to VSS.
6.3 DMI2 / PCI Express* Port 0 Signals
Table 6-7. DMI2 to Port 0 Signals

DMI_RX_DN[3:0] DMI2 Receive Data Input

DMI_RX_DP[3:0]
DMI_TX_DP[3:0] DMI2 Transmit Data Output
DMI_TX_DN[3:0]
6.4 Platform Environment Control Interface (PECI)

Signal
Table 6-8. PECI Signals

PECI (Platform Environment Control Interface) is the serial sideband interface

PECI to the processor and is used primarily for thermal, power and error
management.
6.5 System Reference Clock Signals
Table 6-9. System Reference Clock (BCLK{0/1}) Signals

Reference Clock Differential input. These pins provide the PLL reference clock
BCLK{0/1}_D[N/P] differential input into the processor.
Signal Descriptions
6.6 JTAG and TAP Signals
Table 6-10. JTAG and TAP Signals

Breakpoint and Performance Monitor Signals: I/O signals from the processor
BPM_N[7:0] that indicate the status of breakpoints and programmable counters used for
monitoring processor performance. These are 100 MHz signals.
External Alignment of Reset, used to bring the processor up into a deterministic
EAR_N state. This signal is pulled up on the die; refer to Table 7-6 for details.
Probe Mode Ready is a processor output used by debug tools to determine
PRDY_N processor debug readiness.
Probe Mode Request is used by debug tools to request debug operation of the
PREQ_N processor.
TCK (Test Clock) provides the clock input for the processor Test Bus (also
TCK known as the Test Access Port).
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
TDI serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor. TDO
TDO provides the serial output needed for JTAG specification support.
TMS (Test Mode Select) is a JTAG specification support signal used by debug
TMS tools.
TRST_N (Test Reset) resets the Test Access Port (TAP) logic. TRST_N must be
TRST_N driven low during power on Reset.
6.7 Serial VID Interface (SVID) Signals
Table 6-11. SVID Signals

SVIDALERT_N Serial VID alert.
SVIDCLK Serial VID clock.
SVIDDATA Serial VID data out.
Signal Descriptions
6.8 Processor Asynchronous Sideband and

Miscellaneous Signals
Table 6-12. Processor Asynchronous Sideband Signals (Sheet 1 of 2)

Input which allows the platform to enable or disable built-in self test (BIST) on the
BIST_ENABLE processor. This signal is pulled up on the die; refer to Table 7-6 for details.
Indicates that the system has experienced a fatal or catastrophic error and cannot
continue to operate. The processor will assert CAT_ERR_N for nonrecoverable machine
check errors and other internal unrecoverable errors. It is expected that every
processor in the system will wire-OR CAT_ERR_N for all processors. Since this is an I/O
land, external agents are allowed to assert this land, which will cause the processor to
CAT_ERR_N take a machine check exception. This signal is sampled after PWRGOOD assertion.
On the processor, CAT_ERR_N is used for signaling the following types of errors:
• Legacy MCERR’s, CAT_ERR_N is asserted for 16 BCLKs.
• Legacy IERR’s, CAT_ERR_N remains asserted until warm or cold reset.
CPU_ONLY_RESET Resets all the processors on the platform without resetting the DMI2 links.
Error status signals for integrated I/O (IIO) unit:

0 = Hardware correctable error (no operating system or firmware action necessary)
ERROR_N[2:0] 1 = Non-fatal error (operating system or firmware action required to contain and
recover)
2 = Fatal error (system reset likely required to recover)
Memory throttle control. MEM_HOT_C01_N and MEM_HOT_C23_N signals have two
modes of operation – input and output mode.
Input mode is externally asserted and is used to detect external events such as
VR_HOT# from the memory voltage regulator and causes the processor to throttle the
MEM_HOT_C01_N appropriate memory channels.
MEM_HOT_C23_N Output mode is asserted by the processor known as level mode. In level mode, the
output indicates that a particular branch of memory subsystem is hot.
MEM_HOT_C01_N is used for memory channels 0 & 1 while MEM_HOT_C23_N is used
for memory channels 2 & 3.
Power Management Sync. A sideband signal to communicate power management
PMSYNC status from the Platform Controller Hub (PCH) to the processor.
PROCHOT_N will go active when the processor temperature monitoring sensor detects
that the processor has reached its maximum safe operating temperature. This
indicates that the processor Thermal Control Circuit has been activated, if enabled.
This signal can also be driven to the processor to activate the Thermal Control Circuit.
PROCHOT_N
This signal is sampled after PWRGOOD assertion.
If PROCHOT_N is asserted at the deassertion of RESET_N, the processor will tristate its
outputs.
Power Good is a processor input. The processor requires this signal to be a clean
indication that BCLK, VTTA/VTTD, VSA, VCCPLL, VCCD_01 and VCCD_23 supplies are stable
and within their specifications.
“Clean” implies that the signal will remain low (capable of sinking leakage current),
without glitches, from the time that the power supplies are turned on until they come
within specification. The signal must then transition monotonically to a high state.
PWRGOOD can be driven inactive at any time, but clocks and power must again be
stable before a subsequent rising edge of PWRGOOD. PWRGOOD transitions from
PWRGOOD inactive to active when all supplies except VCC are stable. VCC has a VBOOT of zero
volts and is not included in PWRGOOD indication in this phase. However, for the active
to inactive transition, if any processor power supply (VCC, VTTA/VTTD, VSA, VCCD, or
VCCPLL) is about to fail or is out of regulation, the PWRGOOD is to be negated.
The signal must be supplied to the processor; it is used to protect internal circuits
against voltage sequencing issues. It should be driven high throughout boundary scan
operation.
Note: VCC has a Vboot setting of 0.0 V and is not included in the PWRGOOD indication
and VSA has a Vboot setting of 0.9 V.
Signal Descriptions
Table 6-12. Processor Asynchronous Sideband Signals (Sheet 2 of 2)

Asserting the RESET_N signal resets the processor to a known state and invalidates its
RESET_N internal caches without writing back any of their contents. Some PLL and error states
are not effected by reset and only PWRGOOD forces them to a known state.
Test[4:0] must be individually connected to an appropriate power source or ground

TEST[4:0] through a resistor for proper processor operation.
Assertion of THERMTRIP_N (Thermal Trip) indicates one of two possible critical over-
temperature conditions: One, the processor junction temperature has reached a level
beyond which permanent silicon damage may occur and Two, the system memory
interface has exceeded a critical temperature limit set by BIOS.
Measurement of the processor junction temperature is accomplished through multiple
internal thermal sensors that are monitored by the Digital Thermal Sensor (DTS).
Simultaneously, the Power Control Unit (PCU) monitors external memory temperatures
using the dedicated SMBus interface to the DIMMs.
THERMTRIP_N If any of the DIMMs exceed the BIOS defined limits, the PCU will signal THERMTRIP_N
to prevent damage to the DIMMs. Once activated, the processor will stop all execution
and shut down all PLLs. To further protect the processor, its core voltage (VCC), VTTA,
VTTD, VSA, VCCPLL, VCCD supplies must be removed following the assertion of
THERMTRIP_N. Once activated, THERMTRIP_N remains latched until RESET_N is
asserted. While the assertion of the RESET_N signal may de-assert THERMTRIP_N, if
the processor's junction temperature remains at or above the trip level, THERMTRIP_N
will again be asserted after RESET_N is de-asserted.
This signal can also be asserted if the system memory interface has exceeded a critical
temperature limit set by BIOS. This signal is sampled after PWRGOOD assertion.
Table 6-13. Miscellaneous Signals

These configuration straps are used to inform the processor that a non-
standard value for BCLK is going to is been applied at reset. A "11" encoding
on these inputs will inform the processor to run at DEFAULT BCLK =
100 MHz. These signals have internal pull-up to VTT.
The encoding is as follows:
BCLK_SELECT1 BCLK_SELECT0 BCLK Selected
BCLK_SELECT[1:0]
X X 100 MHz (default)
1 1 100 MHz
1 0 125 MHz
0 1 Reserved
0 0 Reserved
CORE_VREF_CAP A capacitor must be connected from this land.
CORE_RBIAS This input is used to control bias currents.

Provides dedicated bias resistor sensing to minimize the voltage drop caused
CORE_RBIAS_SENSE by packaging and platform effects.
This output can be used by the platform to determine if the installed
processor is a Intel® Core™ i7 processor family for the LGA-2011 socket or a
PROC_SEL_N future processor planned for the platforms. There is no connection to the
processor silicon for this signal. This signal is also used by the VCCPLL and VTT
rails to switch their output voltage to support future processors.
RESERVED. All signals that are RSVD must be left unconnected on the board.
RSVD Refer to Section 7.1.9 for details.
SKTOCC_N (Socket occupied) is used to indicate that a processor is present.
SKTOCC_N This is pulled to ground on the processor package; there is no connection to
the processor silicon for this signal.
TESTHI_BH48 TESTHI_XX signal must be pulled up on the board.
TESTHI_BF48
TESTHI_AT50
Signal Descriptions
6.9 Processor Power and Ground Supplies
Table 6-14. Power and Ground Signals

Variable power supply for the processor cores, lowest level caches (LLC), ring
interface, and home agent. It is provided by a VR12 compliant regulator. The
output voltage of this supply is selected by the processor using the serial
VCC voltage ID (SVID) bus.
Note: VCC has a Vboot setting of 0.0 V and is not included in the PWRGOOD
indication.
VCC_SENSE and VSS_VCC_SENSE provide an isolated, low impedance
VCC_SENSE connection to the processor core power and ground. These signals must be
VSS_VCC_SENSE connected to the voltage regulator feedback circuit, which insures the output
voltage (that is, processor voltage) remains within specification.
VSA_SENSE and VSS_VSA_SENSE provide an isolated, low impedance

VSA_SENSE connection to the processor system agent (VSA) power plane. These signals
VSS_VSA_SENSE must be connected to the voltage regulator feedback circuit, which insures
the output voltage (that is, processor voltage) remains within specification.
VTTD_SENSE and VSS_VTTD_SENSE provide an isolated, low impedance
VTTD_SENSE connection to the processor I/O power plane. These signals must be
VSS_VTTD_SENSE connected to the voltage regulator feedback circuit, which insures the output
voltage (that is, processor voltage) remains within specification.
Power supply for the processor system memory interface. Provided by two
VR12 compliant regulators or two non-VR12 voltage regulators (simple
switching VRs for example). VCCD_01 and VCCD_23 are used for memory
channels 0, 1 & 2, 3 respectively. VCCD_01 and VCCD_23 will also be
VCCD_01 and VCCD_23 referred to as VCCD. VCCD is generic for VCCD_01, VCCD_23.
Note: The processor must be provided VCCD_01 and VCCD_23 for proper
operation, even in configurations where no memory is populated. A
VR12.0 controller is recommended, but not required.
VCCPLL Fixed power supply (1.8 V) for the processor phased lock loop (PLL).
Variable power supply for the processor system agent units. These include
logic (non-I/O) for the integrated I/O controller, the integrated memory
VSA controller (iMC), and the Power Control Unit (PCU). The output voltage of this
supply is selected by the processor, using the serial voltage ID (SVID) bus.
Note: VSA has a Vboot setting of 0.9 V.
VSS Processor ground node.
VTTA Combined fixed analog and digital power supply for I/O sections of Direct
Media Interface Gen 2 (DMI2) interface and PCI Express* interface. Will also
VTTD be referred to as VTT.
Electrical Specifications
7 Electrical Specifications
7.1 Processor Signaling

The processor includes 2011 lands that use various signaling technologies. Signals are
grouped by electrical characteristics and buffer type into various signal groups. These
include DDR3 (Reference Clock, Command, Control, and Data), PCI Express*, DMI2,
Platform Environmental Control Interface (PECI), System Reference Clock, SMBus,
JTAG and Test Access Port (TAP), SVID Interface, Processor Asynchronous Sideband,
Miscellaneous, and Power/Other signals. Refer to Table 7-5 for details.
Intel strongly recommends performing analog simulations of all interfaces. Refer to

Section 1.7, “Related Documents” for signal integrity model availability.
7.1.1 System Memory Interface Signal Groups

The system memory interface uses DDR3 technology that consists of numerous signal
groups. These groups include – Reference Clocks, Command Signals, Control Signals,
and Data Signals. Each group consists of numerous signals that may use various
signaling technologies. Refer to Table 7-5 for further details. Throughout this chapter,
the system memory interface maybe referred to as DDR3.
7.1.2 PCI Express* Signals

The PCI Express Signal Group consists of PCI Express* ports 1, 2, and 3, and PCI
Express miscellaneous signals. Refer to Table 7-5 for further details.
7.1.3 DMI2/PCI Express* Signals

The Direct Media Interface (DMI2) Gen 2 sends and receives packets and/or commands
to the PCH. The DMI2 is an extension of the standard PCI Express Specification. The
DMI2/PCI Express Signals consist of DMI2 receive and transmit input/output signals
and a control signal. Refer to Table 7-5 for further details.
7.1.4 Platform Environmental Control Interface (PECI)

PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and chipset components to external system management logic and
thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS)
that reports a relative die temperature as an offset from Thermal Control Circuit (TCC)
activation temperature. Temperature sensors located throughout the die are
implemented as analog-to-digital converters calibrated at the factory. PECI provides an
interface for external devices to read processor temperature, perform processor
manageability functions, and manage processor interface tuning and diagnostics. Refer
to Section 2.4, “Platform Environment Control Interface (PECI)” for processor specific
implementation details for PECI. Refer to the processor Thermal Mechanical
Specification and Design Guide (see Section 1.7, “Related Documents”) for additional
details regarding PECI and for a list of supported PECI commands.
The PECI interface operates at a nominal voltage set by VTTD. The set of DC electrical
specifications shown in Table 7-13 is used with devices normally operating from a VTTD
interface supply.
7.1.4.1 Input Device Hysteresis

The PECI client and host input buffers must use a Schmitt-triggered input design for
improved noise immunity. Refer to Figure 7-1 and Table 7-13.
Figure 7-1. Input Device Hysteresis
7.1.5 System Reference Clocks (BCLK{0/1}_DP,

BCLK{0/1}_DN)
The processor core, processor uncore, PCI Express*, and DDR3 memory interface
frequencies are generated from BCLK{0/1}_DP and BCLK{0/1}_DN signals. The
processor maximum core frequency and DDR memory frequency are set during
manufacturing. It is possible to override the processor core frequency setting using
software. This permits operation at lower core frequencies than the factory set
maximum core frequency.
The processor core frequency is configured during reset by using values stored within
the device during manufacturing. The stored value sets the lowest core multiplier at
which the particular processor can operate. If higher speeds are desired, the
appropriate ratio can be configured using the IA32_PERF_CTL MSR (MSR 199h); Bits
15:0.
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK{0/1}_DP, BCLK{0/1}_DN input, with
exceptions for spread spectrum clocking. DC specifications for the BCLK{0/1}_DP,
BCLK{0/1}_DN inputs are provided in Table 7-14.
7.1.5.1 PLL Power Supply

An on-die PLL filter solution is implemented on the processor. Refer to Table 7-9 and
Table 7-10 for DC specifications.
7.1.6 JTAG and Test Access Port (TAP) Signals

Due to the voltage levels supported by other components in the JTAG and Test Access
Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Two copies of each signal may be
required with each driving a different voltage level.
7.1.7 Processor Sideband Signals

The processor includes asynchronous sideband signals that provide asynchronous
input, output or I/O signals between the processor and the platform or Platform
Controller Hub. Details can be found in Table 7-5.
All processor Asynchronous Sideband signals are required to be asserted/deasserted

for a defined number of BCLKs in order for the processor to recognize the proper signal
state. These are outlined in Table 7-18 (DC specifications).
7.1.8 Power, Ground and Sense Signals

Processors also include various other signals including power/ground and sense points.
Details can be found in Table 7-5.
7.1.8.1 Power and Ground Lands

All VCC, VCCPLL, VSA, VCCD, VTTA, and VTTD lands must be connected to their
respective processor power planes, while all VSS lands must be connected to the
system ground plane.
For clean on-chip power distribution, processors include lands for all required voltage
supplies. These are listed in Table 7-1.
Table 7-1. Power and Ground Lands

Power and
Comments
Ground Lands
Each VCC land must be supplied with the voltage determined by the SVID Bus signals.
VCC Table 7-3 defines the voltage level associated with each core SVID pattern.
Note: VCC has a VBOOT setting of 0.0 V.
Each VCCPLL land is connected to a 1.80 V supply, power the Phase Lock Loop (PLL) clock
VCCPLL
generation circuitry. An on-die PLL filter solution is implemented within the processor.
Each VCCD land is connected to a 1.50 V supply to provide power to the processor DDR3
VCCD_01 interface. These supplies also power the DDR3 memory subsystem. VCCD may be
VCCD_23 controlled by the SVID Bus using a VR12 controller and or a non-VR12 regulator may be
used. VCCD is the generic term for VCCD_01, VCCD_23.
VTTA VTTA lands must be supplied by a fixed 1.05 V supply.
VTTD VTTD lands must be supplied by a fixed 1.05 V supply.
Each VSA land must be supplied with the voltage determined by the SVID Bus signals,
VSA
typically set at 0.85 V. VSA has a VBOOT setting of 0.9 V.
VSS Ground
7.1.8.2 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings between low and full power states. This may
cause voltages on power planes to sag below their minimum values if bulk decoupling is
not adequate. Large electrolytic bulk capacitors (CBULK), help maintain the output
voltage during current transients; for example, coming out of an idle condition. Care
must be taken in the baseboard design to ensure that the voltages provided to the
processor remains within the specifications listed in Table 7-9. Failure to do so can
result in timing violations or reduced lifetime of the processor.
7.1.8.3 Voltage Identification (VID)

The Voltage Identification (VID) specification for the VCC, VSA, and optionally the VCCD
voltage are defined by the VR12/IMVP7 Pulse Width Modulation (PWM) Specification.
The reference voltage or the VID setting is set using the SVID communication bus
between the processor and the voltage regulator controller chip. The VID setting is the
nominal voltage to be delivered to the processor VCC, VSA, and the VCCD lands.
Table 7-3 specifies the reference voltage level corresponding to the VID value
transmitted over serial VID. The VID codes will change due to temperature and/or
current load changes to minimize the power and to maximize the performance of the
part. The specifications are set so that a voltage regulator can operate with all
supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two
processor units with the same core frequency may have different default VID settings.
The processor uses voltage identification signals to support automatic selection of VCC,
VSA, and if desired the VCCD power supply voltages. If the processor socket is empty
(SKTOCC_N high), or a “not supported” response is received from the SVID bus, then
the voltage regulation circuit cannot supply the voltage that is requested, the voltage
regulator must disable itself or not power on. Vout MAX register (30h) is programmed
by the processor to set the maximum supported VID code and if the programmed VID
code is higher than the VID supported by the VR, then VR will respond with a “not
supported” acknowledgement.
7.1.8.3.1 SVID Commands
The processor provides the ability to operate while transitioning to a new VID and its
associated processor core voltage. This is represented by a DC shift in the loadline. It
should be noted that a low-to-high or high-to-low voltage state change may result in as
many VID transitions as necessary to reach the target voltage. Transitions above the
maximum specified VID are not supported. The processor supports the following VR
commands:
• SetVID_fast (20 mV/μs for VCC, 10m V/μs for VCC/VSA/VCCD),
• SetVID_slow (5m V/μs for VCC, 2.5 mV/μs for VCC/VSA/VCCD), and
• Slew Rate Decay (downward voltage only and it’s a function of the output
capacitance’s time constant) commands. Table 7-3 and Table 7-17 includes SVID
step sizes and DC shift ranges. Minimum and maximum voltages must be
maintained as shown in Table 7-8.
The VR used must be capable of regulating its output to the value defined by the new
VID. Power source characteristics must be ensured to be stable whenever the supply to
the voltage regulator is stable.
7.1.8.3.2 SetVID Fast Command
The SetVID-fast command contains the target VID in the payload byte. The range of
voltage is defined in the VID table. The VR should ramp to the new VID setting with a
fast slew rate as defined in the slew rate data register; typically 10 to 20 mV/us
depending on platform, voltage rail, and the amount of decoupling capacitance.
The SetVID-fast command is preemptive, the VR interrupts its current processes and
moves to the new VID. The SetVID-fast command operates on 1 VR address at a time.
This command is used in the processor for package C6 fast exit and entry.
7.1.8.3.3 SetVID Slow
The SetVID-slow command contains the target VID in the payload byte. The range of
voltage is defined in the VID table. The VR should ramp to the new VID setting with a
“slow” slew rate as defined in the slow slew rate data register. The SetVID_Slow is 1/4
slower than the SetVID_fast slew rate.
The SetVID-slow command is preemptive, the VR interrupts its current processes and
moves to the new VID. This is the instruction used for normal P-state voltage change.
This command is used in the processor for the Intel Enhanced SpeedStep Technology
transitions.
7.1.8.3.4 SetVID Decay
The SetVID-Decay command is the slowest of the DVID transitions. It is only used for
VID down transitions. The VR does not control the slew rate, the output voltage
declines with the output load current only.
The SetVID-Decay command is preemptive; that is, the VR interrupts its current
processes and moves to the new VID.
7.1.8.3.5 SVID Power State Functions – SetPS
The processor has three power state functions and these will be set seamlessly using
the SVID bus using the SetPS command. Based on the power state command, the
SetPS commands sends information to VR controller to configure the VR to improve
efficiency, especially at light loads. For example, typical power states are:
• PS(00h): Represents full power or active mode

• PS(01h): Represents a light load 5 A to 20 A
• PS(02h): Represents a very light load <5 A
The VR may change its configuration to meet the processor’s power needs with greater
efficiency. For example, it may reduce the number of active phases, transition from
CCM (Continuous Conduction Mode) to DCM (Discontinuous Conduction Mode) mode,
reduce the switching frequency or pulse skip, or change to asynchronous regulation.
For example, typical power states are 00h = run in normal mode; a command of
01h = shed phases mode, and an 02h = pulse skip.
The VR may reduce the number of active phases from PS(00h) to PS(01h) or PS(02h)
for example. There are multiple VR design schemes that can be used to maintain a
greater efficiency in these different power states, please work with your VR controller
suppliers for optimizations.
The SetPS command sends a byte that is encoded as to what power state the VR
should transition to.
If a power state is not supported by the controller, the slave should acknowledge with
command rejected (11b)
If the VR is in a low power state and receives a SetVID command moving the VID up,
then the VR exits the low power state to normal mode (PS0) to move the voltage up as
fast as possible. The processor must re-issue low power state (PS1, PS2, or PS3)
command if it is in a low current condition at the new higher voltage. See Figure 7-2 for
VR power state transitions.
Figure 7-2. VR Power-State Transitions
7.1.8.3.6 SVID Voltage Rail Addressing
The processor addresses 4 different voltage rail control segments within VR12 (VCC,
VCCD_01, VCCD_23, and VSA). The SVID data packet contains a 4-bit addressing
code.
Table 7-2. SVID Address Usage

PWM Address (HEX) Processor
00 Vcc
01 Vsa
02 VCCD_01
03 +1 not used
04 VCCD_23
05 +1 not used
Notes:
1. Check with VR vendors for determining the physical address assignment method for their controllers.
2. VR addressing is assigned on a per voltage rail basis.
3. Dual VR controllers will have two addresses with the lowest order address, always being the higher phase
count.
4. For future platform flexibility, the VR controller should include an address offset, as shown with +1 not
used.
Table 7-3. Voltage Identification Definition

HEX Vcc HEX Vcc & Vsa HEX Vcc & Vsa HEX Vcc & Vsa HEX Vcc & Vsa HEX Vcc
00 0.00000 55 0.67000 78 0.84500 9B 1.02000 BE 1.19500 E1 1.37000
33 0.50000 56 0.67500 79 0.85000 9C 1.02500 BF 1.20000 E2 1.37500
34 0.50500 57 0.68000 7A 0.85500 9D 1.03000 C0 1.20500 E3 1.38000
35 0.51000 58 0.68500 7B 0.86000 9E 1.03500 C1 1.21000 E4 1.38500
36 0.51500 59 0.69000 7C 0.86500 9F 1.04000 C2 1.21500 E5 1.39000
37 0.52000 5A 0.69500 7D 0.87000 A0 1.04500 C3 1.22000 E6 1.39500
38 0.52500 5B 0.70000 7E 0.87500 A1 1.05000 C4 1.22500 E7 1.40000
39 0.53000 5C 0.70500 7F 0.88000 A2 1.05500 C5 1.23000 E8 1.40500
3A 0.53500 5D 0.71000 80 0.88500 A3 1.06000 C6 1.23500 E9 1.41000
3B 0.54000 5E 0.71500 81 0.89000 A4 1.06500 C7 1.24000 EA 1.41500
3C 0.54500 5F 0.72000 82 0.89500 A5 1.07000 C8 1.24500 EB 1.42000
3D 0.55000 60 0.72500 83 0.90000 A6 1.07500 C9 1.25000 EC 1.42500
3E 0.55500 61 0.73000 84 0.90500 A7 1.08000 CA 1.25500 ED 1.43000
3F 0.56000 62 0.73500 85 0.91000 A8 1.08500 CB 1.26000 EE 1.43500
40 0.56500 63 0.74000 86 0.91500 A9 1.09000 CC 1.26500 EF 1.44000
41 0.57000 64 0.74500 87 0.92000 AA 1.09500 CD 1.27000 F0 1.44500
42 0.57500 65 0.75000 88 0.92500 AB 1.10000 CE 1.27500 F1 1.45000
43 0.58000 66 0.75500 89 0.93000 AC 1.10500 CF 1.28000 F2 1.45500

44 0.58500 67 0.76000 8A 0.93500 AD 1.11000 D0 1.28500 F3 1.46000
45 0.59000 68 0.76500 8B 0.94000 AE 1.11500 D1 1.29000 F4 1.46500
46 0.59500 69 0.77000 8C 0.94500 AF 1.12000 D2 1.29500 F5 1.47000
47 0.60000 6A 0.77500 8D 0.95000 B0 1.12500 D3 1.30000 F6 1.47500
48 0.60500 6B 0.78000 8E 0.95500 B1 1.13000 D4 1.30500 F7 1.48000
49 0.61000 6C 0.78500 8F 0.96000 B2 1.13500 D5 1.31000 F8 1.48500
4A 0.61500 6D 0.79000 90 0.96500 B3 1.14000 D6 1.31500 F9 1.49000
4B 0.62000 6E 0.79500 91 0.97000 B4 1.14500 D7 1.32000 FA 1.49500
4C 0.62500 6F 0.80000 92 0.97500 B5 1.15000 D8 1.32500 FB 1.50000
4D 0.63000 70 0.80500 93 0.98000 B6 1.15500 D9 1.33000 FC 1.50500
4E 0.63500 71 0.81000 94 0.98500 B7 1.16000 DA 1.33500 FD 1.51000
4F 0.64000 72 0.81500 95 0.99000 B8 1.16500 DB 1.34000 FE 1.51500
50 0.64500 73 0.82000 96 0.99500 B9 1.17000 DC 1.34500 FF 1.52000

51 0.65000 74 0.82500 97 1.00000 BA 1.17500 DD 1.35000
52 0.65500 75 0.83000 98 1.00500 BB 1.18000 DE 1.35500
53 0.66000 76 0.83500 99 1.01000 BC 1.18500 DF 1.36000
54 0.66500 77 0.84000 9A 1.01500 BD 1.19000 E0 1.36500
Notes:
1. 00h = Off State
2. VID Range HEX 01–32 are not used by the processor.
3. For VID Ranges supported, see Table 7-9
4. VCCD is a fixed voltage of 1.5 V.
7.1.9 Reserved or Unused Signals

All Reserved (RSVD) signals must not be connected. Connection of these signals to VCC,
VTTA, VTTD, VCCD, VCCPLL, VSS, or to any other signal (including each other) can result in
component malfunction or incompatibility with future processors. See Chapter 8,
"Processor Land Listing," for a land listing of the processor and the location of all
Reserved signals.
For reliable operation, always connect unused inputs or bi-directional signals to an

appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (VSS). Unused outputs maybe left unconnected; however, this may
interfere with some Test Access Port (TAP) functions, complicate debug probing, and
prevent boundary scan testing. A resistor must be used when tying bi-directional
signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability.
7.2 Signal Group Summary

Signals are grouped by buffer type and similar characteristics as listed in Table 7-4. The
buffer type indicates which signaling technology and specifications apply to the signals.
Table 7-4. Signal Description Buffer Types

Signal Description
Analog reference or output. May be used as a threshold voltage or for buffer

Analog
compensation
Asynchronous1 Signal has no timing relationship with any system reference clock.
CMOS CMOS buffers: 1.05 V or 1.5 V tolerant
DDR3 DDR3 buffers: 1.5 V tolerant
Direct Media Interface Gen 2 signals. These signals are compatible with PCI Express*
DMI2
2.0 and 1.0 Signaling Environment AC Specifications.
Open Drain CMOS Open Drain CMOS (ODCMOS) buffers: 1.05 V tolerant
PCI Express* interface signals. These signals are compatible with PCI Express*
PCI Express* Signalling Environment AC Specifications and are AC coupled. The buffers are not
3.3-V tolerant. Refer to the PCIe specification.
Reference Voltage reference signal.
SSTL Source Series Terminated Logic. (JEDEC SSTL_15)
Note:
1. Qualifier for a buffer type.
Table 7-5. Signal Groups (Sheet 1 of 3)

Differential/Single
Buffer Type Signals1
Ended
DDR3 Reference Clocks2
Differential SSTL Output DDR{0/1/2/3}_CLK_D[N/P][3:0]
DDR3 Command Signals2
DDR{0/1/2/3}_BA[2:0]
DDR{0/1/2/3}_CAS_N
DDR{0/1/2/3}_MA[15:00]
SSTL Output
Single ended DDR{0/1/2/3}_MA_PAR
DDR{0/1/2/3}_RAS_N
DDR{0/1/2/3}_WE_N
CMOS1.5v Output DDR_RESET_C{01/23}_N
DDR3 Control Signals2
DDR{0/1/2/3}_CS_N[1:0]
DDR{0/1/2/3}_CS_N[5:4]
CMOS1.5v Output
DDR{0/1/2/3}_ODT[3:0]
DDR{0/1/2/3}_CKE[3:0]
Single ended
Reference Output DDR_VREFDQTX_C{01/23}
DDR_VREFDQRX_C{0/1/2/3}
Reference Input
DDR{01/23}_RCOMP[2:0]
DDR3 Data Signals2
Differential SSTL Input/Output DDR{0/1/2/3}_DQS_D[N/P][08:00]
DDR{0/1/2/3}_DQ[63:00]
Single ended SSTL Input/Output
DDR{0/1/2/3}_ECC[7:0]3
DDR3 Miscellaneous Signals2
Single ended CMOS1.5v Input DRAM_PWR_OK_C{0/1/2/3}
PCI Express* Port 1, 2, & 3 Signals
PE1A_RX_D[N/P][3:0]
PE1B_RX_D[N/P][7:4]
PE2A_RX_D[N/P][3:0]
PE2B_RX_D[N/P][7:4]
PE2C_RX_D[N/P][11:8]
Differential PCI Express* Input
PE2D_RX_D[N/P][15:12]
PE3A_RX_D[N/P][3:0]
PE3B_RX_D[N/P][7:4]
PE3C_RX_D[N/P][11:8]
PE3D_RX_D[N/P][15:12]
PE1A_TX_D[N/P][3:0]
PE1B_TX_D[N/P][7:4]
PE2A_TX_D[N/P][3:0]
PE2B_TX_D[N/P][7:4]
PE2C_TX_D[N/P][11:8]
Differential PCI Express* Output
PE2D_TX_D[N/P][15:12]
PE3A_TX_D[N/P][3:0]
PE3B_TX_D[N/P][7:4]
PE3C_TX_D[N/P][11:8]
PE3D_TX_D[N/P][15:12]

Differential/Single
Ended
PCI Express* Miscellaneous Signals
Analog Input PE_RBIAS_SENSE

Single ended PE_RBIAS
Reference Input/Output
PE_VREF_CAP
DMI2/PCI Express* Signals
DMI2 Input DMI_RX_D[N/P][3:0]

Differential
DMI2 Output DMI_TX_D[N/P][3:0]
Platform Environmental Control Interface (PECI)
Single ended PECI PECI
System Reference Clock (BCLK{0/1})
Differential CMOS1.05v Input BCLK{0/1}_D[N/P]
SMBus
Open Drain CMOS DDR_SCL_C{01/23}

Single ended
Input/Output DDR_SDA_C{01/23}
JTAG & TAP Signals
CMOS1.05v Input TCK, TDI, TMS, TRST_N
CMOS1.05v Input/Output PREQ_N
Open Drain CMOS BPM_N[7:0]

Single ended
Input/Output EAR_N
CMOS1.05v Output PRDY_N
Open Drain CMOS Output TDO
Serial VID Interface (SVID) Signals
CMOS1.05v Input SVIDALERT_N
Open Drain CMOS SVIDDATA

Single ended
Input/Output
Open Drain CMOS Output SVIDCLK
Processor Asynchronous Sideband Signals
PWRGOOD
CMOS1.05v Input PMSYNC
RESET_N
CAT_ERR_N
Single ended
Open Drain CMOS CPU_ONLY_RESET
Input/Output MEM_HOT_C{01/23}_N
PROCHOT_N
Open Drain CMOS Output THERMTRIP_N
BIST_ENABLE
Single ended CMOS1.05v Input
BCLK_SELECT[1:0]
PROC_SEL_N
N/A Output
SKTOCC_N
Analog Input CORE_RBIAS_SENSE

Single ended
Analog Input/Output CORE_RBIAS

Differential/Single
Ended
Power/Other Signals
VCC, VTTA, VTTD, VCCD_01, VCCD_23,VCCPLL, VSA

Power / Ground
and VSS
VCC_SENSE
VSS_VCC_SENSE
VSS_VTTD_SENSE
Sense Points
VTTD_SENSE
VSA_SENSE
VSS_VSA_SENSE
Notes:
1. Refer to Chapter 6, "Signal Descriptions," for signal description details.
2. DDR{0/1/2/3} refers to DDR3 Channel 0, DDR3 Channel 1, DDR3 Channel 2, and DDR3 Channel 3.
3. ECC DIMMs are not supported on the processor; thus, these signals are not used.
Table 7-6. Signals with On-Die Termination

Pull Up /Pull
Signal Name Rail Value Units Notes
Down
BCLK_SELECT[1:0] Pull up VTT 2K Ohm
BIST_ENABLE Pull Up VTT 2K Ohm
EAR_N Pull Up VTT 2K Ohm 1
Notes:
1. Refer to Table 7-16 for details on the RON (Buffer on Resistance) value for this signal.
7.3 Power-On Configuration (POC) Options

Several configuration options can be configured by hardware. The processor samples
its hardware configuration at reset, on the active-to-inactive transition of RESET_N, or
upon assertion of PWRGOOD (inactive-to-active transition). For specifics on these
options, refer to Table 7-7.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset transition of the
latching signal (RESET_N or PWRGOOD).
Table 7-7. Power-On Configuration Option Lands

Configuration Option Land Name Notes
BCLK input select BCLK_SELECT[1:0]
Execute BIST (Built-In Self Test) BIST_ENABLE 1
Power-up Sequence Halt for ITP configuration EAR_N 2
Notes:
1. BIST_ENABLE is sampled at RESET_N de-assertion.
2. This signal is sampled at PWRGOOD assertion.
7.4 Absolute Maximum and Minimum Ratings

Table 7-8 specifies absolute maximum and minimum ratings. At conditions outside
functional operation condition limits, but within absolute maximum and minimum
ratings, neither functionality nor long-term reliability can be expected. If a device is
returned to conditions within functional operation limits after having been subjected to
conditions outside these limits (but within the absolute maximum and minimum
ratings) the device may be functional, but with its lifetime degraded depending on
exposure to conditions exceeding the functional operation condition limits.
Although the processor contains protective circuitry to resist damage from Electro-
Static Discharge (ESD), precautions should always be taken to avoid high static
voltages or electric fields.
Table 7-8. Processor Absolute Minimum and Maximum Ratings

Symbol Parameter Min Max Unit Notes
VCC Processor core voltage with respect to Vss -0.3 1.4 V 1
VCCPLL Processor PLL voltage with respect to Vss -0.3 2.0 V 1
Processor I/O supply voltage for DDR3 with

VCCD -0.3 1.85 V 1
respect to Vss
VSA Processor SA voltage with respect to Vss -0.3 1.4 V 1
VTTA Processor analog I/O voltage with respect to Vss

-0.3 1.4 V 1
VTTD
Notes:
1. For functional operation, all processor electrical, signal quality, mechanical, and thermal specifications must
be satisfied.
7.4.1 Storage Conditions Specifications

Environmental storage condition limits define the temperature and relative humidity
limits to which the device is exposed to while being stored in a Moisture Barrier Bag.
The storage condition specifications are included in the processor Thermal Mechanical
Specification and Design Guide (see Section 1.7, “Related Documents”).
7.5 DC Specifications
DC specifications are defined at the processor pads, unless otherwise noted.
DC specifications are only valid while meeting the thermal specifications as specified in
the processor Thermal Mechanical Specification and Design Guide (see Section 1.7,
“Related Documents”), clock frequency, and input voltages. Care should be taken to
read all notes associated with each specification.
7.5.1 Voltage and Current Specifications
Table 7-9. Voltage Specification

Voltage
Symbol Parameter Min Typ Max Unit Notes1
Plane
VCCVID VCC VID Range - 0.6 1.35 V 2, 3, 18
VCCLL VCC Loadline Slope 3, 4, 7, 8,

VCC 0.8 m 12, 17
VCC Tolerance Band 3, 4, 7, 8,

VCCTOB VCC 15 mV 12, 17
VCC Ripple 3, 4, 7, 8,
VCCRipple Vcc 5 mV 12, 17
VCCPLL PLL Voltage VCCPLL 0.955*VCCPLL_TYP 1.8 1.045*VCCPLL_TYP V 10, 11
VCCD I/O Voltage for DDR3

(VCCD_01, VCCD 0.95*VCCD_TYP 1.5 1.05*VCCD_TYP V 11, 14, 15
VCCD_23)
VTT (VTTA, VTT Uncore Voltage 3, 5, 9,

VTT 0.957*VTT_TYP 1.05 1.043*VTT_TYP V
VTTD) 11
VSA VID Range 2, 3, 13,

VSA_VID VSA 0.6 0.965 1.20 V 18
VSA Tolerance Band

3, 6, 16,
VSATOB (DC+AC+Ripple+Gro VSA 64 mV 18
und Noise)
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are
based on pre-silicon characterization and will be updated as further data becomes available.
2. Individual processor VID values may be calibrated during manufacturing such that two devices at the same
speed may have different settings.
3. These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required.
4. The VCC voltage specification requirements are measured across the remote sense pin pairs (VCC_SENSE
and VSS_VCC_SENSE) on the processor package. Voltage measurement should be taken with a DC to
100 MHz bandwidth oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using a 1.5 pF
maximum probe capacitance, and 1 M  minimum impedance. The maximum length of the ground wire on
the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope
probe.
5. The VTTA, and VTTD voltage specification requirements are measured across the remote sense pin pairs
(VTTD_SENSE and VSS_VTTD_SENSE) on the processor package. Voltage measurement should be taken
with a DC to 100 MHz bandwidth oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using a
1.5 pF maximum probe capacitance, and 1 M  minimum impedance. The maximum length of the ground
wire on the probe should be less than 5 mm to ensure external noise from the system is not coupled in the
scope probe.
6. The VSA voltage specification requirements are measured across the remote sense pin pairs (VSA_SENSE
and VSS_VSA_SENSE) on the processor package. Voltage measurement should be taken with a DC to
100 MHz bandwidth oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using a 1.5 pF
maximum probe capacitance, and 1 M  minimum impedance. The maximum length of the ground wire on
the probe should be less than 5 mm to ensure external noise from the system is not coupled in the scope
probe.
7. The processor should not be subjected to any static VCC level that exceeds the VCC_MAX associated with any
particular current. Failure to adhere to this specification can shorten processor lifetime.
8. Minimum VCC and maximum ICC are specified at the maximum processor temperature. Refer to the
Thermal Mechanical Specification and Design Guide (see Section 1.7, “Related Documents”) for thermal
specifications. ICC_MAX is specified at the relative VCC_MAX point on the VCC load line. The processor is
capable of drawing ICC_MAX for up to 10 ms.
9. The processor should not be subjected to any static VTTA, VTTD level that exceeds the VTT_MAX associated
with any particular current. Failure to adhere to this specification can shorten processor lifetime.
10. Baseboard bandwidth is limited to 20 MHz.
11. DC + AC + Ripple specification.
12. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage
regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and
VSS_SENSE lands.
13. VSA_VID does not have a loadline, the output voltage is expected to be the VID value.
14. VCCD tolerance at processor pins. Tolerance for VR at remote sense is ±3.3%*VCCD.
15. The VCCPLL, VCCD01, VCCD23 voltage specification requirements are measured across vias on the platform.
Choose VCCPLL, VCCD01, or VCCD23 vias close to the socket and measure with a DC to 100 MHz bandwidth
oscilloscope limit (or DC to 20 MHz for older model oscilloscopes), using 1.5 pF maximum probe
capacitance, and 1 M minimum impedance. The maximum length of the ground wire on the probe should
be less than 5 mm to ensure external noise from the system is not coupled in the scope probe.
16. DC + AC + Ripple + Ground Noise specification.
17. VCC has a Vboot setting of 0.0 V and is not included in the PWRGOOD indication.
18. VSA has a Vboot setting of 0.9 V.
Table 7-10. Current (Icc_Max and Icc_TDC) Specification

4-Core 6-Core
Symbol Parameter Voltage Plane Unit Notes1
Max Max
ICC_MAX
Max. Processor Current: VCC 150 165 A

ICC_MAX
ITT_MAX (TDP - 130W) VTTA/VTTD 24 24 A
ISA_MAX VSA 24 24 A
4, 5
ICCD_01_MAX VCCD_01 4 4 A
ICCD_23_MAX VCCD_23 4 4 A
ICCPLL_MAX VCCPLL 2 2 A
ICC_TDC
Thermal Design Current: VCC 115 135 A

ICC_TDC
ITT_TDC (TDP - 130 W) VTTA/VTTD 20 20 A
ISA_TDC VSA 20 20 A
2, 5
ICCD_01_TDC VCCD_01 3 3 A
ICCD_23_TDC VCCD_23 3 3 A
ICCPLL_TDC VCCPLL 2 2 A
DDR3 System Memory VCCD_01 TBD TBD A
ICCD_S3 Interface Supply Current in VCCD_23 3, 4
Standby State
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are
based on pre-silicon characterization and will be updated as further data becomes available.
2. ICC_TDC (Thermal Design Current) is the sustained (DC equivalent) current that the processor is capable of
drawing indefinitely and should be used for the voltage regulator thermal assessment. The voltage
regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the
processor of a thermal excursion.
3. Specification is at TCASE = 50 °C. Characterized by design (not tested).
4. ICCD_01_MAX and ICCD_23_MAX refers only to the processor’s current draw and does not account for the
current consumption by the memory devices.
5. Minimum VCC and maximum ICC are specified at the maximum processor temperature. Refer to the
processor Thermal Mechanical Specification and Design Guide (see Section 1.7, “Related Documents”) for
thermal specifications. ICC_MAX is specified at the relative VCC_MAX point on the VCC load line. The
processor is capable of drawing ICC_MAX for up to 10 ms.
7.5.2 Die Voltage Validation

Core voltage (VCC) overshoot events at the processor must meet the specifications in
Table 7-11 when measured across the VCC_SENSE and VSS_VCC_SENSE lands.
Overshoot events that are < 10 ns in duration may be ignored. These measurements of
processor die level overshoot should be taken with a 100 MHz bandwidth limited
oscilloscope.
7.5.2.1 VCC Overshoot Specifications

The processor can tolerate short transient overshoot events where VCC exceeds the VID
voltage when transitioning from a high-to-low current load condition. This overshoot
cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot above
VID). These specifications apply to the processor die voltage as measured across the
VCC_SENSE and VSS_VCC_SENSE lands.
Table 7-11. VCC Overshoot Specifications

Symbol Parameter Min Max Units Figure Notes
VOS_MAX Magnitude of VCC overshoot above VID — 65 mV 7-3
Time duration of VCC overshoot above

TOS_MAX — 25 ms 7-3
VccMAX value at the new lighter load
Figure 7-3. VCC Overshoot Example Waveform
Notes:
1. VOS is the measured overshoot voltage.
2. TOS_MAX is the measured time duration above VccMAX(I1).
3. Istep: Load Release Current Step, for example, I2 to I1, where I2 > I1.
4. VccMAX(I1) = VID - I1*RLL + 15 mV
7.5.3 Signal DC Specifications

DC specifications are defined at the processor pads, unless otherwise noted. DC
specifications are only valid while meeting specifications for case temperature (TCASE
specified in the processor Thermal Mechanical Specification and Design Guide; see
Section 1.7, “Related Documents”), clock frequency, and input voltages. Care should be
taken to read all notes associated with each specification.
Table 7-12. DDR3 Signal DC Specifications

Symbol Parameter Min Typ Max Units Notes1
IIL Input Leakage Current -500 — +500 uA 10
Data Signals
VIL Input Low Voltage — — 0.43*VCCD V 2, 3

VIH Input High Voltage 0.57*VCCD — V 2, 4, 5
DDR3 Data Buffer On
RON 21 — 31  6
Resistance
On-Die Termination for Data 45 55
Data ODT —  8
Signals 90 110
Reference Clock Signals, Command, and Data Signals
VOL Output Low Voltage (VCCD/ 2)* (RON

— — V 2, 7
/(RON+RVTT_TERM))
Output High Voltage VCCD – ((VCCD/ 2)*
VOH — (RON/(RON+RVTT_TERM)) — V 2, 5, 7
Reference Clock Signal
DDR3 Clock Buffer On

RON 21 — 31  6
Resistance
Command Signals
DDR3 Command Buffer On
RON 16 — 24  6
Resistance
DDR3 Reset Buffer On
RON 25 — 75  6
Resistance
Output Low Voltage, Signals
VOL_CMOS1.5v — — 0.2*VCCD V 1, 2
DDR_RESET_ C{01/23}_N
Output High Voltage, Signals
VOH_CMOS1.5v 0.9*VCCD — — V 1, 2
DDR_RESET_ C{01/23}_N
IIL_CMOS1.5v Input Leakage Current -100 — +100 uA 1, 2
Control Signals
DDR3 Control Buffer On

RON 21 — 31  6
Resistance
DDR01_RCOMP[0] COMP Resistance 128.7 130 131.3  9, 12
DDR01_RCOMP[1] COMP Resistance 25.839 26.1 26.361  9, 12
DDR01_RCOMP[2] COMP Resistance 198 200 202  9, 12
DDR23_RCOMP[0] COMP Resistance 128.7 130 131.3  9, 12
DDR23_RCOMP[1] COMP Resistance 25.839 26.1 26.361  9, 12
DDR23_RCOMP[2] COMP Resistance 198 200 202  9, 12
Input Low Voltage 0.55*VCCD 2, 3, 11,
VIL DRAM_PWR_OK_C{01/23} — — V 13
– 0.2
Input High Voltage 0.55*VCCD 2, 4, 5,
VIH — — V
DRAM_PWR_OK_C{01/23} +0.2 11, 13
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The voltage rail VCCD will be set to 1.50 V nominal.
3. VIL is the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
4. VIH is the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
5. VIH and VOH may experience excursions above VCCD.
6. This is the pull-down driver resistance. Reset drive does not have a termination.
7. RVTT_TERM is the termination on the DIMM and not controlled by the processor. Refer to the applicable DIMM
datasheet.
8. The minimum and maximum values for these signals are programmable by BIOS to one of the pairs.
9. COMP resistance must be provided on the system board with 1% resistors.
10. Input leakage current is specified for all DDR3 signals.
11. DRAM_PWR_OK_C{01/23} must have a maximum of 30 ns rise or fall time over VCCD * 0.55 + 300 mV
and -200 mV and the edge must be monotonic.
12. The DDR01/23_RCOMP error tolerance is ±5% from the compensated value.
13. DRAM_PWR_OK_C{01/23}: Data Scrambling should be enabled for production environments. Disabling
Data scrambling can be used for debug and testing purposes only. Running systems with Data Scrambling
off will make the configuration out of specification. For details, refer to Volume 2 of the Datasheet.
Table 7-13. PECI DC Specifications

Symbol Definition and Conditions Min Max Units Figure Notes1
VIn Input Voltage Range -0.150 VTTD V
VHysteresis Hysteresis 0.100 * VTTD — V
VN Negative-edge threshold voltage 0.275 * VTTD 0.500 * VTTD V 7-1 2
VP Positive-edge threshold voltage 0.550 * VTTD 0.725 * VTTD V 7-1 2
High level output source

ISOURCE -6.0 — mA
VOH = 0.75 * VTT
High impedance state leakage to
ILeak+ N/A 50 μA 3
VTTD (Vleak = VOL)
High impedance leakage to GND
ILeak- N/A 25 μA 3
(Vleak = VOH)
CBus Bus capacitance per node N/A 10 pF 4,5
Signal noise immunity above

VNoise 0.100 * VTTD N/A Vp-p
300 MHz
Notes:
1. VTTD supplies the PECI interface. PECI behavior does not affect VTTD min/max specification
2. It is expected that the PECI driver will take into account, the variance in the receiver input thresholds and
consequently, be able to drive its output within safe limits (-0.150 V to 0.275*VTTD for the low level and
0.725*VTTD to VTTD+0.150 V for the high level).
3. The leakage specification applies to powered devices on the PECI bus.
4. One node is counted for each client and one node for the system host. Extended trace lengths might appear
as additional nodes.
5. Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and consequently
limit the maximum bit rate at which the interface can operate.
Table 7-14. System Reference Clock (BCLK{0/1}) DC Specifications
Symbol Parameter Signal Min Max Unit Figure Notes1
Differential Input High

VBCLK_diff_ih Differential 0.150 N/A V
Voltage
Differential Input Low
VBCLK_diff_il Differential — -0.150 V
Voltage
Absolute Crossing Point Single
Vcross (abs) Ended 0.250 0.550 V 2, 4, 7
Relative Crossing Point 0.250 + 0.550 +

Vcross(rel) Single 0.5*(VHavg 0.5*(VHavg V 3, 4, 5
Ended – 0.700) – 0.700)
Vcross Range of Crossing

Points
Single
Ended N/A 0.140 V 6
Threshold Voltage Single Vcross +

VTH Ended Vcross – 0.1 0.1 V
IIL Input Leakage Current N/A — 1.50 A 8
Cpad Pad Capacitance N/A 0.9 1.1 pF
Notes:
2. Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK{0/1}_DN is
equal to the falling edge of BCLK{0/1}_DP.
3. VHavg is the statistical average of the VH measured by the oscilloscope.
4. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
5. VHavg can be measured directly using “Vtop” on Agilent* and “High” on Tektronix oscilloscopes.
6. VCROSS is defined as the total variation of all crossing voltages as defined in Note 3.
7. The rising edge of BCLK{0/1}_DN is equal to the falling edge of BCLK{0/1}_DP.
8. For Vin between 0 and Vih.
Table 7-15. SMBus DC Specifications

Symbol Parameter Min Max Units Notes
VIL Input Low Voltage — 0.3*VTT V
VIH Input High Voltage 0.7*VTT — V
VOL Output Low Voltage — 0.2*VTT V
VOH Output High Voltage — VTT(max) V
RON Buffer On Resistance — 14 
Leakage Current, Signals DDR_SCL_C{01/23},

IL -100 +100 A
DDR_SDA_C{01/23}
Table 7-16. JTAG and TAP Signals DC Specifications

VIL Input Low Voltage — 0.3*VTT V
VIH Input High Voltage 0.7*VTT — V
Output Low Voltage

VOL — 0.12*VTT V
(RTEST = 500 ohm)
Output High Voltage
VOH 0.88*VTT — V
(RTEST = 500 ohm)
Buffer On Resistance Signals BPM[7:0], TDO,
RON — 14 
EAR_N
Input Leakage Current, Signals PREQ_N, TCK,
IIL -50 +50 A
TDI, TMS, TRST_N
Input Leakage Current, Signals BPM_N[7:0], TDO,
IIL EAR_N — +900 A
(RTEST = 50 ohm)
Output Current, Signal PRDY_N
IO -1.50 +1.50 mA
(RTEST = 500 ohm)
Input Edge Rate
Signals: BPM_N[7:0], EAR_N, PREQ_N, TCK, TDI, 0.05 — V/ns 1
TMS, TRST_N
Notes:
1. These are measured between VIL and VIH.
Table 7-17. Serial VID Interface (SVID) DC Specifications

Symbol Parameter Min Typ Max Units Notes
VTT CPU I/O Voltage VTT - 3% 1.05 VTT + 3% V
Input Low Voltage SVIDDATA,

VIL — — 0.3*VTT V 1
SVIDALERT_N
Input High Voltage SVIDDATA,
VIH 0.7*VTT — — V 1
SVIDALERT_N
Output High Voltage SVIDCLK,
VOH — — VTT(max) V 1
SVIDDATA
Buffer On Resistance SVIDCLK,
RON — 14  2
SVIDDATA
Input Leakage Current, Signals
IIL — — +900 A 3
SVIDCLK, SVIDDATA
Input Leakage Current, Signal
IIL -500 — +500 A 3
SVIDALERT_N
Notes:
1. VTT refers to instantaneous VTT.
2. Measured at 0.31*VTT
3. Vin between 0 V and VTT
Table 7-18. Processor Asynchronous Sideband DC Specifications

Input Edge Rate

Signals: CAT_ERR_N,
0.05 — V/ns 5
MEM_HOT_C{01/23}_N, PMSYNC,
PROCHOT_N, PWRGOOD, RESET_N
CMOS1.05 V Signals
VIL_CMOS1.05v Input Low Voltage — 0.3*VTT V 1,2
VIH_CMOS1.05v Input High Voltage 0.7*VTT V 1,2
Input Low Voltage

VIL_MAX — 0.320 V 1,2,4
Signal PWRGOOD
Input High Voltage
VIH_MIN 0.640 — V 1,2,4
Signal PWRGOOD
VOL_CMOS1.05v Output Low Voltage — 0.12*VTT V 1,2
VOH_CMOS1.05v Output High Voltage 0.88*VTT — V 1,2
IIL_CMOS1.05v Input Leakage Current -50 +50 A 1,2
Output Current
IO_CMOS1.05v -1.50 +1.50 mA 1,2
(RTEST = 500 ohm)
Non-Monotonicity Amplitude, Rising Edge
ANM_Rise — 0.135 V 4
Signal PWRGOOD
Non-Monotonicity Amplitude, Falling Edge
ANM_Fall — 0.165 V 4
Signal PWRGOOD
Open Drain CMOS (ODCMOS) Signals
VIL_ODCMOS Input Low Voltage — 0.3*VTT V 1,2
VIH_ODCMOS Input High Voltage 0.7*VTT — V 1,2
Output High Voltage, Signals CAT_ERR_N,

VOH_ODCMOS ERROR_N[2:0], THERMTRIP_N, — VTT(max) V 1,2
PROCHOT_N, CPU_ONLY_RESET
Output Leakage Current,
IOL -100 +100 A 3
Signal: MEM_HOT_C{01/23}_N
Output Leakage Current
IOL — +900 A 3
(RTEST = 50 ohm)
Buffer On Resistance, Signals: CAT_ERR_N,
CPU_ONLY_RESET, ERROR_N[2:0],
RON MEM_HOT_C{01/23}_N, — 14  1,2
PROCHOT_N, THERMTRIP_N
Note:
1. This table applies to the miscellaneous signals specified in Table 7-5.
3. For Vin between 0 and VOH.
4. PWRGOOD Non Monotonicity duration (TNM) time is maximum 1.3 ns.
5. These are measured between VIL and VIH and the edge must be monotonic.
Table 7-19. Miscellaneous Signals DC Specifications

Symbol Parameter Min Typical Max Units Notes
PROC_SEL_N Signal
VO_ABS_MAX Output Absolute Max Voltage — 1.10 1.80 V 1
IO Output Current — — 0 A 1
SKTOCC_N Signal
VO_ABS_MAX Output Absolute Max Voltage — 3.30 3.50 V
IOMAX Output Max Current — — 1 mA
Notes:
1. 10 kpull-up and 4 kpull-down to a voltage divider from +3.3 V.
7.5.3.1 PCI Express* DC Specifications

The DC specifications for the PCI Express* are available in the PCI Express* Base
Specification. This document will provide only the processor exceptions to the PCI
Express* Base Specification.
7.5.3.2 DMI2/PCI Express* DC Specifications

The DC specifications for the DMI2/PCI Express* are available in the PCI Express® Base
Specification 2.0 and 1.0. This document will provide only the processor exceptions to
the PCI Express® Base Specification 2.0 and 1.0.
7.5.3.3 Reset and Miscellaneous Signal DC Specifications

For a power-on Reset, RESET_N must stay active for at least 3.5 milliseconds after VCC
and BCLK have reached their proper specifications. RESET_N must not be kept asserted
for more than 100 ms while PWRGOOD is asserted. RESET_N must be held asserted for
at least 3.5 milliseconds before it is deasserted again. RESET_N must be held asserted
before PWRGOOD is asserted. This signal does not have on-die termination and must
be terminated on the system board.
Processor Land Listing
8 Processor Land Listing
This chapter provides sorted land list. Table 8-1 is a listing of all processor lands ordered
alphabetically by land name. Table 8-2 is a listing of all processor lands ordered by land number.
Table 8-1. Land Name (Sheet 1 of 45) Table 8-1. Land Name (Sheet 2 of 45)
Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction
BCLK_SELECT[0] BD48 CMOS I DDR0_CLK_DP[3] CH22 SSTL O
BCLK_SELECT[1] AJ55 CMOS I DDR0_CS_N[0] CN25 SSTL O
BCLK0_DN CM44 CMOS I DDR0_CS_N[1] CH26 SSTL O
BCLK0_DP CN43 CMOS I DDR0_CS_N[4] CG27 SSTL O
BCLK1_DN BA45 CMOS I DDR0_CS_N[5] CF26 SSTL O
BCLK1_DP AW45 CMOS I DDR0_DQ[00] CC7 SSTL I/O
BIST_ENABLE AT48 CMOS I DDR0_DQ[01] CD8 SSTL I/O
BPM_N[0] AR43 ODCMOS I/O DDR0_DQ[02] CK8 SSTL I/O
BPM_N[1] AT44 ODCMOS I/O DDR0_DQ[03] CL9 SSTL I/O
BPM_N[2] AU43 ODCMOS I/O DDR0_DQ[04] BY6 SSTL I/O
BPM_N[3] AV44 ODCMOS I/O DDR0_DQ[05] CA7 SSTL I/O
BPM_N[4] BB44 ODCMOS I/O DDR0_DQ[06] CJ7 SSTL I/O
BPM_N[5] AW43 ODCMOS I/O DDR0_DQ[07] CL7 SSTL I/O
BPM_N[6] BA43 ODCMOS I/O DDR0_DQ[08] CB2 SSTL I/O
BPM_N[7] AY44 ODCMOS I/O DDR0_DQ[09] CB4 SSTL I/O
CAT_ERR_N CC51 ODCMOS I/O DDR0_DQ[10] CH4 SSTL I/O
CORE_RBIAS CE53 Analog I/O DDR0_DQ[11] CJ5 SSTL I/O
CORE_RBIAS_SENSE CC53 Analog I DDR0_DQ[12] CA1 SSTL I/O
CORE_VREF_CAP CU51 I/O DDR0_DQ[13] CA3 SSTL I/O
CPU_ONLY_RESET AN43 ODCMOS I/O DDR0_DQ[14] CG3 SSTL I/O
DDR_RESET_C01_N CB18 CMOS1.5v O DDR0_DQ[15] CG5 SSTL I/O
DDR_RESET_C23_N AE27 CMOS1.5v O DDR0_DQ[16] CK12 SSTL I/O
DDR_SCL_C01 CY42 ODCMOS I/O DDR0_DQ[17] CM12 SSTL I/O
DDR_SCL_C23 U43 ODCMOS I/O DDR0_DQ[18] CK16 SSTL I/O
DDR_SDA_C01 CW41 ODCMOS I/O DDR0_DQ[19] CM16 SSTL I/O
DDR_SDA_C23 R43 ODCMOS I/O DDR0_DQ[20] CG13 SSTL I/O
DDR_VREFDQRX_C01 BY16 DC I DDR0_DQ[21] CL11 SSTL I/O
DDR_VREFDQRX_C23 J1 DC I DDR0_DQ[22] CJ15 SSTL I/O
DDR_VREFDQTX_C01 CN41 DC O DDR0_DQ[23] CL15 SSTL I/O
DDR_VREFDQTX_C23 P42 DC O DDR0_DQ[24] BY10 SSTL I/O
DDR0_BA[0] CM28 SSTL O DDR0_DQ[25] BY12 SSTL I/O
DDR0_BA[1] CN27 SSTL O DDR0_DQ[26] CB12 SSTL I/O
DDR0_BA[2] CM20 SSTL O DDR0_DQ[27] CD12 SSTL I/O
DDR0_CAS_N CL29 SSTL O DDR0_DQ[28] BW9 SSTL I/O
DDR0_CKE[0] CL19 SSTL O DDR0_DQ[29] CA9 SSTL I/O
DDR0_CKE[1] CM18 SSTL O DDR0_DQ[30] CH10 SSTL I/O
DDR0_CKE[2] CH20 SSTL O DDR0_DQ[31] CF10 SSTL I/O
DDR0_CKE[3] CP18 SSTL O DDR0_DQ[32] CE31 SSTL I/O
DDR0_CLK_DN[0] CF24 SSTL O DDR0_DQ[33] CC31 SSTL I/O
DDR0_CLK_DN[1] CE23 SSTL O DDR0_DQ[34] CE35 SSTL I/O
DDR0_CLK_DN[2] CE21 SSTL O DDR0_DQ[35] CC35 SSTL I/O
DDR0_CLK_DN[3] CF22 SSTL O DDR0_DQ[36] CD30 SSTL I/O
DDR0_CLK_DP[0] CH24 SSTL O DDR0_DQ[37] CB30 SSTL I/O
DDR0_CLK_DP[1] CG23 SSTL O DDR0_DQ[38] CD34 SSTL I/O
DDR0_CLK_DP[2] CG21 SSTL O DDR0_DQ[39] CB34 SSTL I/O
DDR0_DQ[40] CL31 SSTL I/O DDR0_ECC[3] CF18 SSTL I/O

DDR0_DQ[41] CJ31 SSTL I/O DDR0_ECC[4] CB14 SSTL I/O
DDR0_DQ[42] CL35 SSTL I/O DDR0_ECC[5] CD14 SSTL I/O
DDR0_DQ[43] CJ35 SSTL I/O DDR0_ECC[6] CG17 SSTL I/O
DDR0_DQ[44] CK30 SSTL I/O DDR0_ECC[7] CK18 SSTL I/O
DDR0_DQ[45] CH30 SSTL I/O DDR0_MA[00] CL25 SSTL O
DDR0_DQ[46] CK34 SSTL I/O DDR0_MA[01] CR25 SSTL O
DDR0_DQ[47] CH34 SSTL I/O DDR0_MA[02] CG25 SSTL O
DDR0_DQ[48] CB38 SSTL I/O DDR0_MA[03] CK24 SSTL O
DDR0_DQ[49] CD38 SSTL I/O DDR0_MA[04] CM24 SSTL O
DDR0_DQ[50] CE41 SSTL I/O DDR0_MA[05] CL23 SSTL O
DDR0_DQ[51] CD42 SSTL I/O DDR0_MA[06] CN23 SSTL O
DDR0_DQ[52] CC37 SSTL I/O DDR0_MA[07] CM22 SSTL O
DDR0_DQ[53] CE37 SSTL I/O DDR0_MA[08] CK22 SSTL O
DDR0_DQ[54] CC41 SSTL I/O DDR0_MA[09] CN21 SSTL O
DDR0_DQ[55] CB42 SSTL I/O DDR0_MA[10] CK26 SSTL O
DDR0_DQ[56] CH38 SSTL I/O DDR0_MA[11] CL21 SSTL O
DDR0_DQ[57] CK38 SSTL I/O DDR0_MA[12] CK20 SSTL O
DDR0_DQ[58] CH42 SSTL I/O DDR0_MA[13] CG29 SSTL O
DDR0_DQ[59] CK42 SSTL I/O DDR0_MA[14] CG19 SSTL O
DDR0_DQ[60] CJ37 SSTL I/O DDR0_MA[15] CN19 SSTL O
DDR0_DQ[61] CL37 SSTL I/O DDR0_ODT[0] CE25 SSTL O
DDR0_DQ[62] CJ41 SSTL I/O DDR0_ODT[1] CE27 SSTL O
DDR0_DQ[63] CL41 SSTL I/O DDR0_ODT[2] CH28 SSTL O
DDR0_DQS_DN[00] CG7 SSTL I/O DDR0_ODT[3] CF28 SSTL O
DDR0_DQS_DN[01] CE3 SSTL I/O DDR0_RAS_N CE29 SSTL O
DDR0_DQS_DN[02] CH14 SSTL I/O DDR0_WE_N CN29 SSTL O
DDR0_DQS_DN[03] CD10 SSTL I/O DDR01_RCOMP[0] CA17 Analog I
DDR0_DQS_DN[04] CE33 SSTL I/O DDR01_RCOMP[1] CC19 Analog I
DDR0_DQS_DN[05] CL33 SSTL I/O DDR01_RCOMP[2] CB20 Analog I
DDR0_DQS_DN[06] CB40 SSTL I/O DDR1_BA[0] DB26 SSTL O
DDR0_DQS_DN[07] CH40 SSTL I/O DDR1_BA[1] DC25 SSTL O
DDR0_DQS_DN[08] CE17 SSTL I/O DDR1_BA[2] DF18 SSTL O
DDR0_DQS_DP[00] CH8 SSTL I/O DDR1_CAS_N CY30 SSTL O
DDR0_DQS_DP[01] CF4 SSTL I/O DDR1_CKE[0] CT20 SSTL O
DDR0_DQS_DP[02] CK14 SSTL I/O DDR1_CKE[1] CU19 SSTL O
DDR0_DQS_DP[03] CE11 SSTL I/O DDR1_CKE[2] CY18 SSTL O
DDR0_DQS_DP[04] CC33 SSTL I/O DDR1_CKE[3] DA17 SSTL O
DDR0_DQS_DP[05] CJ33 SSTL I/O DDR1_CLK_DN[0] CV20 SSTL O
DDR0_DQS_DP[06] CD40 SSTL I/O DDR1_CLK_DN[1] CV22 SSTL O
DDR0_DQS_DP[07] CK40 SSTL I/O DDR1_CLK_DN[2] CY24 SSTL O
DDR0_DQS_DP[08] CC17 SSTL I/O DDR1_CLK_DN[3] DA21 SSTL O
DDR0_ECC[0] CE15 SSTL I/O DDR1_CLK_DP[0] CY20 SSTL O
DDR0_ECC[1] CC15 SSTL I/O DDR1_CLK_DP[1] CY22 SSTL O
DDR0_ECC[2] CH18 SSTL I/O DDR1_CLK_DP[2] CV24 SSTL O
DDR1_CLK_DP[3] DC21 SSTL O DDR1_DQ[40] DA33 SSTL I/O

DDR1_CS_N[0] DB24 SSTL O DDR1_DQ[41] DD32 SSTL I/O
DDR1_CS_N[1] CU23 SSTL O DDR1_DQ[42] DC35 SSTL I/O
DDR1_CS_N[4] CU25 SSTL O DDR1_DQ[43] DA35 SSTL I/O
DDR1_CS_N[5] CT24 SSTL O DDR1_DQ[44] DA31 SSTL I/O
DDR1_DQ[00] CP4 SSTL I/O DDR1_DQ[45] CY32 SSTL I/O
DDR1_DQ[01] CP2 SSTL I/O DDR1_DQ[46] DF34 SSTL I/O
DDR1_DQ[02] CV4 SSTL I/O DDR1_DQ[47] DE35 SSTL I/O
DDR1_DQ[03] CY4 SSTL I/O DDR1_DQ[48] CR37 SSTL I/O
DDR1_DQ[04] CM4 SSTL I/O DDR1_DQ[49] CU37 SSTL I/O
DDR1_DQ[05] CL3 SSTL I/O DDR1_DQ[50] CR41 SSTL I/O
DDR1_DQ[06] CV2 SSTL I/O DDR1_DQ[51] CU41 SSTL I/O
DDR1_DQ[07] CW3 SSTL I/O DDR1_DQ[52] CT36 SSTL I/O
DDR1_DQ[08] DA7 SSTL I/O DDR1_DQ[53] CV36 SSTL I/O
DDR1_DQ[09] DC7 SSTL I/O DDR1_DQ[54] CT40 SSTL I/O
DDR1_DQ[10] DC11 SSTL I/O DDR1_DQ[55] CV40 SSTL I/O
DDR1_DQ[11] DE11 SSTL I/O DDR1_DQ[56] DE37 SSTL I/O
DDR1_DQ[12] CY6 SSTL I/O DDR1_DQ[57] DF38 SSTL I/O
DDR1_DQ[13] DB6 SSTL I/O DDR1_DQ[58] DD40 SSTL I/O
DDR1_DQ[14] DB10 SSTL I/O DDR1_DQ[59] DB40 SSTL I/O
DDR1_DQ[15] DF10 SSTL I/O DDR1_DQ[60] DA37 SSTL I/O
DDR1_DQ[16] CR7 SSTL I/O DDR1_DQ[61] DC37 SSTL I/O
DDR1_DQ[17] CU7 SSTL I/O DDR1_DQ[62] DA39 SSTL I/O
DDR1_DQ[18] CT10 SSTL I/O DDR1_DQ[63] DF40 SSTL I/O
DDR1_DQ[19] CP10 SSTL I/O DDR1_DQS_DN[00] CT4 SSTL I/O
DDR1_DQ[20] CP6 SSTL I/O DDR1_DQS_DN[01] DC9 SSTL I/O
DDR1_DQ[21] CT6 SSTL I/O DDR1_DQS_DN[02] CV8 SSTL I/O
DDR1_DQ[22] CW9 SSTL I/O DDR1_DQS_DN[03] CR15 SSTL I/O
DDR1_DQ[23] CV10 SSTL I/O DDR1_DQS_DN[04] CT32 SSTL I/O
DDR1_DQ[24] CR13 SSTL I/O DDR1_DQS_DN[05] CY34 SSTL I/O
DDR1_DQ[25] CU13 SSTL I/O DDR1_DQS_DN[06] CR39 SSTL I/O
DDR1_DQ[26] CR17 SSTL I/O DDR1_DQS_DN[07] DE39 SSTL I/O
DDR1_DQ[27] CU17 SSTL I/O DDR1_DQS_DN[08] DE15 SSTL I/O
DDR1_DQ[28] CT12 SSTL I/O DDR1_DQS_DP[00] CR3 SSTL I/O
DDR1_DQ[29] CV12 SSTL I/O DDR1_DQS_DP[01] DE9 SSTL I/O
DDR1_DQ[30] CT16 SSTL I/O DDR1_DQS_DP[02] CU9 SSTL I/O
DDR1_DQ[31] CV16 SSTL I/O DDR1_DQS_DP[03] CU15 SSTL I/O
DDR1_DQ[32] CT30 SSTL I/O DDR1_DQS_DP[04] CP32 SSTL I/O
DDR1_DQ[33] CP30 SSTL I/O DDR1_DQS_DP[05] DB34 SSTL I/O
DDR1_DQ[34] CT34 SSTL I/O DDR1_DQS_DP[06] CU39 SSTL I/O
DDR1_DQ[35] CP34 SSTL I/O DDR1_DQS_DP[07] DC39 SSTL I/O
DDR1_DQ[36] CU29 SSTL I/O DDR1_DQS_DP[08] DC15 SSTL I/O
DDR1_DQ[37] CR29 SSTL I/O DDR1_ECC[0] DE13 SSTL I/O
DDR1_DQ[38] CU33 SSTL I/O DDR1_ECC[1] DF14 SSTL I/O
DDR1_DQ[39] CR33 SSTL I/O DDR1_ECC[2] DD16 SSTL I/O
DDR1_ECC[3] DB16 SSTL I/O DDR2_CS_N[4] AA19 SSTL O

DDR1_ECC[4] DA13 SSTL I/O DDR2_CS_N[5] P18 SSTL O
DDR1_ECC[5] DC13 SSTL I/O DDR2_DQ[00] T40 SSTL I/O
DDR1_ECC[6] DA15 SSTL I/O DDR2_DQ[01] V40 SSTL I/O
DDR1_ECC[7] DF16 SSTL I/O DDR2_DQ[02] P36 SSTL I/O
DDR1_MA[00] DC23 SSTL O DDR2_DQ[03] T36 SSTL I/O
DDR1_MA[01] DE23 SSTL O DDR2_DQ[04] R41 SSTL I/O
DDR1_MA[02] DF24 SSTL O DDR2_DQ[05] U41 SSTL I/O
DDR1_MA[03] DA23 SSTL O DDR2_DQ[06] R37 SSTL I/O
DDR1_MA[04] DB22 SSTL O DDR2_DQ[07] U37 SSTL I/O
DDR1_MA[05] DF22 SSTL O DDR2_DQ[08] AE41 SSTL I/O
DDR1_MA[06] DE21 SSTL O DDR2_DQ[09] AD40 SSTL I/O
DDR1_MA[07] DF20 SSTL O DDR2_DQ[10] AA37 SSTL I/O
DDR1_MA[08] DB20 SSTL O DDR2_DQ[11] AC37 SSTL I/O
DDR1_MA[09] DA19 SSTL O DDR2_DQ[12] AC41 SSTL I/O
DDR1_MA[10] DF26 SSTL O DDR2_DQ[13] AA41 SSTL I/O
DDR1_MA[11] DE19 SSTL O DDR2_DQ[14] AF38 SSTL I/O
DDR1_MA[12] DC19 SSTL O DDR2_DQ[15] AE37 SSTL I/O
DDR1_MA[13] DB30 SSTL O DDR2_DQ[16] U33 SSTL I/O
DDR1_MA[14] DB18 SSTL O DDR2_DQ[17] R33 SSTL I/O
DDR1_MA[15] DC17 SSTL O DDR2_DQ[18] W29 SSTL I/O
DDR1_ODT[0] CT22 SSTL O DDR2_DQ[19] U29 SSTL I/O
DDR1_ODT[1] DA25 SSTL O DDR2_DQ[20] T34 SSTL I/O
DDR1_ODT[2] CY26 SSTL O DDR2_DQ[21] P34 SSTL I/O
DDR1_ODT[3] CV26 SSTL O DDR2_DQ[22] V30 SSTL I/O
DDR1_RAS_N DB28 SSTL O DDR2_DQ[23] T30 SSTL I/O
DDR1_WE_N CV28 SSTL O DDR2_DQ[24] AC35 SSTL I/O
DDR2_BA[0] R17 SSTL O DDR2_DQ[25] AE35 SSTL I/O
DDR2_BA[1] L17 SSTL O DDR2_DQ[26] AE33 SSTL I/O
DDR2_BA[2] P24 SSTL O DDR2_DQ[27] AF32 SSTL I/O
DDR2_CAS_N T16 SSTL O DDR2_DQ[28] AA35 SSTL I/O
DDR2_CKE[0] AA25 SSTL O DDR2_DQ[29] W35 SSTL I/O
DDR2_CKE[1] T26 SSTL O DDR2_DQ[30] AB32 SSTL I/O
DDR2_CKE[2] U27 SSTL O DDR2_DQ[31] AD32 SSTL I/O
DDR2_CKE[3] AD24 SSTL O DDR2_DQ[32] AC13 SSTL I/O
DDR2_CLK_DN[0] Y24 SSTL O DDR2_DQ[33] AE13 SSTL I/O
DDR2_CLK_DN[1] Y22 SSTL O DDR2_DQ[34] AG11 SSTL I/O
DDR2_CLK_DN[2] W21 SSTL O DDR2_DQ[35] AF10 SSTL I/O
DDR2_CLK_DN[3] W23 SSTL O DDR2_DQ[36] AD14 SSTL I/O
DDR2_CLK_DP[0] AB24 SSTL O DDR2_DQ[37] AA13 SSTL I/O
DDR2_CLK_DP[1] AB22 SSTL O DDR2_DQ[38] AB10 SSTL I/O
DDR2_CLK_DP[2] AA21 SSTL O DDR2_DQ[39] AD10 SSTL I/O
DDR2_CLK_DP[3] AA23 SSTL O DDR2_DQ[40] V6 SSTL I/O
DDR2_CS_N[0] AB20 SSTL O DDR2_DQ[41] Y6 SSTL I/O
DDR2_CS_N[1] AE19 SSTL O DDR2_DQ[42] AF8 SSTL I/O
DDR2_DQ[43] AG7 SSTL I/O DDR2_ECC[6] W27 SSTL I/O

DDR2_DQ[44] U7 SSTL I/O DDR2_ECC[7] AA27 SSTL I/O
DDR2_DQ[45] W7 SSTL I/O DDR2_MA[00] AB18 SSTL O
DDR2_DQ[46] AD8 SSTL I/O DDR2_MA[01] R19 SSTL O
DDR2_DQ[47] AE7 SSTL I/O DDR2_MA[02] U19 SSTL O
DDR2_DQ[48] R13 SSTL I/O DDR2_MA[03] T20 SSTL O
DDR2_DQ[49] U13 SSTL I/O DDR2_MA[04] P20 SSTL O
DDR2_DQ[50] T10 SSTL I/O DDR2_MA[05] U21 SSTL O
DDR2_DQ[51] V10 SSTL I/O DDR2_MA[06] R21 SSTL O
DDR2_DQ[52] T14 SSTL I/O DDR2_MA[07] P22 SSTL O
DDR2_DQ[53] V14 SSTL I/O DDR2_MA[08] T22 SSTL O
DDR2_DQ[54] R9 SSTL I/O DDR2_MA[09] R23 SSTL O
DDR2_DQ[55] U9 SSTL I/O DDR2_MA[10] T18 SSTL O
DDR2_DQ[56] W3 SSTL I/O DDR2_MA[11] U23 SSTL O
DDR2_DQ[57] Y4 SSTL I/O DDR2_MA[12] T24 SSTL O
DDR2_DQ[58] AF4 SSTL I/O DDR2_MA[13] R15 SSTL O
DDR2_DQ[59] AE5 SSTL I/O DDR2_MA[14] W25 SSTL O
DDR2_DQ[60] U3 SSTL I/O DDR2_MA[15] U25 SSTL O
DDR2_DQ[61] V4 SSTL I/O DDR2_ODT[0] Y20 SSTL O
DDR2_DQ[62] AF2 SSTL I/O DDR2_ODT[1] W19 SSTL O
DDR2_DQ[63] AE3 SSTL I/O DDR2_ODT[2] AD18 SSTL O
DDR2_DQS_DN[00] T38 SSTL I/O DDR2_ODT[3] Y18 SSTL O
DDR2_DQS_DN[01] AD38 SSTL I/O DDR2_RAS_N U17 SSTL O
DDR2_DQS_DN[02] W31 SSTL I/O DDR2_WE_N P16 SSTL O
DDR2_DQS_DN[03] AA33 SSTL I/O DDR23_RCOMP[0] U15 Analog I
DDR2_DQS_DN[04] AC11 SSTL I/O DDR23_RCOMP[1] AC15 Analog I
DDR2_DQS_DN[05] AB8 SSTL I/O DDR23_RCOMP[2] Y14 Analog I
DDR2_DQS_DN[06] U11 SSTL I/O DDR3_BA[0] A17 SSTL O
DDR2_DQS_DN[07] AC3 SSTL I/O DDR3_BA[1] E19 SSTL O
DDR2_DQS_DN[08] AB28 SSTL I/O DDR3_BA[2] B24 SSTL O
DDR2_DQS_DP[00] V38 SSTL I/O DDR3_CAS_N B14 SSTL O
DDR2_DQS_DP[01] AB38 SSTL I/O DDR3_CKE[0] K24 SSTL O
DDR2_DQS_DP[02] U31 SSTL I/O DDR3_CKE[1] M24 SSTL O
DDR2_DQS_DP[03] AC33 SSTL I/O DDR3_CKE[2] J25 SSTL O
DDR2_DQS_DP[04] AE11 SSTL I/O DDR3_CKE[3] N25 SSTL O
DDR2_DQS_DP[05] AC7 SSTL I/O DDR3_CLK_DN[0] J23 SSTL O
DDR2_DQS_DP[06] W11 SSTL I/O DDR3_CLK_DN[1] J21 SSTL O
DDR2_DQS_DP[07] AB4 SSTL I/O DDR3_CLK_DN[2] M20 SSTL O
DDR2_DQS_DP[08] AC27 SSTL I/O DDR3_CLK_DN[3] K22 SSTL O
DDR2_ECC[0] AF30 SSTL I/O DDR3_CLK_DP[0] L23 SSTL O
DDR2_ECC[1] AF28 SSTL I/O DDR3_CLK_DP[1] L21 SSTL O
DDR2_ECC[2] Y26 SSTL I/O DDR3_CLK_DP[2] K20 SSTL O
DDR2_ECC[3] AB26 SSTL I/O DDR3_CLK_DP[3] M22 SSTL O
DDR2_ECC[4] AB30 SSTL I/O DDR3_CS_N[0] G19 SSTL O
DDR2_ECC[5] AD30 SSTL I/O DDR3_CS_N[1] J19 SSTL O
DDR3_CS_N[4] K18 SSTL O DDR3_DQ[43] L9 SSTL I/O

DDR3_CS_N[5] G17 SSTL O DDR3_DQ[44] K14 SSTL I/O
DDR3_DQ[00] B40 SSTL I/O DDR3_DQ[45] M14 SSTL I/O
DDR3_DQ[01] A39 SSTL I/O DDR3_DQ[46] K10 SSTL I/O
DDR3_DQ[02] C37 SSTL I/O DDR3_DQ[47] M10 SSTL I/O
DDR3_DQ[03] E37 SSTL I/O DDR3_DQ[48] E7 SSTL I/O
DDR3_DQ[04] F40 SSTL I/O DDR3_DQ[49] F6 SSTL I/O
DDR3_DQ[05] D40 SSTL I/O DDR3_DQ[50] N7 SSTL I/O
DDR3_DQ[06] F38 SSTL I/O DDR3_DQ[51] P6 SSTL I/O
DDR3_DQ[07] A37 SSTL I/O DDR3_DQ[52] C7 SSTL I/O
DDR3_DQ[08] N39 SSTL I/O DDR3_DQ[53] D6 SSTL I/O
DDR3_DQ[09] L39 SSTL I/O DDR3_DQ[54] L7 SSTL I/O
DDR3_DQ[10] L35 SSTL I/O DDR3_DQ[55] M6 SSTL I/O
DDR3_DQ[11] J35 SSTL I/O DDR3_DQ[56] G3 SSTL I/O
DDR3_DQ[12] M40 SSTL I/O DDR3_DQ[57] H2 SSTL I/O
DDR3_DQ[13] K40 SSTL I/O DDR3_DQ[58] N3 SSTL I/O
DDR3_DQ[14] K36 SSTL I/O DDR3_DQ[59] P4 SSTL I/O
DDR3_DQ[15] H36 SSTL I/O DDR3_DQ[60] F4 SSTL I/O
DDR3_DQ[16] A35 SSTL I/O DDR3_DQ[61] H4 SSTL I/O
DDR3_DQ[17] F34 SSTL I/O DDR3_DQ[62] L1 SSTL I/O
DDR3_DQ[18] D32 SSTL I/O DDR3_DQ[63] M2 SSTL I/O
DDR3_DQ[19] F32 SSTL I/O DDR3_DQS_DN[00] B38 SSTL I/O
DDR3_DQ[20] E35 SSTL I/O DDR3_DQS_DN[01] L37 SSTL I/O
DDR3_DQ[21] C35 SSTL I/O DDR3_DQS_DN[02] G33 SSTL I/O
DDR3_DQ[22] A33 SSTL I/O DDR3_DQS_DN[03] P28 SSTL I/O
DDR3_DQ[23] B32 SSTL I/O DDR3_DQS_DN[04] B10 SSTL I/O
DDR3_DQ[24] M32 SSTL I/O DDR3_DQS_DN[05] L11 SSTL I/O
DDR3_DQ[25] L31 SSTL I/O DDR3_DQS_DN[06] J7 SSTL I/O
DDR3_DQ[26] M28 SSTL I/O DDR3_DQS_DN[07] L3 SSTL I/O
DDR3_DQ[27] L27 SSTL I/O DDR3_DQS_DN[08] G27 SSTL I/O
DDR3_DQ[28] L33 SSTL I/O DDR3_DQS_DP[00] D38 SSTL I/O
DDR3_DQ[29] K32 SSTL I/O DDR3_DQS_DP[01] J37 SSTL I/O
DDR3_DQ[30] N27 SSTL I/O DDR3_DQS_DP[02] E33 SSTL I/O
DDR3_DQ[31] M26 SSTL I/O DDR3_DQS_DP[03] N29 SSTL I/O
DDR3_DQ[32] D12 SSTL I/O DDR3_DQS_DP[04] D10 SSTL I/O
DDR3_DQ[33] A11 SSTL I/O DDR3_DQS_DP[05] N11 SSTL I/O
DDR3_DQ[34] C9 SSTL I/O DDR3_DQS_DP[06] K6 SSTL I/O
DDR3_DQ[35] E9 SSTL I/O DDR3_DQS_DP[07] M4 SSTL I/O
DDR3_DQ[36] F12 SSTL I/O DDR3_DQS_DP[08] E27 SSTL I/O
DDR3_DQ[37] B12 SSTL I/O DDR3_ECC[0] G29 SSTL I/O
DDR3_DQ[38] F10 SSTL I/O DDR3_ECC[1] J29 SSTL I/O
DDR3_DQ[39] A9 SSTL I/O DDR3_ECC[2] E25 SSTL I/O
DDR3_DQ[40] J13 SSTL I/O DDR3_ECC[3] C25 SSTL I/O
DDR3_DQ[41] L13 SSTL I/O DDR3_ECC[4] F30 SSTL I/O
DDR3_DQ[42] J9 SSTL I/O DDR3_ECC[5] H30 SSTL I/O
DDR3_ECC[6] F26 SSTL I/O PE_RBIAS AH52 PCIEX3 I/O

DDR3_ECC[7] H26 SSTL I/O PE_RBIAS_SENSE AF52 PCIEX3 I
DDR3_MA[00] A19 SSTL O PE_VREF_CAP AJ43 PCIEX3 I/O
DDR3_MA[01] E21 SSTL O PE1A_RX_DN[0] E51 PCIEX3 I
DDR3_MA[02] F20 SSTL O PE1A_RX_DN[1] F52 PCIEX3 I
DDR3_MA[03] B20 SSTL O PE1A_RX_DN[2] F54 PCIEX3 I
DDR3_MA[04] D20 SSTL O PE1A_RX_DN[3] G55 PCIEX3 I
DDR3_MA[05] A21 SSTL O PE1A_RX_DP[0] C51 PCIEX3 I
DDR3_MA[06] F22 SSTL O PE1A_RX_DP[1] D52 PCIEX3 I
DDR3_MA[07] B22 SSTL O PE1A_RX_DP[2] D54 PCIEX3 I
DDR3_MA[08] D22 SSTL O PE1A_RX_DP[3] E55 PCIEX3 I
DDR3_MA[09] G23 SSTL O PE1A_TX_DN[0] K42 PCIEX3 O
DDR3_MA[10] D18 SSTL O PE1A_TX_DN[1] L43 PCIEX3 O
DDR3_MA[11] A23 SSTL O PE1A_TX_DN[2] K44 PCIEX3 O
DDR3_MA[12] E23 SSTL O PE1A_TX_DN[3] L45 PCIEX3 O
DDR3_MA[13] A13 SSTL O PE1A_TX_DP[0] H42 PCIEX3 O
DDR3_MA[14] D24 SSTL O PE1A_TX_DP[1] J43 PCIEX3 O
DDR3_MA[15] F24 SSTL O PE1A_TX_DP[2] H44 PCIEX3 O
DDR3_ODT[0] L19 SSTL O PE1A_TX_DP[3] J45 PCIEX3 O
DDR3_ODT[1] F18 SSTL O PE1B_RX_DN[4] L53 PCIEX3 I
DDR3_ODT[2] E17 SSTL O PE1B_RX_DN[5] M54 PCIEX3 I
DDR3_ODT[3] J17 SSTL O PE1B_RX_DN[6] L57 PCIEX3 I
DDR3_RAS_N B16 SSTL O PE1B_RX_DN[7] M56 PCIEX3 I
DDR3_WE_N A15 SSTL O PE1B_RX_DP[4] J53 PCIEX3 I
DMI_RX_DN[0] E47 PCIEX I PE1B_RX_DP[5] K54 PCIEX3 I
DMI_RX_DN[1] D48 PCIEX I PE1B_RX_DP[6] J57 PCIEX3 I
DMI_RX_DN[2] E49 PCIEX I PE1B_RX_DP[7] K56 PCIEX3 I
DMI_RX_DN[3] D50 PCIEX I PE1B_TX_DN[4] K46 PCIEX3 O
DMI_RX_DP[0] C47 PCIEX I PE1B_TX_DN[5] L47 PCIEX3 O
DMI_RX_DP[1] B48 PCIEX I PE1B_TX_DN[6] K48 PCIEX3 O
DMI_RX_DP[2] C49 PCIEX I PE1B_TX_DN[7] L49 PCIEX3 O
DMI_RX_DP[3] B50 PCIEX I PE1B_TX_DP[4] H46 PCIEX3 O
DMI_TX_DN[0] D42 PCIEX O PE1B_TX_DP[5] J47 PCIEX3 O
DMI_TX_DN[1] E43 PCIEX O PE1B_TX_DP[6] H48 PCIEX3 O
DMI_TX_DN[2] D44 PCIEX O PE1B_TX_DP[7] J49 PCIEX3 O
DMI_TX_DN[3] E45 PCIEX O PE2A_RX_DN[0] N55 PCIEX3 I
DMI_TX_DP[0] B42 PCIEX O PE2A_RX_DN[1] V54 PCIEX3 I
DMI_TX_DP[1] C43 PCIEX O PE2A_RX_DN[2] V56 PCIEX3 I
DMI_TX_DP[2] B44 PCIEX O PE2A_RX_DN[3] W55 PCIEX3 I
DMI_TX_DP[3] C45 PCIEX O PE2A_RX_DP[0] L55 PCIEX3 I
DRAM_PWR_OK_C01 CW17 CMOS1.5v I PE2A_RX_DP[1] T54 PCIEX3 I
DRAM_PWR_OK_C23 L15 CMOS1.5v I PE2A_RX_DP[2] T56 PCIEX3 I
EAR_N CH56 ODCMOS I/O PE2A_RX_DP[3] U55 PCIEX3 I
MEM_HOT_C01_N CB22 ODCMOS I/O PE2A_TX_DN[0] AR49 PCIEX3 O
MEM_HOT_C23_N E13 ODCMOS I/O PE2A_TX_DN[1] AP50 PCIEX3 O
PE2A_TX_DN[2] AR51 PCIEX3 O PE2D_RX_DP[15] AY56 PCIEX3 I

PE2A_TX_DN[3] AP52 PCIEX3 O PE2D_TX_DN[12] AY50 PCIEX3 O
PE2A_TX_DP[0] AN49 PCIEX3 O PE2D_TX_DN[13] BA49 PCIEX3 O
PE2A_TX_DP[1] AM50 PCIEX3 O PE2D_TX_DN[14] AY48 PCIEX3 O
PE2A_TX_DP[2] AN51 PCIEX3 O PE2D_TX_DN[15] BA47 PCIEX3 O
PE2A_TX_DP[3] AM52 PCIEX3 O PE2D_TX_DP[12] AV50 PCIEX3 O
PE2B_RX_DN[4] AD54 PCIEX3 I PE2D_TX_DP[13] AW49 PCIEX3 O
PE2B_RX_DN[5] AD56 PCIEX3 I PE2D_TX_DP[14] AV48 PCIEX3 O
PE2B_RX_DN[6] AE55 PCIEX3 I PE2D_TX_DP[15] AW47 PCIEX3 O
PE2B_RX_DN[7] AF58 PCIEX3 I PE3A_RX_DN[0] AH44 PCIEX3 I
PE2B_RX_DP[4] AB54 PCIEX3 I PE3A_RX_DN[1] AJ45 PCIEX3 I
PE2B_RX_DP[5] AB56 PCIEX3 I PE3A_RX_DN[2] AH46 PCIEX3 I
PE2B_RX_DP[6] AC55 PCIEX3 I PE3A_RX_DN[3] AC49 PCIEX3 I
PE2B_RX_DP[7] AE57 PCIEX3 I PE3A_RX_DP[0] AF44 PCIEX3 I
PE2B_TX_DN[4] AJ53 PCIEX3 O PE3A_RX_DP[1] AG45 PCIEX3 I
PE2B_TX_DN[5] AK54 PCIEX3 O PE3A_RX_DP[2] AF46 PCIEX3 I
PE2B_TX_DN[6] AR53 PCIEX3 O PE3A_RX_DP[3] AA49 PCIEX3 I
PE2B_TX_DN[7] AT54 PCIEX3 O PE3A_TX_DN[0] K50 PCIEX3 O
PE2B_TX_DP[4] AG53 PCIEX3 O PE3A_TX_DN[1] L51 PCIEX3 O
PE2B_TX_DP[5] AH54 PCIEX3 O PE3A_TX_DN[2] U47 PCIEX3 O
PE2B_TX_DP[6] AN53 PCIEX3 O PE3A_TX_DN[3] T48 PCIEX3 O
PE2B_TX_DP[7] AP54 PCIEX3 O PE3A_TX_DP[0] H50 PCIEX3 O
PE2C_RX_DN[10] AL57 PCIEX3 I PE3A_TX_DP[1] J51 PCIEX3 O
PE2C_RX_DN[11] AU57 PCIEX3 I PE3A_TX_DP[2] R47 PCIEX3 O
PE2C_RX_DN[8] AK56 PCIEX3 I PE3A_TX_DP[3] P48 PCIEX3 O
PE2C_RX_DN[9] AM58 PCIEX3 I PE3B_RX_DN[4] AB50 PCIEX3 I
PE2C_RX_DP[10] AJ57 PCIEX3 I PE3B_RX_DN[5] AB52 PCIEX3 I
PE2C_RX_DP[11] AR57 PCIEX3 I PE3B_RX_DN[6] AC53 PCIEX3 I
PE2C_RX_DP[8] AH56 PCIEX3 I PE3B_RX_DN[7] AC51 PCIEX3 I
PE2C_RX_DP[9] AK58 PCIEX3 I PE3B_RX_DP[4] Y50 PCIEX3 I
PE2C_TX_DN[10] BB54 PCIEX3 O PE3B_RX_DP[5] Y52 PCIEX3 I
PE2C_TX_DN[11] BA51 PCIEX3 O PE3B_RX_DP[6] AA53 PCIEX3 I
PE2C_TX_DN[8] AY52 PCIEX3 O PE3B_RX_DP[7] AA51 PCIEX3 I
PE2C_TX_DN[9] BA53 PCIEX3 O PE3B_TX_DN[4] T52 PCIEX3 O
PE2C_TX_DP[10] AY54 PCIEX3 O PE3B_TX_DN[5] U51 PCIEX3 O
PE2C_TX_DP[11] AW51 PCIEX3 O PE3B_TX_DN[6] T50 PCIEX3 O
PE2C_TX_DP[8] AV52 PCIEX3 O PE3B_TX_DN[7] U49 PCIEX3 O
PE2C_TX_DP[9] AW53 PCIEX3 O PE3B_TX_DP[4] P52 PCIEX3 O
PE2D_RX_DN[12] AV58 PCIEX3 I PE3B_TX_DP[5] R51 PCIEX3 O
PE2D_RX_DN[13] AT56 PCIEX3 I PE3B_TX_DP[6] P50 PCIEX3 O
PE2D_RX_DN[14] BA57 PCIEX3 I PE3B_TX_DP[7] R49 PCIEX3 O
PE2D_RX_DN[15] BB56 PCIEX3 I PE3C_RX_DN[10] AH50 PCIEX3 I
PE2D_RX_DP[12] AT58 PCIEX3 I PE3C_RX_DN[11] AJ49 PCIEX3 I
PE2D_RX_DP[13] AP56 PCIEX3 I PE3C_RX_DN[8] AH48 PCIEX3 I
PE2D_RX_DP[14] AY58 PCIEX3 I PE3C_RX_DN[9] AJ51 PCIEX3 I
PE3C_RX_DP[10] AF50 PCIEX3 I RSVD AB48

PE3C_RX_DP[11] AG49 PCIEX3 I RSVD AC29
PE3C_RX_DP[8] AF48 PCIEX3 I RSVD AC39
PE3C_RX_DP[9] AG51 PCIEX3 I RSVD AC5
PE3C_TX_DN[10] U45 PCIEX3 O RSVD AD12
PE3C_TX_DN[11] AB46 PCIEX3 O RSVD AD16
PE3C_TX_DN[8] T46 PCIEX3 O RSVD AD20
PE3C_TX_DN[9] AC47 PCIEX3 O RSVD AD22
PE3C_TX_DP[10] R45 PCIEX3 O RSVD AD28
PE3C_TX_DP[11] Y46 PCIEX3 O RSVD AD4
PE3C_TX_DP[8] P46 PCIEX3 O RSVD AE21
PE3C_TX_DP[9] AA47 PCIEX3 O RSVD AE23
PE3D_RX_DN[12] AJ47 PCIEX3 I RSVD AE25
PE3D_RX_DN[13] AR47 PCIEX3 I RSVD AL47
PE3D_RX_DN[14] AP46 PCIEX3 I RSVD AL55
PE3D_RX_DN[15] AR45 PCIEX3 I RSVD AM44
PE3D_RX_DP[12] AG47 PCIEX3 I RSVD AP48
PE3D_RX_DP[13] AN47 PCIEX3 I RSVD AR55
PE3D_RX_DP[14] AM46 PCIEX3 I RSVD AU55
PE3D_RX_DP[15] AN45 PCIEX3 I RSVD AV46
PE3D_TX_DN[12] AC45 PCIEX3 O RSVD AY46
PE3D_TX_DN[13] AB44 PCIEX3 O RSVD B18
PE3D_TX_DN[14] AA43 PCIEX3 O RSVD B34
PE3D_TX_DN[15] P44 PCIEX3 O RSVD B46
PE3D_TX_DP[12] AA45 PCIEX3 O RSVD BC47
PE3D_TX_DP[13] Y44 PCIEX3 O RSVD BC51
PE3D_TX_DP[14] AC43 PCIEX3 O RSVD BD44
PE3D_TX_DP[15] T44 PCIEX3 O RSVD BD46
PECI BJ47 PECI I/O RSVD BD50
PMSYNC K52 CMOS I RSVD BD58
PRDY_N R53 CMOS O RSVD BE43
PREQ_N U53 CMOS I/O RSVD BE45
PROC_SEL_N AH42 O RSVD BE47
PROCHOT_N BD52 ODCMOS I/O RSVD BE53
PWRGOOD BJ53 CMOS I RSVD BE55
RESET_N CK44 CMOS I RSVD BE57
RSVD AK52 RSVD BF46
RSVD A53 RSVD BF50
RSVD AA15 RSVD BF52
RSVD AA17 RSVD BF54
RSVD AA7 RSVD BF56
RSVD AB12 RSVD BF58
RSVD AB16 RSVD BG43
RSVD AB34 RSVD BG45
RSVD AB40 RSVD BG49
RSVD BG51 RSVD BR51

RSVD BG53 RSVD BT44
RSVD BG55 RSVD BT58
RSVD BG57 RSVD BU43
RSVD BH44 RSVD BU53
RSVD BH46 RSVD BU55
RSVD BH50 RSVD BU57
RSVD BH52 RSVD BV46
RSVD BH54 RSVD BV48
RSVD BH56 RSVD BV50
RSVD BJ43 RSVD BV52
RSVD BJ45 RSVD BV54
RSVD BJ49 RSVD BV56
RSVD BJ51 RSVD BV58
RSVD BK44 RSVD BW45
RSVD BK58 RSVD BW47
RSVD BL43 RSVD BW49
RSVD BL45 RSVD BW51
RSVD BL53 RSVD BW53
RSVD BL55 RSVD BW55
RSVD BL57 RSVD BW57
RSVD BM44 RSVD BY46
RSVD BM46 RSVD BY48
RSVD BM48 RSVD BY50
RSVD BM50 RSVD BY52
RSVD BM52 RSVD BY54
RSVD BM54 RSVD BY56
RSVD BM56 RSVD C53
RSVD BM58 RSVD CA45
RSVD BN47 RSVD CA47
RSVD BN49 RSVD CA49
RSVD BN51 RSVD CA51
RSVD BN53 RSVD CB10
RSVD BN55 RSVD CB24
RSVD BN57 RSVD CB26
RSVD BP44 RSVD CB28
RSVD BP46 RSVD CB32
RSVD BP48 RSVD CB54
RSVD BP50 RSVD CC11
RSVD BP52 RSVD CC21
RSVD BP54 RSVD CC23
RSVD BP56 RSVD CC25
RSVD BR43 RSVD CC27
RSVD BR47 RSVD CC39
RSVD BR49 RSVD CC5
RSVD CC55 RSVD CK52

RSVD CD16 RSVD CK54
RSVD CD32 RSVD CK56
RSVD CD4 RSVD CL13
RSVD CD44 RSVD CL27
RSVD CD46 RSVD CL39
RSVD CD48 RSVD CL45
RSVD CD50 RSVD CL47
RSVD CD52 RSVD CL49
RSVD CD54 RSVD CL51
RSVD CD56 RSVD CL53
RSVD CE19 RSVD CL55
RSVD CE39 RSVD CM26
RSVD CE43 RSVD CM46
RSVD CE45 RSVD CM48
RSVD CE47 RSVD CM50
RSVD CE49 RSVD CM52
RSVD CE51 RSVD CM54
RSVD CE55 RSVD CM56
RSVD CE7 RSVD CN45
RSVD CF16 RSVD CN47
RSVD CF20 RSVD CN49
RSVD CF44 RSVD CN51
RSVD CF46 RSVD CP14
RSVD CF48 RSVD CP38
RSVD CF50 RSVD CP54
RSVD CF52 RSVD CP58
RSVD CF54 RSVD CP8
RSVD CF56 RSVD CR1
RSVD CF8 RSVD CR19
RSVD CG11 RSVD CR21
RSVD CG45 RSVD CR23
RSVD CG47 RSVD CR27
RSVD CG49 RSVD CR31
RSVD CG51 RSVD CR53
RSVD CH32 RSVD CR55
RSVD CJ13 RSVD CR57
RSVD CJ39 RSVD CT14
RSVD CJ53 RSVD CT18
RSVD CJ55 RSVD CT2
RSVD CK28 RSVD CT26
RSVD CK32 RSVD CT38
RSVD CK46 RSVD CT44
RSVD CK48 RSVD CT46
RSVD CK50 RSVD CT48
RSVD CT50 RSVD DB42

RSVD CT52 RSVD DB44
RSVD CT56 RSVD DB46
RSVD CT58 RSVD DB48
RSVD CT8 RSVD DB50
RSVD CU21 RSVD DB52
RSVD CU27 RSVD DB54
RSVD CU31 RSVD DB56
RSVD CU43 RSVD DB8
RSVD CU45 RSVD DC33
RSVD CU47 RSVD DC43
RSVD CU49 RSVD DC45
RSVD CU53 RSVD DC47
RSVD CU55 RSVD DC49
RSVD CU57 RSVD DC51
RSVD CV44 RSVD DC53
RSVD CV46 RSVD DC55
RSVD CV48 RSVD DD42
RSVD CV50 RSVD DD44
RSVD CV52 RSVD DD46
RSVD CV56 RSVD DD48
RSVD CW43 RSVD DD50
RSVD CW45 RSVD DD52
RSVD CW47 RSVD DD54
RSVD CW49 RSVD DD8
RSVD CY14 RSVD DE25
RSVD CY28 RSVD DE33
RSVD CY38 RSVD DE43
RSVD CY46 RSVD DE45
RSVD CY48 RSVD DE47
RSVD CY54 RSVD DE49
RSVD CY56 RSVD DE51
RSVD CY58 RSVD DE55
RSVD D14 RSVD E11
RSVD D16 RSVD E15
RSVD D34 RSVD E39
RSVD D46 RSVD E53
RSVD D56 RSVD E57
RSVD DA27 RSVD F14
RSVD DA29 RSVD F16
RSVD DA53 RSVD F28
RSVD DA55 RSVD F46
RSVD DA57 RSVD F56
RSVD DB14 RSVD F58
RSVD DB38 RSVD G11
RSVD G15 TEST1 CW1 O

RSVD G21 TEST2 F2 O
RSVD G39 TEST3 D4 O
RSVD G7 TEST4 BA55 I
RSVD H28 TESTHI_AT50 AT50 CMOS I
RSVD H56 TESTHI_BF48 BF48 Open Drain I/O
RSVD H58 TESTHI_BH48 BH48 Open Drain I/O
RSVD H6 THERMTRIP_N BL47 ODCMOS O
RSVD J15 TMS BV44 CMOS I
RSVD J3 TRST_N CT54 CMOS I
RSVD K12 VCC AG19 PWR
RSVD M12 VCC AG33 PWR
RSVD M48 VCC AL1 PWR
RSVD N31 VCC AL11 PWR
RSVD R25 VCC AL13 PWR
RSVD R27 VCC AL15 PWR
RSVD T12 VCC AL17 PWR
RSVD T32 VCC AL3 PWR
RSVD U39 VCC AL5 PWR
RSVD V12 VCC AL7 PWR
RSVD V32 VCC AL9 PWR
RSVD V52 VCC AM10 PWR
RSVD W15 VCC AM12 PWR
RSVD Y16 VCC AM2 PWR
RSVD Y8 VCC AM8 PWR
SKTOCC_N BU49 O VCC AN1 PWR
SVIDALERT_N CR43 CMOS I VCC AN11 PWR
SVIDCLK CB44 ODCMOS O VCC AN13 PWR
SVIDDATA BR45 ODCMOS I/O VCC AN15 PWR
TCK BY44 CMOS I VCC AN17 PWR
TDI BW43 CMOS I VCC AN3 PWR
TDO CA43 ODCMOS O VCC AN5 PWR
TEST0 DB4 O VCC AN7 PWR
VCC AN9 PWR VCC BA13 PWR

VCC AP10 PWR VCC BA15 PWR
VCC AP6 PWR VCC BB10 PWR
VCC AP8 PWR VCC BB12 PWR
VCC AU1 PWR VCC BB14 PWR
VCC AU5 PWR VCC BE1 PWR
VCC AV10 PWR VCC BE15 PWR
VCC AV6 PWR VCC BF10 PWR
VCC AV8 PWR VCC BF12 PWR
VCC AW1 PWR VCC BF14 PWR
VCC AW5 PWR VCC BG1 PWR
VCC AY10 PWR VCC BG15 PWR
VCC AY6 PWR VCC BH10 PWR
VCC AY8 PWR VCC BH12 PWR
VCC BA1 PWR VCC BH14 PWR
VCC BA11 PWR VCC BH16 PWR
VCC BH2 PWR VCC BR7 PWR

VCC BH4 PWR VCC BR9 PWR
VCC BH6 PWR VCC BT10 PWR
VCC BH8 PWR VCC BT12 PWR
VCC BJ1 PWR VCC BT14 PWR
VCC BJ5 PWR VCC BU1 PWR
VCC BK10 PWR VCC BU15 PWR
VCC BK6 PWR VCC BV10 PWR
VCC BK8 PWR VCC BV12 PWR
VCC BN1 PWR VCC BV14 PWR
VCC BN5 PWR VCC BY18 PWR
VCC BP10 PWR VCC BY30 PWR
VCC BP6 PWR VCC CA25 PWR
VCC BP8 PWR VCC CA29 PWR
VCC BR1 PWR VCC_SENSE BW3 O
VCC BR11 PWR VCCD_01 CD20 PWR
VCC BR5 PWR VCCD_01 CJ19 PWR
VCCD_01 CJ21 PWR VCCPLL BY14 PWR

VCCD_01 CJ23 PWR VCCPLL CA13 PWR
VCCD_01 CJ25 PWR VCCPLL CA15 PWR
VCCD_01 CJ27 PWR VSA AE15 PWR
VCCD_01 CP20 PWR VSA AE17 PWR
VCCD_01 CP22 PWR VSA AF18 PWR
VCCD_01 CP24 PWR VSA AG15 PWR
VCCD_01 CP26 PWR VSA AG17 PWR
VCCD_01 CP28 PWR VSA AH10 PWR
VCCD_01 CW19 PWR VSA AH12 PWR
VCCD_01 DD18 PWR VSA AH6 PWR
VCCD_01 DD20 PWR VSA AH8 PWR
VCCD_01 DD22 PWR VSA AJ1 PWR
VCCD_23 AC17 PWR VSA AJ3 PWR
VCCD_23 AC25 PWR VSA B54 PWR
VCCD_23 C15 PWR VSA G43 PWR
VCCD_23 C17 PWR VSA G49 PWR
VCCD_23 C19 PWR VSA N45 PWR
VCCD_23 C21 PWR VSA N51 PWR
VCCD_23 C23 PWR VSA_SENSE AG13 O
VCCD_23 G13 PWR VSS A41 GND
VCCD_23 H16 PWR VSS A43 GND
VCCD_23 N15 PWR VSS A51 GND
VCCD_23 N17 PWR VSS A7 GND
VCCD_23 N19 PWR VSS AA11 GND
VCCD_23 V16 PWR VSS AA31 GND
VSS AB14 GND VSS AK10 GND

VSS AC31 GND VSS AK2 GND
VSS AC9 GND VSS AK4 GND
VSS AD26 GND VSS AK42 GND
VSS AD50 GND VSS AL43 GND
VSS AE29 GND VSS AL51 GND
VSS AE31 GND VSS AL53 GND
VSS AE39 GND VSS AM56 GND
VSS AE43 GND VSS AN55 GND
VSS AE47 GND VSS AN57 GND
VSS AE49 GND VSS AP42 GND
VSS AF12 GND VSS AR1 GND
VSS AF56 GND VSS AT10 GND
VSS AF6 GND VSS AT12 GND
VSS AG1 GND VSS AT14 GND
VSS AH58 GND VSS AT8 GND
VSS AJ15 GND VSS AU45 GND
VSS AJ17 GND VSS AU47 GND
VSS AU49 GND VSS BF44 GND

VSS AU51 GND VSS BG47 GND
VSS AV42 GND VSS BH58 GND
VSS AV54 GND VSS BJ55 GND
VSS AV56 GND VSS BJ57 GND
VSS AW55 GND VSS BK42 GND
VSS AW57 GND VSS BK46 GND
VSS B36 GND VSS BK48 GND
VSS BB42 GND VSS BL1 GND
VSS BC1 GND VSS BL49 GND
VSS BC17 GND VSS BM10 GND
VSS BC57 GND VSS BN43 GND
VSS BC7 GND VSS BN45 GND
VSS BC9 GND VSS BP58 GND
VSS BD10 GND VSS BR53 GND
VSS BD12 GND VSS BR57 GND
VSS BD14 GND VSS BT46 GND
VSS BD6 GND VSS BU45 GND
VSS BD8 GND VSS BU51 GND
VSS BE49 GND VSS BW1 GND
VSS BE51 GND VSS BW11 GND
VSS BF42 GND VSS BW13 GND
VSS BW15 GND VSS CD18 GND

VSS BW7 GND VSS CE13 GND
VSS BY24 GND VSS CE5 GND
VSS BY4 GND VSS CE9 GND
VSS BY42 GND VSS CF12 GND
VSS C11 GND VSS CF32 GND
VSS C55 GND VSS CG15 GND
VSS CA11 GND VSS CG31 GND
VSS CA5 GND VSS CH12 GND
VSS CB16 GND VSS CH44 GND
VSS CB6 GND VSS CJ11 GND
VSS CB8 GND VSS CJ17 GND
VSS CC13 GND VSS CJ29 GND
VSS CK10 GND VSS CR11 GND

VSS CL17 GND VSS CR5 GND
VSS CL43 GND VSS CR9 GND
VSS CL5 GND VSS CT28 GND
VSS CM10 GND VSS CT42 GND
VSS CM14 GND VSS CU1 GND
VSS CM38 GND VSS CV14 GND
VSS CN11 GND VSS CV38 GND
VSS CN31 GND VSS CW11 GND
VSS CP12 GND VSS CW53 GND
VSS CP42 GND VSS CY10 GND
VSS CY50 GND VSS E29 GND

VSS D2 GND VSS E41 GND
VSS D26 GND VSS E5 GND
VSS D36 GND VSS F36 GND
VSS D8 GND VSS F42 GND
VSS DA11 GND VSS F44 GND
VSS DA45 GND VSS G1 GND
VSS DB12 GND VSS G41 GND
VSS DC3 GND VSS G53 GND
VSS DD10 GND VSS H10 GND
VSS DE17 GND VSS H52 GND
VSS DE7 GND VSS J11 GND
VSS DF12 GND VSS J27 GND
VSS DF52 GND VSS K2 GND
VSS DF8 GND VSS K26 GND
VSS E1 GND VSS K28 GND
VSS K30 GND VSS R7 GND

VSS K34 GND VSS T28 GND
VSS K8 GND VSS T4 GND
VSS L25 GND VSS T42 GND
VSS L5 GND VSS U35 GND
VSS M34 GND VSS U5 GND
VSS M36 GND VSS V26 GND
VSS N13 GND VSS V48 GND
VSS N37 GND VSS W13 GND
VSS P10 GND VSS W51 GND
VSS P26 GND VSS Y10 GND
VSS R11 GND VSS Y42 GND
VSS R29 GND VSS Y56 GND
VSS R3 GND VSS_VCC_SENSE BY2 O
VSS R31 GND VSS_VSA_SENSE AF14 O
VSS R35 GND VSS_VTTD_SENSE BT42 O
VSS R39 GND VTTA AE45 PWR
VSS R5 GND VTTA AE53 PWR
VSS R55 GND VTTA AM48 PWR
Table 8-1. Land Name (Sheet 45 of 45)

Land Name Land No. Buffer Type Direction
VTTA AM54 PWR

VTTA AU53 PWR
VTTA CA53 PWR
VTTA CC45 PWR
VTTA CG55 PWR
VTTA CJ49 PWR
VTTA CR45 PWR
VTTA CR51 PWR
VTTA DA49 PWR
VTTA W49 PWR
VTTA Y54 PWR
VTTD AF22 PWR
VTTD AF24 PWR
VTTD AG21 PWR
VTTD AG23 PWR
VTTD AM42 PWR
VTTD AT42 PWR
VTTD AY42 PWR
VTTD BD42 PWR
VTTD BH42 PWR
VTTD BK56 PWR
VTTD BL51 PWR
VTTD BM42 PWR
VTTD BR55 PWR
VTTD BU47 PWR
VTTD BV42 PWR
VTTD BY20 PWR
VTTD BY22 PWR
VTTD CA21 PWR
VTTD CA23 PWR
VTTD_SENSE BP42 O
Table 8-2. Land Number (Sheet 1 of 45) Table 8-2. Land Number (Sheet 2 of 45)
Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction
A11 DDR3_DQ[33] SSTL I/O AA55 VSS GND

A13 DDR3_MA[13] SSTL O AA7 RSVD
A15 DDR3_WE_N SSTL O AA9 VSS GND
A17 DDR3_BA[0] SSTL O AB10 DDR2_DQ[38] SSTL I/O
A19 DDR3_MA[00] SSTL O AB12 RSVD
A21 DDR3_MA[05] SSTL O AB14 VSS GND
A23 DDR3_MA[11] SSTL O AB16 RSVD
A33 DDR3_DQ[22] SSTL I/O AB18 DDR2_MA[00] SSTL O
A35 DDR3_DQ[16] SSTL I/O AB20 DDR2_CS_N[0] SSTL O
A37 DDR3_DQ[07] SSTL I/O AB22 DDR2_CLK_DP[1] SSTL O
A39 DDR3_DQ[01] SSTL I/O AB24 DDR2_CLK_DP[0] SSTL O
A41 VSS GND AB26 DDR2_ECC[3] SSTL I/O
A43 VSS GND AB28 DDR2_DQS_DN[08] SSTL I/O
A45 VSS GND AB30 DDR2_ECC[4] SSTL I/O
A47 VSS GND AB32 DDR2_DQ[30] SSTL I/O
A49 VSS GND AB34 RSVD
A5 VSS GND AB36 VSS GND
A51 VSS GND AB38 DDR2_DQS_DP[01] SSTL I/O
A53 RSVD AB4 DDR2_DQS_DP[07] SSTL I/O
A7 VSS GND AB40 RSVD
A9 DDR3_DQ[39] SSTL I/O AB42 VSS GND
AA11 VSS GND AB44 PE3D_TX_DN[13] PCIEX3 O
AA13 DDR2_DQ[37] SSTL I/O AB46 PE3C_TX_DN[11] PCIEX3 O
AA15 RSVD AB48 RSVD
AA17 RSVD AB50 PE3B_RX_DN[4] PCIEX3 I
AA19 DDR2_CS_N[4] SSTL O AB52 PE3B_RX_DN[5] PCIEX3 I
AA21 DDR2_CLK_DP[2] SSTL O AB54 PE2B_RX_DP[4] PCIEX3 I
AA23 DDR2_CLK_DP[3] SSTL O AB56 PE2B_RX_DP[5] PCIEX3 I
AA25 DDR2_CKE[0] SSTL O AB6 VSS GND
AA27 DDR2_ECC[7] SSTL I/O AB8 DDR2_DQS_DN[05] SSTL I/O
AA29 VSS GND AC11 DDR2_DQS_DN[04] SSTL I/O
AA3 VSS GND AC13 DDR2_DQ[32] SSTL I/O
AA31 VSS GND AC15 DDR23_RCOMP[1] Analog I
AA33 DDR2_DQS_DN[03] SSTL I/O AC17 VCCD_23 PWR
AA35 DDR2_DQ[28] SSTL I/O AC19 VCCD_23 PWR
AA39 VSS GND AC23 VCCD_23 PWR
AA43 PE3D_TX_DN[14] PCIEX3 O AC27 DDR2_DQS_DP[08] SSTL I/O
AA45 PE3D_TX_DP[12] PCIEX3 O AC29 RSVD
AA47 PE3C_TX_DP[9] PCIEX3 O AC3 DDR2_DQS_DN[07] SSTL I/O
AA49 PE3A_RX_DP[3] PCIEX3 I AC31 VSS GND
AA5 VSS GND AC33 DDR2_DQS_DP[03] SSTL I/O
AA51 PE3B_RX_DP[7] PCIEX3 I AC35 DDR2_DQ[24] SSTL I/O
AA53 PE3B_RX_DP[6] PCIEX3 I AC37 DDR2_DQ[11] SSTL I/O
AC39 RSVD AE23 RSVD

AC41 DDR2_DQ[12] SSTL I/O AE25 RSVD
AC43 PE3D_TX_DP[14] PCIEX3 O AE27 DDR_RESET_C23_N CMOS1.5v O
AC45 PE3D_TX_DN[12] PCIEX3 O AE29 VSS GND
AC47 PE3C_TX_DN[9] PCIEX3 O AE3 DDR2_DQ[63] SSTL I/O
AC49 PE3A_RX_DN[3] PCIEX3 I AE31 VSS GND
AC5 RSVD AE33 DDR2_DQ[26] SSTL I/O
AC51 PE3B_RX_DN[7] PCIEX3 I AE35 DDR2_DQ[25] SSTL I/O
AC53 PE3B_RX_DN[6] PCIEX3 I AE37 DDR2_DQ[15] SSTL I/O
AC55 PE2B_RX_DP[6] PCIEX3 I AE39 VSS GND
AC7 DDR2_DQS_DP[05] SSTL I/O AE41 DDR2_DQ[08] SSTL I/O
AC9 VSS GND AE43 VSS GND
AD10 DDR2_DQ[39] SSTL I/O AE45 VTTA PWR
AD12 RSVD AE47 VSS GND
AD14 DDR2_DQ[36] SSTL I/O AE49 VSS GND
AD16 RSVD AE5 DDR2_DQ[59] SSTL I/O
AD18 DDR2_ODT[2] SSTL O AE51 VSS GND
AD20 RSVD AE53 VTTA PWR
AD22 RSVD AE55 PE2B_RX_DN[6] PCIEX3 I
AD24 DDR2_CKE[3] SSTL O AE57 PE2B_RX_DP[7] PCIEX3 I
AD26 VSS GND AE7 DDR2_DQ[47] SSTL I/O
AD28 RSVD AE9 VSS GND
AD30 DDR2_ECC[5] SSTL I/O AF10 DDR2_DQ[35] SSTL I/O
AD32 DDR2_DQ[31] SSTL I/O AF12 VSS GND
AD34 VSS GND AF14 VSS_VSA_SENSE O
AD36 VSS GND AF16 VSS GND
AD38 DDR2_DQS_DN[01] SSTL I/O AF18 VSA PWR
AD4 RSVD AF2 DDR2_DQ[62] SSTL I/O
AD40 DDR2_DQ[09] SSTL I/O AF20 VSS GND
AD42 VSS GND AF22 VTTD PWR
AD44 VSS GND AF24 VTTD PWR
AD46 VSS GND AF26 VSS GND
AD48 VSS GND AF28 DDR2_ECC[1] SSTL I/O
AD50 VSS GND AF30 DDR2_ECC[0] SSTL I/O
AD52 VSS GND AF32 DDR2_DQ[27] SSTL I/O
AD54 PE2B_RX_DN[4] PCIEX3 I AF34 VSS GND
AD56 PE2B_RX_DN[5] PCIEX3 I AF36 VSS GND
AD6 VSS GND AF38 DDR2_DQ[14] SSTL I/O
AD8 DDR2_DQ[46] SSTL I/O AF4 DDR2_DQ[58] SSTL I/O
AE11 DDR2_DQS_DP[04] SSTL I/O AF40 VSS GND
AE13 DDR2_DQ[33] SSTL I/O AF42 VSS GND
AE15 VSA PWR AF44 PE3A_RX_DP[0] PCIEX3 I
AE17 VSA PWR AF46 PE3A_RX_DP[2] PCIEX3 I
AE19 DDR2_CS_N[1] SSTL O AF48 PE3C_RX_DP[8] PCIEX3 I
AE21 RSVD AF50 PE3C_RX_DP[10] PCIEX3 I
AF52 PE_RBIAS_SENSE PCIEX3 I AH50 PE3C_RX_DN[10] PCIEX3 I

AF54 VSS GND AH52 PE_RBIAS PCIEX3 I/O
AF56 VSS GND AH54 PE2B_TX_DP[5] PCIEX3 O
AF58 PE2B_RX_DN[7] PCIEX3 I AH56 PE2C_RX_DP[8] PCIEX3 I
AF6 VSS GND AH58 VSS GND
AF8 DDR2_DQ[42] SSTL I/O AH6 VSA PWR
AG1 VSS GND AH8 VSA PWR
AG11 DDR2_DQ[34] SSTL I/O AJ1 VSA PWR
AG13 VSA_SENSE O AJ11 VSA PWR
AG15 VSA PWR AJ13 VSA PWR
AG17 VSA PWR AJ15 VSS GND
AG19 VCC PWR AJ17 VSS GND
AG21 VTTD PWR AJ3 VSA PWR
AG23 VTTD PWR AJ43 PE_VREF_CAP PCIEX3 I/O
AG25 VCC PWR AJ45 PE3A_RX_DN[1] PCIEX3 I
AG27 VCC PWR AJ47 PE3D_RX_DN[12] PCIEX3 I
AG29 VCC PWR AJ49 PE3C_RX_DN[11] PCIEX3 I
AG3 VSS GND AJ5 VSA PWR
AG31 VCC PWR AJ51 PE3C_RX_DN[9] PCIEX3 I
AG33 VCC PWR AJ53 PE2B_TX_DN[4] PCIEX3 O
AG35 VCC PWR AJ55 BCLK_SELECT[1] CMOS I
AG37 VCC PWR AJ57 PE2C_RX_DP[10] PCIEX3 I
AG39 VCC PWR AJ7 VSA PWR
AG41 VCC PWR AJ9 VSA PWR
AG43 VSS GND AK10 VSS GND
AG45 PE3A_RX_DP[1] PCIEX3 I AK12 VSS GND
AG47 PE3D_RX_DP[12] PCIEX3 I AK14 VSS GND
AG49 PE3C_RX_DP[11] PCIEX3 I AK16 VSS GND
AG51 PE3C_RX_DP[9] PCIEX3 I AK4 VSS GND
AG53 PE2B_TX_DP[4] PCIEX3 O AK42 VSS GND
AG7 DDR2_DQ[43] SSTL I/O AK48 VSS GND
AH10 VSA PWR AK52 RSVD
AH12 VSA PWR AK54 PE2B_TX_DN[5] PCIEX3 O
AH14 VSA PWR AK56 PE2C_RX_DN[8] PCIEX3 I
AH16 VSA PWR AK58 PE2C_RX_DP[9] PCIEX3 I
AH2 VSA PWR AK6 VSS GND
AH4 VSA PWR AK8 VSS GND
AH42 PROC_SEL_N O AL1 VCC PWR
AH44 PE3A_RX_DN[0] PCIEX3 I AL11 VCC PWR
AH46 PE3A_RX_DN[2] PCIEX3 I AL13 VCC PWR
AH48 PE3C_RX_DN[8] PCIEX3 I AL15 VCC PWR
AL17 VCC PWR AN7 VCC PWR

AL3 VCC PWR AN9 VCC PWR
AL43 VSS GND AP10 VCC PWR
AL47 RSVD AP14 VCC PWR
AL5 VCC PWR AP2 VCC PWR
AL53 VSS GND AP42 VSS GND
AL55 RSVD AP44 VSS GND
AL57 PE2C_RX_DN[10] PCIEX3 I AP46 PE3D_RX_DN[14] PCIEX3 I
AL7 VCC PWR AP48 RSVD
AL9 VCC PWR AP50 PE2A_TX_DN[1] PCIEX3 O
AM10 VCC PWR AP52 PE2A_TX_DN[3] PCIEX3 O
AM12 VCC PWR AP54 PE2B_TX_DP[7] PCIEX3 O
AM14 VCC PWR AP56 PE2D_RX_DP[13] PCIEX3 I
AM16 VCC PWR AP58 VSS GND
AM2 VCC PWR AP6 VCC PWR
AM4 VCC PWR AP8 VCC PWR
AM42 VTTD PWR AR1 VSS GND
AM44 RSVD AR11 VSS GND
AM46 PE3D_RX_DP[14] PCIEX3 I AR13 VSS GND
AM48 VTTA PWR AR15 VSS GND
AM50 PE2A_TX_DP[1] PCIEX3 O AR17 VSS GND
AM52 PE2A_TX_DP[3] PCIEX3 O AR3 VSS GND
AM54 VTTA PWR AR43 BPM_N[0] ODCMOS I/O
AM56 VSS GND AR45 PE3D_RX_DN[15] PCIEX3 I
AM58 PE2C_RX_DN[9] PCIEX3 I AR47 PE3D_RX_DN[13] PCIEX3 I
AM6 VCC PWR AR49 PE2A_TX_DN[0] PCIEX3 O
AM8 VCC PWR AR5 VSS GND
AN1 VCC PWR AR51 PE2A_TX_DN[2] PCIEX3 O
AN11 VCC PWR AR53 PE2B_TX_DN[6] PCIEX3 O
AN13 VCC PWR AR55 RSVD
AN15 VCC PWR AR57 PE2C_RX_DP[11] PCIEX3 I
AN17 VCC PWR AR7 VSS GND
AN3 VCC PWR AR9 VSS GND
AN43 CPU_ONLY_RESET ODCMOS I/O AT10 VSS GND
AN45 PE3D_RX_DP[15] PCIEX3 I AT12 VSS GND
AN47 PE3D_RX_DP[13] PCIEX3 I AT14 VSS GND
AN49 PE2A_TX_DP[0] PCIEX3 O AT16 VSS GND
AN5 VCC PWR AT2 VSS GND
AN51 PE2A_TX_DP[2] PCIEX3 O AT4 VSS GND
AN53 PE2B_TX_DP[6] PCIEX3 O AT42 VTTD PWR
AN55 VSS GND AT44 BPM_N[1] ODCMOS I/O
AN57 VSS GND AT46 VSS GND
AT48 BIST_ENABLE CMOS I AW15 VCC PWR

AT50 TESTHI_AT50 CMOS I AW17 VCC PWR
AT52 VSS GND AW3 VCC PWR
AT54 PE2B_TX_DN[7] PCIEX3 O AW43 BPM_N[5] ODCMOS I/O
AT56 PE2D_RX_DN[13] PCIEX3 I AW45 BCLK1_DP CMOS I
AT58 PE2D_RX_DP[12] PCIEX3 I AW47 PE2D_TX_DP[15] PCIEX3 O
AT6 VSS GND AW49 PE2D_TX_DP[13] PCIEX3 O
AT8 VSS GND AW5 VCC PWR
AU1 VCC PWR AW51 PE2C_TX_DP[11] PCIEX3 O
AU11 VCC PWR AW53 PE2C_TX_DP[9] PCIEX3 O
AU13 VCC PWR AW55 VSS GND
AU15 VCC PWR AW57 VSS GND
AU17 VCC PWR AW7 VCC PWR
AU3 VCC PWR AW9 VCC PWR
AU43 BPM_N[2] ODCMOS I/O AY10 VCC PWR
AU45 VSS GND AY12 VCC PWR
AU5 VCC PWR AY2 VCC PWR
AU53 VTTA PWR AY42 VTTD PWR
AU55 RSVD AY44 BPM_N[7] ODCMOS I/O
AU57 PE2C_RX_DN[11] PCIEX3 I AY46 RSVD
AU7 VCC PWR AY48 PE2D_TX_DN[14] PCIEX3 O
AU9 VCC PWR AY50 PE2D_TX_DN[12] PCIEX3 O
AV10 VCC PWR AY52 PE2C_TX_DN[8] PCIEX3 O
AV12 VCC PWR AY54 PE2C_TX_DP[10] PCIEX3 O
AV14 VCC PWR AY56 PE2D_RX_DP[15] PCIEX3 I
AV16 VCC PWR AY58 PE2D_RX_DP[14] PCIEX3 I
AV2 VCC PWR AY6 VCC PWR
AV4 VCC PWR AY8 VCC PWR
AV42 VSS GND B10 DDR3_DQS_DN[04] SSTL I/O
AV44 BPM_N[3] ODCMOS I/O B12 DDR3_DQ[37] SSTL I/O
AV46 RSVD B14 DDR3_CAS_N SSTL O
AV48 PE2D_TX_DP[14] PCIEX3 O B16 DDR3_RAS_N SSTL O
AV50 PE2D_TX_DP[12] PCIEX3 O B18 RSVD
AV52 PE2C_TX_DP[8] PCIEX3 O B20 DDR3_MA[03] SSTL O
AV54 VSS GND B22 DDR3_MA[07] SSTL O
AV56 VSS GND B24 DDR3_BA[2] SSTL O
AV58 PE2D_RX_DN[12] PCIEX3 I B32 DDR3_DQ[23] SSTL I/O
AV6 VCC PWR B34 RSVD
AV8 VCC PWR B36 VSS GND
AW1 VCC PWR B38 DDR3_DQS_DN[00] SSTL I/O
AW11 VCC PWR B40 DDR3_DQ[00] SSTL I/O
AW13 VCC PWR B42 DMI_TX_DP[0] PCIEX O
B44 DMI_TX_DP[2] PCIEX O BC15 VSS GND

B46 RSVD BC17 VSS GND
B48 DMI_RX_DP[1] PCIEX I BC3 VSS GND
B50 DMI_RX_DP[3] PCIEX I BC43 VSS GND
B52 VSS GND BC45 VSS GND
B54 VSA PWR BC47 RSVD
BA1 VCC PWR BC51 RSVD
BA11 VCC PWR BC53 VSS GND
BA43 BPM_N[6] ODCMOS I/O BD10 VSS GND
BA45 BCLK1_DN CMOS I BD12 VSS GND
BA47 PE2D_TX_DN[15] PCIEX3 O BD14 VSS GND
BA49 PE2D_TX_DN[13] PCIEX3 O BD16 VSS GND
BA5 VCC PWR BD2 VSS GND
BA51 PE2C_TX_DN[11] PCIEX3 O BD4 VSS GND
BA53 PE2C_TX_DN[9] PCIEX3 O BD42 VTTD PWR
BA55 TEST4 I BD44 RSVD
BA57 PE2D_RX_DN[14] PCIEX3 I BD46 RSVD
BA7 VCC PWR BD48 BCLK_SELECT[0] CMOS I
BA9 VCC PWR BD50 RSVD
BB10 VCC PWR BD52 PROCHOT_N ODCMOS I/O
BB12 VCC PWR BD54 VSS GND
BB16 VCC PWR BD58 RSVD
BB42 VSS GND BE1 VCC PWR
BB44 BPM_N[4] ODCMOS I/O BE11 VCC PWR
BB54 PE2C_TX_DN[10] PCIEX3 O BE43 RSVD
BB56 PE2D_RX_DN[15] PCIEX3 I BE45 RSVD
BB58 VSS GND BE47 RSVD
BB6 VCC PWR BE49 VSS GND
BB8 VCC PWR BE5 VCC PWR
BC1 VSS GND BE51 VSS GND
BC11 VSS GND BE53 RSVD
BC13 VSS GND BE55 RSVD
BE57 RSVD BH46 RSVD

BE7 VCC PWR BH48 TESTHI_BH48 Open Drain I/O
BE9 VCC PWR BH50 RSVD
BF10 VCC PWR BH52 RSVD
BF16 VCC PWR BH58 VSS GND
BF2 VCC PWR BH6 VCC PWR
BF4 VCC PWR BH8 VCC PWR
BF42 VSS GND BJ1 VCC PWR
BF44 VSS GND BJ11 VCC PWR
BF46 RSVD BJ13 VCC PWR
BF48 TESTHI_BF48 Open Drain I/O BJ15 VCC PWR
BF54 RSVD BJ43 RSVD
BF56 RSVD BJ45 RSVD
BF58 RSVD BJ47 PECI PECI I/O
BF6 VCC PWR BJ49 RSVD
BF8 VCC PWR BJ5 VCC PWR
BG1 VCC PWR BJ51 RSVD
BG11 VCC PWR BJ53 PWRGOOD CMOS I
BG13 VCC PWR BJ55 VSS GND
BG15 VCC PWR BJ57 VSS GND
BG17 VCC PWR BJ7 VCC PWR
BG3 VCC PWR BJ9 VCC PWR
BG43 RSVD BK10 VCC PWR
BG47 VSS GND BK14 VCC PWR
BG5 VCC PWR BK2 VCC PWR
BG53 RSVD BK42 VSS GND
BG55 RSVD BK44 RSVD
BG57 RSVD BK46 VSS GND
BG7 VCC PWR BK48 VSS GND
BG9 VCC PWR BK50 VSS GND
BH10 VCC PWR BK52 VSS GND
BH12 VCC PWR BK54 VSS GND
BH14 VCC PWR BK56 VTTD PWR
BH16 VCC PWR BK58 RSVD
BH2 VCC PWR BK6 VCC PWR
BH4 VCC PWR BK8 VCC PWR
BH42 VTTD PWR BL1 VSS GND
BH44 RSVD BL11 VSS GND

BL13 VSS GND BN55 RSVD

BL15 VSS GND BN57 RSVD
BL17 VSS GND BN7 VCC PWR
BL3 VSS GND BN9 VCC PWR
BL43 RSVD BP10 VCC PWR
BL45 RSVD BP12 VCC PWR
BL47 THERMTRIP_N ODCMOS O BP14 VCC PWR
BL49 VSS GND BP16 VCC PWR
BL5 VSS GND BP2 VCC PWR
BL51 VTTD PWR BP4 VCC PWR
BL53 RSVD BP42 VTTD_SENSE O
BL55 RSVD BP44 RSVD
BL57 RSVD BP46 RSVD
BL7 VSS GND BP48 RSVD
BL9 VSS GND BP50 RSVD
BM10 VSS GND BP52 RSVD
BM16 VSS GND BP58 VSS GND
BM2 VSS GND BP6 VCC PWR
BM4 VSS GND BP8 VCC PWR
BM42 VTTD PWR BR1 VCC PWR
BM44 RSVD BR11 VCC PWR
BM54 RSVD BR43 RSVD
BM56 RSVD BR45 SVIDDATA ODCMOS I/O
BM58 RSVD BR47 RSVD
BM6 VSS GND BR49 RSVD
BM8 VSS GND BR5 VCC PWR
BN1 VCC PWR BR51 RSVD
BN11 VCC PWR BR53 VSS GND
BN13 VCC PWR BR55 VTTD PWR
BN15 VCC PWR BR57 VSS GND
BN17 VCC PWR BR7 VCC PWR
BN3 VCC PWR BR9 VCC PWR
BN43 VSS GND BT10 VCC PWR
BN45 VSS GND BT12 VCC PWR
BN47 RSVD BT14 VCC PWR
BN5 VCC PWR BT2 VCC PWR
BN53 RSVD BT42 VSS_VTTD_SENSE O

BT44 RSVD BW11 VSS GND

BT46 VSS GND BW13 VSS GND
BT52 VSS GND BW3 VCC_SENSE O
BT54 VSS GND BW43 TDI CMOS I
BT56 VSS GND BW45 RSVD
BT58 RSVD BW47 RSVD
BT6 VCC PWR BW49 RSVD
BT8 VCC PWR BW5 VSS GND
BU1 VCC PWR BW51 RSVD
BU17 VCC PWR BW7 VSS GND
BU3 VCC PWR BW9 DDR0_DQ[28] SSTL I/O
BU43 RSVD BY10 DDR0_DQ[24] SSTL I/O
BU45 VSS GND BY12 DDR0_DQ[25] SSTL I/O
BU47 VTTD PWR BY14 VCCPLL PWR
BU49 SKTOCC_N O BY16 DDR_VREFDQRX_C01 DC I
BU5 VCC PWR BY18 VCC PWR
BU51 VSS GND BY2 VSS_VCC_SENSE O
BU53 RSVD BY20 VTTD PWR
BU55 RSVD BY22 VTTD PWR
BU57 RSVD BY24 VSS GND
BV10 VCC PWR BY30 VCC PWR
BV4 VCC PWR BY4 VSS GND
BV42 VTTD PWR BY40 VCC PWR
BV44 TMS CMOS I BY42 VSS GND
BV46 RSVD BY44 TCK CMOS I
BV48 RSVD BY46 RSVD
BV50 RSVD BY48 RSVD
BV52 RSVD BY50 RSVD
BV54 RSVD BY52 RSVD
BV56 RSVD BY54 RSVD
BV58 RSVD BY56 RSVD
BV6 VCC PWR BY58 VSS GND
BV8 VCC PWR BY6 DDR0_DQ[04] SSTL I/O
BW1 VSS GND BY8 VSS GND

C11 VSS GND CA49 RSVD

C13 VSS GND CA5 VSS GND
C15 VCCD_23 PWR CA51 RSVD
C17 VCCD_23 PWR CA53 VTTA PWR
C19 VCCD_23 PWR CA55 VSS GND
C21 VCCD_23 PWR CA57 VSS GND
C23 VCCD_23 PWR CA7 DDR0_DQ[05] SSTL I/O
C25 DDR3_ECC[3] SSTL I/O CA9 DDR0_DQ[29] SSTL I/O
C3 VSS GND CB10 RSVD
C33 VSS GND CB12 DDR0_DQ[26] SSTL I/O
C35 DDR3_DQ[21] SSTL I/O CB14 DDR0_ECC[4] SSTL I/O
C37 DDR3_DQ[02] SSTL I/O CB16 VSS GND
C39 VSS GND CB18 DDR_RESET_C01_N CMOS1.5v O
C43 DMI_TX_DP[1] PCIEX O CB20 DDR01_RCOMP[2] Analog I
C45 DMI_TX_DP[3] PCIEX O CB22 MEM_HOT_C01_N ODCMOS I/O
C47 DMI_RX_DP[0] PCIEX I CB24 RSVD
C49 DMI_RX_DP[2] PCIEX I CB26 RSVD
C5 VSS GND CB28 RSVD
C51 PE1A_RX_DP[0] PCIEX3 I CB30 DDR0_DQ[37] SSTL I/O
C53 RSVD CB32 RSVD
C7 DDR3_DQ[52] SSTL I/O CB36 VSS GND
C9 DDR3_DQ[34] SSTL I/O CB38 DDR0_DQ[48] SSTL I/O
CA1 DDR0_DQ[12] SSTL I/O CB4 DDR0_DQ[09] SSTL I/O
CA11 VSS GND CB40 DDR0_DQS_DN[06] SSTL I/O
CA13 VCCPLL PWR CB42 DDR0_DQ[55] SSTL I/O
CA15 VCCPLL PWR CB44 SVIDCLK ODCMOS O
CA17 DDR01_RCOMP[0] Analog I CB46 VSS GND
CA19 VSS GND CB48 VSS GND
CA21 VTTD PWR CB50 VSS GND
CA23 VTTD PWR CB52 VSS GND
CA25 VCC PWR CB54 RSVD
CA27 VSS GND CB56 VSS GND
CA29 VCC PWR CB6 VSS GND
CA3 DDR0_DQ[13] SSTL I/O CB8 VSS GND
CA31 VSS GND CC11 RSVD
CA33 VSS GND CC13 VSS GND
CA35 VSS GND CC15 DDR0_ECC[1] SSTL I/O
CA37 VSS GND CC17 DDR0_DQS_DP[08] SSTL I/O
CA39 VSS GND CC19 DDR01_RCOMP[1] Analog I
CA41 VSS GND CC21 RSVD
CA43 TDO ODCMOS O CC23 RSVD
CA45 RSVD CC25 RSVD
CA47 RSVD CC27 RSVD

CC29 VSS GND CE11 DDR0_DQS_DP[03] SSTL I/O

CC3 VSS GND CE13 VSS GND
CC31 DDR0_DQ[33] SSTL I/O CE15 DDR0_ECC[0] SSTL I/O
CC33 DDR0_DQS_DP[04] SSTL I/O CE17 DDR0_DQS_DN[08] SSTL I/O
CC35 DDR0_DQ[35] SSTL I/O CE19 RSVD
CC37 DDR0_DQ[52] SSTL I/O CE21 DDR0_CLK_DN[2] SSTL O
CC39 RSVD CE23 DDR0_CLK_DN[1] SSTL O
CC41 DDR0_DQ[54] SSTL I/O CE25 DDR0_ODT[0] SSTL O
CC43 VSS GND CE27 DDR0_ODT[1] SSTL O
CC45 VTTA PWR CE29 DDR0_RAS_N SSTL O
CC47 VSS GND CE3 DDR0_DQS_DN[01] SSTL I/O
CC49 VSS GND CE31 DDR0_DQ[32] SSTL I/O
CC5 RSVD CE33 DDR0_DQS_DN[04] SSTL I/O
CC51 CAT_ERR_N ODCMOS I/O CE35 DDR0_DQ[34] SSTL I/O
CC53 CORE_RBIAS_SENSE Analog I CE37 DDR0_DQ[53] SSTL I/O
CC55 RSVD CE39 RSVD
CC7 DDR0_DQ[00] SSTL I/O CE41 DDR0_DQ[50] SSTL I/O
CC9 VSS GND CE43 RSVD
CD10 DDR0_DQS_DN[03] SSTL I/O CE45 RSVD
CD12 DDR0_DQ[27] SSTL I/O CE47 RSVD
CD14 DDR0_ECC[5] SSTL I/O CE49 RSVD
CD16 RSVD CE5 VSS GND
CD18 VSS GND CE51 RSVD
CD20 VCCD_01 PWR CE53 CORE_RBIAS Analog I/O
CD22 VCCD_01 PWR CE55 RSVD
CD24 VCCD_01 PWR CE7 RSVD
CD26 VCCD_01 PWR CE9 VSS GND
CD28 VCCD_01 PWR CF10 DDR0_DQ[31] SSTL I/O
CD30 DDR0_DQ[36] SSTL I/O CF12 VSS GND
CD32 RSVD CF14 VSS GND
CD34 DDR0_DQ[38] SSTL I/O CF16 RSVD
CD36 VSS GND CF18 DDR0_ECC[3] SSTL I/O
CD38 DDR0_DQ[49] SSTL I/O CF20 RSVD
CD4 RSVD CF22 DDR0_CLK_DN[3] SSTL O
CD40 DDR0_DQS_DP[06] SSTL I/O CF24 DDR0_CLK_DN[0] SSTL O
CD42 DDR0_DQ[51] SSTL I/O CF26 DDR0_CS_N[5] SSTL O
CD44 RSVD CF28 DDR0_ODT[3] SSTL O
CD56 RSVD CF4 DDR0_DQS_DP[01] SSTL I/O
CD6 VSS GND CF40 VSS GND
CD8 DDR0_DQ[01] SSTL I/O CF42 VSS GND

CF44 RSVD CH28 DDR0_ODT[2] SSTL O

CF46 RSVD CH30 DDR0_DQ[45] SSTL I/O
CF48 RSVD CH32 RSVD
CF52 RSVD CH36 VSS GND
CF6 VSS GND CH40 DDR0_DQS_DN[07] SSTL I/O
CG11 RSVD CH44 VSS GND
CG13 DDR0_DQ[20] SSTL I/O CH46 VSS GND
CG15 VSS GND CH48 VSS GND
CG17 DDR0_ECC[6] SSTL I/O CH50 VSS GND
CG19 DDR0_MA[14] SSTL O CH52 VSS GND
CG21 DDR0_CLK_DP[2] SSTL O CH54 VSS GND
CG23 DDR0_CLK_DP[1] SSTL O CH56 EAR_N ODCMOS I/O
CG25 DDR0_MA[02] SSTL O CH6 VSS GND
CG27 DDR0_CS_N[4] SSTL O CH8 DDR0_DQS_DP[00] SSTL I/O
CG29 DDR0_MA[13] SSTL O CJ11 VSS GND
CG3 DDR0_DQ[14] SSTL I/O CJ13 RSVD
CG31 VSS GND CJ15 DDR0_DQ[22] SSTL I/O
CG33 VSS GND CJ17 VSS GND
CG35 VSS GND CJ19 VCCD_01 PWR
CG45 RSVD CJ29 VSS GND
CG47 RSVD CJ3 VSS GND
CG49 RSVD CJ31 DDR0_DQ[41] SSTL I/O
CG5 DDR0_DQ[15] SSTL I/O CJ33 DDR0_DQS_DP[05] SSTL I/O
CG51 RSVD CJ35 DDR0_DQ[43] SSTL I/O
CG53 VSS GND CJ37 DDR0_DQ[60] SSTL I/O
CG55 VTTA PWR CJ39 RSVD
CG7 DDR0_DQS_DN[00] SSTL I/O CJ41 DDR0_DQ[62] SSTL I/O
CG9 VSS GND CJ43 VSS GND
CH10 DDR0_DQ[30] SSTL I/O CJ45 VSS GND
CH12 VSS GND CJ47 VSS GND
CH14 DDR0_DQS_DN[02] SSTL I/O CJ49 VTTA PWR
CH16 VSS GND CJ5 DDR0_DQ[11] SSTL I/O
CH18 DDR0_ECC[2] SSTL I/O CJ51 VSS GND
CH20 DDR0_CKE[2] SSTL O CJ53 RSVD
CH22 DDR0_CLK_DP[3] SSTL O CJ55 RSVD
CH24 DDR0_CLK_DP[0] SSTL O CJ7 DDR0_DQ[06] SSTL I/O
CH26 DDR0_CS_N[1] SSTL O CJ9 VSS GND

CK10 VSS GND CL45 RSVD

CK12 DDR0_DQ[16] SSTL I/O CL47 RSVD
CK14 DDR0_DQS_DP[02] SSTL I/O CL49 RSVD
CK16 DDR0_DQ[18] SSTL I/O CL5 VSS GND
CK18 DDR0_ECC[7] SSTL I/O CL51 RSVD
CK20 DDR0_MA[12] SSTL O CL53 RSVD
CK22 DDR0_MA[08] SSTL O CL55 RSVD
CK24 DDR0_MA[03] SSTL O CL7 DDR0_DQ[07] SSTL I/O
CK26 DDR0_MA[10] SSTL O CL9 DDR0_DQ[03] SSTL I/O
CK28 RSVD CM10 VSS GND
CK30 DDR0_DQ[44] SSTL I/O CM12 DDR0_DQ[17] SSTL I/O
CK34 DDR0_DQ[46] SSTL I/O CM16 DDR0_DQ[19] SSTL I/O
CK36 VSS GND CM18 DDR0_CKE[1] SSTL O
CK38 DDR0_DQ[57] SSTL I/O CM20 DDR0_BA[2] SSTL O
CK4 VSS GND CM22 DDR0_MA[07] SSTL O
CK40 DDR0_DQS_DP[07] SSTL I/O CM24 DDR0_MA[04] SSTL O
CK42 DDR0_DQ[59] SSTL I/O CM26 RSVD
CK44 RESET_N CMOS I CM28 DDR0_BA[0] SSTL O
CK56 RSVD CM4 DDR1_DQ[04] SSTL I/O
CK6 VSS GND CM40 VSS GND
CK8 DDR0_DQ[02] SSTL I/O CM42 VSS GND
CL11 DDR0_DQ[21] SSTL I/O CM44 BCLK0_DN CMOS I
CL13 RSVD CM46 RSVD
CL15 DDR0_DQ[23] SSTL I/O CM48 RSVD
CL17 VSS GND CM50 RSVD
CL19 DDR0_CKE[0] SSTL O CM52 RSVD
CL21 DDR0_MA[11] SSTL O CM54 RSVD
CL23 DDR0_MA[05] SSTL O CM56 RSVD
CL25 DDR0_MA[00] SSTL O CM6 VSS GND
CL27 RSVD CM8 VSS GND
CL29 DDR0_CAS_N SSTL O CN11 VSS GND
CL3 DDR1_DQ[05] SSTL I/O CN13 VSS GND
CL31 DDR0_DQ[40] SSTL I/O CN15 VSS GND
CL33 DDR0_DQS_DN[05] SSTL I/O CN17 VSS GND
CL35 DDR0_DQ[42] SSTL I/O CN19 DDR0_MA[15] SSTL O
CL37 DDR0_DQ[61] SSTL I/O CN21 DDR0_MA[09] SSTL O
CL39 RSVD CN23 DDR0_MA[06] SSTL O
CL41 DDR0_DQ[63] SSTL I/O CN25 DDR0_CS_N[0] SSTL O
CL43 VSS GND CN27 DDR0_BA[1] SSTL O

CN29 DDR0_WE_N SSTL O CP58 RSVD

CN3 VSS GND CP6 DDR1_DQ[20] SSTL I/O
CN31 VSS GND CP8 RSVD
CN33 VSS GND CR1 RSVD
CN35 VSS GND CR11 VSS GND
CN37 VSS GND CR13 DDR1_DQ[24] SSTL I/O
CN39 VSS GND CR15 DDR1_DQS_DN[03] SSTL I/O
CN41 DDR_VREFDQTX_C01 DC O CR17 DDR1_DQ[26] SSTL I/O
CN43 BCLK0_DP CMOS I CR19 RSVD
CN45 RSVD CR21 RSVD
CN47 RSVD CR23 RSVD
CN49 RSVD CR25 DDR0_MA[01] SSTL O
CN51 RSVD CR29 DDR1_DQ[37] SSTL I/O
CN53 VSS GND CR3 DDR1_DQS_DP[00] SSTL I/O
CN7 VSS GND CR35 VSS GND
CP10 DDR1_DQ[19] SSTL I/O CR39 DDR1_DQS_DN[06] SSTL I/O
CP12 VSS GND CR41 DDR1_DQ[50] SSTL I/O
CP14 RSVD CR43 SVIDALERT_N CMOS I
CP16 VSS GND CR45 VTTA PWR
CP18 DDR0_CKE[3] SSTL O CR47 VSS GND
CP2 DDR1_DQ[01] SSTL I/O CR49 VSS GND
CP20 VCCD_01 PWR CR5 VSS GND
CP22 VCCD_01 PWR CR51 VTTA PWR
CP24 VCCD_01 PWR CR53 RSVD
CP30 DDR1_DQ[33] SSTL I/O CR7 DDR1_DQ[16] SSTL I/O
CP32 DDR1_DQS_DP[04] SSTL I/O CR9 VSS GND
CP34 DDR1_DQ[35] SSTL I/O CT10 DDR1_DQ[18] SSTL I/O
CP36 VSS GND CT12 DDR1_DQ[28] SSTL I/O
CP38 RSVD CT14 RSVD
CP4 DDR1_DQ[00] SSTL I/O CT16 DDR1_DQ[30] SSTL I/O
CP40 VSS GND CT18 RSVD
CP44 VSS GND CT20 DDR1_CKE[0] SSTL O
CP46 VSS GND CT22 DDR1_ODT[0] SSTL O
CP48 VSS GND CT24 DDR1_CS_N[5] SSTL O
CP52 VSS GND CT28 VSS GND
CP54 RSVD CT30 DDR1_DQ[32] SSTL I/O
CP56 VSS GND CT32 DDR1_DQS_DN[04] SSTL I/O

CT34 DDR1_DQ[34] SSTL I/O CV10 DDR1_DQ[23] SSTL I/O

CT38 RSVD CV14 VSS GND
CT4 DDR1_DQS_DN[00] SSTL I/O CV16 DDR1_DQ[31] SSTL I/O
CT40 DDR1_DQ[54] SSTL I/O CV18 VSS GND
CT42 VSS GND CV2 DDR1_DQ[06] SSTL I/O
CT44 RSVD CV20 DDR1_CLK_DN[0] SSTL O
CT46 RSVD CV22 DDR1_CLK_DN[1] SSTL O
CT48 RSVD CV24 DDR1_CLK_DP[2] SSTL O
CT50 RSVD CV26 DDR1_ODT[3] SSTL O
CT52 RSVD CV28 DDR1_WE_N SSTL O
CT54 TRST_N CMOS I CV30 VSS GND
CU1 VSS GND CV4 DDR1_DQ[02] SSTL I/O
CU11 VSS GND CV40 DDR1_DQ[55] SSTL I/O
CU13 DDR1_DQ[25] SSTL I/O CV42 VSS GND
CU15 DDR1_DQS_DP[03] SSTL I/O CV44 RSVD
CU17 DDR1_DQ[27] SSTL I/O CV46 RSVD
CU19 DDR1_CKE[1] SSTL O CV48 RSVD
CU21 RSVD CV50 RSVD
CU23 DDR1_CS_N[1] SSTL O CV52 RSVD
CU25 DDR1_CS_N[4] SSTL O CV54 VSS GND
CU27 RSVD CV56 RSVD
CU29 DDR1_DQ[36] SSTL I/O CV58 VSS GND
CU3 VSS GND CV6 VSS GND
CU31 RSVD CV8 DDR1_DQS_DN[02] SSTL I/O
CU33 DDR1_DQ[38] SSTL I/O CW1 TEST1 O
CU35 VSS GND CW11 VSS GND
CU37 DDR1_DQ[49] SSTL I/O CW13 VSS GND
CU39 DDR1_DQS_DP[06] SSTL I/O CW15 VSS GND
CU41 DDR1_DQ[51] SSTL I/O CW17 DRAM_PWR_OK_C01 CMOS1.5v I
CU43 RSVD CW19 VCCD_01 PWR
CU5 VSS GND CW27 VCCD_01 PWR
CU51 CORE_VREF_CAP I/O CW29 VSS GND
CU53 RSVD CW3 DDR1_DQ[07] SSTL I/O
CU55 RSVD CW31 VSS GND
CU57 RSVD CW33 VSS GND
CU7 DDR1_DQ[17] SSTL I/O CW35 VSS GND
CU9 DDR1_DQS_DP[02] SSTL I/O CW37 VSS GND

CW39 VSS GND D16 RSVD

CW41 DDR_SDA_C01 ODCMOS I/O D18 DDR3_MA[10] SSTL O
CW43 RSVD D2 VSS GND
CW45 RSVD D20 DDR3_MA[04] SSTL O
CW5 VSS GND D26 VSS GND
CW51 VSS GND D32 DDR3_DQ[18] SSTL I/O
CW53 VSS GND D34 RSVD
CW55 VSS GND D36 VSS GND
CW57 VSS GND D38 DDR3_DQS_DP[00] SSTL I/O
CW7 VSS GND D4 TEST3 O
CW9 DDR1_DQ[22] SSTL I/O D40 DDR3_DQ[05] SSTL I/O
CY10 VSS GND D42 DMI_TX_DN[0] PCIEX O
CY12 VSS GND D44 DMI_TX_DN[2] PCIEX O
CY14 RSVD D46 RSVD
CY16 VSS GND D48 DMI_RX_DN[1] PCIEX I
CY18 DDR1_CKE[2] SSTL O D50 DMI_RX_DN[3] PCIEX I
CY2 VSS GND D52 PE1A_RX_DP[1] PCIEX3 I
CY20 DDR1_CLK_DP[0] SSTL O D54 PE1A_RX_DP[2] PCIEX3 I
CY22 DDR1_CLK_DP[1] SSTL O D56 RSVD
CY24 DDR1_CLK_DN[2] SSTL O D6 DDR3_DQ[53] SSTL I/O
CY26 DDR1_ODT[2] SSTL O D8 VSS GND
CY28 RSVD DA11 VSS GND
CY30 DDR1_CAS_N SSTL O DA13 DDR1_ECC[4] SSTL I/O
CY32 DDR1_DQ[45] SSTL I/O DA15 DDR1_ECC[6] SSTL I/O
CY34 DDR1_DQS_DN[05] SSTL I/O DA17 DDR1_CKE[3] SSTL O
CY36 VSS GND DA19 DDR1_MA[09] SSTL O
CY38 RSVD DA21 DDR1_CLK_DN[3] SSTL O
CY4 DDR1_DQ[03] SSTL I/O DA23 DDR1_MA[03] SSTL O
CY40 VSS GND DA25 DDR1_ODT[1] SSTL O
CY42 DDR_SCL_C01 ODCMOS I/O DA27 RSVD
CY44 VSS GND DA29 RSVD
CY48 RSVD DA31 DDR1_DQ[44] SSTL I/O
CY50 VSS GND DA33 DDR1_DQ[40] SSTL I/O
CY52 VSS GND DA35 DDR1_DQ[43] SSTL I/O
CY6 DDR1_DQ[12] SSTL I/O DA43 VSS GND
CY8 VSS GND DA45 VSS GND
D10 DDR3_DQS_DP[04] SSTL I/O DA47 VSS GND
D12 DDR3_DQ[32] SSTL I/O DA49 VTTA PWR
D14 RSVD DA5 VSS GND

DA51 VSS GND DC35 DDR1_DQ[42] SSTL I/O

DA53 RSVD DC37 DDR1_DQ[61] SSTL I/O
DA55 RSVD DC39 DDR1_DQS_DP[07] SSTL I/O
DA57 RSVD DC41 VSS GND
DA7 DDR1_DQ[08] SSTL I/O DC43 RSVD
DA9 VSS GND DC45 RSVD
DB10 DDR1_DQ[14] SSTL I/O DC47 RSVD
DB12 VSS GND DC49 RSVD
DB14 RSVD DC5 VSS GND
DB16 DDR1_ECC[3] SSTL I/O DC51 RSVD
DB18 DDR1_MA[14] SSTL O DC53 RSVD
DB2 VSS GND DC55 RSVD
DB20 DDR1_MA[08] SSTL O DC7 DDR1_DQ[09] SSTL I/O
DB22 DDR1_MA[04] SSTL O DC9 DDR1_DQS_DN[01] SSTL I/O
DB24 DDR1_CS_N[0] SSTL O DD10 VSS GND
DB26 DDR1_BA[0] SSTL O DD12 VSS GND
DB28 DDR1_RAS_N SSTL O DD14 VSS GND
DB30 DDR1_MA[13] SSTL O DD16 DDR1_ECC[2] SSTL I/O
DB32 VSS GND DD18 VCCD_01 PWR
DB34 DDR1_DQS_DP[05] SSTL I/O DD20 VCCD_01 PWR
DB36 VSS GND DD22 VCCD_01 PWR
DB38 RSVD DD24 VCCD_01 PWR
DB4 TEST0 O DD26 VCCD_01 PWR
DB40 DDR1_DQ[59] SSTL I/O DD32 DDR1_DQ[41] SSTL I/O
DB42 RSVD DD34 VSS GND
DB48 RSVD DD40 DDR1_DQ[58] SSTL I/O
DB50 RSVD DD42 RSVD
DB52 RSVD DD44 RSVD
DB54 RSVD DD46 RSVD
DB56 RSVD DD48 RSVD
DB58 VSS GND DD50 RSVD
DB6 DDR1_DQ[13] SSTL I/O DD52 RSVD
DB8 RSVD DD54 RSVD
DC11 DDR1_DQ[10] SSTL I/O DD6 VSS GND
DC13 DDR1_ECC[5] SSTL I/O DD8 RSVD
DC15 DDR1_DQS_DP[08] SSTL I/O DE11 DDR1_DQ[11] SSTL I/O
DC17 DDR1_MA[15] SSTL O DE13 DDR1_ECC[0] SSTL I/O
DC19 DDR1_MA[12] SSTL O DE15 DDR1_DQS_DN[08] SSTL I/O
DC21 DDR1_CLK_DP[3] SSTL O DE17 VSS GND
DC23 DDR1_MA[00] SSTL O DE19 DDR1_MA[11] SSTL O
DC25 DDR1_BA[1] SSTL O DE21 DDR1_MA[06] SSTL O
DC3 VSS GND DE23 DDR1_MA[01] SSTL O
DC33 RSVD DE25 RSVD

DE33 RSVD E3 VSS GND

DE35 DDR1_DQ[47] SSTL I/O E31 VSS GND
DE37 DDR1_DQ[56] SSTL I/O E33 DDR3_DQS_DP[02] SSTL I/O
DE39 DDR1_DQS_DN[07] SSTL I/O E35 DDR3_DQ[20] SSTL I/O
DE41 VSS GND E37 DDR3_DQ[03] SSTL I/O
DE43 RSVD E39 RSVD
DE47 RSVD E43 DMI_TX_DN[1] PCIEX O
DE49 RSVD E45 DMI_TX_DN[3] PCIEX O
DE51 RSVD E47 DMI_RX_DN[0] PCIEX I
DE53 VSS GND E49 DMI_RX_DN[2] PCIEX I
DE7 VSS GND E51 PE1A_RX_DN[0] PCIEX3 I
DE9 DDR1_DQS_DP[01] SSTL I/O E53 RSVD
DF10 DDR1_DQ[15] SSTL I/O E55 PE1A_RX_DP[3] PCIEX3 I
DF12 VSS GND E57 RSVD
DF14 DDR1_ECC[1] SSTL I/O E7 DDR3_DQ[48] SSTL I/O
DF16 DDR1_ECC[7] SSTL I/O E9 DDR3_DQ[35] SSTL I/O
DF18 DDR1_BA[2] SSTL O F10 DDR3_DQ[38] SSTL I/O
DF20 DDR1_MA[07] SSTL O F12 DDR3_DQ[36] SSTL I/O
DF22 DDR1_MA[05] SSTL O F14 RSVD
DF24 DDR1_MA[02] SSTL O F16 RSVD
DF26 DDR1_MA[10] SSTL O F18 DDR3_ODT[1] SSTL O
DF34 DDR1_DQ[46] SSTL I/O F2 TEST2 O
DF36 VSS GND F20 DDR3_MA[02] SSTL O
DF38 DDR1_DQ[57] SSTL I/O F22 DDR3_MA[06] SSTL O
DF40 DDR1_DQ[63] SSTL I/O F24 DDR3_MA[15] SSTL O
DF42 VSS GND F26 DDR3_ECC[6] SSTL I/O
DF44 VSS GND F28 RSVD
DF46 VSS GND F30 DDR3_ECC[4] SSTL I/O
DF48 VSS GND F32 DDR3_DQ[19] SSTL I/O
DF52 VSS GND F36 VSS GND
E1 VSS GND F4 DDR3_DQ[60] SSTL I/O
E11 RSVD F40 DDR3_DQ[04] SSTL I/O
E13 MEM_HOT_C23_N ODCMOS I/O F42 VSS GND
E15 RSVD F44 VSS GND
E17 DDR3_ODT[2] SSTL O F46 RSVD
E19 DDR3_BA[1] SSTL O F48 VSS GND
E21 DDR3_MA[01] SSTL O F50 VSS GND
E23 DDR3_MA[12] SSTL O F52 PE1A_RX_DN[1] PCIEX3 I
E25 DDR3_ECC[2] SSTL I/O F54 PE1A_RX_DN[2] PCIEX3 I
E27 DDR3_DQS_DP[08] SSTL I/O F56 RSVD
E29 VSS GND F58 RSVD

F6 DDR3_DQ[49] SSTL I/O H36 DDR3_DQ[15] SSTL I/O

F8 VSS GND H38 VSS GND
G1 VSS GND H4 DDR3_DQ[61] SSTL I/O
G11 RSVD H40 VSS GND
G13 VCCD_23 PWR H42 PE1A_TX_DP[0] PCIEX3 O
G15 RSVD H44 PE1A_TX_DP[2] PCIEX3 O
G17 DDR3_CS_N[5] SSTL O H46 PE1B_TX_DP[4] PCIEX3 O
G19 DDR3_CS_N[0] SSTL O H48 PE1B_TX_DP[6] PCIEX3 O
G21 RSVD H50 PE3A_TX_DP[0] PCIEX3 O
G23 DDR3_MA[09] SSTL O H52 VSS GND
G25 VSS GND H54 VSS GND
G27 DDR3_DQS_DN[08] SSTL I/O H56 RSVD
G29 DDR3_ECC[0] SSTL I/O H58 RSVD
G3 DDR3_DQ[56] SSTL I/O H6 RSVD
G31 VSS GND H8 VSS GND
G33 DDR3_DQS_DN[02] SSTL I/O J1 DDR_VREFDQRX_C23 DC I
G35 VSS GND J11 VSS GND
G37 VSS GND J13 DDR3_DQ[40] SSTL I/O
G39 RSVD J15 RSVD
G41 VSS GND J17 DDR3_ODT[3] SSTL O
G43 VSA PWR J19 DDR3_CS_N[1] SSTL O
G45 VSS GND J21 DDR3_CLK_DN[1] SSTL O
G47 VSS GND J23 DDR3_CLK_DN[0] SSTL O
G49 VSA PWR J25 DDR3_CKE[2] SSTL O
G51 VSS GND J29 DDR3_ECC[1] SSTL I/O
G53 VSS GND J3 RSVD
G55 PE1A_RX_DN[3] PCIEX3 I J31 VSS GND
G7 RSVD J35 DDR3_DQ[11] SSTL I/O
G9 VSS GND J37 DDR3_DQS_DP[01] SSTL I/O
H10 VSS GND J39 VSS GND
H12 VSS GND J41 VSS GND
H14 VSS GND J43 PE1A_TX_DP[1] PCIEX3 O
H16 VCCD_23 PWR J45 PE1A_TX_DP[3] PCIEX3 O
H18 VCCD_23 PWR J47 PE1B_TX_DP[5] PCIEX3 O
H2 DDR3_DQ[57] SSTL I/O J49 PE1B_TX_DP[7] PCIEX3 O
H20 VCCD_23 PWR J5 VSS GND
H22 VCCD_23 PWR J51 PE3A_TX_DP[1] PCIEX3 O
H24 VCCD_23 PWR J53 PE1B_RX_DP[4] PCIEX3 I
H26 DDR3_ECC[7] SSTL I/O J55 VSS GND
H28 RSVD J57 PE1B_RX_DP[6] PCIEX3 I
H30 DDR3_ECC[5] SSTL I/O J7 DDR3_DQS_DN[06] SSTL I/O
H32 VSS GND J9 DDR3_DQ[42] SSTL I/O
H34 VSS GND K10 DDR3_DQ[46] SSTL I/O

K12 RSVD L41 VSS GND

K14 DDR3_DQ[44] SSTL I/O L43 PE1A_TX_DN[1] PCIEX3 O
K16 RSVD L45 PE1A_TX_DN[3] PCIEX3 O
K18 DDR3_CS_N[4] SSTL O L47 PE1B_TX_DN[5] PCIEX3 O
K2 VSS GND L49 PE1B_TX_DN[7] PCIEX3 O
K20 DDR3_CLK_DP[2] SSTL O L5 VSS GND
K22 DDR3_CLK_DN[3] SSTL O L51 PE3A_TX_DN[1] PCIEX3 O
K24 DDR3_CKE[0] SSTL O L53 PE1B_RX_DN[4] PCIEX3 I
K26 VSS GND L55 PE2A_RX_DP[0] PCIEX3 I
K28 VSS GND L57 PE1B_RX_DN[6] PCIEX3 I
K30 VSS GND L7 DDR3_DQ[54] SSTL I/O
K32 DDR3_DQ[29] SSTL I/O L9 DDR3_DQ[43] SSTL I/O
K34 VSS GND M10 DDR3_DQ[47] SSTL I/O
K36 DDR3_DQ[14] SSTL I/O M12 RSVD
K38 RSVD M14 DDR3_DQ[45] SSTL I/O
K4 RSVD M16 RSVD
K40 DDR3_DQ[13] SSTL I/O M18 RSVD
K42 PE1A_TX_DN[0] PCIEX3 O M2 DDR3_DQ[63] SSTL I/O
K44 PE1A_TX_DN[2] PCIEX3 O M20 DDR3_CLK_DN[2] SSTL O
K46 PE1B_TX_DN[4] PCIEX3 O M22 DDR3_CLK_DP[3] SSTL O
K48 PE1B_TX_DN[6] PCIEX3 O M24 DDR3_CKE[1] SSTL O
K50 PE3A_TX_DN[0] PCIEX3 O M26 DDR3_DQ[31] SSTL I/O
K52 PMSYNC CMOS I M28 DDR3_DQ[26] SSTL I/O
K54 PE1B_RX_DP[5] PCIEX3 I M30 RSVD
K56 PE1B_RX_DP[7] PCIEX3 I M32 DDR3_DQ[24] SSTL I/O
K58 RSVD M34 VSS GND
K6 DDR3_DQS_DP[06] SSTL I/O M36 VSS GND
K8 VSS GND M38 RSVD
L1 DDR3_DQ[62] SSTL I/O M4 DDR3_DQS_DP[07] SSTL I/O
L11 DDR3_DQS_DN[05] SSTL I/O M40 DDR3_DQ[12] SSTL I/O
L13 DDR3_DQ[41] SSTL I/O M42 VSS GND
L15 DRAM_PWR_OK_C23 CMOS1.5v I M44 VSS GND
L17 DDR2_BA[1] SSTL O M46 VSS GND
L19 DDR3_ODT[0] SSTL O M48 RSVD
L21 DDR3_CLK_DP[1] SSTL O M50 VSS GND
L23 DDR3_CLK_DP[0] SSTL O M52 VSS GND
L25 VSS GND M54 PE1B_RX_DN[5] PCIEX3 I
L27 DDR3_DQ[27] SSTL I/O M56 PE1B_RX_DN[7] PCIEX3 I
L29 VSS GND M6 DDR3_DQ[55] SSTL I/O
L3 DDR3_DQS_DN[07] SSTL I/O M8 VSS GND
L31 DDR3_DQ[25] SSTL I/O N11 DDR3_DQS_DP[05] SSTL I/O
L33 DDR3_DQ[28] SSTL I/O N13 VSS GND
L35 DDR3_DQ[10] SSTL I/O N15 VCCD_23 PWR
L37 DDR3_DQS_DN[01] SSTL I/O N17 VCCD_23 PWR
L39 DDR3_DQ[09] SSTL I/O N19 VCCD_23 PWR

N21 VCCD_23 PWR P54 VSS GND

N23 VCCD_23 PWR P56 VSS GND
N25 DDR3_CKE[3] SSTL O P6 DDR3_DQ[51] SSTL I/O
N27 DDR3_DQ[30] SSTL I/O P8 VSS GND
N29 DDR3_DQS_DP[03] SSTL I/O R11 VSS GND
N3 DDR3_DQ[58] SSTL I/O R13 DDR2_DQ[48] SSTL I/O
N31 RSVD R15 DDR2_MA[13] SSTL O
N33 VSS GND R17 DDR2_BA[0] SSTL O
N35 VSS GND R19 DDR2_MA[01] SSTL O
N37 VSS GND R21 DDR2_MA[06] SSTL O
N39 DDR3_DQ[08] SSTL I/O R23 DDR2_MA[09] SSTL O
N41 VSS GND R25 RSVD
N43 VSS GND R27 RSVD
N45 VSA PWR R29 VSS GND
N47 VSS GND R3 VSS GND
N49 VSS GND R31 VSS GND
N5 VSS GND R33 DDR2_DQ[17] SSTL I/O
N51 VSA PWR R35 VSS GND
N53 VSS GND R37 DDR2_DQ[06] SSTL I/O
N55 PE2A_RX_DN[0] PCIEX3 I R39 VSS GND
N7 DDR3_DQ[50] SSTL I/O R41 DDR2_DQ[04] SSTL I/O
N9 VSS GND R43 DDR_SDA_C23 ODCMOS I/O
P10 VSS GND R45 PE3C_TX_DP[10] PCIEX3 O
P12 VSS GND R47 PE3A_TX_DP[2] PCIEX3 O
P14 VSS GND R49 PE3B_TX_DP[7] PCIEX3 O
P16 DDR2_WE_N SSTL O R5 VSS GND
P18 DDR2_CS_N[5] SSTL O R51 PE3B_TX_DP[5] PCIEX3 O
P20 DDR2_MA[04] SSTL O R53 PRDY_N CMOS O
P22 DDR2_MA[07] SSTL O R55 VSS GND
P24 DDR2_BA[2] SSTL O R7 VSS GND
P26 VSS GND R9 DDR2_DQ[54] SSTL I/O
P28 DDR3_DQS_DN[03] SSTL I/O T10 DDR2_DQ[50] SSTL I/O
P30 VSS GND T12 RSVD
P32 VSS GND T14 DDR2_DQ[52] SSTL I/O
P34 DDR2_DQ[21] SSTL I/O T16 DDR2_CAS_N SSTL O
P36 DDR2_DQ[02] SSTL I/O T18 DDR2_MA[10] SSTL O
P38 VSS GND T20 DDR2_MA[03] SSTL O
P4 DDR3_DQ[59] SSTL I/O T22 DDR2_MA[08] SSTL O
P40 VSS GND T24 DDR2_MA[12] SSTL O
P42 DDR_VREFDQTX_C23 DC O T26 DDR2_CKE[1] SSTL O
P44 PE3D_TX_DN[15] PCIEX3 O T28 VSS GND
P46 PE3C_TX_DP[8] PCIEX3 O T30 DDR2_DQ[23] SSTL I/O
P48 PE3A_TX_DP[3] PCIEX3 O T32 RSVD
P50 PE3B_TX_DP[6] PCIEX3 O T34 DDR2_DQ[20] SSTL I/O
P52 PE3B_TX_DP[4] PCIEX3 O T36 DDR2_DQ[03] SSTL I/O

T38 DDR2_DQS_DN[00] SSTL I/O V20 VCCD_23 PWR

T4 VSS GND V22 VCCD_23 PWR
T40 DDR2_DQ[00] SSTL I/O V24 VCCD_23 PWR
T42 VSS GND V26 VSS GND
T44 PE3D_TX_DP[15] PCIEX3 O V28 VSS GND
T46 PE3C_TX_DN[8] PCIEX3 O V30 DDR2_DQ[22] SSTL I/O
T48 PE3A_TX_DN[3] PCIEX3 O V32 RSVD
T50 PE3B_TX_DN[6] PCIEX3 O V34 VSS GND
T52 PE3B_TX_DN[4] PCIEX3 O V36 VSS GND
T54 PE2A_RX_DP[1] PCIEX3 I V38 DDR2_DQS_DP[00] SSTL I/O
T56 PE2A_RX_DP[2] PCIEX3 I V4 DDR2_DQ[61] SSTL I/O
T6 VSS GND V40 DDR2_DQ[01] SSTL I/O
T8 VSS GND V42 VSS GND
U11 DDR2_DQS_DN[06] SSTL I/O V44 VSS GND
U13 DDR2_DQ[49] SSTL I/O V46 VSS GND
U15 DDR23_RCOMP[0] Analog I V48 VSS GND
U17 DDR2_RAS_N SSTL O V50 VSS GND
U19 DDR2_MA[02] SSTL O V52 RSVD
U21 DDR2_MA[05] SSTL O V54 PE2A_RX_DN[1] PCIEX3 I
U23 DDR2_MA[11] SSTL O V56 PE2A_RX_DN[2] PCIEX3 I
U25 DDR2_MA[15] SSTL O V6 DDR2_DQ[40] SSTL I/O
U27 DDR2_CKE[2] SSTL O V8 VSS GND
U29 DDR2_DQ[19] SSTL I/O W11 DDR2_DQS_DP[06] SSTL I/O
U3 DDR2_DQ[60] SSTL I/O W13 VSS GND
U31 DDR2_DQS_DP[02] SSTL I/O W15 RSVD
U33 DDR2_DQ[16] SSTL I/O W17 RSVD
U35 VSS GND W19 DDR2_ODT[1] SSTL O
U37 DDR2_DQ[07] SSTL I/O W21 DDR2_CLK_DN[2] SSTL O
U39 RSVD W23 DDR2_CLK_DN[3] SSTL O
U41 DDR2_DQ[05] SSTL I/O W25 DDR2_MA[14] SSTL O
U43 DDR_SCL_C23 ODCMOS I/O W27 DDR2_ECC[6] SSTL I/O
U45 PE3C_TX_DN[10] PCIEX3 O W29 DDR2_DQ[18] SSTL I/O
U47 PE3A_TX_DN[2] PCIEX3 O W3 DDR2_DQ[56] SSTL I/O
U49 PE3B_TX_DN[7] PCIEX3 O W31 DDR2_DQS_DN[02] SSTL I/O
U5 VSS GND W33 VSS GND
U51 PE3B_TX_DN[5] PCIEX3 O W35 DDR2_DQ[29] SSTL I/O
U53 PREQ_N CMOS I/O W37 VSS GND
U55 PE2A_RX_DP[3] PCIEX3 I W39 RSVD
V10 DDR2_DQ[51] SSTL I/O W45 VSS GND
V12 RSVD W47 VSS GND
V14 DDR2_DQ[53] SSTL I/O W49 VTTA PWR
V16 VCCD_23 PWR W5 VSS GND
V18 VCCD_23 PWR W51 VSS GND

Table 8-2. Land Number (Sheet 45 of 45)

Land No. Land Name Buffer Type Direction
W53 VSS GND

W55 PE2A_RX_DN[3] PCIEX3 I
W7 DDR2_DQ[45] SSTL I/O
W9 VSS GND
Y10 VSS GND
Y12 VSS GND
Y14 DDR23_RCOMP[2] Analog I
Y16 RSVD
Y18 DDR2_ODT[3] SSTL O
Y20 DDR2_ODT[0] SSTL O
Y22 DDR2_CLK_DN[1] SSTL O
Y24 DDR2_CLK_DN[0] SSTL O
Y26 DDR2_ECC[2] SSTL I/O
Y28 VSS GND
Y30 VSS GND
Y32 VSS GND
Y34 RSVD
Y36 VSS GND
Y38 VSS GND
Y4 DDR2_DQ[57] SSTL I/O
Y40 VSS GND
Y42 VSS GND
Y44 PE3D_TX_DP[13] PCIEX3 O
Y46 PE3C_TX_DP[11] PCIEX3 O
Y48 RSVD
Y50 PE3B_RX_DP[4] PCIEX3 I
Y52 PE3B_RX_DP[5] PCIEX3 I
Y54 VTTA PWR
Y56 VSS GND
Y6 DDR2_DQ[41] SSTL I/O
Y8 RSVD
§§

Package Mechanical Specifications
9 Package Mechanical
Specifications
For mechanical specifications and design guidelines refer to the Intel® Core™ i7
Processor Family for the LGA-2011 Socket Thermal Mechanical Specification and Design
Guide.

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Intel® Core™ i7 Processor Family for

the LGA-2011 Socket

Supporting Desktop Intel® Core™ i7-3960X and i7-3970X Extreme Edition

Reference Number: 326196-003

001 • Initial Release November 2011

Included in this family of processors is an integrated memory controller (IMC) and

Figure 1-1. Processor Platform Block Diagram Example

1.1 Processor Feature Details

1.1.1 Supported Technologies

1.2.2 PCI Express*

• Supports receiving and decoding 64 bits of address from PCI Express*

1.2.3 Direct Media Interface Gen 2 (DMI2)

1.2.4 Platform Environment Control Interface (PECI)

1.3 Power Management Support

1.3.2 System States Support

1.3.3 Memory Controller

1.3.4 PCI Express*

1.4 Thermal Management Support

1.5 Package Summary

Table 1-1. Terminology (Sheet 1 of 3)

ASPM Active State Power Management

Table 1-1. Terminology (Sheet 2 of 3)

Table 1-1. Terminology (Sheet 3 of 3)

1.7 Related Documents

Table 1-2. Reference Documents

Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info

PCI Local Bus Specification http://www.pcisig.com/

System Management Bus (SMBus) Specification http://smbus.org/

DDR3 SDRAM Specification http://www.jedec.org

Intel® 64 and IA-32 Architectures Software Developer's Manuals

Intel® Virtualization Technology Specification for Directed I/O Architecture http://download.intel.co

This chapter describes the functional behaviors supported by the processor.

2.1 System Memory Interface

2.1.2 System Memory Timing Support

2.2 PCI Express* Interface

Note: The processor is capable of up to 8.0 GT/s speeds.

2.2.1 PCI Express* Architecture

Figure 2-1. PCI Express* Layering Diagram

PCI Express uses packets to communicate information between components. Packets

Figure 2-2. Packet Flow through the Layers

2.2.1.1 Transaction Layer

2.2.1.2 Data Link Layer

2.2.1.3 Physical Layer

2.2.2 PCI Express* Configuration Mechanism

PCI Express extends the configuration space to 4096 bytes per-device/function, as

2.3 DMI2/PCI Express* Interface

Note: Only DMI2 x4 configuration is supported.

2.3.1 DMI2 Error Flow

2.3.2 DMI2 Link Down

2.4 Platform Environment Control Interface (PECI)

3.1 Intel® Virtualization Technology (Intel® VT)

3.1.1 Intel® Virtualization Technology (Intel® VT) for Intel® 64

3.1.2 Intel® Virtualization Technology (Intel® VT) for Intel® 64

3.1.3 Intel® Virtualization Technology (Intel® VT) for

3.1.3.1 Intel® Virtualization Technology (Intel® VT) for

3.1.3.2 Intel® Virtualization Technology (Intel® VT) for

3.1.4 Intel® Virtualization Technology Processor Extensions

3.2 Security Technologies

Beyond improving performance, the AES instructions provide important security