p4_478

Intel® Pentium® 4 Processor in the 478-pin
Package at 1.50 GHz, 1.60 GHz, 1.70 GHz,

1.80 GHz, 1.90 GHz, and 2 GHz
Datasheet
Product Features
■ Available at 1.50, 1.60, 1.70, 1.80, 1.90 ■8 KB Level 1 data cache
and 2 GHz ■ 256 KB Advanced Transfer Cache (on-
■ Binary compatible with applications die, full speed Level 2 (L2) cache) with
running on previous members of the 8-way associativity and Error
Intel microprocessor line Correcting Code (ECC)
®
■ Intel NetBurst™ micro-architecture ■ 144 new Streaming SIMD Extensions 2
■ System bus frequency at 400 MHz (SSE2) instructions
■ Rapid Execution Engine: Arithmetic ■ Enhanced floating point and multimedia
Logic Units (ALUs) run at twice the unit for enhanced video, audio,
processor core frequency encryption, and 3D performance
■ Hyper Pipelined Technology ■ Power Management capabilities
■ Advance Dynamic Execution — System Management mode

— Very deep out-of-order execution — Multiple low-power states
— Enhanced branch prediction ■ Optimized for 32-bit applications
running on advanced 32-bit operating
■ Level 1 Execution Trace Cache stores
systems
12K micro-ops and removes decoder
latency from main execution loops ■ 8-way cache associativity provides
improved cache hit rate on load/store
operations.
The Intel® Pentium® 4 processor is designed for high-performance desktops and entry
level workstations. It is binary compatible with previous Intel Architecture processors.
The Pentium 4 processor provides great performance for applications running on
advanced operating systems such as Windows* 98, Windows ME, Windows 2000 and
UNIX*. This is achieved by the Intel® NetBurst™ micro-architecture which brings a new
level of performance for system buyers. The Pentium 4 processor extends the power of
the Pentium III processor with performance headroom for advanced audio and video
internet capabilities. Systems based on Pentium 4 processors also include the latest
features to simplify system management and lower the total cost of ownership for large
and small business environments. The Pentium 4 processor offers great performance
for today’s and tomorrow’s applications.
Order Number: 249887-001

August 2001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Pentium® 4 Processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2001
Intel, Intel Logo, Pentium, and Intel NetBurst are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and
other countries.
*Other brands and names may be claimed as the property of others.
Contents
Contents
1.0 Introduction .................................................................................................................. 7
1.1 Terminology........................................................................................................... 8
1.1.1 Processor Packaging Terminology........................................................... 8
1.2 References ............................................................................................................ 9
2.0 Electrical Specifications ........................................................................................11
2.1 System Bus and GTLREF ...................................................................................11
2.2 Power and Ground Pins ......................................................................................11
2.3 Decoupling Guidelines ........................................................................................11
2.3.1 VCC Decoupling .....................................................................................12
2.3.2 System Bus AGTL+ Decoupling.............................................................12
2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking .......................12
2.4 Voltage Identification ...........................................................................................12
2.4.1 Phase Lock Loop (PLL) Power and Filter...............................................14
2.5 Reserved, Unused, and TESTHI Pins.................................................................15
2.6 System Bus Signal Groups .................................................................................16
2.7 Asynchronous GTL+ Signals...............................................................................17
2.8 Test Access Port (TAP) Connection....................................................................18
2.9 System Bus Frequency Select Signals (BSEL[1:0])............................................18
2.10 Maximum Ratings................................................................................................18
2.11 Processor DC Specifications...............................................................................19
2.12 AGTL+ System Bus Specifications .....................................................................24
2.13 System Bus AC Specifications ............................................................................25
2.14 Processor AC Timing Waveforms .......................................................................29
3.0 System Bus Signal Quality Specifications ....................................................35
3.1 BCLK Signal Quality Specifications and Measurement Guidelines.....................35
3.2 System Bus Signal Quality Specifications and Measurement Guidelines...........36
3.3 System Bus Signal Quality Specifications and Measurement Guidelines...........37
3.3.1 Overshoot/Undershoot Guidelines .........................................................37
3.3.2 Overshoot/Undershoot Magnitude .........................................................38
3.3.3 Overshoot/Undershoot Pulse Duration...................................................38
3.3.4 Activity Factor .........................................................................................38
3.3.5 Reading Overshoot/Undershoot Specification Tables............................39
3.3.6 Determining if a System Meets the
Over/Undershoot Specifications.............................................................39
4.0 Package Mechanical Specifications .........................................................................45
4.1 Package Load Specifications ..............................................................................48
4.2 Processor Insertion Specifications ......................................................................49
4.3 Processor Mass Specifications ...........................................................................49
4.4 Processor Materials.............................................................................................49
4.5 Processor Markings.............................................................................................49
4.6 Processor Pin-Out Coordinates...........................................................................50
5.0 Pin Listing and Signal Definitions ...........................................................................51
5.1 Pentium® 4 Processor in the 478-pin Package Pin Assignments.......................51
3
Contents
5.2 Alphabetical Signals Reference .......................................................................... 67

6.0 Thermal Specifications and Design Considerations ................................. 75
6.1 Thermal Specifications........................................................................................ 77
6.2 Thermal Analysis................................................................................................. 77
6.2.1 Thermal Solution Performance............................................................... 77
6.2.2 Measurements For Thermal Specifications............................................ 77
7.0 Features ....................................................................................................................... 79
7.1 Power-On Configuration Options ........................................................................ 79
7.2 Clock Control and Low Power States.................................................................. 79
7.2.1 Normal State—State 1 ........................................................................... 79
7.2.2 AutoHALT Powerdown State—State 2 .................................................. 79
7.2.3 Stop-Grant State—State 3 ..................................................................... 80
7.2.4 HALT/Grant Snoop State—State 4 ........................................................ 81
7.2.5 Sleep State—State 5.............................................................................. 81
7.2.6 Deep Sleep State—State 6 .................................................................... 82
7.3 Thermal Monitor .................................................................................................. 82
7.3.1 Thermal Diode........................................................................................ 84
8.0 Boxed Processor Specifications ................................................................................ 85
8.1 Introduction ......................................................................................................... 85
8.2 Mechanical Specifications................................................................................... 86
8.2.1 Boxed Processor Cooling Solution Dimensions ..................................... 86
8.2.2 Boxed Processor Fan Heatsink Weight.................................................. 87
8.2.3 Boxed Processor Retention Mechanism and
Heatsink Attach Clip Assembly .............................................................. 87
8.3 Electrical Requirements ...................................................................................... 88
8.3.1 Fan Heatsink Power Supply ................................................................... 88
8.4 Thermal Specifications........................................................................................ 89
8.4.1 Boxed Processor Cooling Requirements ............................................... 90
8.4.2 Variable Speed Fan ............................................................................... 91
9.0 Debug Tools Specifications........................................................................................ 93
9.1 Logic Analyzer Interface (LAI)............................................................................. 93
9.1.1 Mechanical Considerations .................................................................... 93
9.1.2 Electrical Considerations........................................................................ 93
4
Contents
Figures
1 Typical VCCIOPLL, VCCA and VSSA Power Distribution ..................................14
2 Phase Lock Loop (PLL) Filter Requirements ......................................................15
3 Vcc Static and Transient Tolerance1, 2, 3 ..........................................................22
4 AC Test Circuit ....................................................................................................29
5 TCK Clock Waveform..........................................................................................30
6 Differential Clock Waveform................................................................................30
7 System Bus Common Clock Valid Delay Timings...............................................31
8 System Bus Reset and Configuration Timings....................................................31
9 Source Synchronous 2X (Address) Timings .......................................................32
10 Source Synchronous 4X Timings ........................................................................33
11 Power-On Reset and Configuration Timings.......................................................33
12 THERMTRIP# Power Down Sequence...............................................................34
13 Test Reset Timings .............................................................................................34
14 BCLK Signal Integrity Waveform.........................................................................36
15 Low-to-High System Bus Receiver Ringback Tolerance.....................................37
16 High-to-Low System Bus Receiver Ringback Tolerance.....................................37
17 Maximum Acceptable Overshoot/Undershoot Waveform ...................................43
18 Exploded View of Processor Components on a System Board ..........................45
19 Pentium® 4 Processor in the 478-pin Package...................................................46
20 Processor Cross-Section and Keep-in ................................................................47
21 Processor Pin Detail............................................................................................47
22 IHS Flatness Specification ..................................................................................48
23 Processor Markings.............................................................................................49
24 The Coordinates of the Processor Pins as Viewed From the
Top of the Package .............................................................................................50
25 Example Pentium® 4 Processor in the 478-pin Package Thermal
Solution (Not to scale) .........................................................................................76
26 Guideline Locations for Case Temperature (TCASE) Thermocouple
Placement ...........................................................................................................78
27 Stop Clock State Machine ...................................................................................80
28 Mechanical Representation of the Boxed Pentium® 4 Processor in the
478-pin Package .................................................................................................85
29 Side View Space Requirements for the Boxed Processor ..................................86
30 Top View Space Requirements for the Boxed Processor ...................................87
31 Boxed Processor Fan Heatsink Power Cable Connector Description.................88
32 MotherBoard Power Header Placement Relative to Processor Socket ..............89
33 Boxed Processor Fan Heatsink Airspace Keepout
Requirements (side 1 view).................................................................................90
34 Boxed Processor Fan Heatsink Airspace Keepout
Requirements (side 2 view).................................................................................91
35 Boxed Processor Fan Heatsink Set Points .........................................................91
5
Contents
Tables
1 References ........................................................................................................... 9
2 Voltage Identification Definition .......................................................................... 13
3 System Bus Pin Groups ..................................................................................... 17
4 BSEL[1:0] Frequency Table for BCLK[1:0] ........................................................ 18
5 Processor DC Absolute Maximum Ratings ........................................................ 19
6 Voltage and Current Specifications .................................................................... 20
7 Vcc Static and Transient Tolerance ................................................................... 21
8 System Bus Differential BCLK Specifications .................................................... 22
9 AGTL+ Signal Group DC Specifications ............................................................ 23
10 Asynchronous GTL+ Signal Group DC Specifications ....................................... 23
11 TAP Signal Group DC Specifications ................................................................. 24
12 AGTL+ Bus Voltage Definitions .......................................................................... 25
13 System Bus Differential Clock Specifications ..................................................... 26
14 System Bus Common Clock AC Specifications ................................................. 26
15 System Bus Source Synch AC Specifications AGTL+ Signal Group ................. 26
16 Asynchronous GTL+ Signals AC Specifications ................................................ 28
17 System Bus AC Specifications (Reset Conditions) ............................................ 28
18 TAP Signals AC Specifications .......................................................................... 28
19 BCLK Signal Quality Specifications ................................................................... 35
20 Ringback Specifications for AGTL+, Asynchronous GTL+, and
TAP Signal Groups ............................................................................................ 36
21 Source Synchronous (400MHz) AGTL+ Signal Group
Overshoot/Undershoot Tolerance ...................................................................... 41
22 Source Synchronous (200MHz) AGTL+ Signal Group
23 Common Clock (100MHz) AGTL+ Signal Group
24 Asynchronous GTL+ and TAP Signal Groups
25 Description Table for Processor Dimensions ..................................................... 46
26 Package Dynamic and Static Load Specifications ............................................. 48
27 Processor Mass ................................................................................................. 49
28 Processor Material Properties ............................................................................ 49
29 Pin Listing by Pin Name ..................................................................................... 52
30 Pin Listing by Pin Number .................................................................................. 59
31 Signal Description .............................................................................................. 67
32 Pentium® 4 Processor in the 478-pin Package Thermal Design Power ............ 77
33 Power-On Configuration Option Pins ................................................................. 79
34 Thermal Diode Parameters ................................................................................ 84
35 Thermal Diode Interface ..................................................................................... 84
36 Fan Heatsink Power and Signal Specifications .................................................. 89
37 Boxed Processor Fan Heatsink Set Points ........................................................ 92
6
Intel® Pentium® 4 Processor in the 478-pin Package
1.0 Introduction
The Intel® Pentium® 4 Processor in the 478-pin Package is a follow on to the Pentium® 4
processor in the 423-pin package with Intel® NetBurstTM micro-architecture. The Pentium
4 processor in the 478-pin package utilizes Flip-Chip Pin Grid Array (FC-PGA2) package
technology, and plugs into a 478-pin surface mount, Zero Insertion Force (ZIF) socket,
referred to as the mPGA478B socket. The Pentium 4 processor in the 478-pin package
like its predecessor, the Pentium 4 processor in the 423-pin package, is based on the
same Intel 32-bit micro-architecture, and maintains the tradition of compatibility with IA-32
software.
The Pentium 4 processor in the 478-pin package uses the same 0.18 micron processor
core as the Pentium 4 processor in the 423-pin package and is designed for single
processor desktop systems. The Intel NetBurst micro-architecture features include hyper
pipelined technology, a rapid execution engine, a 400 MHz system bus, and an execution
trace cache. The hyper pipelined technology doubles the pipeline depth in the Pentium 4
processor, allowing the processor to reach much higher core frequencies. The rapid
execution engine allows the two integer ALUs in the processor to run at twice the core
frequency, which allows many integer instructions to execute in 1/2 clock tick. The 400
MHz system bus is a quad-pumped bus running off a 100 MHz system clock making 3.2
GB/sec data transfer rates possible. The execution trace cache is a first level cache that
stores approximately 12k decoded micro-operations, which removes the decoder from the
main execution path, thereby increasing performance.
Additional features within the Intel NetBurst micro-architecture include advanced dynamic
execution, advanced transfer cache, enhanced floating point and multi-media unit, and
Streaming SIMD Extensions 2 (SSE2). The advanced dynamic execution improves
speculative execution and branch prediction internal to the processor. The advanced
transfer cache is a 256KB, on-die level 2 (L2) cache with increased bandwidth over
previous micro-architectures. The floating point and multi-media units have been
improved by making the registers 128 bits wide and adding a separate register for data
movement. Finally, SSE2 adds 144 new instructions for double-precision floating point,
SIMD integer, and memory management. Power management capabilities such as
AutoHALT, Stop-Grant, Sleep, and Deep Sleep have also been retained.
The Streaming SIMD Extensions 2 enable break-through levels of performance in

multimedia applications including 3-D graphics, video decoding/encoding, and speech
recognition. The new packed double-precision floating-point instructions enhance
performance for applications that require greater range and precision, including scientific
and engineering applications and advanced 3-D geometry techniques, such as ray
tracing.
The Pentium 4 processor in the 478-pin package 400 MHz Intel NetBurst micro-
architecture system bus utilizes a split-transaction, deferred reply protocol like the
Pentium 4 processor in the 423-pin package. This system bus is not compatible with the
P6 processor family bus. The 400 MHz Intel NetBurst micro-architecture system bus uses
Source-Synchronous Transfer (SST) of address and data to improve performance by
transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with
the 4X data bus, the address bus can deliver addresses two times per bus clock and is
referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus
and 2X address bus provide a data bus bandwidth of up to 3.2 Gbytes/second.
7
Intel will be enabling support components for the Pentium 4 processor in the 478-pin
package including heatsink, heat sink retention mechanism, and socket. Manufacturability
is a high priority; hence, mechanical assembly can be completed from the top of the
motherboard and should not require any special tooling. The enabled components for the
478-pin package will be similar but different from the enabled components for the 423-pin
package due to package stackup differences.
The processor system bus uses a variant of GTL+ signalling technology called Assisted
Gunning Transceiver Logic (AGTL+) signalling technology.
1.1 Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the
active state when driven to a low level. For example, when RESET# is low, a reset has
been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In
the case of signals where the name does not imply an active state but describes part of a
binary sequence (such as address or data), the ‘#’ symbol implies that the signal is
inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers
to a hex ‘A’ (H= High logic level, L= Low logic level).
“System Bus” refers to the interface between the processor and system core logic (a.k.a.
the chipset components). The system bus is a multiprocessing interface to processors,
memory, and I/O.
1.1.1 Processor Packaging Terminology

Commonly used terms are explained here for clarification:
• Pentium® 4 processor in the 478-pin package (also referred as the Processor)
— 0.18 micron Pentium® 4 processor core in the FC-PGA2 package.
• Pentium® 4 processor in the 423-pin package — 0.18 micron Pentium® 4
processor core in the PGA package.
• Processor — For this document, the term processor is the generic form of Pentium 4
processor in the 478-pin package.
• Keep out zone — The area on or near the processor that system design can not
utilize.
• Intel® 850 chipset— Chipset which supports RDRAM* memory technology for the
Intel® Pentium® 4 Processor in the 478-pin Package..
• Processor core — Processor core die with integrated L2 cache.
• FC-PGA2 package — Flip-Chip Pin Grid Array package with 50 mil pin pitch and
Integrated Heat Spreader.
• mPGA478B socket — Surface mount, 478 pin, Zero Insertion Force (ZIF) socket with
50 mil pin pitch. Mates the processor to the system board.
• Integrated heat spreader —The surface used to make contact between a heatsink or
other thermal solution and the processor. Abbreviated IHS.
• Retention mechanism —The structure mounted on the system board which provides
support and retention of the processor heatsink.
8
1.2 References
Material and concepts available in the following documents may be beneficial when
reading this document:
Table 1. References
Document Order Number1
Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850

249888
Chipset Platform Design Guide
Intel® Pentium® 4 Processor in the 478-pin Package Thermal Design
249889
Guide
Intel® Pentium® 4 Processor VR-Down Design Guidelines 249891
CK00 Clock Synthesizer/Driver Design Guidelines 249206
Intel® Pentium® 4 Processor 478-Pin Socket (mPGA478B) Design
249890
Guidelines
Intel® Architecture Software Developer's Manual 243193
Volume I: Basic Architecture 243190
Volume II: Instruction Set Reference 243191
Volume III: System Programming Guide 243192
Intel® Pentium® 4 Processor in the 478-pin Package I/O Buffer Models2
Intel® Pentium® 4 Processor in the 478-pin Package Overshoot Checker
ITP700 Debug Port Design Guide
Note:
1. Contact your Intel representative for the latest revision of the documents without order
numbers.
2. The I/O Buffer Models are in IBIS format.
9
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10
2.0 Electrical Specifications
2.1 System Bus and GTLREF

Most Pentium® 4 processor in the 478-pin package system bus signals use Assisted
Gunning Transceiver Logic (AGTL+) signalling technology. As with the Intel P6 family of
microprocessors, this signalling technology provides improved noise margins and
reduced ringing through low voltage swings and controlled edge rates. Like the Pentium®
4 processor in the 423-pin package, the termination voltage level for the Pentium 4
processor in the 478-pin package AGTL+ signals is VCC, which is the operating voltage of
the processor core. The use of a termination voltage that is determined by the processor
core allows better voltage scaling on the system bus for the Pentium 4 processor in the
478-pin package. Because of the speed improvements to data and address bus, signal
integrity and platform design methods have become more critical than with previous
processor families. Design guidelines for the Pentium 4 processor in the 478-pin package
system bus are detailed in the Intel® Pentium® 4 Processor in the 478-pin Package and
Intel® 850 Chipset Platform Design Guide.
The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
system board (see Table 12 for GTLREF specifications). Termination resistors are
provided on the processor silicon and are terminated to its core voltage (VCC). Intel
chipsets will also provide on-die termination, thus eliminating the need to terminate the
bus on the system board for most AGTL+ signals.
Some AGTL+ signals do not include on-die termination and must be terminated on the
system board. See Table 3 for details regarding these signals.
The AGTL+ bus depends on incident wave switching. Therefore timing calculations for
AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal
simulation of the system bus, including trace lengths, is highly recommended when
designing a system.
2.2 Power and Ground Pins

For clean on-chip power distribution, the Pentium 4 processor in the 478-pin package has
85 VCC (power) and 181 VSS (ground) inputs. All power pins must be connected to VCC,
while all VSS pins must be connected to a system ground plane.The processor VCC pins
must be supplied the voltage determined by the VID (Voltage ID) pins.
2.3 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large average current swings between low and full power states.
This may cause voltages on power planes to sag below their minimum values if bulk
decoupling is not adequate. Care must be taken in the board design to ensure that the
voltage provided to the processor remains within the specifications listed in Table 6.
Failure to do so can result in timing violations or reduced lifetime of the component. For
11
further information and design guidelines, refer to the Intel® Pentium® 4 Processor in the
478-pin Package and Intel® 850 Chipset Platform Design Guide and the Intel® Pentium®
4 Processor VR-Down Design Guidelines.
2.3.1 VCC Decoupling

Regulator solutions need to provide bulk capacitance with a low Effective Series
Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket.
Bulk decoupling for the large current swings when the part is powering on, or entering/
exiting low power states, must be provided by the voltage regulator solution (VR). For
more details on this topic, refer to the Intel® Pentium® 4 Processor in the 478-pin
Package and Intel® 850 Chipset Platform Design Guide, and the Intel® Pentium® 4
Processor VR-Down Design Guidelines.
2.3.2 System Bus AGTL+ Decoupling

The Pentium 4 processor in the 478-pin package integrates signal termination on the die
as well as incorporates high frequency decoupling capacitance on the processor package.
Decoupling must also be provided by the system motherboard for proper AGTL+ bus
operation. For more information, refer to the Intel® Pentium® 4 Processor in the 478-pin
Package and Intel® 850 Chipset Platform Design Guide.
2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the system bus interface speed as well as the core frequency
of the processor. As in previous generation processors, the Pentium 4 processor in the
478-pin package core frequency is a multiple of the BCLK[1:0] frequency. The Pentium 4
processor in the 478-pin package bus ratio multiplier will be set at its default ratio during
manufacturing. No jumpers or user intervention is necessary, and the processor will
automatically run at the speed indicated on the package.
Like the Pentium 4 processor in the 423-pin package, the Pentium 4 processor in the 478-
pin package uses a differential clocking implementation. For more information on the
Pentium 4 processor in the 478-pin package clocking refer to the CK00 Clock
Synthesizer/Driver Design Guidelines.
2.4 Voltage Identification

The VID specification for Pentium 4 processor in the 478-pin package is supported by the
Intel® Pentium® 4 Processor VR-Down Design Guidelines. The voltage set by the VID
pins is the maximum voltage allowed by the processor. A minimum voltage is provided in
Table 6 and changes with frequency. This allows processors running at a higher frequency
to have a relaxed minimum voltage specification. The specifications have been set such
that one voltage regulator can work with all supported frequencies.
The Pentium 4 processor in the 478-pin package uses five voltage identification pins,
VID[4:0], to support automatic selection of power supply voltages. Table 2 specifies the
voltage level corresponding to the state of VID[4:0]. A ‘1’ in this table refers to a high
voltage level and a ‘0’ refers to low voltage level. The definition provided in Table 2 is not
related in any way to previous P6 processors or VRs, but is compatible with Pentium 4
12
processor in the 423-pin package. If the processor socket is empty (VID[4:0] = 11111), or
the voltage regulation circuit cannot supply the voltage that is requested, it must disable
itself. See the Intel® Pentium® 4 Processor VR-Down Design Guidelines for more details.
Power source characteristics must be guaranteed to be stable whenever the supply to the
voltage regulator is stable.
Table 2. Voltage Identification Definition

Processor Pins
VID4 VID3 VID2 VID1 VID0 VCC_MAX

1 1 1 1 1 VRM output off
1 1 1 1 0 1.100
1 1 1 0 1 1.125
1 1 1 0 0 1.150
1 1 0 1 1 1.175
1 1 0 1 0 1.200
1 1 0 0 1 1.225
1 1 0 0 0 1.250
1 0 1 1 1 1.275
1 0 1 1 0 1.300
1 0 1 0 1 1.325
1 0 1 0 0 1.350
1 0 0 1 1 1.375
1 0 0 1 0 1.400
1 0 0 0 1 1.425
1 0 0 0 0 1.450
0 1 1 1 1 1.475
0 1 1 1 0 1.500
0 1 1 0 1 1.525
0 1 1 0 0 1.550
0 1 0 1 1 1.575
0 1 0 1 0 1.600
0 1 0 0 1 1.625
0 1 0 0 0 1.650
0 0 1 1 1 1.675
0 0 1 1 0 1.700
0 0 1 0 1 1.725
0 0 1 0 0 1.750
0 0 0 1 1 1.775
0 0 0 1 0 1.800
0 0 0 0 1 1.825
0 0 0 0 0 1.850
13
2.4.1 Phase Lock Loop (PLL) Power and Filter

VCCA and VCCIOPLL are power sources required by the PLL clock generators on the
Pentium 4 processor in the 478-pin package silicon. Since these PLLs are analog in
nature, they require quiet power supplies for minimum jitter. Jitter is detrimental to the
system: it degrades external I/O timings as well as internal core timings (i.e. maximum
frequency). To prevent this degradation, these supplies must be low pass filtered from
VCC. A typical filter topology is shown in Figure 1.
The AC low-pass requirements, with input at VCC and output measured across the
capacitor (CA or CIO in Figure 1), is as follows:
• < 0.2 dB gain in pass band
• < 0.5 dB attenuation in pass band < 1 Hz (see DC drop in next set of requirements)
• > 34 dB attenuation from 1 MHz to 66 MHz
• > 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in Figure 2. For recommendations on implementing

the filter refer to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850
Chipset Platform Design Guide.
Figure 1. Typical VCCIOPLL, VCCA and VSSA Power Distribution
VCC L
R VCCA
CA PLL
Processor
VSSA Core
CIO
R VCCIOPLL
L
14
.
Figure 2. Phase Lock Loop (PLL) Filter Requirements
0.2 dB
0 dB
-0.5 dB
forbidden
zone
-28 dB
forbidden
zone
-34 dB
DC 1 Hz fpeak 1 MHz 66 MHz fcore
passband high frequency

band
NOTES:
1. Diagram not to scale.
2. No specification for frequencies beyond fcore (core frequency).
3. fpeak, if existent, should be less than 0.05 MHz.
2.5 Reserved, Unused, and TESTHI Pins

All RESERVED pins must remain unconnected. Connection of these pins to VCC, VSS, or
to any other signal (including each other) can result in component malfunction or
incompatibility with a future Pentium 4 processor in the 478-pin package. See Chapter 5.0
for a pin listing of the processor and the location of all RESERVED pins.
For reliable operation, always connect unused inputs or bidirectional signals to an

appropriate signal level. In a system level design, on-die termination has been included on
the Pentium 4 processor to allow signals to be terminated within the processor silicon.
Most unused AGTL+ inputs should be left as no connects, as AGTL+ termination is
provided on the processor silicon. However, see Table 3 for details on AGTL+ signals that
do not include on-die termination. Unused active high inputs should be connected through
a resistor to ground (VSS). Unused outputs can be left unconnected, however this may
interfere with some TAP functions, complicate debug probing, and prevent boundary scan
testing. A resistor must be used when tying bidirectional signals to power or ground. When
tying any signal to power or ground, a resistor will also allow for system testability. For
unused AGTL+ input or I/O signals, use pull-up resistors of the same value for the on-die
termination resistors (RTT). See Table 12.
15
TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Input and used outputs must be terminated on the system board. Unused
outputs may be terminated on the system board or left unconnected. Note that leaving
unused output unterminated may interfere with some TAP functions, complicate debug
probing, and prevent boundary scan testing. Signal termination for these signal types is
discussed in the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850
Chipset Platform Design Guide and the ITP700 Debug Port Design Guide.
TESTHI[11:8] and TESTHI1 must be connected to VCC via a pull-up resistor. TESTHI[5:2],
TESTHI0, and TESTHI12 must be connected to VCC via a pull-up resistor or be tied
directly to VCC. The TESTHI pins may use individual pull-up resistors or be grouped
together as detailed below. If connected individually use pull-up resistors with values
between 1 kΩ and 10 kΩ. If connected in groups use a single pull-up resistor per group
with a value between 1 kΩ and 4.7 kΩ. The groupings are as follows: 1) TESTHI[1:0], 2)
TESTHI[5:2], 3) TESTHI[10:8], and 4) TESTHI[12:11].
Additionally, if the ITPCLKOUT[1:0] pins are not used (refer to Section 5.2) then they may
be tied directly to VCC, connected individually to VCC using pull-up resistors with values
between 1 kΩ and 10 kΩ, or grouped with TESTHI[5:2] with a single pull-up resistor with a
value between 1 kΩ and 4.7 kΩ. Tying ITPCLKOUT[1:0] directly to VCC or sharing a pull-
up resistor to VCC will prevent use of debug interposers. This implementation is strongly
discouraged for system boards that do not implement an onboard debug port.
2.6 System Bus Signal Groups

In order to simplify the following discussion, the system bus signals have been combined
into groups by buffer type. AGTL+ input signals have differential input buffers, which use
GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the
AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+
Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two
sets of timing parameters. One set is for common clock signals which are dependent upon
the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source
synchronous signals which are relative to their respective strobe lines (data and address)
as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#,
IGNNE#, etc.) and can become active at any time during the clock cycle. Table 3 identifies
which signals are common clock, source synchronous, and asynchronous.
16
Table 3. System Bus Pin Groups

Signal Group Type Signals1
Synchronous
AGTL+ Common Clock Input BPRI#, DEFER#, RESET#2, RS[2:0]#, RSP#, TRDY#
to BCLK[1:0]
AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#2, BR0#2,
Synchronous
AGTL+ Common Clock I/O DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#,
to BCLK[1:0]
MCERR#
Signals Associated Strobe
REQ[4:0]#, A[16:3]#5 ADSTB0#

Synchronous
AGTL+ Source Synchronous I/O to assoc. A[35:17]#5 ADSTB1#
strobe D[15:0]#, DBI0# DSTBP0#, DSTBN0#
D[31:16]#, DBI1# DSTBP1#, DSTBN1#
Synchronous
AGTL+ Strobes ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
to BCLK[1:0]
A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI,
Asynchronous GTL+ Input4, 5
PWRGOOD, SMI#, SLP#, STPCLK#
Asynchronous GTL+ Output4 FERR#, IERR#2, THERMTRIP#, PROCHOT#
Synchronous
TAP Input4 TCK, TDI, TMS, TRST#
to TCK
Synchronous
TAP Output4 TDO
to TCK
System Bus Clock Clock BCLK[1:0], ITP_CLK[1:0]3
VCC, VCCA, VCCIOPLL, VID[4:0], VSS, VSSA, GTLREF[3:0],
COMP[1:0], RESERVED, TESTHI[12:8], TESTHI[5:0],
Power/Other
THERMDA, THERMDC, VCC_SENSE, VSS_SENSE,
VCCVID, BSEL[1:0], SKTOCC#, DBR3, ITPCLKOUT[1:0]
NOTE:
1. Refer to Section 5.2 for signal descriptions.
2. These AGTL+ signals do not have on-die termination and must be terminated on the system board.
3. In processor systems where there is no debug port implemented on the system board, these signals are used
to support a debug port interposer. In systems with the debug port implemented on the system board, these
signals are no connects.
4. These signal groups are not terminated by the processor. Refer to Section 2.5, the ITP700 Debug Port
Design Guide, and the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform
Design Guide for termination requirements and further details.
5. The value of these pins during the active-to-inactive edge of RESET# determine processor configuration
options. See Section 7.1 for details.
2.7 Asynchronous GTL+ Signals

The Pentium 4 processor in the 478-pin package does not utilize CMOS voltage levels on
any signals that connect to the processor. As a result, legacy input signals such as
A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, and
17
STPCLK# utilize GTL+ input buffers. Legacy output FERR# and other non-AGTL+ signals
(THERMTRIP# and PROCHOT#) utilize GTL+ output buffers. All of these signals follow
the same DC requirements as AGTL+ signals, however the outputs are not actively driven
high (during a logical 0 to 1 transition) by the processor (the major difference between
GTL+ and AGTL+). These signals do not have setup or hold time specifications in relation
to BCLK[1:0]. However, all of the Asynchronous GTL+ signals are required to be asserted
for at least two BCLKs in order for the processor to recognize them. See Section 2.11 and
Section 2.13 for the DC and AC specifications for the Asynchronous GTL+ signal groups.
See section Section 7.2 for additional timing requirements for entering and leaving the low
power states.
2.8 Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the Pentium 4 processor in the 478-pin package be first in
the TAP chain and followed by any other components within the system. A translation
buffer should be used to connect to the rest of the chain unless one of the other
components is capable of accepting an input of the appropriate voltage level. Similar
considerations must be made for TCK, TMS, TRST#, TDI, and TDO. Two copies of each
signal may be required, with each driving a different voltage level.
2.9 System Bus Frequency Select Signals (BSEL[1:0])

The BSEL[1:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). Table 4 defines the possible combinations of the signals and the frequency
associated with each combination. The required frequency is determined by the
processor, chipset, and clock synthesizer. All agents must operate at the same frequency.
The Pentium 4 processor in the 478-pin package currently operates at a 400 MHz system
bus frequency (selected by a 100 MHz BCLK[1:0] frequency). Individual processors will
only operate at their specified system bus frequency.
For more information about these pins refer to Section 5.2 and the appropriate platform
design guidelines.
Table 4. BSEL[1:0] Frequency Table for BCLK[1:0]

BSEL1 BSEL0 Function
L L 100 MHz
L H RESERVED
H L RESERVED
H H RESERVED
2.10 Maximum Ratings

Table 5 lists the processor’s maximum environmental stress ratings. Functional operation
at the absolute maximum and minimum is neither implied nor guaranteed. The processor
should not receive a clock while subjected to these conditions. Functional operating
18
parameters are listed in the AC and DC tables. Extended exposure to the maximum
ratings may affect device reliability. Furthermore, although the processor contains
protective circuitry to resist damage from electro static discharge (ESD), one should
always take precautions to avoid high static voltages or electric fields.
Table 5. Processor DC Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes
Processor storage
TSTORAGE –40 85 °C 2
temperature
Any processor supply
VCC –0.5 2.10 V 1
voltage with respect to VSS
AGTL+ buffer DC input
VinAGTL+ –0.3 2.10 V
voltage with respect to VSS
Asynch GTL+ buffer DC
VinAsynch_GTL+ input voltage with respect –0.3 2.10 V
to VSS
IVID Max VID pin current 5 mA
NOTE:
1. This rating applies to any processor pin.
2. Contact Intel for storage requirements in excess of one year.
2.11 Processor DC Specifications

The processor DC specifications in this section are defined at the processor core
silicon and not at the package pins unless noted otherwise. See Chapter 5.0 for the
pin signal definitions and signal pin assignments. Most of the signals on the processor
system bus are in the AGTL+ signal group. The DC specifications for these signals are
listed in Table 9.
Previously, legacy signals and Test Access Port (TAP) signals to the processor used low-
voltage CMOS buffer types. However, these interfaces now follow DC specifications
similar to GTL+. The DC specifications for these signal groups are listed in Table 11.
Table 6 through Table 11 list the DC specifications for the Pentium 4 processor in the 478-
pin package and are valid only while meeting specifications for case temperature, clock
frequency, and input voltages. Care should be taken to read all notes associated with
each parameter.
19
Table 6. Voltage and Current Specifications

Symbol Parameter Min Typ Max Unit Notes1, 9
VCC for processor at

1.50 GHz 1.580
1.60 GHz 1.570
VCC 1.70 GHz 1.565 Refer to Table 7 and Figure 3 V 2, 3, 4, 5
1.80 GHz 1.560
1.90 GHz 1.545
2 GHz 1.540
ICC for processor at
1.50 GHz 43.5
1.60 GHz 45.9
ICC 1.70 GHz 48.1 A
1.80 GHz 50.4
1.90 GHz 55.2
2 GHz 57.4
ICC Stop-Grant
1.50 GHz 12.4
1.60 GHz 12.6
ISGNT
1.70 GHz 12.9 A 6, 8
ISLP
1.80 GHz 13.1
1.90 GHz 16.5
2 GHz 16.7
ITCC ICC TCC active ICC A 7
ICC PLL ICC for PLL pins 30 mA
NOTES:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations, not empirical
data. These specifications will be updated with characterized data from silicon measurements at a later date.
2. These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required. See Section 2.4 and Table 2 for more information.
3. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE pins at the socket with
a 100MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The
maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the
system is not coupled into the scope probe.
4. Refer to Table 7 and Figure 3 for the minimum, typical, and maximum VCC allowed for a given current. The
processor should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given
current. Moreover, VCC should never exceed the VID voltage. Failure to adhere to this specification can
shorten the processor lifetime.
5. VCC_MIN is defined at ICC_MAX.
6. The current specified is also for AutoHALT State.
7. The maximum instantaneous current the processor will draw while the thermal control circuit is active as
indicated by the assertion of PROCHOT# is the same as the maximum ICC for the processor.
8. ICC Stop-Grant and ICC Sleep are specified at VCC_MAX.
9. These specifications apply to processors with a VID setting of 1.75V.
20
Table 7. Vcc Static and Transient Tolerance

Voltage Deviation from VID Setting (V)1, 2, 3
Icc (A)
Maximum Typical Minimum
0 0.000 -0.025 -0.050

5 -0.010 -0.037 -0.064
10 -0.019 -0.048 -0.078
15 -0.029 -0.060 -0.092
20 -0.038 -0.072 -0.106
25 -0.048 -0.083 -0.120
30 -0.057 -0.095 -0.133
35 -0.067 -0.107 -0.147
40 -0.076 -0.119 -0.161
45 -0.085 -0.130 -0.175
50 -0.095 -0.142 -0.189
55 -0.105 -0.154 -0.203
60 -0.114 -0.165 -0.217
65 -0.124 -0.177 -0.231
70 -0.133 -0.189 -0.245
NOTES:
1. The loadline specifications include both static and transient limits.
2. This table is intended to aid in reading descrete points on Figure 3.
3. The loadlines specify voltage limits at the die measured at the VCC_sense and VSS_sense pins. Voltage
regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer to
the Intel® Pentium® 4 Processor VR-Down Design Guidelines for socket loadline guidelines and VR
implementation details.
21
Figure 3. Vcc Static and Transient Tolerance1, 2, 3
1.800
1.750
1.700
Vcc Maximum
1.650
Vcc [V]
Vcc Typical
1.600
Vcc Minimum
1.550
1.500
1.450
0 10 20 30 40 50 60 70 80
Icc Load [A]
NOTES:
1. The loadline specification includes both static and transient limits.
2. This loadline specification applies to processors with a VID setting of 1.75V.
3. The loadlines specify voltage limits at the die measured at the VCC_sense and VSS_sense pins. Voltage
regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer to
the Intel® Pentium® 4 Processor VR-Down Design Guidelines for socket loadline guidelines and VR
Table 8. System Bus Differential BCLK Specifications

Symbol Parameter Min Typ Max Unit Figure Notes1
VL Input Low Voltage 0 V 6

VH Input High Voltage 0.660 0.710 0.850 V 6
VCROSS Crossing Voltage 0.45*(VH-VL) 0.5*(VH-VL) 0.55*(VH-VL) V 6 2, 3
VOV Overshoot N/A N/A VH + 0.3 V 6 4
VUS Undershoot VL - 0.3 N/A N/A V 6 5
VRBM Ringback Margin 0.200 N/A N/A V 6 6
VTH Threshold Region VCROSS -0.100 VCROSS+0.100 V 6 7
NOTES:.
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of
BCLK1.
3. The VL and VH used to calculate VCROSS are the actual VL and VH seen by the processor.
22
4. Overshoot is defined as the absolute value of the maximum voltage allowed above the VH level.
5. Undershoot is defined as the absolute minimum voltage value allowed below the VSS level.
6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback
and the maximum Falling Edge Ringback.
7. Threshold Region is defined as a region entered about the crossing voltage in which the differential receiver
switches. It includes input threshold hysteresis.
Table 9. AGTL+ Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes1
VIL Input Low Voltage 0.0 GTLREF - 0.100 V 2, 6

VIH Input High Voltage GTLREF + 0.100 VCC V 3, 4, 6
VOH Output High Voltage N/A VCC V 4, 6
IOL Output Low Current N/A 64 mA 7
ILI Input Leakage Current N/A ± 100 µA
ILO Output Leakage Current N/A ± 100 µA
RON Buffer On Resistance 5 11 Ω 5
NOTES:
2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
4. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the
signal quality specifications in Chapter 3.0.
5. Refer to processor I/O Buffer Models for I/V characteristics.
6. The VCC referred to in these specifications is the instantaneous VCC.
7. VOL_MAX of 0.560 V is guaranteed when driving into a test load of 50 ohms as indicated in Figure 4, with RTT
enabled.
Table 10. Asynchronous GTL+ Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes1
VIL Input Low Voltage 0.0 GTLREF-0.100 3

VIH Input High Voltage GTLREF+0.100 VCC 4, 5, 7
VOH Output High Voltage VCC V 2, 5, 7
IOL Output Low Current 64 mA 8, 9
ILI Input Leakage Current N/A ± 100 µA
ILO Output Leakage Current N/A ± 100 µA
RON Buffer On Resistance 5 11 Ω 6
NOTES:
2. All outputs are open drain.
3. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the
signal quality specifications in Chapter 3.0.
6. Refer to the processor I/O Buffer Models for I/V characteristics.
7. The VCC referred to in these specifications refers to instantaneous VCC.
8. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
9. VOL_MAX of 0.560 V is guaranteed when driving into a test load of 50 ohms as indicated in Figure 4, with Rtt
enabled.
23
Table 11. TAP Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes1, 2
VHYS TAP Input Hysteresis 200 300 mV 8

TAP input low to high
VT+ (0.5 * VCC) + 0.100 (0.5 * VCC) + 0.150 V 5
threshold voltage
TAP input high to low
VT- (0.5 * VCC) - 0.150 (0.5 * VCC) - 0.100 V 5
threshold voltage
VOH Output High Voltage N/A VCC V 3, 5
IOL Output Low Current 45 mA 6, 7
ILI Input Leakage Current ± 100 µA
ILO Output Leakage Current ± 100 µA
RON Buffer On Resistance 6.25 13.25 Ω 4
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. All outputs are open drain
3. VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality
specifications in Chapter 3.0.
4. Refer to the processor I/O Buffer Models for I/V characteristics.
5. The VCC referred to in these specifications refers to instantaneous VCC.
6. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
7. VOL_MAX of 0.360 V is guaranteed when driving into a test load as indicated in Figure 4.
8. VHYS represents the amount of hysteresis, nominally centered about 1/2 Vcc, for all TAP inputs.
2.12 AGTL+ System Bus Specifications

Routing topology recommendations may be found in the Intel® Pentium® 4 Processor in
the 478-pin Package and Intel® 850 Chipset Platform Design Guide. Termination resistors
are not required for most AGTL+ signals, as these are integrated into the processor
silicon.
Valid high and low levels are determined by the input buffers which compare a signal’s
voltage with a reference voltage called GTLREF (known as VREF in previous
documentation).
Table 12 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should
be generated on the system board using high precision voltage divider circuits. It is
important that the system board impedance is held to the specified tolerance, and that the
intrinsic trace capacitance for the AGTL+ signal group traces is known and well-controlled.
For more details on platform design see the Intel® Pentium® 4 Processor in the 478-pin
24
Table 12. AGTL+ Bus Voltage Definitions

Symbol Parameter Min Typ Max Units Notes1
Bus Reference
GTLREF 2/3 VCC - 2% 2/3 VCC 2/3 VCC + 2% V 2, 3, 6
Voltage
Termination
RTT 45 50 55 Ω 4
Resistance
COMP
COMP[1:0] 50.49 51 51.51 Ω 5
Resistance
NOTES:
2. The tolerances for this specification have been stated generically to enable the system designer to calculate
the minimum and maximum values across the range of VCC.
3. GTLREF should be generated from VCC by a voltage divider of 1% resistors or 1% matched resistors. Refer
to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide
for implementation details.
4. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Refer to processor I/O
buffer models for I/V characteristics.
5. COMP resistance must be provided on the system board with 1% resistors. See the Intel® Pentium® 4
Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for implementation details.
6. The VCC referred to in these specifications is the instantaneous VCC.
2.13 System Bus AC Specifications

The processor system bus timings specified in this section are defined at the
processor core silicon and are thus not measurable at the processor pins. See
Chapter 5.0 for the Pentium 4 processor in the 478-pin package pin signal definitions.
Table 13 through Table 18 list the AC specifications associated with the processor system
bus.
All AGTL+ timings are referenced to GTLREF for both ‘0’ and ‘1’ logic levels unless
otherwise specified.
The timings specified in this section should be used in conjunction with the I/O buffer
models provided by Intel. These I/O buffer models, which include package information,
are available for the Pentium 4 processor in the 478-pin package in IBIS format. AGTL+
layout guidelines are also available in the Intel® Pentium® 4 Processor in the 478-pin
Care should be taken to read all notes associated with a particular timing parameter.
25
Table 13. System Bus Differential Clock Specifications

T# Parameter Min Nom Max Unit Figure Notes1
System Bus Frequency 100 MHz

T1: BCLK[1:0] Period 10.0 10.2 ns 6 2
T2: BCLK[1:0] Period Stability 200 ps 6 3, 4
T3: BCLK[1:0] High Time 3.94 5 6.12 ns 6
T4: BCLK[1:0] Low Time 3.94 5 6.12 ns 6
T5: BCLK[1:0] Rise Time 175 700 ps 6 5
T6: BCLK[1:0] Fall Time 175 700 ps 6 5
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies.
2. The period specified here is the average period. A given period may vary from this specification as governed
by the period stability specification (T2).
3. For the clock jitter specification, refer to the CK00 Clock Synthesizer/Driver Design Guidelines.
4. In this context, period stability is defined as the worst case timing difference between successive crossover
voltages. In other words, the largest absolute difference between adjacent clock periods must be less than
the period stability.
5. Slew rate is measured between the 35% and 65% points of the clock swing (VL to VH).
.
Table 14. System Bus Common Clock AC Specifications

T# Parameter Min Max Unit Figure Notes1,2,3
T10: Common Clock Output Valid Delay 0.200 1.45 ns 7 4

T11: Common Clock Input Setup Time 0.65 N/A ns 7 5
T12: Common Clock Input Hold Time 0.40 N/A ns 7 5
T13: RESET# Pulse Width 1.00 10.00 ms 8 6, 7, 8
NOTES:
2. Not 100% tested. Specified by design characterization.
3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the
BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the
processor core.
4. Valid delay timings for these signals are specified into the test circuit described in Figure 4 and with GTLREF
at 2/3 VCC ± 2%.
5. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate
of 0.4 V/ ns to 4.0V/ns.
6. RESET# can be asserted asynchronously, but must be deasserted synchronously.
7. This should be measured after VCC and BCLK[1:0] become stable.
8. Maximum specification applies only while PWRGOOD is asserted.
.
Table 15. System Bus Source Synch AC Specifications AGTL+ Signal Group (Page 1 of 2)
T# Parameter Min Typ Max Unit Figure Notes1,2,3,4
T20: Source Synchronous Data Output

0.20 1.20 ns 9, 10 5
Valid Delay (first data/address only)
T21: TVBD: Source Synchronous Data
0.85 ns 10 5, 8
Output Valid Before Strobe
T22: TVAD: Source Synchronous Data
0.85 ns 10 5, 8
Output Valid After Strobe
26
Table 15. System Bus Source Synch AC Specifications AGTL+ Signal Group (Page 2 of 2)
T# Parameter Min Typ Max Unit Figure Notes1,2,3,4
T23: TVBA: Source Synchronous

1.88 ns 9 5, 8
Address Output Valid Before Strobe
T24: TVAA: Source Synchronous
1.88 ns 9 5, 9
Address Output Valid After Strobe
T25: TSUSS: Source Synchronous Input
0.21 ns 9, 10 6
Setup Time to Strobe
T26: THSS: Source Synchronous Input
0.21 ns 9, 10 6
Hold Time to Strobe
T27: TSUCC: Source Synchronous Input
0.65 ns 9, 10 7
Setup Time to BCLK[1:0]
T28: TFASS: First Address Strobe to
1/2 BCLK 9 10
Second Address Strobe
T29: TFDSS: First Data Strobe to
n/4 BCLK 10 11, 12
Subsequent Strobes
T30: Data Strobe ‘n’ (DSTBN#) Output
8.80 10.20 ns 10 13
Valid Delay
T31: Address Strobe Output Valid
2.27 4.23 ns 9
Delay
NOTE:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
3. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source
synchronous data signals are referenced to the falling edge of their associated data strobe. Source
synchronous address signals are referenced to the rising and falling edge of their associated address strobe.
All source synchronous AGTL+ signal timings are referenced at GTLREF at the processor core.
4. Unless otherwise noted these specifications apply to both data and address timings.
5. Valid delay timings for these signals are specified into the test circuit described in Figure 4 and with GTLREF
at 2/3 VCC ± 2%.
6. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate
of 0.3 V/ns to 4.0V/ns.
7. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each
respective strobe.
8. This specification represents the minimum time the data or address will be valid before its strobe. Refer to the
Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for more
information on the definitions and use of these specifications.
9. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the
Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for more
information on the definitions and use of these specifications.
10.The rising edge of ADSTB# must come approximately 1/2 BCLK period (5 ns) after the falling edge of
ADSTB#.
11. For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.
12.The second data strobe (falling edge of DSTBn#) must come approximately 1/4 BCLK period (2.5 ns) after
the first falling edge of DSTBp#. The third data strobe (falling edge of DSTBp#) must come approximately 2/4
BCLK period (5 ns) after the first falling edge of DSTBp#. The last data strobe (falling edge of DSTBn#) must
come approximately 3/4 BCLK period (7.5 ns) after the first falling edge of DSTBp#.
13.This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.
27
Table 16. Asynchronous GTL+ Signals AC Specifications

T# Parameter Min Max Unit Figure Notes1,2,3,6
T35: Asynch GTL+ Input Pulse Width, except

2 BCLKs
PWRGOOD
T36: PWRGOOD to RESET# de-assertion time 1 10 ms 11
T37: PWRGOOD Inactive Pulse Width 10 BCLKs 11 4
T38: PROCHOT# pulse width 500 us 13 5
T39: THERMTRIP# Assertion until Vcc removal 0.5 s 12
NOTES:
2. All AC timings for the Asynch GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage. All
Asynch GTL+ signal timings are referenced at GTLREF.
3. These signals may be driven asynchronously.
4. Refer to the PWRGOOD definition for more details regarding the behavior of this signal.
5. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the
assertion and before the deassertion of PROCHOT# for the processor to complete current instruction
execution.
6. See section Section 7.2 for additional timing requirements for entering and leaving the low power states.
Table 17. System Bus AC Specifications (Reset Conditions)

T# Parameter Min Max Unit Figure Notes
T45: Reset Configuration Signals (A[31:3]#,
4 BCLKs 8 1
BR0#, INIT#, SMI#) Setup Time
T46: Reset Configuration Signals (A[31:3]#,
2 20 BCLKs 8 2
BR0#, INIT#, SMI#) Hold Time
NOTES:
1. Before the deassertion of RESET#.
2. After clock that deasserts RESET#.
3. After the assertion of RESET#.
Table 18. TAP Signals AC Specifications

Parameter Min Max Unit Figure Notes1,2,3,9
T55: TCK Period 60.0 ns 5

T56: TCK Rise Time 9.5 ns 5 4
T57: TCK Fall Time 9.5 ns 5 4
T58: TMS, TDI Rise Time 8.5 ns 5 4
T59: TMS, TDI Fall Time 8.5 ns 5 4
T61: TDI, TMS Setup Time 0 ns 5, 7
T62: TDI, TMS Hold Time 3 ns 5, 7
T63: TDO Clock to Output Delay 0.5 3.5 ns 6
T64: TRST# Assert Time 2 TCK 13 8
NOTES:
3. All AC timings for the TAP signals are referenced to the TCK signal at GTLREF at the processor pins. All TAP
signal timings (TMS, TDI, etc) are referenced at VT+ and VT- at the processor pins.
4. Rise and fall times are measured from the 20% to 80% points of the signal swing.
28
5. Referenced to the rising edge of TCK.

6. Referenced to the falling edge of TCK.
7. Specification for a minimum swing defined between TAP VIL_MAX to VIH_MIN. This assumes a minimum edge
rate of 0.5V/ns.
8. TRST# must be held asserted for 2 TCK periods to be guarantee that it is recognized by the processor.
9. It is recommended that TMS be asserted while TRST# is being deasserted.
2.14 Processor AC Timing Waveforms

The following figures are used in conjunction with the AC timing tables, Table 13 through
Table 18.
Note: For Figure 5 through Figure 13, the following apply:
1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage
(VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal
timings are referenced at GTLREF at the processor core.
2. All source synchronous AC timings for AGTL+ signals are referenced to their
associated strobe (address or data) at GTLREF. Source synchronous data signals are
referenced to the falling edge of their associated data strobe. Source synchronous
address signals are referenced to the rising and falling edge of their associated address
strobe. All source synchronous AGTL+ signal timings are referenced at GTLREF at the
processor silicon.
3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at VCROSS. All
AGTL+ strobe signal timings are referenced at GTLREF at the processor silicon.
4. All AC timings for the TAP signals are referenced to the TCK signal at VT+ and VT- at
the processor pins. All TAP signal timings (TMS, TDI, etc) are referenced at the processor
pins.
The circuit used to test the AC specifications is shown in Figure 4.

Figure 4. AC Test Circuit
VCC
VCC Rload
600 mils, 42 ohms, 169 ps/in 2.4nH
1.2pF
AC Timings test measurements made here.
Rload = 50 ohms
29
Figure 5. TCK Clock Waveform
80%
50%
20%
tr = T56, T58 (Rise Time)

tf = T57, T59 (Fall Time)
tp = T55 (TCK Period)
Figure 6. Differential Clock Waveform
Tph
Overshoot
BCLK1 VH
Rising Edge
Ringback
Crossing Crossing Ringback
Threshold Voltage Voltage Margin
Region
Falling Edge
Ringback,
BCLK0
VL
Undershoot
Tpl
Tp
Tp = T1 (BCLK[1:0] period)
T2 = BCLK[1:0] Period stability (not shown)
Tph =T3 (BCLK[1:0] pulse high time)
Tpl = T4 (BCLK[1:0] pulse low time)
T5 = BCLK[1:0] rise time through the threshold region
T6 = BCLK[1:0] fall time through the threshold region
30
Figure 7. System Bus Common Clock Valid Delay Timings
T0 T1 T2
BCLK1
BCLK0
TP
Common Clock
valid valid
Signal (@ driver)
TQ TR
Common Clock
valid
Signal (@ receiver)
TP = T10: TCO (Data Valid Output Delay)

TQ = T11: TSU (Common Clock Setup)
TR = T12: TH (Common Clock Hold Time)
Figure 8. System Bus Reset and Configuration Timings
BCLK
RESET#
Tv
Tw Tx
Configuration
(A[31:3], BR0#,
INIT#, SMI#)
Tv = T13 (RESET# Pulse Width)

Tw = T45 (Reset Configuration Signals Setup Time)
Tx = T46 (Reset Configuration Signals Hold Time)
31
Figure 9. Source Synchronous 2X (Address) Timings
T1 T2
2.5 ns 5.0 ns 7.5 ns
BCLK1
BCLK0
TP
ADSTB# (@ driver)
TR
TH TJ TH TJ
A# (@ driver) valid valid
TS
ADSTB# (@ receiver)
TK
A# (@ receiver) valid valid
TN TM
TH = T23: Source Sync. Address Output Valid Before Address Strobe
TJ = T24: Source Sync. Address Output Valid After Address Strobe
TK = T27: Source Sync. Input Setup to BCLK
TM = T26: Source Sync. Input Hold Time
TN = T25: Source Sync. Input Setup Time
TP = T28: First Address Strobe to Second Address Strobe
TS = T20: Source Sync. Output Valid Delay
TR = T31: Address Strobe Output Valid Delay
32
Figure 10. Source Synchronous 4X Timings
T0 T1 T2
2.5 ns 5.0 ns 7.5 ns
BCLK1
BCLK0
DSTBp# (@ driver) TH
DSTBn# (@ driver)
TA TB TA TD
D# (@ driver)
TJ
DSTBp# (@ receiver)
DSTBn# (@ receiver)
TC
D# (@ receiver)
TE TG TE TG
TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe
TB = T22: Source Sync. Data Output Valid Delay After Data Strobe
TC = T27: Source Sync. Setup Time to BCLK
TD = T30: Source Sync. Data Strobe 'N' (DSTBN#) Output Valid Delay
TE = T25: Source Sync. Input Setup Time
TG = T26: Source Sync. Input Hold Time
TH = T29: First Data Strobe to Subsequent Strobes
TJ = T20: Source Sync. Data Output Valid Delay
Figure 11. Power-On Reset and Configuration Timings
BCLK
VCC, Vcc
core,
VREF
PWRGOOD
Ta Tb
RESET#
Tc
Configuration
(A20M#, IGNNE#, Valid Ratio
LINT[1:0])
Ta T= T37 (PWRGOOD
= T15 (PWRGOODInactive PulseWidth)
Inactive Pulse Width)
Tb T=a T36 (PWRGOOD
= T10 to RESET#
(RESET# Pulse Width) de-assertion time)
b
Tc T
=c T46, T49
= T20 (Reset
(Reset Configuration
Configuration SignalsSignals
(A20M#,Hold Time)
IGNNE#, LINT[1:0]) Hold Time)
33
Figure 12. THERMTRIP# Power Down Sequence
T39
THERMTRIP#
Vcc
T39 < 0.5 seconds

Note: THERMTRIP# is undefined when RESET# is active
Figure 13. Test Reset Timings
TRST# 1.25V
GTLREF
Tq
Tq = T64, T38 (TRST# Pulse Width, PROCHOT# Pulse Width)
Tq = T37 (TRST# Pulse Width)
PCB-773
34
3.0 System Bus Signal Quality Specifications
Source synchronous data transfer requires the clean reception of data signals and their
associated strobes. Ringing below receiver thresholds, non-monotonic signal edges, and
excessive voltage swing will adversely affect system timings. Ringback and signal non-
monotinicity cannot be tolerated since these phenomena may inadvertently advance
receiver state machines. Excessive signal swings (overshoot and undershoot) are
detrimental to silicon gate oxide integrity, and can cause device failure if absolute voltage
limits are exceeded. Additionally, overshoot and undershoot can cause timing degradation
due to the build up of inter-symbol interference (ISI) effects.
For these reasons, it is important that the designer work to achieve a solution that
provides acceptable signal quality across all systematic variations encountered in volume
manufacturing.
This section documents signal quality metrics used to derive topology and routing
guidelines through simulation, and all specifications are at the processor silicon and
cannot be measured at the processor pins. The Intel® Pentium® 4 Processor in the 478-
pin Package Overshoot Checker is to be utilized to determine pass/fail signal quality
conditions found through simulation analysis with the Pentium® 4 Processor in the 478-
pin Package I/O Buffer Models (IBIS format). This tool takes into account the
specifications contained in this section.
Specifications for signal quality are for measurements at the processor core only and are
only observable through simulation. The same is true for all system bus AC timing
specifications in Section 2.13. Therefore, proper simulation of the Pentium 4 processor in
the 478-pin package system bus is the only means to verify proper timing and signal
quality metrics, and Intel highly recommends simulation during system design and
measurement during system analysis.
3.1 BCLK Signal Quality Specifications and Measurement

Guidelines
Table 19 describes the signal quality specifications at the processor silicon for the
processor system bus clock (BCLK) signals. Figure 14 describes the signal quality
waveform for the system bus clock at the processor silicon. Specifications are defined at
the processor silicon, not the 478-pin socket pins.
Table 19. BCLK Signal Quality Specifications

Parameter Min Max Unit Figure Notes1
BCLK[1:0] Overshoot N/A 0.30 V 14

BCLK[1:0] Undershoot N/A 0.30 V 14
BCLK[1:0] Ringback Margin 0.20 N/A V 14
BCLK[1:0] Threshold Region N/A 0.10 V 14 2
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium® 4 processor in the 478-pin
package frequencies.
35
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This
specification is an absolute value.
Figure 14. BCLK Signal Integrity Waveform
Overshoot
BCLK1 VH
Rising Edge
Ringback
Crossing Crossing Ringback
Threshold Voltage Voltage Margin
Region
Falling Edge
Ringback,
BCLK0
VL
Undershoot
3.2 System Bus Signal Quality Specifications and

Measurement Guidelines
Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which
are available in the Platform Design Guidelines.
Table 20 provides the signal quality specifications for all processor signals for use in
simulating signal quality at the processor silicon. In the future, the Pentium® 4 Processor
in the 478-pin Package Overshoot, Undershoot and Timing Validation Guidelines will be
available to assist in comparing specifications for signal quality at the processor silicon
with measurements taken at the processor pins.
The Pentium® 4 processor in the 478-pin package maximum allowable overshoot and
undershoot specifications for a given duration of time are detailed in Table 21 through
Table 24. Figure 15 shows the system bus ringback tolerance for low-to-high transitions
and Figure 16 shows ringback tolerance for high-to-low transitions.
Table 20. Ringback Specifications for AGTL+, Asynchronous GTL+, and TAP Signal Groups
Maximum Ringback
Notes
Signal Group Transition (with Input Diodes Present) Unit Figure
All Signals 0→1 GTLREF + 0.100 V 15 1,2,3,4,5,6,7

All Signals 1→0 GTLREF - 0.100 V 16 1,2,3,4,5,6,7
NOTES:
1. All signal integrity specifications are measured at the processor silicon.
2. Unless otherwise noted, all specifications in this table apply to all Pentium® 4 processor in the 478-pin
package frequencies and cache sizes.
3. Specifications are for the edge rate of 0.3 - 4.0V/ns.
36
4. All values specified by design characterization.

5. Please see Section 3.3 for maximum allowable overshoot.
6. Ringback between GTLREF + 100 mV and GTLREF - 100 mV is not supported.
7. Intel recommends simulations not exceed a ringback value of GTLREF +/- 200 mV to allow margin for other
sources of system noise.
Figure 15. Low-to-High System Bus Receiver Ringback Tolerance
VCC
+100 mV Noise Margin
GTLREF
-100 mV
VSS
Figure 16. High-to-Low System Bus Receiver Ringback Tolerance
V CC
+100 mV
GTLREF
-100 mV Noise Margin
V SS
3.3 System Bus Signal Quality Specifications and

Measurement Guidelines
3.3.1 Overshoot/Undershoot Guidelines

Overshoot (or undershoot) is the absolute value of the maximum voltage above the
nominal high voltage (or below VSS) as shown in Figure 17. The overshoot/undershoot
guidelines limit transitions beyond VCC or VSS due to the fast signal edge rates. The
processor can be damaged by repeated overshoot or undershoot events on any input,
37
output, or I/O buffer if the charge is large enough (i.e., if the over/undershoot is great
enough). Determining the impact of an overshoot/undershoot condition requires
knowledge of the magnitude, the pulse direction, and the activity factor (AF) of the incident
waveform. Permanent damage to the processor is the likely result of excessive overshoot/
undershoot.
When performing simulations to determine impact of overshoot and undershoot, ESD

diodes must be properly characterized. ESD protection diodes do not act as voltage
clamps and will not provide overshoot or undershoot protection. ESD diodes modelled
within Intel I/O buffer models do not clamp undershoot or overshoot and will yield correct
simulation results. If other I/O buffer models are being used to characterize the Pentium 4
processor in the 478-pin package system bus, care must be taken to ensure that ESD
models do not clamp extreme voltage levels. Intel I/O buffer models also contain I/O
capacitance characterization. Therefore, removing the ESD diodes from an I/O buffer
model will impact results and may yield excessive overshoot/undershoot.
3.3.2 Overshoot/Undershoot Magnitude

Magnitude describes the maximum potential difference between a signal and its voltage
reference level. For the Pentium 4 processor in the 478-pin package both are referenced
to VSS. It is important to note that overshoot and undershoot conditions are separate and
their impact must be determined independently.
Overshoot/undershoot magnitude levels must observe the absolute maximum

specifications listed in Table 21 through Table 24. These specifications must not be
violated at any time regardless of bus activity or system state. Within these specifications
are threshold levels that define different allowed pulse durations. Provided that the
magnitude of the overshoot/undershoot is within the absolute maximum specifications
(2.3V for overshoot and -0.65V for undershoot), the pulse magnitude, duration and activity
factor must all be used to determine if the overshoot/undershoot pulse is within
specifications.
3.3.3 Overshoot/Undershoot Pulse Duration

Pulse duration describes the total time an overshoot/undershoot event exceeds the
overshoot/undershoot reference voltage (maximum overshoot = 2.3V, maximum
undershoot = -0.65V). The total time could encompass several oscillations above the
reference voltage. Multiple overshoot/undershoot pulses within a single overshoot/
undershoot event may need to be measured to determine the total pulse duration.
Note 1: Oscillations below the reference voltage can not be subtracted from the total
overshoot/undershoot pulse duration.
3.3.4 Activity Factor

Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence
relative to a clock. Since the highest frequency of assertion of any common clock signal is
every other clock, an AF = 1 indicates that the specific overshoot (or undershoot)
waveform occurs every other clock cycle. Thus, an AF = 0.01 indicates that the specific
overshoot (or undershoot) waveform occurs one time in every 200 clock cycles.
38
For source synchronous signals (address, data, and associated strobes), the activity
factor is in reference to the strobe edge, since the highest frequency of assertion of any
source synchronous signal is every active edge of its associated strobe. An AF = 1
indicates that the specific overshoot (or undershoot) waveform occurs every strobe cycle.
The specifications provided in Table 21 through Table 24 show the maximum pulse
duration allowed for a given overshoot/undershoot magnitude at a specific activity factor.
Each table entry is independent of all others, meaning that the pulse duration reflects the
existence of overshoot/undershoot events of that magnitude ONLY. A platform with an
overshoot/undershoot that just meets the pulse duration for a specific magnitude where
the AF < 1, means that there can be no other overshoot/undershoot events, even of lesser
magnitude (note that if AF = 1, then the event occurs at all times and no other events can
occur).
Note 1: Activity factor for AGTL+ signals is referenced to BCLK[1:0] frequency.

Note 2: Activity factor for source synchronous (2x) signals is referenced to ADSTB[1:0]#.
Note 3: Activity factor for source synchronous (4x) signals is referenced to DSTBP[3:0]#
and DSTBN[3:0]#.
3.3.5 Reading Overshoot/Undershoot Specification Tables

The overshoot/undershoot specification for the Pentium 4 processor in the 478-pin
package is not a simple single value. Instead, many factors are needed to determine the
over/undershoot specification. In addition to the magnitude of the overshoot, the following
parameters must also be known: the width of the overshoot and the activity factor (AF). To
determine the allowed overshoot for a particular overshoot event, the following must be
done:
1. Determine the signal group a particular signal falls into. For AGTL+ signals operating
in the common clock domain, use Table 23. For AGTL+ signals operating in the 2x
source synchronous domain, use Table 22. For AGTL+ signals operating in the 4x
source synchronous domain, use Table 23. Finally, all other signals reside in the
33MHz domain (asynchronous GTL+, TAP, etc.) and are referenced in Table 24.
2. Determine the magnitude of the overshoot (relative to VSS)
3. Determine the activity factor (how often does this overshoot occur?)
4. Next, from the appropriate specification table, determine the maximum pulse duration
(in nanoseconds) allowed.
5. Compare the specified maximum pulse duration to the signal being measured. If the
pulse duration measured is less than the pulse duration shown in the table, then the
signal meets the specifications.
Undershoot events must be analyzed separately from overshoot events as they are
mutually exclusive.
3.3.6 Determining if a System Meets the Over/Undershoot Specifications

The overshoot/undershoot specifications listed in the following tables specify the
allowable overshoot/undershoot for a single overshoot/undershoot event. However most
systems will have multiple overshoot and/or undershoot events that each have their own
39
set of parameters (duration, AF and magnitude). While each overshoot on its own may
meet the overshoot specification, when you add the total impact of all overshoot events,
the system may fail. A guideline to ensure a system passes the overshoot and undershoot
specifications is shown below. Results from simulation may also be evaluated by utilizing
the Intel® Pentium® 4 Processor in the 478-pin Package Overshoot Checker through the
use of time-voltage data files.
1. Ensure no signal ever exceeds VCC_MAX or -0.25V OR
2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/
undershoot specifications in the following tables OR
3. If multiple overshoots and/or multiple undershoots occur, measure the worst case
pulse duration for each magnitude and compare the results against the AF = 1
specifications. If all of these worst case overshoot or undershoot events meet the
specifications (measured time < specifications) in the table (where AF=1), then the
system passes.
The following notes apply to Table 21 through Table 24.
NOTES:
1. Absolute Maximum Overshoot magnitude of 2.3V must never be exceeded.
2. Absolute Maximum Overshoot is measured relative to VSS, Pulse Duration of
overshoot is measured relative to VCC.
3. Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative
to VCC.
4. Ringback below VCC can not be subtracted from overshoots/undershoots.
5. Lesser undershoot does not allocate longer or larger overshoot.
6. OEM's are strongly encouraged to follow Intel provided layout guidelines.
7. All values specified by design characterization.
40
Table 21. Source Synchronous (400MHz) AGTL+ Signal Group Overshoot/Undershoot

Tolerance
Absolute Absolute
Pulse Pulse Pulse
Maximum Maximum
Duration (ns) Duration (ns) Duration (ns) Notes 1,2,3
Overshoot Undershoot
AF = 1 AF = 0.1 AF = 0.01
(V) (V)
2.30 -0.585 0.06 0.63 5.00

2.25 -0.535 0.11 1.10 5.00
2.20 -0.485 0.22 2.20 5.00
2.15 -0.435 0.41 4.10 5.00
2.10 -0.385 0.75 5.00 5.00
2.05 -0.335 1.35 5.00 5.00
2.00 -0.285 2.50 5.00 5.00
1.95 -0.235 4.70 5.00 5.00
1.90 -0.185 5.00 5.00 5.00
1.85 -0.135 5.00 5.00 5.00
1.80 -0.085 5.00 5.00 5.00
NOTES:
1. These specifications are measured at the processor silicon.
2. BCLK period is 10 ns.
3. AF is referenced to associated source synchronous strobes.
Table 22. Source Synchronous (200MHz) AGTL+ Signal Group Overshoot/Undershoot

Tolerance
Absolute Absolute
Pulse Pulse Pulse
Maximum Maximum
AF = 1 AF = 0.1 AF = 0.01
(V) (V)
2.30 -0.585 0.12 1.2 10.0

2.25 -0.535 0.22 2.2 10.0
2.20 -0.485 0.44 4.4 10.0
2.15 -0.435 0.82 8.2 10.0
2.10 -0.385 1.5 10.0 10.0
2.05 -0.335 2.7 10.0 10.0
2.00 -0.285 5.0 10.0 10.0
1.95 -0.235 9.4 10.0 10.0
1.90 -0.185 10.0 10.0 10.0
1.85 -0.135 10.0 10.0 10.0
1.80 -0.085 10.0 10.0 10.0
NOTES:
3. AF is referenced to associated source synchronous strobes.
41
Table 23. Common Clock (100MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance
Absolute Absolute
Pulse Pulse Pulse
Maximum Maximum
AF = 1 AF = 0.1 AF = 0.01
(V) (V)
2.30 -0.585 0.24 2.4 20.0

2.25 -0.535 0.44 4.4 20.0
2.20 -0.485 0.88 8.8 20.0
2.15 -0.435 1.64 16.4 20.0
2.10 -0.385 3.0 20.0 20.0
2.05 -0.335 5.4 20.0 20.0
2.00 -0.285 10.0 20.0 20.0
1.95 -0.235 18.8 20.0 20.0
1.90 -0.185 20.0 20.0 20.0
1.85 -0.135 20.0 20.0 20.0
1.80 -0.085 20.0 20.0 20.0
NOTES:
3. AF is referenced to BCLK[1:0].
Table 24. Asynchronous GTL+ and TAP Signal Groups Overshoot/Undershoot Tolerance
Absolute Absolute
Pulse Pulse Pulse
Maximum Maximum
Duration (ns) Duration (ns) Duration (ns) Notes 1,2
AF = 1 AF = 0.1 AF = 0.01
(V) (V)
2.30 -0.585 0.72 7.2 60.0

2.25 -0.535 1.32 13.2 60.0
2.20 -0.485 2.64 26.4 60.0
2.15 -0.435 4.92 49.2 60.0
2.10 -0.385 9.0 60.0 60.0
2.05 -0.335 16.2 60.0 60.0
2.00 -0.285 30.0 60.0 60.0
1.95 -0.235 56.4 60.0 60.0
1.90 -0.185 60.0 60.0 60.0
1.85 -0.135 60.0 60.0 60.0
1.80 -0.085 60.0 60.0 60.0
NOTES:
1. These specifications are specified at the processor silicon.
2. This table assumes a 33MHz time domain.
42
Figure 17. Maximum Acceptable Overshoot/Undershoot Waveform
Maximum Time-dependent
Absolute Overshoot
Overshoot
VMAX
VCC
GTLREF
VOL
VSS
VMIN
Time-dependent
Maximum Undershoot
Absolute
Undershoot
43
44
4.0 Package Mechanical Specifications
The Pentium® 4 processor in the 478-pin package is packaged in a Flip-Chip Pin Grid
Array (FC-PGA2) package. Components of the package include an integrated heat
spreader (IHS), processor core, and the substrate which is the pin carrier. Mechanical
specifications for the processor are given in this section. See Section 1.1 for a terminology
listing. The processor socket which accepts the Pentium 4 processor in the 478-pin
package is referred to as a 478-Pin micro PGA (mPGA478B) socket. See the Intel®
Pentium® 4 Processor 478-Pin Socket (mPGA478B) Design Guidelines for complete
details on the mPGA478B socket.
Note: For Figure 18 through Figure 24 the following notes apply:
1. Unless otherwise specified, the following drawings are dimensioned in millimeters.
2. All dimensions are not tested, but guaranteed by design characterization.
3. Figures and drawings labeled as “Reference Dimensions” are provided for

informational purposes only. Reference dimensions are extracted from the mechanical
design database and are nominal dimensions with no tolerance information applied.
Reference dimensions are NOT checked as part of the processor manufacturing process.
Unless noted as such, dimensions in parentheses without tolerances are reference
dimensions.
4. Drawings are not to scale.
Note: The drawing below is not to scale and is for reference only. The socket and system board
are supplied as a reference only.
Figure 18. Exploded View of Processor Components on a System Board
Heat Spreader
31 mm
3.5m m
2.0m m
Substrate
478 pins
35m m square
mPGA478B
System board
Socket
45
Figure 19. Pentium® 4 Processor in the 478-pin Package
Table 25. Description Table for Processor Dimensions

Code Letter mm
Notes 1
Min Nominal Max
A1 2.266 2.378 2.490
A2 0.980 1.080 1.180
B1 30.800 31.000 31.200
B2 30.800 31.000 31.200
C1 33.000 Includes Placement Tolerance
C2 33.000 Includes Placement Tolerance
D 34.900 35.000 35.100
D1 31.500 31.750 32.000
G1 13.970 Keepin Zone Dimension
H 1.270
L 1.950 2.030 2.110
φP 0.280 0.305 0.330
PIN TP 0.254 Diametric True Position (Pin-to-Pin)
46
Figure 20 details the keep in specification for pin-side components. The Pentium 4
processor in the 478-pin package may contain pin side capacitors mounted to the
processor package.
Figure 22 details the flatness and tilt specifications for the IHS. Tilt is measured with the
reference datum set to the bottom of the processor interposer.
Figure 20. Processor Cross-Section and Keep-in
FCPGA 2
IHS
Substrate
1.25mm
13.97m m
Com ponent Keepin
Socket must allow clearance

for pin shoulders and m ate
flush with this surface
Figure 21. Processor Pin Detail
Ø 0.305±0.025
Ø 0.65 MAX
PINHEAD DIAMETER
Ø 1.032 MAX
KEEP OUT ZONE
0.3 MAX
SOLDER FILLET HEIGHT
2.03±0.08
ALL DIMENSIONS ARE IN MILIMETERS
NOTES:
1. Pin plating consists of 0.2 micrometers Au over 2.0 micrometer Ni.
2. 0.254 mm diametric true position, pin to pin.
47
Figure 22. IHS Flatness Specification
IHS
SUBSTRATE
NOTES:
1. Flatness is specific as overall, not per unit of length.
2. All dimensions are in mm.
4.1 Package Load Specifications

Table 26 provides dynamic and static load specifications for the Pentium 4 processor in
the 478-pin package IHS. These mechanical load limits should not be exceeded during
heatsink assembly, mechanical stress testing, or standard drop and shipping conditions.
The heatsink attach solutions must not induce continuous stress onto the processor with
the exception of a uniform load to maintain the heat sink-to-processor thermal interface. It
is not recommended to use any portion of the processor interposer as a mechanical
reference or load bearing surface for thermal solutions.
Table 26. Package Dynamic and Static Load Specifications

Parameter Max Unit Notes
Static 100 lbf 1, 2, 3

Dynamic 200 lbf 1, 3, 4
NOTES:
1. This specification applies to a uniform compressive load.
2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and
processor interface.
3. These parameters are based on limited testing for design characterization
4. Dynamic loading specifications are defined assuming a maximum duration of 11ms and 200 lbf is achieved
by superimposing a 100 lbf dynamic load (1 lbm heatsink at 50g) on the static compressive load.
48
4.2 Processor Insertion Specifications

The Pentium 4 processor in the 478-pin package can be inserted and removed 15 times
from a mPGA478B socket meeting the Intel® Pentium® 4 Processor 478-Pin Socket
(mPGA478B) Design Guidelines document.
4.3 Processor Mass Specifications

Table 27 specifies the processor’s mass. This includes all components which make up the
entire processor product.
Table 27. Processor Mass

Processor Mass (grams)
Pentium 4 processor in the 478-pin package 19
4.4 Processor Materials

The Pentium 4 processor in the 478-pin package is assembled from several components.
The basic material properties are described in Table 28.
Table 28. Processor Material Properties

Component Material Notes
Integrated Heat Spreader Nickel over copper

Substrate Fiber-reinforced resin
Substrate pins Gold over nickel
4.5 Processor Markings

Figure 23 details the processor top-side markings and is provided to aid in the
identification of the Pentium 4 processor in the 478-pin package.
Figure 23. Processor Markings
Frequency/Cache/Bus/Voltage
2.0GHZ/256/400/1.75V
SYYYY XXXXXX
S-Spec/Country of Assy
FFFFFFFF-NNNN
i m ©‘01 2-D Matrix Mark
FPO - Serial #
49
4.6 Processor Pin-Out Coordinates

Figure 24. The Coordinates of the Processor Pins as Viewed From the Top of the Package
50
5.0 Pin Listing and Signal Definitions
5.1 Pentium® 4 Processor in the 478-pin Package Pin

Assignments
Section 5.1 contains the pinlist for the Pentium® 4 processor in the 478-pin package in
Table 29 and Table 30. Table 29 is a listing of all processor pins ordered alphabetically by
pin name. Table 30 is also a listing of all processor pins but ordered by pin number.
51
Table 29. Pin Listing by Pin Name
Table 29. Pin Listing by Pin Name Pin Name

Pin Signal Buffer
Direction
Number Type
Pin Signal Buffer AP#[0] AC1 Common Clock Input/Output
Pin Name Direction
Number Type
AP#[1] V5 Common Clock Input/Output
A#[03] K2 Source Synch Input/Output
BCLK[0] AF22 Bus Clock Input
BCLK[1] AF23 Bus Clock Input
A#[05] L6 Source Synch Input/Output
BINIT# AA3 Common Clock Input/Output
BNR# G2 Common Clock Input/Output
BPM#[0] AC6 Common Clock Input/Output
A#[08] M6 Source Synch Input/Output
BPM#[1] AB5 Common Clock Input/Output
BPM#[2] AC4 Common Clock Input/Output
BPM#[3] Y6 Common Clock Input/Output
BPM#[4] AA5 Common Clock Input/Output
A#[12] N1 Source Synch Input/Output
BPM#[5] AB4 Common Clock Input/Output
BPRI# D2 Common Clock Input
BR0# H6 Common Clock Input/Output
BSEL0 AD6 Power/Other Output
BSEL1 AD5 Power/Other Output
A#[17] T1 Source Synch Input/Output
COMP[0] L24 Power/Other Input/Output
A#[18] R2 Source Synch Input/Output
COMP[1] P1 Power/Other Input/Output
A#[19] P3 Source Synch Input/Output
D#[0] B21 Source Synch Input/Output
D#[02] A23 Source Synch Input/Output
D#[03] A25 Source Synch Input/Output
A#[23] U1 Source Synch Input/Output
D#[04] C21 Source Synch Input/Output
D#[05] D22 Source Synch Input/Output
A#[27] V2 Source Synch Input/Output
A#[29] W1 Source Synch Input/Output
D#[10] G22 Source Synch Input/Output
D#[11] H21 Source Synch Input/Output
A#[32] V3 Source Synch Input/Output
A#[33] W2 Source Synch Input/Output
D#[14] J21 Source Synch Input/Output
A#[34] Y1 Source Synch Input/Output
A#[35] AB1 Source Synch Input/Output
D#[16] H22 Source Synch Input/Output
A20M# C6 Asynch GTL+ Input
D#[17] E24 Source Synch Input/Output
ADS# G1 Common Clock Input/Output
D#[18] G23 Source Synch Input/Output
ADSTB#[0] L5 Source Synch Input/Output
D#[19] F23 Source Synch Input/Output
ADSTB#[1] R5 Source Synch Input/Output
D#[20] F24 Source Synch Input/Output
52
Table 29. Pin Listing by Pin Name Table 29. Pin Listing by Pin Name
Pin Signal Buffer Pin Signal Buffer

Pin Name Direction Pin Name Direction
Number Type Number Type
D#[21] E25 Source Synch Input/Output D#[60] Y21 Source Synch Input/Output
D#[22] F26 Source Synch Input/Output D#[61] AA25 Source Synch Input/Output
D#[23] D26 Source Synch Input/Output D#[62] AA22 Source Synch Input/Output
D#[24] L21 Source Synch Input/Output D#[63] AA24 Source Synch Input/Output
D#[25] G26 Source Synch Input/Output DBI#[0] E21 Source Synch Input/Output
D#[26] H24 Source Synch Input/Output DBI#[1] G25 Source Synch Input/Output
D#[27] M21 Source Synch Input/Output DBI#[2] P26 Source Synch Input/Output
D#[28] L22 Source Synch Input/Output DBI#[3] V21 Source Synch Input/Output
D#[29] J24 Source Synch Input/Output DBR# AE25 Power/Other Output
D#[30] K23 Source Synch Input/Output DBSY# H5 Common Clock Input/Output
D#[31] H25 Source Synch Input/Output DEFER# E2 Common Clock Input
D#[32] M23 Source Synch Input/Output DP#[0] J26 Common Clock Input/Output
D#[33] N22 Source Synch Input/Output DP#[1] K25 Common Clock Input/Output
D#[34] P21 Source Synch Input/Output DP#[2] K26 Common Clock Input/Output
D#[35] M24 Source Synch Input/Output DP#[3] L25 Common Clock Input/Output
D#[36] N23 Source Synch Input/Output DRDY# H2 Common Clock Input/Output
D#[37] M26 Source Synch Input/Output DSTBN#[0] E22 Source Synch Input/Output
D#[38] N26 Source Synch Input/Output DSTBN#[1] K22 Source Synch Input/Output
D#[39] N25 Source Synch Input/Output DSTBN#[2] R22 Source Synch Input/Output
D#[40] R21 Source Synch Input/Output DSTBN#[3] W22 Source Synch Input/Output
D#[41] P24 Source Synch Input/Output DSTBP#[0] F21 Source Synch Input/Output
D#[42] R25 Source Synch Input/Output DSTBP#[1] J23 Source Synch Input/Output
D#[43] R24 Source Synch Input/Output DSTBP#[2] P23 Source Synch Input/Output
D#[44] T26 Source Synch Input/Output DSTBP#[3] W23 Source Synch Input/Output
D#[45] T25 Source Synch Input/Output FERR# B6 Asynch AGL+ Output
D#[46] T22 Source Synch Input/Output GTLREF AA21 Power/Other Input
D#[47] T23 Source Synch Input/Output GTLREF AA6 Power/Other Input
D#[48] U26 Source Synch Input/Output GTLREF F20 Power/Other Input
D#[49] U24 Source Synch Input/Output GTLREF F6 Power/Other Input
D#[50] U23 Source Synch Input/Output HIT# F3 Common Clock Input/Output
D#[51] V25 Source Synch Input/Output HITM# E3 Common Clock Input/Output
D#[52] U21 Source Synch Input/Output IERR# AC3 Common Clock Output
D#[53] V22 Source Synch Input/Output IGNNE# B2 Asynch GTL+ Input
D#[54] V24 Source Synch Input/Output INIT# W5 Asynch GTL+ Input
D#[55] W26 Source Synch Input/Output ITPCLKOUT[0] AA20 Power/Other Output
D#[56] Y26 Source Synch Input/Output ITPCLKOUT[1] AB22 Power/Other Output
D#[57] W25 Source Synch Input/Output ITP_CLK0 AC26 TAP input
D#[58] Y23 Source Synch Input/Output ITP_CLK1 AD26 TAP input
D#[59] Y24 Source Synch Input/Output LINT0 D1 Asynch GTL+ Input
53

LINT1 E5 Asynch GTL+ Input TESTHI11 A6 Power/Other Input

LOCK# G4 Common Clock Input/Output TESTHI12 AD25 Power/Other Input
MCERR# V6 Common Clock Input/Output THERMDA B3 Power/Other
PROCHOT# C3 Asynch GTL+ Output THERMDC C4 Power/Other
PWRGOOD AB23 Asynch GTL+ Input THERMTRIP# A2 Asynch GTL+ Output
REQ#[0] J1 Source Synch Input/Output TMS F7 TAP Input
REQ#[1] K5 Source Synch Input/Output TRDY# J6 Common Clock Input
REQ#[2] J4 Source Synch Input/Output TRST# E6 TAP Input
REQ#[3] J3 Source Synch Input/Output VCC A10 Power/Other
REQ#[4] H3 Source Synch Input/Output VCC A12 Power/Other
RESERVED A22 VCC A14 Power/Other
RESERVED A7 VCC A16 Power/Other
RESERVED AD2 VCC A18 Power/Other
RESERVED AD3 VCC A20 Power/Other
RESERVED AE21 VCC A8 Power/Other
RESERVED AF3 VCC AA10 Power/Other
RESET# AB25 Common Clock Input VCC AA16 Power/Other
RS#[0] F1 Common Clock Input VCC AA18 Power/Other
RS#[1] G5 Common Clock Input VCC AA8 Power/Other
RS#[2] F4 Common Clock Input VCC AB11 Power/Other
RSP# AB2 Common Clock Input VCC AB13 Power/Other
SKTOCC# AF26 Power/Other Output VCC AB15 Power/Other
SLP# AB26 Asynch GTL+ Input VCC AB17 Power/Other
SMI# B5 Asynch GTL+ Input VCC AB19 Power/Other
STPCLK# Y4 Asynch GTL+ Input VCC AB7 Power/Other
TCK D4 TAP Input VCC AB9 Power/Other
TDI C1 TAP Input VCC AC10 Power/Other
TDO D5 TAP Output VCC AC12 Power/Other
TESTHI0 AD24 Power/Other Input VCC AC14 Power/Other
TESTHI1 AA2 Power/Other Input VCC AC16 Power/Other
TESTHI2 AC21 Power/Other Input VCC AC18 Power/Other
TESTHI3 AC20 Power/Other Input VCC AC8 Power/Other
TESTHI4 AC24 Power/Other Input VCC AD11 Power/Other
TESTHI5 AC23 Power/Other Input VCC AD13 Power/Other
TESTHI8 U6 Power/Other Input VCC AD15 Power/Other
TESTHI9 W4 Power/Other Input VCC AD17 Power/Other
TESTHI10 Y3 Power/Other Input VCC AD19 Power/Other
54

VCC AD7 Power/Other VCC D7 Power/Other

VCC AD9 Power/Other VCC D9 Power/Other
VCC AE10 Power/Other VCC E10 Power/Other
VCC AE8 Power/Other VCC F11 Power/Other
VCC AF11 Power/Other VCC F13 Power/Other
VCC AF2 Power/Other VCCA AD20 Power/Other
VCC AF21 Power/Other VCCIOPLL AE23 Power/Other
VCC AF5 Power/Other VCCSENSE A5 Power/Other Output
VCC AF7 Power/Other VCCVID AF4 Power/Other Input
VCC AF9 Power/Other VID0 AE5 Power/Other Output
VCC B11 Power/Other VID1 AE4 Power/Other Output
VCC B19 Power/Other VSS D10 Power/Other
VCC B7 Power/Other VSS A11 Power/Other
VCC B9 Power/Other VSS A13 Power/Other
VCC C10 Power/Other VSS A15 Power/Other
VCC D11 Power/Other VSS A9 Power/Other
VCC D13 Power/Other VSS AA1 Power/Other
55

VSS AA17 Power/Other VSS AE11 Power/Other

VSS AB10 Power/Other VSS AE26 Power/Other
VSS AB16 Power/Other VSS AF1 Power/Other
VSS AC11 Power/Other VSS AF8 Power/Other
VSS AC13 Power/Other VSS B10 Power/Other
VSS AD1 Power/Other VSS C11 Power/Other
56

VSS C9 Power/Other VSS H4 Power/Other

VSS D12 Power/Other VSS J2 Power/Other
VSS D20 Power/Other VSS K21 Power/Other
VSS D6 Power/Other VSS L1 Power/Other
VSS D8 Power/Other VSS L23 Power/Other
VSS E1 Power/Other VSS L26 Power/Other
VSS E11 Power/Other VSS L4 Power/Other
VSS E13 Power/Other VSS M2 Power/Other
VSS E23 Power/Other VSS N21 Power/Other
VSS E9 Power/Other VSS P2 Power/Other
VSS F10 Power/Other VSS P22 Power/Other
VSS F16 Power/Other VSS R1 Power/Other
VSS F25 Power/Other VSS T21 Power/Other
VSS G21 Power/Other VSS T6 Power/Other
VSS G24 Power/Other VSS U2 Power/Other
VSS H1 Power/Other VSS U5 Power/Other
VSS H23 Power/Other VSS V1 Power/Other
VSS H26 Power/Other VSS V23 Power/Other
57
Table 29. Pin Listing by Pin Name
Pin Signal Buffer

Pin Name Direction
Number Type
VSS V26 Power/Other

VSS V4 Power/Other
VSS W21 Power/Other
VSS W24 Power/Other
VSS W3 Power/Other
VSS W6 Power/Other
VSS Y2 Power/Other
VSS Y22 Power/Other
VSS Y25 Power/Other
VSS Y5 Power/Other
VSSA AD22 Power/Other
VSSSENSE A4 Power/Other Output
58
Table 30. Pin Listing by Pin Number
Table 30. Pin Listing by Pin Number Pin

Pin Name
Signal Buffer
Direction
Number Type
Pin Signal Buffer AA13 VSS Power/Other
Pin Name Direction
Number Type
AA14 VCC Power/Other
A2 THERMTRIP# Asynch GTL+ Output
AA15 VSS Power/Other
A3 VSS Power/Other
A4 VSSSENSE Power/Other Output
A5 VCCSENSE Power/Other Output
A6 TESTHI11 Power/Other Input
A7 RESERVED
AA20 ITPCLKOUT[0] Power/Other Output
A8 VCC Power/Other
AA21 GTLREF Power/Other Input
A9 VSS Power/Other
AA22 D#[62] Source Synch Input/Output
A10 VCC Power/Other
A11 VSS Power/Other
A12 VCC Power/Other
A13 VSS Power/Other
A14 VCC Power/Other
AB1 A#[35] Source Synch Input/Output
A15 VSS Power/Other
AB2 RSP# Common Clock Input
A16 VCC Power/Other
AB3 VSS Power/Other
A17 VSS Power/Other
AB4 BPM#[5] Common Clock Input/Output
A18 VCC Power/Other
AB5 BPM#[1] Common Clock Input/Output
A19 VSS Power/Other
AB6 VSS Power/Other
A20 VCC Power/Other
AB7 VCC Power/Other
A21 VSS Power/Other
AB8 VSS Power/Other
A22 RESERVED
AB9 VCC Power/Other
A23 D#[02] Source Synch Input/Output
AB10 VSS Power/Other
A24 VSS Power/Other
AB11 VCC Power/Other
A25 D#[03] Source Synch Input/Output
A26 VSS Power/Other
AA1 VSS Power/Other
AA2 TESTHI1 Power/Other Input
AA3 BINIT# Common Clock Input/Output
AA4 VSS Power/Other
AA5 BPM#[4] Common Clock Input/Output
AA6 GTLREF Power/Other Input
AA7 VSS Power/Other
AA8 VCC Power/Other
AA9 VSS Power/Other
AB22 ITPCLKOUT[1] Power/Other Output
AB23 PWRGOOD Asynch GTL+ Input
AB25 RESET# Common Clock Input
59
Table 30. Pin Listing by Pin Number Table 30. Pin Listing by Pin Number

AB26 SLP# Asynch GTL+ Input AD13 VCC Power/Other

AC1 AP#[0] Common Clock Input/Output AD14 VSS Power/Other
AC2 VSS Power/Other AD15 VCC Power/Other
AC3 IERR# Common Clock Output AD16 VSS Power/Other
AC4 BPM#[2] Common Clock Input/Output AD17 VCC Power/Other
AC5 VSS Power/Other AD18 VSS Power/Other
AC6 BPM#[0] Common Clock Input/Output AD19 VCC Power/Other
AC7 VSS Power/Other AD20 VCCA Power/Other
AC8 VCC Power/Other AD21 VSS Power/Other
AC9 VSS Power/Other AD22 VSSA Power/Other
AC10 VCC Power/Other AD23 VSS Power/Other
AC11 VSS Power/Other AD24 TESTHI0 Power/Other Input
AC12 VCC Power/Other AD25 TESTHI12 Power/Other Input
AC13 VSS Power/Other AD26 ITP_CLK1 TAP input
AC14 VCC Power/Other AE1 VID4 Power/Other Output
AC15 VSS Power/Other AE2 VID3 Power/Other Output
AC17 VSS Power/Other AE4 VID1 Power/Other Output
AC19 VSS Power/Other AE6 VCC Power/Other
AC20 TESTHI3 Power/Other Input AE7 VSS Power/Other
AC21 TESTHI2 Power/Other Input AE8 VCC Power/Other
AC22 VSS Power/Other AE9 VSS Power/Other
AC23 TESTHI5 Power/Other Input AE10 VCC Power/Other
AC24 TESTHI4 Power/Other Input AE11 VSS Power/Other
AC25 VSS Power/Other AE12 VCC Power/Other
AC26 ITP_CLK0 TAP input AE13 VSS Power/Other
AD1 VSS Power/Other AE14 VCC Power/Other
AD2 RESERVED AE15 VSS Power/Other
AD3 RESERVED AE16 VCC Power/Other
AD4 VSS Power/Other AE17 VSS Power/Other
AD5 BSEL1 Power/Other Output AE18 VCC Power/Other
AD6 BSEL0 Power/Other Output AE19 VSS Power/Other
AD7 VCC Power/Other AE20 VCC Power/Other
AD8 VSS Power/Other AE21 RESERVED
AD9 VCC Power/Other AE22 VSS Power/Other
AD10 VSS Power/Other AE23 VCCIOPLL Power/Other
AD11 VCC Power/Other AE24 VSS Power/Other
AD12 VSS Power/Other AE25 DBR# Power/Other Output
60

AE26 VSS Power/Other B14 VSS Power/Other

AF1 VSS Power/Other B15 VCC Power/Other
AF2 VCC Power/Other B16 VSS Power/Other
AF3 RESERVED B17 VCC Power/Other
AF4 VCCVID Power/Other Input B18 VSS Power/Other
AF5 VCC Power/Other B19 VCC Power/Other
AF6 VSS Power/Other B20 VSS Power/Other
AF7 VCC Power/Other B21 D#[0] Source Synch Input/Output
AF8 VSS Power/Other B22 D#[01] Source Synch Input/Output
AF9 VCC Power/Other B23 VSS Power/Other
AF10 VSS Power/Other B24 D#[06] Source Synch Input/Output
AF11 VCC Power/Other B25 D#[09] Source Synch Input/Output
AF12 VSS Power/Other B26 VSS Power/Other
AF13 VCC Power/Other C1 TDI TAP Input
AF14 VSS Power/Other C2 VSS Power/Other
AF15 VCC Power/Other C3 PROCHOT# Asynch GTL+ Output
AF16 VSS Power/Other C4 THERMDC Power/Other
AF17 VCC Power/Other C5 VSS Power/Other
AF18 VSS Power/Other C6 A20M# Asynch GTL+ Input
AF20 VSS Power/Other C8 VCC Power/Other
AF22 BCLK[0] Bus Clock Input C10 VCC Power/Other
AF23 BCLK[1] Bus Clock Input C11 VSS Power/Other
AF24 RESERVED C12 VCC Power/Other
AF25 RESERVED C13 VSS Power/Other
AF26 SKTOCC# Power/Other Output C14 VCC Power/Other
B2 IGNNE# Asynch GTL+ Input C15 VSS Power/Other
B3 THERMDA Power/Other C16 VCC Power/Other
B4 VSS Power/Other C17 VSS Power/Other
B5 SMI# Asynch GTL+ Input C18 VCC Power/Other
B6 FERR# Asynch AGL+ Output C19 VSS Power/Other
B7 VCC Power/Other C20 VCC Power/Other
B8 VSS Power/Other C21 D#[04] Source Synch Input/Output
B9 VCC Power/Other C22 VSS Power/Other
B10 VSS Power/Other C23 D#[07] Source Synch Input/Output
B11 VCC Power/Other C24 D#[08] Source Synch Input/Output
B12 VSS Power/Other C25 VSS Power/Other
B13 VCC Power/Other C26 D#[12] Source Synch Input/Output
61

D1 LINT0 Asynch GTL+ Input E14 VCC Power/Other

D2 BPRI# Common Clock Input E15 VSS Power/Other
D3 VSS Power/Other E16 VCC Power/Other
D4 TCK TAP Input E17 VSS Power/Other
D5 TDO TAP Output E18 VCC Power/Other
D6 VSS Power/Other E19 VSS Power/Other
D7 VCC Power/Other E20 VCC Power/Other
D8 VSS Power/Other E21 DBI#[0] Source Synch Input/Output
D9 VCC Power/Other E22 DSTBN#[0] Source Synch Input/Output
D10 VSS Power/Other E23 VSS Power/Other
D11 VCC Power/Other E24 D#[17] Source Synch Input/Output
D12 VSS Power/Other E25 D#[21] Source Synch Input/Output
D13 VCC Power/Other E26 VSS Power/Other
D14 VSS Power/Other F1 RS#[0] Common Clock Input
D15 VCC Power/Other F2 VSS Power/Other
D16 VSS Power/Other F3 HIT# Common Clock Input/Output
D17 VCC Power/Other F4 RS#[2] Common Clock Input
D18 VSS Power/Other F5 VSS Power/Other
D19 VCC Power/Other F6 GTLREF Power/Other Input
D20 VSS Power/Other F7 TMS TAP Input
D21 VSS Power/Other F8 VSS Power/Other
D22 D#[05] Source Synch Input/Output F9 VCC Power/Other
D23 D#[13] Source Synch Input/Output F10 VSS Power/Other
D24 VSS Power/Other F11 VCC Power/Other
D25 D#[15] Source Synch Input/Output F12 VSS Power/Other
D26 D#[23] Source Synch Input/Output F13 VCC Power/Other
E1 VSS Power/Other F14 VSS Power/Other
E2 DEFER# Common Clock Input F15 VCC Power/Other
E3 HITM# Common Clock Input/Output F16 VSS Power/Other
E4 VSS Power/Other F17 VCC Power/Other
E5 LINT1 Asynch GTL+ Input F18 VSS Power/Other
E6 TRST# TAP Input F19 VCC Power/Other
E7 VSS Power/Other F20 GTLREF Power/Other Input
E8 VCC Power/Other F21 DSTBP#[0] Source Synch Input/Output
E9 VSS Power/Other F22 VSS Power/Other
E10 VCC Power/Other F23 D#[19] Source Synch Input/Output
E11 VSS Power/Other F24 D#[20] Source Synch Input/Output
E12 VCC Power/Other F25 VSS Power/Other
E13 VSS Power/Other F26 D#[22] Source Synch Input/Output
62

G1 ADS# Common Clock Input/Output K4 A#[04] Source Synch Input/Output

G2 BNR# Common Clock Input/Output K5 REQ#[1] Source Synch Input/Output
G3 VSS Power/Other K6 VSS Power/Other
G4 LOCK# Common Clock Input/Output K21 VSS Power/Other
G5 RS#[1] Common Clock Input K22 DSTBN#[1] Source Synch Input/Output
G6 VSS Power/Other K23 D#[30] Source Synch Input/Output
G21 VSS Power/Other K24 VSS Power/Other
G22 D#[10] Source Synch Input/Output K25 DP#[1] Common Clock Input/Output
G23 D#[18] Source Synch Input/Output K26 DP#[2] Common Clock Input/Output
G24 VSS Power/Other L1 VSS Power/Other
G25 DBI#[1] Source Synch Input/Output L2 A#[09] Source Synch Input/Output
G26 D#[25] Source Synch Input/Output L3 A#[07] Source Synch Input/Output
H1 VSS Power/Other L4 VSS Power/Other
H2 DRDY# Common Clock Input/Output L5 ADSTB#[0] Source Synch Input/Output
H3 REQ#[4] Source Synch Input/Output L6 A#[05] Source Synch Input/Output
H4 VSS Power/Other L21 D#[24] Source Synch Input/Output
H5 DBSY# Common Clock Input/Output L22 D#[28] Source Synch Input/Output
H6 BR0# Common Clock Input/Output L23 VSS Power/Other
H21 D#[11] Source Synch Input/Output L24 COMP[0] Power/Other Input/Output
H22 D#[16] Source Synch Input/Output L25 DP#[3] Common Clock Input/Output
H23 VSS Power/Other L26 VSS Power/Other
H24 D#[26] Source Synch Input/Output M1 A#[13] Source Synch Input/Output
H25 D#[31] Source Synch Input/Output M2 VSS Power/Other
H26 VSS Power/Other M3 A#[10] Source Synch Input/Output
J1 REQ#[0] Source Synch Input/Output M4 A#[11] Source Synch Input/Output
J2 VSS Power/Other M5 VSS Power/Other
J3 REQ#[3] Source Synch Input/Output M6 A#[08] Source Synch Input/Output
J4 REQ#[2] Source Synch Input/Output M21 D#[27] Source Synch Input/Output
J6 TRDY# Common Clock Input M23 D#[32] Source Synch Input/Output
J21 D#[14] Source Synch Input/Output M24 D#[35] Source Synch Input/Output
J23 DSTBP#[1] Source Synch Input/Output M26 D#[37] Source Synch Input/Output
J24 D#[29] Source Synch Input/Output N1 A#[12] Source Synch Input/Output
J25 VSS Power/Other N2 A#[14] Source Synch Input/Output
J26 DP#[0] Common Clock Input/Output N3 VSS Power/Other
K1 A#[06] Source Synch Input/Output N4 A#[15] Source Synch Input/Output
K2 A#[03] Source Synch Input/Output N5 A#[16] Source Synch Input/Output
K3 VSS Power/Other N6 VSS Power/Other
63

N21 VSS Power/Other T24 VSS Power/Other

N22 D#[33] Source Synch Input/Output T25 D#[45] Source Synch Input/Output
N23 D#[36] Source Synch Input/Output T26 D#[44] Source Synch Input/Output
N24 VSS Power/Other U1 A#[23] Source Synch Input/Output
N25 D#[39] Source Synch Input/Output U2 VSS Power/Other
N26 D#[38] Source Synch Input/Output U3 A#[25] Source Synch Input/Output
P1 COMP[1] Power/Other Input/Output U4 A#[31] Source Synch Input/Output
P2 VSS Power/Other U5 VSS Power/Other
P3 A#[19] Source Synch Input/Output U6 TESTHI8 Power/Other Input
P4 A#[20] Source Synch Input/Output U21 D#[52] Source Synch Input/Output
P6 A#[24] Source Synch Input/Output U23 D#[50] Source Synch Input/Output
P21 D#[34] Source Synch Input/Output U24 D#[49] Source Synch Input/Output
P23 DSTBP#[2] Source Synch Input/Output U26 D#[48] Source Synch Input/Output
P24 D#[41] Source Synch Input/Output V1 VSS Power/Other
P25 VSS Power/Other V2 A#[27] Source Synch Input/Output
P26 DBI#[2] Source Synch Input/Output V3 A#[32] Source Synch Input/Output
R1 VSS Power/Other V4 VSS Power/Other
R2 A#[18] Source Synch Input/Output V5 AP#[1] Common Clock Input/Output
R3 A#[21] Source Synch Input/Output V6 MCERR# Common Clock Input/Output
R4 VSS Power/Other V21 DBI#[3] Source Synch Input/Output
R5 ADSTB#[1] Source Synch Input/Output V22 D#[53] Source Synch Input/Output
R6 A#[28] Source Synch Input/Output V23 VSS Power/Other
R21 D#[40] Source Synch Input/Output V24 D#[54] Source Synch Input/Output
R22 DSTBN#[2] Source Synch Input/Output V25 D#[51] Source Synch Input/Output
R23 VSS Power/Other V26 VSS Power/Other
R24 D#[43] Source Synch Input/Output W1 A#[29] Source Synch Input/Output
R25 D#[42] Source Synch Input/Output W2 A#[33] Source Synch Input/Output
R26 VSS Power/Other W3 VSS Power/Other
T1 A#[17] Source Synch Input/Output W4 TESTHI9 Power/Other Input
T2 A#[22] Source Synch Input/Output W5 INIT# Asynch GTL+ Input
T3 VSS Power/Other W6 VSS Power/Other
T4 A#[26] Source Synch Input/Output W21 VSS Power/Other
T5 A#[30] Source Synch Input/Output W22 DSTBN#[3] Source Synch Input/Output
T6 VSS Power/Other W23 DSTBP#[3] Source Synch Input/Output
T21 VSS Power/Other W24 VSS Power/Other
T22 D#[46] Source Synch Input/Output W25 D#[57] Source Synch Input/Output
T23 D#[47] Source Synch Input/Output W26 D#[55] Source Synch Input/Output
64
Table 30. Pin Listing by Pin Number
Pin Signal Buffer

Pin Name Direction
Number Type
Y1 A#[34] Source Synch Input/Output

Y2 VSS Power/Other
Y3 TESTHI10 Power/Other Input
Y4 STPCLK# Asynch GTL+ Input
Y5 VSS Power/Other
Y6 BPM#[3] Common Clock Input/Output
Y21 D#[60] Source Synch Input/Output
Y22 VSS Power/Other
Y25 VSS Power/Other
65
66
5.2 Alphabetical Signals Reference
Table 31. Signal Description (Page 1 of 8)

Name Type Description
A[35:3]# (Address) define a 236-byte physical memory address space. In sub-

phase 1 of the address phase, these pins transmit the address of a transaction.
In sub-phase 2, these pins transmit transaction type information. These signals
must connect the appropriate pins of all agents on the Pentium 4 processor in
Input/ the 478-pin package system bus. A[35:3]# are protected by parity signals
A[35:3]# AP[1:0]#. A[35:3]# are source synchronous signals and are latched into the
Output
receiving buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processor samples a subset
of the A[35:3]# pins to determine power-on configuration. See Section 7.1 for
more details.
If A20M# (Address-20 Mask) is asserted, the processor masks physical address
bit 20 (A20#) before looking up a line in any internal cache and before driving a
read/write transaction on the bus. Asserting A20M# emulates the 8086
processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M#
A20M# Input is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the transaction
address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS#
Input/
ADS# activation to begin parity checking, protocol checking, address decode, internal
Output
snoop, or deferred reply ID match operations associated with the new
transaction.
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and
falling edges. Strobes are associated with signals as shown below.
Input/ Signals Associated Strobe

ADSTB[1:0]#
Output
REQ[4:0]#, A[16:3]# ADSTB0#
A[35:17]# ADSTB1#
AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,
A[35:3]#, and the transaction type on the REQ[4:0]#. A correct parity signal is
high if an even number of covered signals are low and low if an odd number of
covered signals are low. This allows parity to be high when all the covered
signals are high. AP[1:0]# should connect the appropriate pins of all Pentium 4
processor in the 478-pin package system bus agents. The following table defines
the coverage model of these signals.
Input/
AP[1:0]#
Output
Request Signals subphase 1 subphase 2
A[35:24]# AP0# AP1#
A[23:3]# AP1# AP0#
REQ[4:0]# AP1# AP0#
The differential pair BCLK (Bus Clock) determines the system bus frequency. All
processor system bus agents must receive these signals to drive their outputs
BCLK[1:0] Input and latch their inputs.
All external timing parameters are specified with respect to the rising edge of
BCLK0 crossing VCROSS.
67

BINIT# (Bus Initialization) may be observed and driven by all processor system
bus agents and if used, must connect the appropriate pins of all such agents. If
the BINIT# driver is enabled during power-on configuration, BINIT# is asserted
to signal any bus condition that prevents reliable future operation.
If BINIT# observation is enabled during power-on configuration, and BINIT# is
sampled asserted, symmetric agents reset their bus LOCK# activity and bus
Input/
BINIT# request arbitration state machines. The bus agents do not reset their IOQ and
Output
transaction tracking state machines upon observation of BINIT# activation. Once
the BINIT# assertion has been observed, the bus agents will re-arbitrate for the
system bus and attempt completion of their bus queue and IOQ entries.
If BINIT# observation is disabled during power-on configuration, a central agent
may handle an assertion of BINIT# as appropriate to the error handling
architecture of the system.
BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is
Input/
BNR# unable to accept new bus transactions. During a bus stall, the current bus owner
Output
cannot issue any new transactions.
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor
signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance. BPM[5:0]# should connect the appropriate pins of all Pentium 4
processor in the 478-pin package system bus agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is
a processor output used by debug tools to determine processor debug
Input/ readiness.
BPM[5:0]#
Output
BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ#
is used by debug tools to request debug operation of the processor.
Please refer to the Intel® Pentium® 4 Processor in the 478-pin Package and
Intel® 850 Chipset Platform Design Guide for more detailed information.
These signals do not have on-die termination. Refer to Section 2.5, the
Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850
Chipset Platform Design Guide for termination requirements.
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor
system bus. It must connect the appropriate pins of all processor system bus
agents. Observing BPRI# active (as asserted by the priority agent) causes all
BPRI# Input
other agents to stop issuing new requests, unless such requests are part of an
ongoing locked operation. The priority agent keeps BPRI# asserted until all of its
requests are completed, then releases the bus by deasserting BPRI#.
BR0# drives the BREQ0# signal in the system and is used by the processor to
Input/ request the bus. During power-on configuration this pin is sampled to determine
BR0# the agent ID = 0.
Output
This signal does not have on-die termination and must be terminated.
The BCLK[1:0] frequency select signals BSEL[1:0] are used to select the
processor input clock frequency. Table 4 defines the possible combinations of
the signals and the frequency associated with each combination. The required
frequency is determined by the processor, chipset and clock synthesizer. All
BSEL[1:0] Output agents must operate at the same frequency. The Pentium 4 processor in the
478-pin package operates currently at a 400 MHz system bus frequency (100
MHz BCLK[1:0] frequency). For more information about these pins, including
termination recommendations refer to Section 2.9 and the appropriate platform
design guidelines.
COMP[1:0] must be terminated on the system board using precision resistors.
COMP[1:0] Analog Refer to the Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850
Chipset Platform Design Guide for details on implementation.
68

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path
between the processor system bus agents, and must connect the appropriate
pins on all such agents. The data driver asserts DRDY# to indicate a valid data
transfer.
D[63:0]# are quad-pumped signals and will thus be driven four times in a
common clock period. D[63:0]# are latched off the falling edge of both
DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a
pair of one DSTBP# and one DSTBN#. The following table shows the grouping
of data signals to data strobes and DBI#.
Quad-Pumped Signal Groups
Input/ DSTBN#/
D[63:0]# Data Group DBI#
Output DSTBP#
D[15:0]# 0 0
D[31:16]# 1 1
D[47:32]# 2 2
D[63:48]# 3 3
Furthermore, the DBI# pins determine the polarity of the data signals. Each
group of 16 data signals corresponds to one DBI# signal. When the DBI# signal
is active, the corresponding data group is inverted and therefore sampled active
high.
DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]#
signals. The DBI[3:0]# signals are activated when the data on the data bus is
inverted. The bus agent will invert the data bus signals if more than half the bits,
within the covered group, would change level in the next cycle.
DBI[3:0] Assignment To Data Bus
Input/ Bus Signal Data Bus Signals

DBI[3:0]#
Output
DBI3# D[63:48]#
DBI2# D[47:32]#
DBI1# D[31:16]#
DBI0# D[15:0]#
DBR# is used only in processor systems where no debug port is implemented on

the system board. DBR# is used by a debug port interposer so that an in-target
DBR# Output
probe can drive system reset. If a debug port is implemented in the system,
DBR# is a no connect in the system. DBR# is not a processor signal.
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on
Input/ the processor system bus to indicate that the data bus is in use. The data bus is
DBSY#
Output released after DBSY# is deasserted. This signal must connect the appropriate
pins on all processor system bus agents.
DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the
DEFER# Input
responsibility of the addressed memory or Input/Output agent. This signal must
connect the appropriate pins of all processor system bus agents.
DP[3:0]# (Data parity) provide parity protection for the D[63:0]# signals. They are
Input/ driven by the agent responsible for driving D[63:0]#, and must connect the
DP[3:0]#
Output appropriate pins of all Pentium 4 processor in the 478-pin package system bus
agents.
69

DRDY# (Data Ready) is asserted by the data driver on each data transfer,
Input/ indicating valid data on the data bus. In a multi-common clock data transfer,
DRDY#
Output DRDY# may be deasserted to insert idle clocks. This signal must connect the
appropriate pins of all processor system bus agents.
Data strobe used to latch in D[63:0]#.
Input/ D[15:0]#, DBI0# DSTBN0#

DSTBN[3:0]#
Output D[31:16]#, DBI1# DSTBN1#
D[47:32]#, DBI2# DSTBN2#
D[63:48]#, DBI3# DSTBN3#
Data strobe used to latch in D[63:0]#.
Input/ D[15:0]#, DBI0# DSTBP0#

DSTBP[3:0]#
Output
D[31:16]#, DBI1# DSTBP1#
D[47:32]#, DBI2# DSTBP2#
D[63:48]#, DBI3# DSTBP3#
FERR# (Floating-point Error) is asserted when the processor detects an

unmasked floating-point error. FERR# is similar to the ERROR# signal on the
FERR# Output
Intel 387 coprocessor, and is included for compatibility with systems using MS-
DOS*-type floating-point error reporting.
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF
should be set at 2/3 VCC. GTLREF is used by the AGTL+ receivers to determine if
GTLREF Input a signal is a logical 0 or logical 1. Refer to the Intel® Pentium® 4 Processor in
the 478-pin Package and Intel® 850 Chipset Platform Design Guide for more
information.
Input/
HIT# Output HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation
results. Any system bus agent may assert both HIT# and HITM# together to
indicate that it requires a snoop stall, which can be continued by reasserting
HITM# Input/ HIT# and HITM# together.
Output
IERR# (Internal Error) is asserted by a processor as the result of an internal
error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction
on the processor system bus. This transaction may optionally be converted to an
IERR# Output external error signal (e.g., NMI) by system core logic. The processor will keep
IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.
This signals does not have on-die termination. Refer to Section 2.5 for
termination requirements.
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions. If
IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an error.
IGNNE# Input IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
70

INIT# (Initialization), when asserted, resets integer registers inside the processor
without affecting its internal caches or floating-point registers. The processor
then begins execution at the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests during INIT#
INIT# Input assertion. INIT# is an asynchronous signal and must connect the appropriate
pins of all processor system bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
The ITPCLKOUT[1:0] pins do not provide any output for the Pentium® 4
ITPCLKOUT[1:0] Output processor in the 478-pin package. Refer to Section 2.5 for additional details and
termination requirements.
ITP_CLK[1:0] are copies of BCLK that are used only in processor systems
where no debug port is implemented on the system board. ITP_CLK[1:0] are
ITP_CLK[1:0] Input used as BCLK[1:0] references for a debug port implemented on an interposer. If
a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the
system. These are not processor signals.
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC
Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable
interrupt. INTR and NMI are backward compatible with the signals of those
LINT[1:0] Input names on the Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the
APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is
the default configuration.
LOCK# indicates to the system that a transaction must occur atomically. This
signal must connect the appropriate pins of all processor system bus agents. For
a locked sequence of transactions, LOCK# is asserted from the beginning of the
Input/ first transaction to the end of the last transaction.
LOCK#
Output When the priority agent asserts BPRI# to arbitrate for ownership of the processor
system bus, it will wait until it observes LOCK# deasserted. This enables
symmetric agents to retain ownership of the processor system bus throughout
the bus locked operation and ensure the atomicity of lock.
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error
without a bus protocol violation. It may be driven by all processor system bus
agents.
MCERR# assertion conditions are configurable at a system level. Assertion
options are defined by the following options:
Enabled or disabled.
Input/
MCERR# Asserted, if configured, for internal errors along with IERR#.
Output
Asserted, if configured, by the request initiator of a bus transaction
after it observes an error.
Asserted by any bus agent when it observes an error in a bus
transaction.
For more details regarding machine check architecture, please refer to the IA-32
Software Developer’s Manual, Volume 3: System Programming Guide.
PROCHOT# will go active when the processor temperature monitoring sensor
detects that the processor has reached its maximum safe operating temperature.
PROCHOT# Output
This indicates that the processor Thermal Control Circuit has been activated, if
enabled. See Section 7.3 for more details.
71

PWRGOOD (Power Good) is a processor input. The processor requires this

signal to be a clean indication that the clocks and power supplies are stable and
within their specifications. ‘Clean’ implies that the signal will remain low (capable
of sinking leakage current), without glitches, from the time that the power
supplies are turned on until they come within specification. The signal must then
transition monotonically to a high state. Figure 11 illustrates the relationship of
PWRGOOD Input PWRGOOD to the RESET# signal. PWRGOOD can be driven inactive at any
time, but clocks and power must again be stable before a subsequent rising
edge of PWRGOOD. It must also meet the minimum pulse width specification in
Table 16, and be followed by a 1 to 10 ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
REQ[4:0]# (Request Command) must connect the appropriate pins of all
processor system bus agents. They are asserted by the current bus owner to
Input/
REQ[4:0]# define the currently active transaction type. These signals are source
Output
synchronous to ADSTB0#. Refer to the AP[1:0]# signal description for a details
on parity checking of these signals.
Asserting the RESET# signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents. For a
power-on Reset, RESET# must stay active for at least one millisecond after VCC
and BCLK have reached their proper specifications. On observing active
RESET#, all system bus agents will deassert their outputs within two clocks.
RESET# must not be kept asserted for more than 10 ms while PWRGOOD is
RESET# Input asserted.
A number of bus signals are sampled at the active-to-inactive transition of
RESET# for power-on configuration. These configuration options are described
in the Section 7.1.
This signal does not have on-die termination and must be terminated on
the system board.
RS[2:0]# (Response Status) are driven by the response agent (the agent
RS[2:0]# Input responsible for completion of the current transaction), and must connect the
RSP# (Response Parity) is driven by the response agent (the agent responsible
for completion of the current transaction) during assertion of RS[2:0]#, the
signals for which RSP# provides parity protection. It must connect to the
RSP# Input
A correct parity signal is high if an even number of covered signals are low and
low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is
also high, since this indicates it is not being driven by any agent guaranteeing
correct parity.
SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System
SKTOCC# Output
board designers may use this pin to determine if the processor is present.
SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter
the Sleep state. During Sleep state, the processor stops providing internal clock
signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor
will recognize only assertion of the RESET# signal, deassertion of SLP#, and
SLP# Input
removal of the BCLK input while in Sleep state. If SLP# is deasserted, the
processor exits Sleep state and returns to Stop-Grant state, restarting its internal
clock signals to the bus and processor core units. If the BCLK input is stopped
while in the Sleep state the processor will exit the Sleep state and transition to
the Deep Sleep state.
72

SMI# (System Management Interrupt) is asserted asynchronously by system

logic. On accepting a System Management Interrupt, the processor saves the
current state and enter System Management Mode (SMM). An SMI
SMI# Input Acknowledge transaction is issued, and the processor begins program execution
from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor will tristate
its outputs.
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the system bus and APIC units. The processor continues to snoop bus
STPCLK# Input
transactions and service interrupts while in Stop-Grant state. When STPCLK# is
deasserted, the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK#
is an asynchronous input.
TCK (Test Clock) provides the clock input for the processor Test Bus (also known
TCK Input
as the Test Access Port).
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
TDI Input
serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor. TDO
TDO Output
provides the serial output needed for JTAG specification support.
TESTHI[12:8] TESTHI[12:8] and TESTHI[5:0] must be connected to a VCC power source

Input through a resistor for proper processor operation. See Section 2.5 for more
TESTHI[5:0] details.
THERMDA Other Thermal Diode Anode. See Section 7.3.1.
THERMDC Other Thermal Diode Cathode. See Section 7.3.1.
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level beyond which permanent silicon damage may
occur. Measurement of the temperature is accomplished through an internal
thermal sensor which is configured to trip at approximately 135°C. Upon
assertion of THERMTRIP#, the processor will shut off its internal clocks (thus
halting program execution) in an attempt to reduce the processor junction
THERMTRIP# Output temperature. To protect the processor, its core voltage (VCC) must be removed
following the assertion of THERMTRIP#. See Figure 12 and Table 16 for the
appropriate power down sequence and timing requirements. Once activated,
THERMTRIP# remains latched until RESET# is asserted. While the assertion of
the RESET# signal will de-assert THERMTRIP# , if the processor’s junction
temperature remains at or above the trip level, THERMTRIP# will again be
asserted after RESET# is de-asserted.
TMS (Test Mode Select) is a JTAG specification support signal used by debug
TMS Input
tools.
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to
TRDY# Input receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all system bus agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be
TRST# Input driven low during power on Reset. This can be done with a 680 Ω pull-down
resistor.
VCCA provides isolated power for the internal processor core PLLs. Refer to the
VCCA Input Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset
Platform Design Guide for complete implementation details.
73

VCCIOPLL provides isolated power for internal processor system bus PLLs. Follow
the guidelines for VCCA, and refer to the Intel® Pentium® 4 Processor in the 478-
VCCIOPLL Input
pin Package and Intel® 850 Chipset Platform Design Guide for complete
VCCSENSE is an isolated low impedance connection to processor core power
VCCSENSE Output
(VCC). It can be used to sense or measure power near the silicon with little noise.
There is no imput voltage requirement for VCCVID for designs intended to
support only the Pentium 4 processor in the 478-pin package. Refer to the Intel®
VCCVID Input
Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform
Design Guide for more information.
VID[4:0] (Voltage ID) pins can be used to support automatic selection of power
supply voltages (Vcc). These pins are not signals, but are either an open circuit
or a short circuit to VSS on the processor. The combination of opens and shorts
VID[4:0] Output defines the voltage required by the processor. The VID pins are needed to
cleanly support processor voltage specification variations. See Table 2 for
definitions of these pins. The power supply must supply the voltage that is
requested by these pins, or disable itself.
VSSA Input VSSA is the isolated ground for internal PLLs.
VSSSENSE is an isolated low impedance connection to processor core VSS. It can
VSSSENSE Output
be used to sense or measure ground near the silicon with little noise
74
6.0 Thermal Specifications and Design Considerations
The Pentium® 4 processor in the 478-pin package uses an integrated heat spreader (IHS)
for heatsink attachment which is intended to provide for multiple types of thermal
solutions. This section will provide data necessary for development of a thermal solution.
See Figure 25 for an exploded view of an example Pentium 4 processor in the 478-pin
package thermal solution. This is for illustration purposes. For further thermal solution
design details, please refer to the Intel® Pentium® 4 Processor in the 478-pin Package
Thermal Design Guide.
75
Note: The processor is either shipped by itself or with a heatsink for boxed processors. See
Chapter 8.0 for details on boxed processors.
Figure 25. Example Pentium® 4 Processor in the 478-pin Package Thermal Solution (Not to
scale)
Clip Assembly
Fan/Shroud
Heatsink
Retention
Mechanism
Processor
mPGA478B
478-pin Socket
76
6.1 Thermal Specifications

Table 32 specifies the thermal design power dissipation envelope for Pentium 4 processor
in the 478-pin package. Analysis indicates that real applications are unlikely to cause the
processor to consume the maximum possible power consumption. Intel recommends that
system thermal designs target the “Thermal Design Power” indicated in Table 32 instead
of “Max Processor Power.” The Thermal Monitor feature (refer to Section 7.3) is designed
to help protect the processor from overheating while executing high power code that
exceeds the recommendations in this table. For more details on the usage of this feature,
refer to Section 7.3. To ensure maximum flexibility, systems should be designed to the
Flexible Motherboard guidelines, even if a processor with a lower thermal dissipation is
planned. In all cases the Thermal Monitor feature must be enabled for the processor
to be in specification. Table 32 also lists the maximum and minimum processor
temperature specifications for TCASE. A thermal solution must be designed to ensure the
temperature of the processor does not exceed these specifications.
Table 32. Pentium® 4 Processor in the 478-pin Package Thermal Design Power
Processor and Minimum Maximum
Thermal Design
Core Frequency TCASE TCASE Notes1
Power2 (W)
(GHz) (°C) (°C)
1.50 GHz 57.9 5 73

1.60 GHz 60.8 5 75
1.70 GHz 63.5 5 76
1.80 GHz 66.1 5 77
1.90 GHz 72.8 5 75
2 GHz 75.3 5 76
NOTES:
1. These values are specified at VCC_MAX for the processor. The processor should not be subjected to any
static Vcc and Icc combination wherein Vcc exceeds VCC_MAX for a given current.
2. The numbers in this column reflect Intel’s recommended design point and are not indicative of the maximum
power the processor can dissipate under worst conditions. For more details refer to the Intel® Pentium® 4
Processor in the 478-pin Package Thermal Design Guide.
6.2 Thermal Analysis
6.2.1 Thermal Solution Performance

Refer to the Intel® Pentium® 4 Processor in the 478-pin Package Thermal Design Guide.
6.2.2 Measurements For Thermal Specifications
6.2.2.1 Processor Case Temperature Measurement

The maximum and minimum case temperature (TCASE) for the Pentium 4 processor in the
478-pin package is specified in Table 32. This temperature specification is meant to
ensure correct and reliable operation of the processor. Figure 26 illustrates where Intel
recommends TCASE thermal measurements should be made.
77
Figure 26. Guideline Locations for Case Temperature (TCASE) Thermocouple Placement
Measure from edge of processor
0.689”
17.5 mm
Measure TCASE
at this point.
0.689”
17.5 mm
35 mm Package
Thermal interface material (TIM)

should cover the entire surface of
the Integrated Heat Spreader
78
7.0 Features
7.1 Power-On Configuration Options

Several configuration options can be configured by hardware. The Pentium® 4 processor
in the 478-pin package samples the hardware configuration at reset, on the active-to-
inactive transition of RESET#. For specifications on these options, please refer to Table
33.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor; for reset purposes, the processor does not distinguish between a "warm"
reset and a "power-on" reset.
Table 33. Power-On Configuration Option Pins

Configuration Option Pin1
Output tristate SMI#
Execute BIST INIT#
In Order Queue pipelining (set IOQ depth to 1) A7#
Disable MCERR# observation A9#
Disable BINIT# observation A10#
APIC Cluster ID (0-3) A[12:11]#
Disable bus parking A15#
Symmetric agent arbitration ID BR0#
NOTE:
1. Asserting this signal during RESET# will select the corresponding option.
7.2 Clock Control and Low Power States

The use of AutoHALT, Stop-Grant, Sleep, and Deep Sleep states is allowed in Pentium 4
processor in the 478-pin package based systems to reduce power consumption by
stopping the clock to internal sections of the processor, depending on each particular
state. See Figure 27 for a visual representation of the processor low power states.
7.2.1 Normal State—State 1

This is the normal operating state for the processor.
7.2.2 AutoHALT Powerdown State—State 2

AutoHALT is a low power state entered when the processor executes the HALT
instruction. The processor will transition to the Normal state upon the occurrence of SMI#,
BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately
initialize itself.
79
The return from a System Management Interrupt (SMI) handler can be to either Normal
Mode or the AutoHALT Power Down state. See the Intel Architecture Software
Developer's Manual, Volume III: System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the AutoHALT Power
Down state. When the system deasserts the STPCLK# interrupt, the processor will return
execution to the HALT state.
While in AutoHALT Power Down state, the processor will process bus snoops.
Figure 27. Stop Clock State Machine
HALT Instruction and

HALT Bus Cycle Generated
2. Auto HALT Power Down State 1. Normal State
INIT#, BINIT#, INTR, NMI, Normal execution.
BCLK running.
SMI#, RESET#
Snoops and interrupts allowed.
S TP
CLK
# As
serte
d STPCLK# STPCLK#
Snoop Snoop ST P
CL K
Event Event # De Asserted De-asserted
- a ss
Occurs Serviced erted
4. HALT/Grant Snoop State Snoop Event Occurs 3. Stop Grant State

BCLK running. BCLK running.
Service snoops to caches. Snoop Event Serviced Snoops and interrupts allowed.
SLP# SLP#
Asserted De-asserted
5. Sleep State
BCLK running.
No snoops or interrupts allowed.
BCLK BCLK
Input Input
Stopped Restarted
6. Deep Sleep State

BCLK stopped.
No snoops or interrupts allowed.
7.2.3 Stop-Grant State—State 3

When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20
bus clocks after the response phase of the processor-issued Stop Grant Acknowledge
special bus cycle. Once the STPCLK# pin has been asserted, it may only be deasserted
once the processor is in the Stop Grant state.
80
Since the AGTL+ signal pins receive power from the system bus, these pins should not be
driven (allowing the level to return to VCC) for minimum power drawn by the termination
resistors in this state. In addition, all other input pins on the system bus should be driven
to the inactive state.
BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be
latched and can be serviced by software upon exit from the Stop Grant state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay
in Stop-Grant state. A transition back to the Normal state will occur with the de-assertion
of the STPCLK# signal. When re-entering the Stop Grant state from the Sleep state,
STPCLK# should only be de-asserted one or more bus clocks after the de-assertion of
SLP#.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop
on the system bus (see Section 7.2.4). A transition to the Sleep state (see Section 7.2.5)
will occur with the assertion of the SLP# signal.
While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the
processor, and only serviced when the processor returns to the Normal State. Only one
occurrence of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process a system bus snoop.
7.2.4 HALT/Grant Snoop State—State 4

The processor will respond to snoop transactions on the system bus while in Stop-Grant
state or in AutoHALT Power Down state. During a snoop transaction, the processor enters
the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the
system bus has been serviced (whether by the processor or another agent on the system
bus). After the snoop is serviced, the processor will return to the Stop-Grant state or
AutoHALT Power Down state, as appropriate.
7.2.5 Sleep State—State 5

The Sleep state is a very low power state in which the processor maintains its context,
maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep
state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the
processor will enter the Sleep state upon the assertion of the SLP# signal. The SLP# pin
should only be asserted when the processor is in the Stop Grant state. SLP# assertions
while the processor is not in the Stop Grant state is out of specification and may result in
unapproved operation.
Snoop events that occur while in Sleep State or during a transition into or out of Sleep
state will cause unpredictable behavior.
In the Sleep state, the processor is incapable of responding to snoop transactions or

latching interrupt signals. No transitions or assertions of signals (with the exception of
SLP# or RESET#) are allowed on the system bus while the processor is in Sleep state.
Any transition on an input signal before the processor has returned to Stop-Grant state will
result in unpredictable behaviour.
81
If RESET# is driven active while the processor is in the Sleep state, and held active as
specified in the RESET# pin specification, then the processor will reset itself, ignoring the
transition through Stop-Grant State. If RESET# is driven active while the processor is in
the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after
RESET# is asserted to ensure the processor correctly executes the Reset sequence.
While in the Sleep state, the processor is capable of entering its lowest power state, the
Deep Sleep state, by stopping the BCLK[1:0] inputs. (See Section 7.2.6). Once in the
Sleep or Deep Sleep states, the SLP# pin must be de-asserted if another asynchronous
system bus event needs to occur. The SLP# pin has a minimum assertion of one BCLK
period.
When the processor is in Sleep state, it will not respond to interrupts or snoop
transactions.
7.2.6 Deep Sleep State—State 6

Deep Sleep state is the lowest power state the processor can enter while maintaining
context. Deep Sleep state is entered by stopping the BCLK[1:0] inputs (after the Sleep
state was entered from the assertion of the SLP# pin). The processor is in Deep Sleep
state immediately after BLCK[1:0] is stopped. To provide maximum power conservation
hold the BLCK0 input at VOL and the BCLK1 input at VOH during the Deep Sleep state.
Stopping the BCLK input lowers the overall current consumption to leakage levels.
To re-enter the Sleep state, the BLCK input must be restarted. A period of 1 ms (to allow
for PLL stabilization) must occur before the processor can be considered to be in the
Sleep State. Once in the Sleep state, the SLP# pin can be deasserted to re-enter the
Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions
or latching interrupt signals. No transitions or assertions of signals are allowed on the
system bus while the processor is in Deep Sleep state. Any transition on an input signal
before the processor has returned to Stop-Grant state will result in unpredictable
behaviour. The processor has to stay in Deep Sleep mode for minimum of 25 µs.
When the processor is in Deep Sleep state, it will not respond to interrupts or snoop
transactions.
7.3 Thermal Monitor

The Thermal Monitor feature found in the Pentium 4 processor in the 478-pin package
allows system designers to design lower cost thermal solutions without compromising
system integrity or reliability. By using a factory-tuned, precision on-die thermal sensor,
and a fast acting thermal control circuit (TCC), the processor, without the aid of any
additional software or hardware, can keep the processor’s die temperature within factory
specifications under nearly all conditions. Thermal Monitor thus allows the processor and
system thermal solutions to be designed much closer to the power envelopes of real
applications, instead of being designed to the much higher maximum processor power
envelopes.
82
Thermal Monitor controls the processor temperature by modulating the internal processor
core clocks. The processor clocks are modulated when the TCC is activated. Thermal
Monitor uses two modes to activate the TCC: Automatic mode and On-Demand mode.
Automatic mode is required for the processor to operate within specifications and
must first be enabled via BIOS. Once automatic mode is enabled, the TCC will activate
only when the internal die temperature is very near the temperature limits of the
processor. When TCC is enabled, and a high temperature situation exists (i.e. TCC is
active), the clocks will be modulated by alternately turning the clocks off and on at a 50%
duty cycle. Clocks will not be off for more than 3 µs when TCC is active. Cycle times are
processor speed dependent and will decrease linearly as processor core frequencies
increase. A small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near the trip point. Once the
temperature has returned to a non-critical level, and the hysteresis timer has expired,
modulation ceases and TCC goes inactive. Processor performance will be decrease by
~50% when the TCC is active (assuming a 50% duty cycle), however, with a properly
designed and characterised thermal solution the TCC most likely will only be activated
briefly when the system is near maximum temperature and during the most power
intensive applications.
For automatic mode, the 50% duty cycle is factory configured and cannot be modified.
Also, automatic mode does not require any additional hardware, software drivers or
interrupt handling routines.
The TCC may also be activated via On-Demand mode. If bit 4 of the ACPI Thermal
Monitor Control Register is written to a "1" the TCC will be activated immediately,
independent of the processor temperature. When using On-Demand mode to activate the
TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same
ACPI Thermal Monitor Control Register. In automatic mode, the duty cycle is fixed at 50%
on, 50% off, however in On-Demand mode, the duty cycle can be programmed from
12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may
be used at the same time automatic mode is enabled, however, if the system tries to
enable the TCC via On-Demand mode at the same time automatic mode is enabled AND
a high temperature condition exists, the 50% duty cycle of the automatic mode will
override the duty cycle selected by the On-Demand mode.
An external signal, PROCHOT# (processor hot) is asserted at any time the TCC is active
(either in automatic or On-Demand mode). Bus snooping and interrupt latching are also
active while the TCC is active. The temperature at which the thermal control circuit
activates is not user configurable and is not software visible.
Besides the thermal sensor and thermal control circuit, the Thermal Monitor feature also
includes one ACPI register, one performance counter register, three model specific
registers (MSR), and one I/O pin (PROCHOT#). All are available to monitor and control
the state of the Thermal Monitor feature. Thermal Monitor can be configured to generate
an interrupt upon the assertion or de-assertion of PROCHOT# (i.e. upon the activation/
deactivation of TCC).
If automatic mode is disabled the processor will be operating out of specification and
cannot be guaranteed to provide reliable results. Regardless of enabling of the automatic
or On-Demand modes, in the event of a catastrophic cooling failure, the processor will
automatically shut down when the silicon has reached a temperature of approximately
135 °C. At this point the system bus signal THERMTRIP# will go active and stay active
until RESET# has been initiated. THERMTRIP# activation is independent of processor
activity and does not generate any bus cycles. If THERMTRIP# is asserted, processor
core voltage (Vcc) must be removed within the timeframe defined in Table 16.
83
7.3.1 Thermal Diode

The Pentium 4 processor in the 478-pin package incorporates an on-die thermal diode. A
thermal sensor located on the system board may monitor the die temperature of the
Pentium 4 processor in the 478-pin package for thermal management/long term die
temperature change purposes. Table 34 and Table 35 provide the diode parameter and
interface specifications. This thermal diode is separate from the Thermal Monitor’s
thermal sensor and cannot be used to predict the behavior of the Thermal Monitor.
Table 34. Thermal Diode Parameters

Symbol Min Typ Max Unit Notes1
Iforward bias 5 450 uA 2

n_ideality 0.9933 1.0045 1.0368 3, 4
NOTES:
2. Intel does not support or recommend operation of the thermal diode under reverse bias.
3. At room temperature with a forward bias of 630 mV.
4. n_ideality is the diode ideality factor parameter, as represented by the diode equation:
I=Io(e (Vd*q)/(nkT) - 1).
Table 35. Thermal Diode Interface

Pin Name Pin Number Pin Description
THERMDA B3 diode anode

THERMDC C4 diode cathode
84
8.0 Boxed Processor Specifications
8.1 Introduction
The Pentium® 4 processor in the 478-pin package will also be offered as an Intel boxed
processor. Intel boxed processors are intended for system integrators who build systems
from motherboards and standard components. The boxed Pentium 4 processor in the
478-pin package will be supplied with a cooling solution. This chapter documents
motherboard and system requirements for the cooling solution that will be supplied with
the boxed Pentium 4 processor in the 478-pin package. This chapter is particularly
important for OEMs that manufacture motherboards for system integrators. Unless
otherwise noted, all figures in this chapter are dimensioned in millimeters and inches [in
brackets]. Figure 28 shows a mechanical representation of a boxed Pentium 4 processor
in the 478-pin package.
*NOTE* Drawings in this section reflect only the specifications on the Intel boxed
processor product. These dimensions should not be used as a generic keep-out zone for
all cooling solutions. It is the system designer's responsibility to consider their proprietary
cooling solution when designing to the required keep-out zone on their system platform
and chassis. Refer to the Intel® Pentium® 4 Processor in the 478-pin Package Thermal
Design Guide for further guidance. Contact your local Intel Sales Representative for this
document.
Figure 28. Mechanical Representation of the Boxed Pentium® 4 Processor in the 478-pin
Package
NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.
85
8.2 Mechanical Specifications
8.2.1 Boxed Processor Cooling Solution Dimensions

This section documents the mechanical specifications of the boxed Pentium 4 processor
in the 478-pin package. The boxed processor will be shipped with an unattached fan
heatsink. Figure 28 shows a mechanical representation of the boxed Pentium 4 processor
in the 478-pin package.
Clearance is required around the fan heatsink to ensure unimpeded airflow for proper
cooling. The physical space requirements and dimensions for the boxed processor with
assembled fan heatsink are shown in Figure 29 (Side Views), and Figure 30 (Top View).
The airspace requirements for the boxed processor fan heatsink must also be
incorporated into new motherboard and system designs. Airspace requirements are
shown in Figure 33 and Figure 34. Note that some figures have centerlines shown
(marked with alphabetic designations) to clarify relative dimensioning.
Figure 29. Side View Space Requirements for the Boxed Processor
86
Figure 30. Top View Space Requirements for the Boxed Processor
8.2.2 Boxed Processor Fan Heatsink Weight

The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 6.0
and the Intel® Pentium® 4 Processor in the 478-pin Package Thermal Design Guide for
details on the processor weight and heatsink requirements.
8.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip

Assembly
The boxed processor thermal solution requires a processor retention mechanism and a
heatsink attach clip assembly, to secure the processor and fan heatsink in the baseboard
socket. The boxed processor will not ship with retention mechanisms but will ship with the
heatsink attach clip assembly. Motherboards designed for use by system integrators
should include the retention mechanism that supports the boxed Pentium 4 processor in
the 478-pin package. Motherboard documentation should include appropriate retention
mechanism installation instructions.
87
Note: The processor retention mechanism based on the Intel reference design should be
used, to ensure compatibility with the heatsink attach clip assembly and the boxed
processor thermal solution. The heatsink attach clip assembly is latched to the retention
tab features at each corner of the retention mechanism.
8.3 Electrical Requirements
8.3.1 Fan Heatsink Power Supply

The boxed processor's fan heatsink requires a +12V power supply. A fan power cable will
be shipped with the boxed processor to draw power from a power header on the
motherboard. The power cable connector and pinout are shown in Figure 31.
Motherboards must provide a matched power header to support the boxed processor.
Table 36 contains specifications for the input and output signals at the fan heatsink
connector. The fan heatsink outputs a SENSE signal, which is an open-collector output
that pulses at a rate of two pulses per fan revolution. A motherboard pull-up resistor
provides VOH to match the system board-mounted fan speed monitor requirements, if
applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of
the connector should be tied to GND.
The power header on the baseboard must be positioned to allow the fan heatsink power
cable to reach it. The power header identification and location should be documented in
the platform documentation, or on the system board itself. Figure 32 shows the location of
the fan power connector relative to the processor socket. The motherboard power header
should be positioned within 4.33 inches from the center of the processor socket.
Figure 31. Boxed Processor Fan Heatsink Power Cable Connector Description
Pin Signal
1 GND Straight square pin, 3-pin terminal housing with

polarizing ribs and friction locking ramp.
2 +12V 0.100" pin pitch, 0.025" square pin width.
3 SENSE Waldom*/Molex* P/N 22-01-3037 or equivalent.
Match with straight pin, friction lock header on motherboard

Waldom/Molex P/N 22-23-2031, AMP* P/N 640456-3,
or equivalent.
1 2 3
88
Table 36. Fan Heatsink Power and Signal Specifications

Description Min Typ Max Unit Notes
+12V: 12 volt fan power supply 10.2 12 13.8 V

IC: Fan current draw 740 mA
pulses per fan
SENSE: SENSE frequency 2 1
revolution
NOTE:
1. Motherboard should pull this pin up to VCC with a resistor.
Figure 32. MotherBoard Power Header Placement Relative to Processor Socket
8.4 Thermal Specifications

This section describes the cooling requirements of the fan heatsink solution utilized by the
boxed processor.
89
8.4.1 Boxed Processor Cooling Requirements

The boxed processor may be directly cooled with a fan heatsink. However, meeting the
processor's temperature specification is also function of the thermal design of the entire
system, and ultimately the responsibility of the system integrator. The processor
temperature specification is found in Chapter 6.0 of this document. The boxed processor
fan heatsink is able to keep the processor temperature within the specifications (see Table
32) in chassis that provide good thermal management. For the boxed processor fan
heatsink to operate properly, it is critical that the airflow provided to the fan heatsink is
unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan
heatsink. Airspace is required around the fan to ensure that the airflow through the fan
heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling
efficiency and decreases fan life. Figure 33 and Figure 34 illustrate an acceptable
airspace clearance for the fan heatsink. The air temperature entering the fan should be
kept below 40°C. Again, meeting the processor's temperature specification is the
responsibility of the system integrator.
Figure 33. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)
90
Figure 34. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)
8.4.2 Variable Speed Fan

The boxed processor fan will operate at different speeds over a short range of internal
chassis temperatures. This allows the processor fan to operate at a lower speed and
noise level, while internal chassis temperatures are low. If internal chassis temperature
increases beyond a lower set point, the fan speed will rise linearly with the internal
temperature until the higher set point is reached. At that point, the fan speed is at its
maximum. As fan speed increases, so does fan noise levels. Systems should be designed
to provide adequate air around the boxed processor fan heatsink that remains below the
lower set point. These set points, represented in Figure 35 and Table 37, can vary by a
few degrees from fan heatsink to fan heatsink. The internal chassis temperature should be
kept below 40ºC. Meeting the processor’s temperature specification (see Chapter 6.0) is
the responsibility of the system integrator.
Figure 35. Boxed Processor Fan Heatsink Set Points
91
Table 37. Boxed Processor Fan Heatsink Set Points

Boxed Processor Fan
Boxed Processor Fan Speed Notes
Heatsink Set Point (ºC)
When the internal chassis temperature is below or equal to this

set point, the fan operates at its lowest speed. Recommended
33 1
maximum internal chassis temperature for nominal operating
environment.
When the internal chassis temperature is at this point, the fan
operates between its lowest and highest speeds. Recommended
40
maximum internal chassis temperature for worst-case operating
environment.
When the internal chassis temperature is above or equal to this
43 1
set point, the fan operates at its highest speed.
NOTE:
1. Set point variance is approximately ±1°C from fan heatsink to fan heatsink
92
9.0 Debug Tools Specifications
Please refer to the ITP700 Debug Port Design Guide and the Intel® Pentium® 4
Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide for
information regarding debug tools specifications.
9.1 Logic Analyzer Interface (LAI)

Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs)
for use in debugging Pentium 4 processor in the 478-pin package systems. Tektronix* and
Agilent* should be contacted to get specific information about their logic analyzer
interfaces. The following information is general in nature. Specific information must be
obtained from the logic analyzer vendor.
Due to the complexity of Pentium 4 processor in the 478-pin package systems, the LAI is
critical in providing the ability to probe and capture system bus signals. There are two sets
of considerations to keep in mind when designing a Pentium 4 processor in the 478-pin
package system that can make use of an LAI: mechanical and electrical.
9.1.1 Mechanical Considerations

The LAI is installed between the processor socket and the Pentium 4 processor in the
478-pin package. The LAI pins plug into the socket, while the Pentium 4 processor in the
478-pin package pins plug into a socket on the LAI. Cabling that is part of the LAI
egresses the system to allow an electrical connection between the Pentium 4 processor in
the 478-pin package and a logic analyzer. The maximum volume occupied by the LAI,
known as the keepout volume, as well as the cable egress restrictions, should be obtained
from the logic analyzer vendor. System designers must make sure that the keepout
volume remains unobstructed inside the system. Note that it is possible that the keepout
volume reserved for the LAI may differ from the space normally occupied by the Pentium 4
processor in the 478-pin package heatsink. If this is the case, the logic analyzer vendor
will provide a cooling solution as part of the LAI.
9.1.2 Electrical Considerations

The LAI will also affect the electrical performance of the system bus; therefore, it is critical
to obtain electrical load models from each of the logic analyzers to be able to run system
level simulations to prove that their tool will work in the system. Contact the logic analyzer
vendor for electrical specifications and load models for the LAI solution they provide.
93
94
A Configuration Timings .............................................. 33

A10#...........................................................................79
A15#...........................................................................79 D
A20M# .......................................................................16 DBSY#
definition of ........................................................67 definition of........................................................ 69
A7#.............................................................................79 DC Specifications...................................................... 19
A9#.............................................................................79 Debug Tools .............................................................. 93
ADSTB# Decoupling Guidelines.............................................. 11
definition of ........................................................67 Deep Sleep................................................................. 79
ADS# .........................................................................16 Deep Sleep State........................................................ 82
definition of ........................................................67 DEFER#
AGTL+.......................................................................19 definition of........................................................ 69
Alphabetical Signals Reference .................................67 Differential Clock Specifications .............................. 26
AP# differential clocking .................................................. 12
definition of ........................................................67 DINV#
Asychronous ..............................................................16 definition of........................................................ 69
Async GTL+ ............................................17, 23, 24, 28 DP#
AutoHALT.................................................................79 definition of........................................................ 69
AutoHALT Powerdown State....................................79 DRDY#
A# definition of........................................................ 70
defintion of..........................................................67 DSTBN#
definition of........................................................ 70
B DSTBP#
BCLK.......................................................12, 16, 26, 82 definition of........................................................ 70
definition of ........................................................67 D#
BCLK Signal Integrity Waveform.............................36 definition of........................................................ 69
BCLK Signal Quality Specifications .........................35
BCLK.See also System Bus Clock E
BINIT#.................................................................79, 81 Effective Series Resistance ....................................... 12
definition of ........................................................68 end bus agents ........................................................... 24
BNR# ESR.See Effective Series Resistance
definition of ........................................................68
Boxed Processor
Fan Heatsink Dimensions ...................................86 F
Fan Heatsink Weight ..........................................87 FERR#
Boxed Processor Requirements .................................88 definition of........................................................ 70
BPM# frequency................................................................... 12
definition of ........................................................68
BPRI# G
definition of ........................................................68 Ground Pins............................................................... 11
BR0# GTLREF.................................................................... 11
BR# ............................................................................79 GTLREF.See also Voltage reference
Bus Frequency ...........................................................26
Bus Voltage Definitions.............................................25
H
HALT ........................................................................ 79
C HALT/Grant Snoop State.......................................... 81
Clock Control.............................................................79 HALT/Grant Snoop state .......................................... 81
CMOS ..................................................................23, 24 HITM#
Common Clock AC Specifications............................26 definition of........................................................ 70
Common Clock Valid Delay Timings .......................31 HIT#
COMP# definition of........................................................ 70
definition of ........................................................68
95
I Power-On Reset ........................................................ 33

IERR# Processor Connector.................................................. 45
definition of ........................................................70 Processor Dimensions ............................................... 46
IGNNE#.....................................................................16 Processor Insertion Specifications ............................ 49
definition of ........................................................70 Processor Pin-Out Coordinates ................................. 50
IHS.See also Integrated heat spreader processor socket ........................................................ 13
INIT# ...................................................................79, 81 Processor storage temperature................................... 19
definition of ........................................................71 processor supply voltage ........................................... 19
input buffers...............................................................24 PROCHOT#
Integrated heat spreader ...............................................8 definition of........................................................ 71
integrated heat spreader .............................................75 PWRGOOD
Intel Architecture Software Developer's Manual ........9 definition of........................................................ 72
I/O buffer models.......................................................25
R
J reference voltage ....................................................... 24
JTAG Signals AC Specifications...............................28 REQ#
definition of........................................................ 72
RESERVED pins ...................................................... 15
L Reset Condition AC Specifications........................... 28
LINT ....................................................................79, 81 RESET#..................................................... 8, 79, 81, 82
LOCK# Retention mechanism .................................................. 8
definition of ........................................................71 Ringback Specifications............................................ 36
Low Power States ......................................................79 RSP#
definition of........................................................ 72
M RS#
Maximum Ratings .....................................................18 definition of........................................................ 72
MCERR#
definition of ........................................................71 S
mPA478-Pin Socket...................................................45 Sleep.......................................................................... 79
mPGA478 ....................................................................8 Sleep State................................................................. 81
SLP#.................................................................... 81, 82
N definition of........................................................ 72
NMI..............................................................................8 SMI#.................................................................... 79, 81
Normal State ..............................................................79 definition of........................................................ 73
snoop transaction....................................................... 81
snoop transactions ..................................................... 82
O Source Synchronous
Overshoot/Undershoot Strobe Timings............................................. 32, 33
Activity Factor....................................................38 source synchronous ................................................... 16
Guidelines...........................................................37 Source Synchronous AC Specifications.................... 26
Magnitude...........................................................38 Stop Clock State Machine......................................... 80
Pulse Duration ....................................................38 Stop-Grant ................................................................. 79
Tolerance ............................................................41 Stop-Grant State .................................................. 80, 81
Stop-Grant state......................................................... 81
P STPCLK#.................................................................. 80
definition of........................................................ 73
Package Mechanical Specifications...........................45
System Bus.................................................... 11, 12, 16
phase-locked loop ......................................................81
Pin Assignments ........................................................51 Reset and Configuration Timings ...................... 31
System bus .................................................................. 8
PLL.See phase-locked loop
System Bus AC Specifications.................................. 25
power distribution......................................................11
Power Pins .................................................................11 System Bus Clock ..................................................... 12
System Bus Signal Quality Specifications................ 36
Power-On Configuration ...........................................79
System Bus Specifications ........................................ 24
96
T TMS
TCK definition of........................................................ 73
definition of ........................................................73 TRDY#
TDI definition of........................................................ 73
definition of ........................................................73 TRST#
TDO definition of........................................................ 73
definition of ........................................................73
Termination resistors .................................................24 V
TESTHI......................................................................15 VCC........................................................................... 15
definition of ........................................................73 VccA
Thermal Analysis.......................................................77 definition of........................................................ 73
Thermal Diode ...........................................................84 VccIOPLL
Parameters...........................................................84 definition of........................................................ 74
Thermal Monitor..................................................77, 82 Vccsense
Thermal Power...........................................................77 definition of........................................................ 74
Thermal Solution VID............................................................................ 12
Locations for Case Temperature.........................78 definition of........................................................ 74
thermal solution .........................................................75 VID.See also voltage identification
Thermal Specifications ..............................................75 Voltage Identification................................................ 12
Measurements .....................................................77 Voltage Regulator Module ........................................ 12
THERMDA VRM.See Voltage Regulator Module
definition of ........................................................73 VSS ........................................................................... 15
THERMDC VssA
THERMTRIP# Vsssense .................................................................... 74
Timings
Test Reset............................................................34
97
98

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Intel® Pentium® 4 Processor in the 478-pin

Package at 1.50 GHz, 1.60 GHz, 1.70 GHz,

■ Advance Dynamic Execution — System Management mode

Order Number: 249887-001

5.2 Alphabetical Signals Reference .......................................................................... 67

The Streaming SIMD Extensions 2 enable break-through levels of performance in

1.1.1 Processor Packaging Terminology

Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850

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2.0 Electrical Specifications

2.1 System Bus and GTLREF

2.2 Power and Ground Pins

2.3 Decoupling Guidelines

2.3.1 VCC Decoupling

2.3.2 System Bus AGTL+ Decoupling

2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking

2.4 Voltage Identification

Table 2. Voltage Identification Definition

VID4 VID3 VID2 VID1 VID0 VCC_MAX

2.4.1 Phase Lock Loop (PLL) Power and Filter

The filter requirements are illustrated in Figure 2. For recommendations on implementing

DC 1 Hz fpeak 1 MHz 66 MHz fcore

passband high frequency

2.5 Reserved, Unused, and TESTHI Pins

For reliable operation, always connect unused inputs or bidirectional signals to an

2.6 System Bus Signal Groups

Table 3. System Bus Pin Groups

Signals Associated Strobe

REQ[4:0]#, A[16:3]#5 ADSTB0#

2.7 Asynchronous GTL+ Signals

2.8 Test Access Port (TAP) Connection

2.9 System Bus Frequency Select Signals (BSEL[1:0])

Table 4. BSEL[1:0] Frequency Table for BCLK[1:0]

2.10 Maximum Ratings

Table 5. Processor DC Absolute Maximum Ratings

2.11 Processor DC Specifications

Table 6. Voltage and Current Specifications

VCC for processor at

Table 7. Vcc Static and Transient Tolerance

0 0.000 -0.025 -0.050

Figure 3. Vcc Static and Transient Tolerance1, 2, 3

Icc Load [A]

Table 8. System Bus Differential BCLK Specifications

VL Input Low Voltage 0 V 6

Table 9. AGTL+ Signal Group DC Specifications

VIL Input Low Voltage 0.0 GTLREF - 0.100 V 2, 6

Table 10. Asynchronous GTL+ Signal Group DC Specifications

VIL Input Low Voltage 0.0 GTLREF-0.100 3

Table 11. TAP Signal Group DC Specifications

VHYS TAP Input Hysteresis 200 300 mV 8

2.12 AGTL+ System Bus Specifications

Table 12. AGTL+ Bus Voltage Definitions

2.13 System Bus AC Specifications

Table 13. System Bus Differential Clock Specifications

System Bus Frequency 100 MHz

Table 14. System Bus Common Clock AC Specifications

T10: Common Clock Output Valid Delay 0.200 1.45 ns 7 4

T20: Source Synchronous Data Output

T23: TVBA: Source Synchronous

Table 16. Asynchronous GTL+ Signals AC Specifications