Quectel EG91 Series Hardware Design V2.0
Quectel EG91 Series Hardware Design V2.0
Quectel EG91 Series Hardware Design V2.0
Hardware Design
Version: 2.0
Date: 2021-07-01
Status: Released
LTE Standard Module Series
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General Notes
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customers’ requirements. Quectel makes every effort to ensure the quality of the information it makes
available. Quectel does not make any warranty as to the information contained herein, and does not
accept any liability for any injury, loss or damage of any kind incurred by use of or reliance upon the
information. All information supplied herein is subject to change without prior notice.
Disclaimer
While Quectel has made efforts to ensure that the functions and features under development are free
from errors, it is possible that these functions and features could contain errors, inaccuracies and
omissions. Unless otherwise provided by valid agreement, Quectel makes no warranties of any kind,
implied or express, with respect to the use of features and functions under development. To the maximum
extent permitted by law, Quectel excludes all liability for any loss or damage suffered in connection with
the use of the functions and features under development, regardless of whether such loss or damage
may have been foreseeable.
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Copyright
The information contained here is proprietary technical information of Quectel. Transmitting, reproducing,
disseminating and editing this document as well as using the content without permission are forbidden.
Offenders will be held liable for payment of damages. All rights are reserved in the event of a patent grant
or registration of a utility model or design.
Copyright © Quectel Wireless Solutions Co., Ltd. 2021. All rights reserved.
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Safety Information
The following safety precautions must be observed during all phases of operation, such as usage, service
or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal
should notify users and operating personnel of the following safety information by incorporating these
guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers’ failure to
comply with these precautions.
Full attention must be paid to driving at all times in order to reduce the risk of an
accident. Using a mobile while driving (even with a handsfree kit) causes
distraction and can lead to an accident. Please comply with laws and regulations
restricting the use of wireless devices while driving.
Switch off the cellular terminal or mobile before boarding an aircraft. The operation
of wireless appliances in an aircraft is forbidden to prevent interference with
communication systems. If there is an Airplane Mode, it should be enabled prior to
boarding an aircraft. Please consult the airline staff for more restrictions on the use
of wireless devices on an aircraft.
Cellular terminals or mobiles operating over radio signal and cellular network
cannot be guaranteed to connect in certain conditions, such as when the mobile bill
is unpaid or the (U)SIM card is invalid. When emergency help is needed in such
conditions, use emergency call if the device supports it. In order to make or receive
a call, the cellular terminal or mobile must be switched on in a service area with
adequate cellular signal strength. In an emergency, the device with emergency call
function cannot be used as the only contact method considering network
connection cannot be guaranteed under all circumstances.
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Revision History
Barret XIONG/
1.0 2017-03-22 Initial
Rex WANG
1. Added band B28A.
2. Updated the description of UMTS and GSM
features in Table 2.
3. Updated the functional diagram in Figure 1.
4. Updated module operating frequencies in
Table 21.
5. Updated current consumption in Table 26.
6. Updated RF output power in Table 27.
Barret XIONG/
1.1 2018-01-23 7. Updated the conducted RF receiving
Rex WANG
sensitivity in Table 28.
8. Updated the GPRS multi-slot classes in
Table 33.
9. Added thermal consideration in Chapter 5.8
10. Added a GND pad in each of the four corners
of the module’s footprint in Chapter 6.2.
11. Updated storage information in Chapter 7.1.
12. Added packaging information in Chapter 7.3.
1. Added the description of EG91-NA.
2. Updated the functional diagram in Figure 1.
3. Updated pin assignment in Figure 2.
4. Updated GNSS function in Table 1.
Barret XIONG/ 5. Updated GNSS Features in Table 2.
1.2 2018-03-14
Rex WANG 6. Updated reference circuit of USB interface
in Figure 21.
7. Added description of GNSS receiver in
Chapter 4.
8. Updated pin definition of RF antenna in
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Table 21.
9. Updated module operating frequencies in
Table 22.
10. Added description of GNSS antenna
interface in Chapter 5.2.
11. Updated antenna requirements in Table 25.
12. Updated RF output power in Table 32.
1. Added new variants EG91-NS, EG91-V,
EG91-EC and related contents.
2. Opened pin 24 as ADC0 and added related
contents.
3. Updated functional diagram (Figure 1)
4. Updated pin assignment (Figure 2)
5. Updated GNSS features (Table 2)
6. Added USB_BOOT interface information
Barret XIONG/ (Chapter 3.18)
1.3 2019-02-03
Rex WANG 7. Updated storage information (Chapter 8.1)
8. Updated module operating frequencies
(Table 23)
9. Updated antenna requirements (Table 26)
10. Added current consumption of EG91-NS,
EG91-V and EG91-EC (Table 32, 33 and 34)
11. Added conducted RF receiving sensitivity of
EG91-NS, EG91-V and EG91-EC (Table 40,
41 and 42)
1. Modified module name EG91-EC to
EG91-EX, and EG91-V to EG91-VX
Barret XIONG/ 2. Added newly supported 9.x of Android USB
1.4 2019-03-29
Rex WANG serial driver (Table 2)
3. Modified the reflow temperature range as .
238ºC to 245ºC (Chapter 8.2)
1. Updated comment of RF antenna (Table 4)
2. Updated EG91-EX current consumption
Barret XIONG/
1.5 2019-05-24 (Table 36)
Rex WANG
3. Updated EG91-EX conducted RF receiving
sensitivity (Table 44)
1. Updated supported protocols (Table 2).
2. Updated timing of turning on module (Figure
12).
Barret XIONG/ 3. DFOTA is developed.
1.6 2019-07-05
Rex WANG 4. Updated description of USB_BOOT
interface and timing sequence for entering
emergency download mode (Chapter 3.18
and Figure 29).
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Contents
1 Introduction ........................................................................................................................................ 14
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5 Antenna Interfaces............................................................................................................................. 58
5.1. Main/Rx-diversity Antenna Interfaces...................................................................................... 58
5.1.1. Pin Definition .................................................................................................................. 58
5.1.2. Operating Frequency ..................................................................................................... 59
5.1.3. Reference Design of RF Antenna Interface ................................................................... 60
5.2. GNSS Antenna Interface ......................................................................................................... 61
5.3. Reference Design of RF Layout .............................................................................................. 62
5.4. Antenna Installation ................................................................................................................. 64
5.4.1. Antenna Requirement .................................................................................................... 64
5.4.2. Recommended RF Connector for Antenna Installation ................................................. 65
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Table Index
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Figure Index
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1 Introduction
This document defines the EG91 series module and describes its air interface and hardware interface
which are connected with your applications.
This document can help you quickly understand module interface specifications, electrical and
mechanical details, as well as other related information of EG91 series module. With application note and
user guide, you can use EG91 series module to design and set up mobile applications easily.
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2 Product Concept
EG91 series module is an embedded 4G wireless communication module with receive diversity. It
supports LTE-FDD/WCDMA/GSM wireless communication, and provides data connectivity on LTE-FDD,
DC-HSDPA, HSPA+, HSDPA, HSUPA, WCDMA, EDGE and GPRS networks. It can also provide voice
functionality 1 to meet your specific application demands. The following table shows the frequency bands
of EG91 series module.
1 EG91 series module contains Data + Voice version and Data-only version. Data + Voice version supports voice and
data functions, while Data-only version only supports data function.
2 GNSS function is optional.
3 EG91-AUX does not support Rx-diversity.
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With a compact profile of 29.0 mm × 25.0 mm × 2.3 mm, EG91 series module can meet almost all
requirements for M2M applications such as automotive, smart metering, tracking system, security, router,
wireless POS, mobile computing device, PDA phone, tablet PC, etc.
EG91 series module is an SMD type module which can be embedded into applications through its 106
LGA pins.
EG91 series module is integrated with internet service protocols like TCP, UDP and PPP. Extended AT
commands have been developed for you to use these internet service protocols easily.
The following table describes the detailed features of EG91 series module.
Feature Details
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GPRS:
⚫ Support GPRS multi-slot class 33 (33 by default)
⚫ Coding scheme: CS-1, CS-2, CS-3 and CS-4
⚫ Max. 107 kbps (DL), Max. 85.6 kbps (UL)
EDGE:
⚫ Support EDGE multi-slot class 33 (33 by default)
⚫ Support GMSK and 8-PSK for different MCS (Modulation and Coding
Scheme)
⚫ Downlink coding schemes: MCS 1-9
⚫ Uplink coding schemes: MCS 1-9
⚫ Max. 296 kbps (DL)/Max. 236.8 kbps (UL)
⚫ Support TCP/UDP/PPP/FTP/FTPS/HTTP/HTTPS/NTP/PING/QMI/
Internet Protocol Features NITZ/MMS/SMTP/SSL/MQTT/FILE/CMUX/SMTPS protocols
⚫ Support PAP and CHAP protocols for PPP connections
⚫ Text and PDU modes
⚫ Point-to-point MO and MT
SMS
⚫ SMS cell broadcast
⚫ SMS storage: ME by default
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RoHS ⚫ All hardware components are fully compliant with EU RoHS directive
transmission, etc. There is no unrecoverable malfunction. There are also no effects on radio spectrum and no harm to radio
network. Only one or more parameters like Pout might reduce in their value and exceed the specified tolerances. When the
temperature returns to normal operating temperature levels, the module will meet 3GPP specifications again.
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The following figure shows a block diagram of EG91 series module and illustrates the major functional
parts.
⚫ Power management
⚫ Baseband
⚫ DDR + NAND flash
⚫ Radio frequency
⚫ Peripheral interfaces
Duplexer LNA
SAW
VBAT_RF
PA SAW
PRx DRx
GPS
Tx
NAND
Transceiver DDR2
SDRAM
IQ Control
VBAT_BB
PMIC
Control
PWRKEY
RESET_N
Baseband
STATUS
NETLIGHT 19.2M
XO
8
Figure 1: Functional Diagram
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Quectel provides a complete set of evaluation tools to facilitate the use and testing of EG91 series module.
The evaluation tool kit includes the evaluation board (UMTS<E EVB), a USB to RS-232 converter
cable, an earphone, antennas and other peripherals. For more details, see document [1].
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3 Application Interfaces
EG91 series module is equipped with 106 LGA pins that can be connected to your cellular application
platforms. Sub-interfaces included in these pads are described in detail in the following chapters:
⚫ Power supply
⚫ (U)SIM interfaces
⚫ USB interface
⚫ UART interfaces
⚫ PCM and I2C interfaces
⚫ SPI interface
⚫ Network status indication
⚫ ADC interface
⚫ USB_BOOT interface
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The following figure shows the pin assignment of EG91 series module.
(EG91-EX/-NA/-NAL-NAX/-NAXD/-VX)
RESERVED (EG91-E)/ANT_DIV
ANT_MAIN
VBAT_RF
VBAT_RF
GND
GND
GND
GND
GND
GND
GND
NC
NC
103 106
55
53
50
62
61
60
59
58
54
52
51
56
57
ANT_DIV (EG91-E)/ANT_GNSS
(EG91-AUX/-EX/-NA/-NAL/-NAX/
NC 1 49 -NAXD/-VX)
NC 2 48 GND
82 81 80 79
GND 3 47 USIM_GND
PCM_CLK 4 102 101 100 99 46 USIM1_CLK
PCM_SYNC 5 45 USIM1_DATA
63 83 USIM2_PRESENCE 98 78
PCM_DIN 6 44 USIM1_RST
PCM_DOUT 7 43 USIM1_VDD
64 84 USIM2_CLK 97 77
USB_VBUS 8 42 USIM1_PRESENCE
NC 11 39 RI
67 87 USIM2_VDD 94 74
NC 12 38 DCD
NC 13 68 88 93 73 37 RTS
NC 14 36 CTS
89 90 91 92
PWRKEY 15 35 TXD
NC 16 34 RXD
69 70 71 72
RESET_N 17 33 VBAT_BB
W_DISABLE# 18 32 VBAT_BB
19
20
21
25
26
29
30
22
23
24
27
28
31
104 105
RESERVED
DBG_TXD
SPI_CLK
SPI_MISO
NETLIGHT
DBG_RXD
DTR
AP_READY
ST ATUS
SPI_MOSI
ADC0
GND
VDD_EXT
POWER USB UART (U)SIM PCM SPI ANT GND NC RESERVED OTHERS
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NOTE
1. PWRKEY output voltage is 0.8 V because of the diode drop in the baseband chipset.
2. Keep all RESERVED pins and unused pins unconnected.
3. GND pins should be connected to ground in the design.
4. Pin 49 is defined as ANT_GNSS on EG91-AUX/-EX/-NA/-NAL/-NAX/-NAXD/-VX, while it is defined
as ANT_DIV on EG91-E.
5. Pin 56 is RESERVED on EG91-E, while it is defined as ANT_DIV on EG91-EX/-NA/-NAL/-NAX/
-NAXD/-VX. Rx-diversity antenna is not supported on EG91-AUX.
The following tables show the pin definition and description of EG91 series module.
Type Description
AI Analog Input
AO Analog Output
DI Digital Input
DO Digital Output
OD Open Drain
PI Power Input
PO Power Output
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Power Supply
Pin DC
Pin Name I/O Description Comment
No. Characteristics
Power supply for the Vmax = 4.3 V It must be provided with
VBAT_BB 32, 33 PI module’s baseband Vmin = 3.3 V sufficient current up to
part Vnom = 3.8 V 0.8 A.
It must be provided with
Vmax = 4.3 V
Power supply for the sufficient current up to
VBAT_RF 52, 53 PI Vmin = 3.3 V
module’s RF part 1.8 A in a burst
Vnom = 3.8 V
transmission.
Power supply for
Provide 1.8 V for Vnom = 1.8 V external GPIO’s pull up
VDD_EXT 29 PO
external circuit IOmax = 50 mA circuits.
If unused, keep it open.
GND 3, 31, 48, 50, 54, 55, 58, 59, 61, 62, 67–74, 79–82, 89–91, 100–106
Power-on/off
Pin DC
Pin Name I/O Description Comment
No. Characteristics
The output voltage is
Turn on/off the 0.8 V because of the
PWRKEY 15 DI VIH = 0.8 V
module diode drop in the
baseband chipset.
Require pull-up resistor
VIHmax = 2.1 V
to 1.8 V internally.
RESET_N 17 DI Reset the module VIHmin = 1.3 V
Active low.
VILmax = 0.5 V
If unused, keep it open.
Status Indication
Pin DC
Pin Name I/O Description Comment
No. Characteristics
Indicate the
STATUS 20 DO module’s operation
status VOHmin = 1.35 V 1.8 V power domain.
Indicate the VOLmax = 0.45 V If unused, keep it open.
NETLIGHT 21 DO module’s network
activity status
USB Interface
Pin DC
Pin Name I/O Description Comment
No. Characteristics
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Vmax = 5.25 V
USB connection Typical value: 5.0 V
USB_VBUS 8 AI Vmin = 3.0 V
detec If unused, keep it open.
Vnom = 5.0 V
USB differential
USB_DP 9 AIO USB 2.0 compliant
data (+)
Require differential
USB differential
USB_DM 10 AIO impedance of 90 Ω.
data (-)
(U)SIM Interfaces
Pin DC
Pin Name I/O Description Comment
No. Characteristics
Specified ground for Connect to ground of
USIM_GND 47
(U)SIM card (U)SIM card connector.
IOmax = 50 mA
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IOmax = 50 mA
For 1.8 V (U)SIM:
VILmax = 0.6 V
VIHmin = 1.2 V
VOLmax = 0.45 V
VOHmin = 1.35 V
USIM2_DATA 86 DIO (U)SIM2 card data
For 3.0 V (U)SIM:
VILmax = 1.0 V
VIHmin = 1.95 V
VOLmax = 0.45 V
VOHmin = 2.55 V
For 1.8 V (U)SIM:
VOLmax = 0.45 V
VOHmin = 1.35 V
USIM2_CLK 84 DO (U)SIM2 card clock
For 3.0 V (U)SIM:
VOLmax = 0.45 V
VOHmin = 2.55 V
For 1.8 V (U)SIM:
VOLmax = 0.45 V
VOHmin = 1.35 V
USIM2_RST 85 DO (U)SIM2 card reset
For 3.0 V (U)SIM:
VOLmax = 0.45 V
VOHmin = 2.55 V
VILmin = -0.3 V
USIM2_ (U)SIM2 card VILmax = 0.6 V 1.8 V power domain.
83 DI
PRESENCE insertion detection VIHmin = 1.2 V If unused, keep it open.
VIHmax = 2.0 V
Pin DC
Pin Name I/O Description Comment
No. Characteristics
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Pin DC
Pin Name I/O Description Comment
No. Characteristics
Debug UART VOLmax = 0.45 V
DBG_TXD 23 DO
transmit VOHmin = 1.35 V
VILmin = -0.3 V 1.8 V power domain.
Debug UART VILmax = 0.6 V If unused, keep it open.
DBG_RXD 22 DI
receive VIHmin = 1.2 V
VIHmax = 2.0 V
PCM Interface
Pin DC
Pin Name I/O Description Comment
No. Characteristics
VILmin = -0.3 V
VILmax = 0.6 V
PCM_DIN 6 DI PCM data input
VIHmin = 1.2 V 1.8 V power domain.
VIHmax = 2.0 V If unused, keep it open.
VOLmax = 0.45 V
PCM_DOUT 7 DO PCM data output
VOHmin = 1.35 V
PCM data frame VOLmax = 0.45 V 1.8 V power domain. In
PCM_SYNC 5 DIO
sync VOHmin = 1.35 V master mode, it is an
VILmin = -0.3 V output signal. In slave
VILmax = 0.6 V mode, it is an input
PCM_CLK 4 DIO PCM data clock
VIHmin = 1.2 V signal.
VIHmax = 2.0 V If unused, keep it open.
I2C Interface
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Pin DC
Pin Name I/O Description Comment
No. Characteristics
I2C serial clock (for
I2C_SCL 40 OD An external pull-up to
external codec)
1.8 V is required.
I2C serial data
I2C_SDA 41 OD If unused, keep it open.
(for external codec)
ADC Interface
Pin DC
Pin Name I/O Description Comment
No. Characteristics
General-purpose Voltage range:
ADC0 24 AI If unused, keep it open.
ADC interface 0.3 V to VBAT_BB
SPI Interface
Pin DC
Pin Name I/O Description Comment
No. Characteristics
RF Interfaces
Pin DC
Pin Name I/O Description Comment
No. Characteristics
9
GNSS antenna 50 Ω impedance.
ANT_GNSS 49 AI
interface If unused, keep it open.
10
Diversity antenna 50 Ω impedance.
ANT_DIV 56 AI
interface If unused, keep it open.
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Main antenna
ANT_MAIN 60 AIO 50 Ω impedance.
Interface
Other Pins
Pin DC
Pin Name I/O Description Comment
No. Characteristics
1.8 V power domain.
VILmin = -0.3 V Pull-up by default.
Airplane mode VILmax = 0.6 V At low voltage level,
W_DISABLE# 18 DI
control VIHmin = 1.2 V module can enter
VIHmax = 2.0 V airplane mode.
If unused, keep it open.
VILmin = -0.3 V
Application VILmax = 0.6 V 1.8 V power domain.
AP_READY 19 DI
processor ready VIHmin = 1.2 V If unused, keep it open.
VIHmax = 2.0 V
VILmin = -0.3 V
Force the module to 1.8 V power domain.
VILmax = 0.6 V
USB_BOOT 75 DI enter emergency It is recommended to
VIHmin = 1.2 V
download mode reserve the test points.
VIHmax = 2.0 V
Pin DC
Pin Name I/O Description Comment
No. Characteristics
Keep these pins
NC 1, 2, 11–14, 16, 51, 57, 63–66, 76–78, 88, 92–99
unconnected.
Keep these pins
unconnected.
RESERVED 25, 56
Pin 56 is only reserved
on EG91-E.
NOTE
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The table below briefly outlines the operating modes to be mentioned in the following chapters.
Mode Details
EG91 series module is able to reduce its current consumption to a minimum value during the sleep mode.
The following sub-chapters describe the power saving procedures of EG91 series module.
If the host communicates with the module via UART interface, the following preconditions can let the
module enter sleep mode.
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The following figure shows the connection between the module and the host.
Module Host
RXD TXD
TXD RXD
RI EINT
DTR GPIO
AP_READY GPIO
GND GND
Driving the host DTR to low level will wake up the module.
⚫ When EG91 series module has a URC to report, RI signal will wake up the host. See Chapter 3.17
for details about RI behavior.
⚫ AP_READY will detect the sleep state of host (can be configured to high level or low level detection).
See AT+QCFG="apready" for details.
If the host supports USB suspend/resume and remote wakeup functions, the following three preconditions
must be met to let the module enter sleep mode.
The following figure shows the connection between the module and the host.
Module Host
USB_VBUS VDD
USB_DP USB_DP
USB_DM USB_DM
AP_READY GPIO
GND GND
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⚫ Sending data to EG91 series module through USB will wake up the module.
⚫ When EG91 series module has a URC to report, the module will send remote wakeup signals via
USB bus to wake up the host.
If the host supports USB suspend/resume, but does not support remote wakeup function, the RI signal is
needed to wake up the host.
There are three preconditions to let the module enter sleep mode.
The following figure shows the connection between the module and the host.
Module Host
USB_VBUS VDD
USB_DP USB_DP
USB_DM USB_DM
AP_READY GPIO
RI EINT
GND GND
⚫ Sending data to EG91 series module through USB will wake up the module.
⚫ When module has a URC to report, RI signal will wake up the host.
If the host does not support USB suspend function, USB_VBUS should be disconnected with an external
control circuit to let the module enter sleep mode.
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The following figure shows the connection between the module and the host.
Module Host
GPIO
Power
USB_VBUS Switch VDD
USB_DP USB_DP
USB_DM USB_DM
RI EINT
AP_READY GPIO
GND GND
Switching on the power switch to supply power to USB_VBUS will wake up the module.
NOTE
1. Pay attention to the level match shown in dotted line between the module and the host. Refer to
document [2] for more details about EG91 series module power management application.
2. For details of AT+QSCLK, see document [3].
3. For details of AT+QCFG, see document [5] .
When the module enters airplane mode, the RF function will be disabled, and all AT commands related to
it will be inaccessible. This mode can be set via the following ways.
Hardware:
The W_DISABLE# pin is pulled up by default. Driving it to low level will let the module enter airplane
mode.
Software:
AT+CFUN=<fun> provides the choice of the functionality level through setting <fun> as 0, 1 or 4.
⚫ AT+CFUN=0: Minimum functionality mode. Both (U)SIM and RF functions are disabled.
⚫ AT+CFUN=1: Full functionality mode (by default).
⚫ AT+CFUN=4: Airplane mode. RF function is disabled.
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NOTE
1. Airplane mode control via W_DISABLE# is disabled in firmware by default. It can be enabled by
AT+QCFG="airplanecontrol".
2. The execution of AT+CFUN will not affect GNSS function.
EG91 series module provides four VBAT pins for connection with an external power supply. There are two
separate voltage domains for VBAT.
The following table shows the details of VBAT pins and ground pins.
The power supply range of the module is from 3.3 V to 4.3 V. Please make sure that the input voltage will
never drop below 3.3 V. The following figure shows the voltage drop during burst transmission in 2G
network. The voltage drop will be less in 3G and 4G networks.
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Burst Burst
Transmission Transmission
VBAT Ripple
Drop
To decrease voltage drop, a bypass capacitor of about 100 µF with low ESR (ESR = 0.7 Ω) should be
used, and a multi-layer ceramic chip (MLCC) capacitor array should also be reserved due to its ultra-low
ESR. It is recommended to use three ceramic capacitors (100 nF, 33 pF, 10 pF) for composing the MLCC
array, and place these capacitors close to VBAT_BB/VBAT_RF pins. The main power supply from an
external application has to be a single voltage source and can be expanded to two sub paths with star
structure. The width of VBAT_BB trace should be no less than 1 mm, and the width of VBAT_RF trace
should be no less than 2 mm. In principle, the longer the VBAT trace is, the wider it will be.
In addition, in order to avoid the damage caused by electric surge and ESD, it is suggested that a TVS
diode with low reverse stand-off voltage VRWM (4.5 V), low clamping voltage VC and high reverse peak
pulse current IPP should be used. The following figure shows the star structure of the power supply.
VBAT
VBAT_RF
VBAT_BB
+ +
D1 C1 C2 C3 C4 C5 C6 C7 C8
Module
EG91_Series_Hardware_Design 35 / 104
LTE Standard Module Series
Power design for the module is very important, as the performance of the module largely depends on the
power source. The power supply should be able to provide sufficient current up to 2 A at least. If the
voltage drop between the input and output is not too high, it is suggested that an LDO should be used to
supply power for the module. If there is a big voltage difference between the input source and the desired
output (VBAT), a buck converter is preferred to be used as the power supply.
The following figure shows a reference design for +5 V input power source. The typical output of the
power supply is about 3.8 V and the maximum load current is 3 A.
MIC29302WU
DC_IN VBAT
2 4
IN OUT
GND
ADJ
EN
100K
1%
1
51K
5
4.7K 470R
470 μF 100 nF
470 μF 100 nF
47K
VBAT_EN 47K 1%
NOTE
To avoid damaging internal flash, do not switch off the power supply when the module works normally.
Only after the module is shut down by PWRKEY or AT command, then the power supply can be cut off.
AT+CBC can be used to monitor the VBAT_BB voltage value. For more details, refer to document [3].
EG91_Series_Hardware_Design 36 / 104
LTE Standard Module Series
When EG91 series module is in power down mode, it can be turned on to normal mode by driving the
PWRKEY pin to a low level for at least 500 ms. It is recommended to use an open drain/collector driver to
control the PWRKEY. After STATUS pin outputting a high level, PWRKEY pin can be released. A simple
reference circuit is illustrated in the following figure.
PWRKEY
≥ 500 ms
4.7K
10 nF
Turn-on pulse
47K
Another way to control the PWRKEY is using a button directly. When pressing the key, electrostatic strike
may generate from the finger. Therefore, a TVS component is indispensable to be placed nearby the
button for ESD protection. A reference circuit is shown in the following figure.
S1
PWRKEY
TVS
Close to S1
EG91_Series_Hardware_Design 37 / 104
LTE Standard Module Series
NOTE 1
VBAT ≥ 500 ms
VIH = 0. 8 V
RESET_N
≥ 10 s
STATUS
(DO)
≥ 12 s
≥ 13 s
NOTE
1. Make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is no less
than 30 ms.
2. PWRKEY can be pulled down directly to GND with a recommended 10 kΩ resistor if the module
needs to be powered on automatically and shutdown is not needed.
3. BOOT_CONFIG pins (SPI_CLK, USB_BOOT, PCM_CLK, PCM_SYNC) cannot be pulled up
before startup.
Either of the following methods can be used to turn off the module normally:
EG91_Series_Hardware_Design 38 / 104
LTE Standard Module Series
Driving the PWRKEY pin to a low level voltage for at least 650 ms, the module will execute power-off
procedure after the PWRKEY is released. The power-down scenario is illustrated in the following figure.
VBAT
≥ 650 ms ≥ 30 s
PWRKEY
STATUS
It is also a safe way to use AT+QPOWD to turn off the module, which is similar to turning off the module
via PWRKEY pin.
NOTE
1. To avoid damaging internal flash, do not switch off the power supply when the module works
normally. Only after the module is shut down by PWRKEY or AT command, the power supply can be
cut off.
2. When turning off module with the AT command, keep PWRKEY at high level after the execution of
the command. Otherwise, the module will be turned on again after being shut down.
EG91_Series_Hardware_Design 39 / 104
LTE Standard Module Series
The RESET_N pin can be used to reset the module. The module can be reset by driving RESET_N to a
low level voltage for 150–460 ms.
The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button
can be used to control the RESET_N.
RESET_N
150–460 ms
4.7K
Reset pulse
47K
S2
RESET_N
TVS
Close to S2
EG91_Series_Hardware_Design 40 / 104
LTE Standard Module Series
VBA T
460 ms
150 ms
RESET_N VIH 1.3 V
VIL 0.5 V
Module
Running Resetting Restart
Status
NOTE
1. Use RESET_N only when turning off the module by AT+QPOWD and PWRKEY pin are failed.
2. Ensure that there is no large capacitance on PWRKEY and RESET_N pins.
EG91 series module provides two (U)SIM interfaces, and only one (U)SIM card can work at a time. The
(U)SIM1 and (U)SIM2 cards can be switched by AT+QDSIM. For more details, refer to document [3].
The (U)SIM interfaces circuitry meet ETSI and IMT-2000 requirements. Both 1.8 V and 3.0 V (U)SIM
cards are supported.
Connect to ground of
USIM_GND 47 Specified ground for (U)SIM card
(U)SIM card connector.
Either 1.8 V or 3.0 V is
USIM1_VDD 43 PO (U)SIM1 card power supply supported by the module
automatically.
EG91_Series_Hardware_Design 41 / 104
LTE Standard Module Series
EG91 series module supports (U)SIM card hot-plug via USIM_PRESENCE (USIM1_PRESENCE/USIM2
_PRESENCE) pin, and both high and low level detection are supported. The function is disabled by
default, and see AT+QSIMDET in document [3] for more details.
The following figure shows a reference design for (U)SIM interface with an 8-pin (U)SIM card connector.
VDD_EXT USIM_VDD
51K 15K
USIM_GND 100 nF (U)SIM Card Connector
USIM_VDD
VCC GND
USIM_RST 0R
RST VPP
Module USIM_CLK
CLK IO
USIM_PRESENCE 0R
USIM_DATA 0R
GND
33 pF 33 pF 33 pF
GND GND
Figure 17: Reference Circuit of (U)SIM Interface with an 8-pin (U)SIM Card Connector
EG91_Series_Hardware_Design 42 / 104
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If (U)SIM card detection function is not needed, keep USIM_PRESENCE unconnected. A reference circuit
of (U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following figure.
USIM_VDD
15K
USIM_GND 100 nF
(U)SIM Card Connector
USIM_VDD
VCC GND
USIM_RST 0R
RST VPP
Module USIM_CLK
CLK IO
0R
USIM_DATA 0R
33 pF 33 pF 33 pF
GND GND
Figure 18: Reference Circuit of (U)SIM Interface with a 6-pin (U)SIM Card Connector
To enhance the reliability and availability of the (U)SIM cards in your applications, please follow the
criteria below in the (U)SIM circuit design:
⚫ Keep placement of (U)SIM card connector to the module as close as possible. Keep the trace length
as less than 200 mm as possible.
⚫ Keep (U)SIM card signals away from RF and VBAT traces.
⚫ Make sure the bypass capacitor between USIM_VDD and USIM_GND less than 1 μF, and place it as
close to (U)SIM card connector as possible. If the ground is complete on your PCB, USIM_GND can
be connected to PCB ground directly.
⚫ To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and
shield them with surrounded ground.
⚫ To offer good ESD protection, it is recommended to add a TVS diode array whose parasitic
capacitance should not be more than 15 pF. The 0 Ω resistors should be added in series between the
module and the (U)SIM card to facilitate debugging. The 33 pF capacitors are used for filtering
interference of EGSM900. Please note that the (U)SIM peripheral circuit should be close to the
(U)SIM card connector.
⚫ The pull-up resistor on USIM_DATA trace can improve anti-jamming capability when long layout trace
and sensitive occasion are applied, and should be placed close to the (U)SIM card connector.
EG91_Series_Hardware_Design 43 / 104
LTE Standard Module Series
EG91 series module contains one integrated Universal Serial Bus (USB) interface which complies with
the USB 2.0 specification and supports high-speed (480 Mbps) and full-speed (12 Mbps) modes.
The USB interface acts as slave only, and is used for AT command communication, data transmission,
GNSS NMEA sentences output, software debugging, firmware upgrade and voice over USB.
GND 3 Ground
The USB interface is recommended to be reserved for firmware upgrade in your design. The following
figure shows a reference circuit of USB interface.
Test Points
Minimize these stubs
Module MCU
R3 NM_0R
VDD R4 NM_0R
L1 USB_DM
USB_DM
USB_DP USB_DP
EG91_Series_Hardware_Design 44 / 104
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A common mode choke L1 is recommended to be added in series between the module and your MCU to
suppress EMI spurious transmission. Meanwhile, the 0 Ω resistors (R3 and R4) should be added in series
between the module and the test points to facilitate debugging, and the resistors are not mounted by
default. To ensure the integrity of USB data trace signal, L1 & R3 & R4 components must be placed close
to the module, and also these resistors should be placed close to each other. The extra stubs of trace
must be as short as possible.
To meet USB 2.0 specification, the following principles should be complied with when design the USB
interface.
⚫ It is important to route the USB signal traces as differential pairs with ground surrounded. The
impedance of USB differential trace is 90 Ω.
⚫ Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is
important to route the USB differential traces in inner-layer of the PCB, and surround the traces with
ground on that layer and with ground planes above and below.
⚫ Junction capacitance of the ESD protection device might cause influences on USB data lines, so pay
attention to the selection of the device. Typically, the stray capacitance should be less than 2 pF.
⚫ Keep the ESD protection devices as close to the USB connector as possible.
The module provides two UART interfaces: the main UART interface and the debug UART interface. The
following shows their features.
⚫ The main UART interface supports 9600 bps, 19200 bps, 38400 bps, 57600 bps, 115200 bps,
230400 bps, 460800 bps and 921600 bps baud rates, and the default is 115200 bps. It supports RTS
and CTS hardware flow control, and is used for AT command communication and data transmission.
⚫ The debug UART interface supports 115200 bps baud rate. It is used for Linux console and log
output.
The following tables show the pin definition of the two UART interfaces.
RI 39 DO Ring indication
1.8 V power domain
DCD 38 DO Data carrier detect
If unused, keep it open.
CTS 36 DO Clear to send
EG91_Series_Hardware_Design 45 / 104
LTE Standard Module Series
TXD 35 DO Transmit
RXD 34 DI Receive
The module provides 1.8 V UART interfaces. A voltage-level translator should be used if your application
is equipped with a 3.3 V UART interface. A voltage-level translator TXS0108EPWR provided by Texas
Instruments is recommended. The following figure shows a reference design.
0.1 μF
OE GND
120K
RI A1 B1 RI_MCU
DCD A2 B2 DCD_MCU
CTS A3 Translator B3 CTS_MCU
RTS A4 B4 RTS_MCU
DTR A5 B5 DTR_MCU
TXD A6 B6 RXD_MCU
RXD A7 B7 TXD_MCU
51K 51K
A8 B8
Another example with transistor translation circuit is shown as below. For the design of circuits shown in
dotted lines, see that shown in solid lines, but please pay attention to the direction of connection.
EG91_Series_Hardware_Design 46 / 104
LTE Standard Module Series
4.7K
VDD_EXT VDD_EXT
1 nF
MCU/ARM Module
10K
TXD RXD
RXD TXD
1 nF
10K
VDD_EXT
VCC_MCU 4.7K
RTS RTS
CTS CTS
GPIO DTR
EINT RI
GPIO DCD
GND GND
NOTE
1. Transistor circuit solution is not suitable for applications with high baud rates exceeding 460 kbps.
2. Please note that the CTS and RTS pins of the hardware flow control for the UART port are directly
connected, and pay attention to the input and output directions.
EG91 series module provides one Pulse Code Modulation (PCM) digital interface for audio design, which
supports the following modes and one I2C interface:
⚫ Primary mode (short frame synchronization, works as both master and slave)
⚫ Auxiliary mode (long frame synchronization, works as master only)
In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge. The PCM_SYNC falling edge represents the MSB. In this mode, the PCM interface supports
256 kHz, 512 kHz, 1024 kHz or 2048 kHz PCM_CLK at 8 kHz PCM_SYNC, and also supports 4096 kHz
PCM_CLK at 16 kHz PCM_SYNC.
In auxiliary mode, the data is also sampled on the falling edge of the PCM_CLK and transmitted on the
rising edge. The PCM_SYNC rising edge represents the MSB. In this mode, the PCM interface operates
with a 256 kHz, 512 kHz, 1024 kHz or 2048 kHz PCM_CLK and an 8 kHz, 50 % duty cycle PCM_SYNC.
EG91_Series_Hardware_Design 47 / 104
LTE Standard Module Series
EG91 series module supports 16-bit linear data format. The following figures show the primary mode’s
timing relationship with 8 kHz PCM_SYNC and 2048 kHz PCM_CLK, as well as the auxiliary mode’s
timing relationship with 8 kHz PCM_SYNC and 256 kHz PCM_CLK.
125 μs
P CM _S YNC
MS B LS B MS B
P CM _DOUT
MS B LS B MS B
P CM _DIN
125 μs
P CM _CLK 1 2 31 32
P CM _S YNC
MS B LS B
P CM _DOUT
MS B LS B
P CM _DIN
The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio
codec design.
EG91_Series_Hardware_Design 48 / 104
LTE Standard Module Series
PCM_SYNC 5 DIO PCM data frame sync 1.8 V power domain. In master
mode, it is an output signal. In slave
mode, it is an input signal.
PCM_CLK 4 DIO PCM data clock
If unused, keep it open.
I2C serial clock (for
I2C_SCL 40 OD
external codec) Require an external pull-up to 1.8 V
I2C serial data If unused, keep it open.
I2C_SDA 41 OD
(for external codec)
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. See document [3]
about AT+QDAI command for details.
The following figure shows a reference design of PCM interface with external codec IC.
MICBIAS
INP
PCM_CLK BCLK BIAS
INN
PCM_SYNC LRCK
PCM_DOUT DAC
PCM_DIN ADC
LOUTP
I2C_SCL SCL
I2C_SDA SDA LOUTN
4.7K
4.7K
Module Codec
1.8 V
NOTE
EG91_Series_Hardware_Design 49 / 104
LTE Standard Module Series
SPI interface of EG91 series module works as the master only. It provides a duplex, synchronous and
serial communication link with the peripheral devices. It is dedicated to one-to-one connection, without
chip selection. Its operation voltage is 1.8 V with clock rates up to 50 MHz.
The following figure shows a reference design of SPI interface with peripherals.
SPI_CLK SPI_CLK
SPI_MOSI SPI_MOSI
SPI_MISO SPI_MISO
Module Peripherals
NOTE
EG91 series provides 1.8 V SPI interface. A voltage-level translator should be used between the module
and the host if your application is equipped with a 3.3 V processor or device interface.
EG91_Series_Hardware_Design 50 / 104
LTE Standard Module Series
The module provides one network indication pin: NETLIGHT. The pin is used to drive a network status
indication LED.
The following tables describe the pin definition and logic level changes of NETLIGHT in different network
status.
NETLIGHT 21 DO Indicate the module’s network activity status 1.8 V power domain
VBAT
Module
2.2K
4.7K
NETLIGHT
47K
EG91_Series_Hardware_Design 51 / 104
LTE Standard Module Series
3.15. STATUS
The STATUS pin is set as the module’s operation status indicator. It will output high level when the
module is powered on. The following table describes the pin definition of STATUS.
VBAT
Module
2.2K
4.7K
STATUS
47K
The module provides one analog-to-digital converter (ADC) interface. AT+QADC=0 can be used to read
the voltage value on ADC0 pin. For more details about the command, see document [3].
To improve the accuracy of ADC voltage values, the traces of ADC should be surrounded by ground.
EG91_Series_Hardware_Design 52 / 104
LTE Standard Module Series
NOTE
1. It is prohibited to supply any voltage to ADC pins when ADC pins are not powered by VBAT.
2. It is recommended to use resistor divider circuit for ADC application.
3.17. Behaviors of RI
No matter on which port URC is presented, URC will trigger the behavior of RI pin.
NOTE
URC can be outputted from UART port, USB AT port and USB modem port through configuration via
AT+QURCCFG. The default port is USB AT port.
The default behaviors of the RI are shown as below, and can be changed by AT+QCFG="urc/ri/ring".
See document [3] for details.
State Response
EG91_Series_Hardware_Design 53 / 104
LTE Standard Module Series
EG91 series module provides a USB_BOOT pin. You can pull up USB_BOOT to VDD_EXT before
VDD_EXT is powered up, and the module will enter emergency download mode when it is powered on. In
this mode, the module supports firmware upgrade over USB interface.
The following figures show the reference circuit of USB_BOOT interface and timing sequence of entering
emergency download mode.
Module
VDD_EXT
Test point
4.7K
USB_BOOT
Close to test point
TVS
EG91_Series_Hardware_Design 54 / 104
LTE Standard Module Series
NOTE 1
VBAT ≥ 500 ms
VH = 0.8 V
RESET_N
NOTE
1. Make sure that VBAT is stable before pulling down PWRKEY pin. It is recommended that the time
between powering up VBAT and pulling down PWRKEY pin is no less than 30 ms.
2. When using MCU to control module to enter the emergency download mode, follow the above timing
sequence. It is not recommended to pull up USB_BOOT to 1.8 V before powering up VBAT. Short the
test points as shown in Figure 28 can manually force the module to enter download mode.
EG91_Series_Hardware_Design 55 / 104
LTE Standard Module Series
4 GNSS Receiver
EG91 series module includes a fully integrated global navigation satellite system solution that supports
GPS, GLONASS, BeiDou, Galileo and QZSS.
EG91 series module supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1 Hz data
update rate via USB interface by default.
By default, EG91 series module GNSS engine is switched off. It has to be switched on via AT command.
For more details about GNSS engine technology and configurations, see document [4].
Autonomous 34.6 s
Cold start
@ open sky
XTRA enabled 11.57 s
TTFF
(GNSS)
Autonomous 26.09 s
Warm start
@ open sky
XTRA enabled 3.7 s
EG91_Series_Hardware_Design 56 / 104
LTE Standard Module Series
Autonomous 1.8 s
Hot start
@ open sky
XTRA enabled 3.4 s
Accuracy Autonomous
CEP-50 < 2.5 m
(GNSS) @ open sky
NOTE
1. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep
positioning for at least 3 minutes continuously).
2. Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock
within 3 minutes after loss of lock.
3. Cold start sensitivity: the minimum GNSS signal power at which the module can fix position
successfully within 3 minutes after executing cold start command.
The following layout guidelines should be taken into account in your design.
⚫ Maximize the distance among GNSS antenna, main antenna and Rx-diversity antenna 11
⚫ Digital circuits such as (U)SIM card, USB interface, camera module and display connector should be
kept away from the antennas.
⚫ Use ground vias around the GNSS trace and sensitive analog signal traces to provide coplanar
isolation and protection.
⚫ Keep the characteristic impedance for ANT_GNSS trace as 50 Ω.
See Chapter 5 for GNSS antenna reference design and antenna installation information.
EG91_Series_Hardware_Design 57 / 104
LTE Standard Module Series
5 Antenna Interfaces
EG91 series module antenna interfaces include a main antenna interface and an Rx-diversity antenna
interface which is used to resist the fall of signals caused by high speed movement and multipath effect,
and a GNSS antenna interface which is only supported on EG91-AUX/-EX/-NA/-NAL/-NAX/-NAXD/-NAL/
-VX. The impedance of the antenna port is 50 Ω.
The pin definition of main antenna and Rx-diversity antenna interfaces is shown below.
ANT_DIV 50 Ω impedance.
49 AI Diversity antenna interface
(EG91-E) If unused, keep it open.
ANT_DIV
50 Ω impedance.
(EG91-EX/-NA/-NAL/ 56 AI Receive diversity antenna pad
If unused, keep it open.
-NAX/-NAXD/-VX)
NOTE
EG91_Series_Hardware_Design 58 / 104
LTE Standard Module Series
EG91_Series_Hardware_Design 59 / 104
LTE Standard Module Series
A reference design of ANT_MAIN and ANT_DIV antenna pads is shown as below. A π-type matching
circuit should be reserved for better RF performance. The capacitors are not mounted by default.
Main
Module antenna
R1 0R
ANT_MAIN
C1 C2
NM NM
Diversity
antenna
R2 0R
ANT_DIV
C3 C4
NM NM
NOTE
EG91_Series_Hardware_Design 60 / 104
LTE Standard Module Series
ANT_GNSS
49 AI GNSS antenna 50 Ω impedance
(EG91-AUX/-EX/-NA/-NAL/-NAX/-NAXD/-VX)
VDD
0.1 μF GNSS
10R
Antenna
Module
47 nH
0R 100 pF
ANT_GNSS
NM NM
EG91_Series_Hardware_Design 61 / 104
LTE Standard Module Series
NOTE
1. An external LDO can be selected to supply power according to the active antenna requirement.
2. If the module is designed with a passive antenna, then the VDD circuit is not needed.
For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The
impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant,
the height from the reference ground to the signal layer (H), and the spacing between RF traces and
grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic
impedance. The following are reference designs of microstrip or coplanar waveguide with different PCB
structures.
EG91_Series_Hardware_Design 62 / 104
LTE Standard Module Series
Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground)
Figure 35: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground)
To ensure RF performance and reliability, the following principles should be complied with in RF layout
design:
⚫ Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to
50 Ω.
⚫ The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully
connected to ground.
⚫ The distance between the RF pins and the RF connector should be as short as possible, and all the
right-angle traces should be changed to curved ones. The recommended trace angle is 135°.
⚫ There should be clearance under the signal pin of the antenna connector or solder joint.
⚫ The reference ground of RF traces should be complete. Meanwhile, adding some ground vias around
RF traces and the reference ground could help to improve RF performance. The distance between
the ground vias and RF traces should be no less than two times the width of RF signal traces (2 × W).
⚫ Keep RF traces away from interference sources, and avoid intersection and paralleling between
traces on adjacent layers.
EG91_Series_Hardware_Design 63 / 104
LTE Standard Module Series
The following table shows the requirements on main antenna, Rx-diversity antenna 12 and GNSS
antenna.
Type Requirements
NOTE
It is recommended to use a passive GNSS antenna when LTE B13 or B14 is supported, as the use of
active antenna may generate harmonics which will affect the GNSS performance.
EG91_Series_Hardware_Design 64 / 104
LTE Standard Module Series
U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT.
EG91_Series_Hardware_Design 65 / 104
LTE Standard Module Series
EG91_Series_Hardware_Design 66 / 104
LTE Standard Module Series
Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are
listed in the following table.
EG91_Series_Hardware_Design 67 / 104
LTE Standard Module Series
The operating and storage temperatures are listed in the following table.
14
Extended Temperature Range -40 +85 ºC
EG91_Series_Hardware_Design 68 / 104
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LTE Standard Module Series
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EG91_Series_Hardware_Design 79 / 104
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Tracking
Open sky @ Passive antenna 32 mA
(AT+CFUN=0)
EG91_Series_Hardware_Design 80 / 104
LTE Standard Module Series
The following table shows the RF output power of EG91 series module.
LTE-FDD B1/B2/B3/B4/B5/B7/
23 dBm ±2 dB < -39 dBm
B8/B12/B13/B20/B25/B26/B28/B66
NOTE
In GPRS 4 slots TX mode, the maximum output power is reduced by 3.0 dB. The design conforms to the
GSM specification as described in Chapter 13.16 of 3GPP TS 51.010-1.
EG91_Series_Hardware_Design 81 / 104
LTE Standard Module Series
The following tables show the conducted RF receiving sensitivity of EG91 series module.
LTE-FDD B28 (10 MHz) -98.7 dBm N/A N/A -94.8 dBm
LTE-FDD B66 (10 MHz) -97.7 dBm N/A N/A -95.8 dBm
EG91_Series_Hardware_Design 82 / 104
LTE Standard Module Series
LTE-FDD B1 (10 MHz) -97.5 dBm -98.3 dBm -101.4 dBm -96.3 dBm
LTE-FDD B3 (10 MHz) -98.3 dBm -98.5 dBm -101.5 dBm -93.3 dBm
LTE-FDD B7 (10 MHz) -96.3 dBm -98.4 dBm -101.3 dBm -94.3 dBm
LTE-FDD B8 (10 MHz) -97.1 dBm -99.1 dBm -101.2 dBm -93.3 dBm
LTE-FDD B20 (10 MHz) -97 dBm -99 dBm -101.3 dBm -93.3 dBm
LTE-FDD B28A (10 MHz) -98.3 dBm -99 dBm -101.4 dBm -94.8 dBm
LTE-FDD B1 (10 MHz) -98.7 dBm -98.8 dBm -102.4 dBm -96.3 dBm
LTE-FDD B3 (10 MHz) -98.3 dBm -99.5 dBm -102.5 dBm -93.3 dBm
LTE-FDD B7 (10 MHz) -97.5 dBm -98.4 dBm -100.3 dBm -94.3 dBm
LTE-FDD B8 (10 MHz) -98.7 dBm -99.6 dBm -102.2 dBm -93.3 dBm
EG91_Series_Hardware_Design 83 / 104
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LTE-FDD B20 (10 MHz) -97 dBm -97.5 dBm -102.2 dBm -93.3 dBm
LTE-FDD B28 (10 MHz) -98.2 dBm -99.5 dBm -102 dBm -94.8 dBm
LTE-FDD B2 (10 MHz) -98 dBm -99 dBm -102.2 dBm -94.3 dBm
LTE-FDD B4 (10 MHz) -97.8 dBm -99.5 dBm -102.2 dBm -96.3 dBm
LTE-FDD B5 (10 MHz) -99.6 dBm -100.3 dBm -103 dBm -94.3 dBm
LTE-FDD B12 (10 MHz) -99.5 dBm -100 dBm -102.5 dBm -93.3 dBm
LTE-FDD B13 (10 MHz) -99.2 dBm -100 dBm -102.5 dBm -93.3 dBm
LTE-FDD B2 (10 MHz) -98 dBm -99 dBm -102.2 dBm -94.3 dBm
LTE-FDD B4 (10 MHz) -97.8 dBm -99.5 dBm -102.2 dBm -96.3 dBm
LTE-FDD B5 (10 MHz) -99.6 dBm -100.3 dBm -103 dBm -94.3 dBm
LTE-FDD B12 (10 MHz) -99.5 dBm -100 dBm -102.5 dBm -93.3 dBm
LTE-FDD B13 (10 MHz) -99.2 dBm -100 dBm -102.5 dBm -93.3 dBm
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LTE-FDD B2 (10 MHz) -98 dBm -99 dBm -102.2 dBm -94.3 dBm
LTE-FDD B4 (10 MHz) -97.8 dBm -99.5 dBm -102.2 dBm -96.3 dBm
LTE-FDD B5 (10 MHz) -99.4 dBm -100 dBm -102.7 dBm -94.3 dBm
LTE-FDD B12 (10 MHz) -99.5 dBm -100 dBm -102.5 dBm -93.3 dBm
LTE-FDD B13 (10 MHz) -99.2 dBm -100 dBm -102.5 dBm -93.3 dBm
LTE-FDD B25 (10 MHz) -97.6 dBm -99 dBm -102.2 dBm -92.8 dBm
LTE-FDD B26 (10 MHz) -99.1 dBm -99.9 dBm -102.7 dBm -93.8 dBm
LTE-FDD B2 (10 MHz) -98 dBm -99 dBm -102.2 dBm -94.3 dBm
LTE-FDD B4 (10 MHz) -97.8 dBm -99.5 dBm -102.2 dBm -96.3 dBm
LTE-FDD B5 (10 MHz) -99.4 dBm -100 dBm -102.7 dBm -94.3 dBm
LTE-FDD B12 (10 MHz) -99.5 dBm -100 dBm -102.5 dBm -93.3 dBm
LTE-FDD B13 (10 MHz) -99.2 dBm -100 dBm -102.5 dBm -93.3 dBm
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LTE-FDD B25 (10 MHz) -97.6 dBm -99 dBm -102.2 dBm -92.8 dBm
LTE-FDD B26 (10 MHz) -99.1 dBm -99.9 dBm -102.7 dBm -93.8 dBm
LTE-FDD B4 (10 MHz) -98.2 dBm -99.2 dBm -102.2 dBm -96.3 dBm
LTE-FDD B13 (10 MHz) -99.2 dBm -100 dBm -102.5 dBm -93.3 dBm
The module is not protected against electrostatic discharge (ESD) in general. Consequently, it is subject
to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and
packaging procedures must be applied throughout the processing, handling and operation of any
application that incorporates the module.
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In order to achieve better performance of the module, it is recommended to comply with the following
principles for thermal consideration:
⚫ On your PCB design, please keep placement of the module away from heating sources, especially
high power components such as ARM processor, audio power amplifier, power supply, etc.
⚫ Do not place components on the opposite side of the PCB area where the module is mounted, in
order to facilitate adding of heatsink when necessary.
⚫ Do not apply solder mask on the opposite side of the PCB area where the module is mounted, so as
to ensure better heat dissipation performance.
⚫ The reference ground of the area where the module is mounted should be complete, and add ground
vias as many as possible for better heat dissipation.
⚫ Make sure the ground pads of the module and PCB are fully connected.
⚫ According to your application demands, the heatsink can be mounted on the top of the module, or the
opposite side of the PCB area where the module is mounted, or both of them.
⚫ The heatsink should be designed with as many fins as possible to increase heat dissipation area.
Meanwhile, a thermal pad with high thermal conductivity should be used between the heatsink and
module/PCB.
The following shows two kinds of heatsink designs for reference and you can choose one or both of them
according to their application structure.
Thermal Pad
Shielding Cover
Application Board Application Board
Figure 39: Referenced Heatsink Design (Heatsink at the Top of the Module)
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Thermal Pad
Thermal Pad
Module
Heatsink
Heatsink
Application Board
Shielding Cover Application Board
Figure 40: Referenced Heatsink Design (Heatsink at the Backside of Customers’ PCB)
NOTE
1. The module offers the best performance when the internal BB chip stays below 105 °C. When the
maximum temperature of the BB chip reaches or exceeds 105 °C, the module works normal but
provides reduced performance (such as RF output power, data rate, etc.). When the maximum BB
chip temperature reaches or exceeds 115 °C, the module will disconnect from the network, and it will
recover to network connected state after the maximum temperature falls below 115 °C. Therefore,
the thermal design should be maximally optimized to make sure the maximum BB chip temperature
always maintains below 105 °C. You can execute AT+QTEMP and get the maximum BB chip
temperature from the first returned value.
2. For more details about thermal design, see document [7].
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7 Mechanical Dimensions
This chapter describes the mechanical dimensions of the module. All dimensions are measured in
millimeter (mm), and the dimensional tolerances are ±0.2 mm unless otherwise specified.
25±0.15 2.30±0.2
Pin 1
29±0.15
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7.45 7.15
1.10 1.95 1.10
0.50
2.90
0.50
Pin 1
4.85
1.00
5.10
1.70 0.20
29±0.15
1.10 0.85
1.90
4.25 5.95
1.10
0.85
1.00
0.50
1.15 0.55
1.15
0.50
62x1.15 0.40
40x1.0
1.70 0.40
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7.45 7.15
1.10 1.95 1.10
0.50
2.90
0.50
Pin 1
4.85
1.00
5.10
1.70 0.20
29±0.15
1.10 0.85
1.90
4.25 5.95
1.10
0.85
1.00
0.50
1.15 0.55
1.15
0.50
62x1.15 0.40
40x1.0
1.70 0.40
NOTE
The package warpage level of the module conforms to JEITA ED-7306 standard.
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7.45 7.15
1.10 1.95 1.10
0.50
2.90
0.50
Pin 1
4.85
1.00
5.10
1.70 0.20
29±0.15
1.10 0.85
1.90
4.25 5.95
1.10
0.85
1.00
0.50
1.15 0.55
1.15
0.50
62x1.15 0.40
40x1.0
1.70 0.40
NOTE
For easy maintenance of this module, please keep about 3 mm between the module and other
components on the motherboard.
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NOTE
Images above are for illustration purpose only and may differ from the actual module. For authentic
appearance and label, please refer to the module received from Quectel.
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8.1. Storage
The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage
requirements are shown below.
1. Recommended Storage Condition: The temperature should be 23 ±5 °C and the relative humidity
should be 35–60 %.
2. The storage life (in vacuum-sealed packaging) is 12 months in Recommended Storage Condition.
3. The floor life of the module is 168 hours 15 in a plant where the temperature is 23 ±5 °C and relative
humidity is below 60 %. After the vacuum-sealed packaging is removed, the module must be
processed in reflow soldering or other high-temperature operations within 168 hours. Otherwise, the
module should be stored in an environment where the relative humidity is less than 10 % (e.g. a
drying cabinet).
4. The module should be pre-baked to avoid blistering, cracks and inner-layer separation in PCB under
the following circumstances:
⚫ The module is not stored in Recommended Storage Condition;
⚫ Violation of the third requirement above occurs;
⚫ Vacuum-sealed packaging is broken, or the packaging has been removed for over 24 hours;
⚫ Before module repairing.
15 This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. It is recommended to start
the solder reflow process within 24 hours after the package is removed if the temperature and moisture do not conform to,
or are not sure to conform to IPC/JEDEC J-STD-033. And do not remove the packages of tremendous modules if they are
not ready for soldering.
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NOTE
1. To avoid blistering, layer separation and other soldering issues, extended exposure of the module to
the air is forbidden.
2. Take out the module from the package and put it on high-temperature-resistant fixtures before baking.
All modules must be soldered to PCB within 24 hours after the baking, otherwise put them in the
drying oven. If shorter baking time is desired, see IPC/JEDEC J-STD-033 for the baking procedure.
3. Pay attention to ESD protection, such as wearing anti-static gloves, when touching the modules.
Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the
stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly
to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness
of stencil for the module is recommended to be 0.13–0.15 mm. For more details, see document [8].
The peak reflow temperature should be 235–246 ºC, with 246 ºC as the absolute maximum reflow
temperature. To avoid damage to the module caused by repeated heating, it is strongly recommended
that the module should be mounted only after reflow soldering for the other side of PCB has been
completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and related
parameters are shown below.
Temp. (°C)
Reflow Zone
Max slope: Cooling down slope:
2 to 3 °C/s C -1.5 to -3 °C/s
246
235
217
B D
200
Soak Zone
150 A
100
Max slope: 1 to 3 °C/s
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Factor Recommendation
Soak Zone
Reflow Zone
Reflow Cycle
NOTE
If a conformal coating is necessary for the module, do NOT use any coating material that may
chemically react with the PCB or shielding cover, and prevent the coating material from flowing into the
module.
8.3. Packaging
EG91 series module is packaged in a vacuum-sealed bag which is ESD protected. The bag should not be
opened until the devices are ready to be soldered onto the application.
The reel is 330 mm in diameter and each reel contains 250 modules. The following figures show the
packaging details, measured in mm.
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48.5
Cover tape
13
Direction of feed
100
44.5+0.20
-0.00
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1083
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9 Appendix References
Document Name
[1] Quectel_UMTS<E_EVB_User_Guide
[2] Quectel_EC2x&EG9x_Power_Management_Application_Note
[3] Quectel_EG9x_AT_Commands_Manual
[4] Quectel_EC2x&EG9x&EG2x-G&EM05_Series_GNSS_Application_Note
[5] Quectel_EC2x&EG2x&EG9x&EM05_Series_QCFG_AT_Commands_Manual
[6] Quectel_RF_Layout_Application_Note
[7] Quectel_LTE_Module_Thermal_Design_Guide
[8] Quectel_Module_Secondary_SMT_User_Guide
Abbreviation Description
CS Coding Scheme
DL Downlink
FR Full Rate
HR Half Rate
I/O Input/Output
ME Mobile Equipment
MO Mobile Originated
MT Mobile Terminated
PA Power Amplifier
RF Radio Frequency
Rx Receive
TX Transmitting Direction
UL Uplink