EXP.

NO:3a NAME:BVS PRIYANKA

DATE:7-04-2021 REG.NO:20BDS0237
SLOT:L45+46

Design a combinational circuit that generates 9’s

Complement of BCD

AIM: To design a combinational circuit that generates the 9’s

m
er as
complement of BCD code by using LTspice.

co
eH w
o.
TRUTH TABLE OF FULL ADDER:
rs e
ou urc
BCD 9’S COMPLEMENT
o

A B C D w x y z
aC s
vi y re

0 0 0 0 0 1 0 0 1
1 0 0 0 1 1 0 0 0
ed d

2 0 0 1 0 0 1 1 1
ar stu

3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 0 1
is
Th

5 0 1 0 1 0 1 0 0

6 0 1 1 0 0 0 1 1
sh

7 0 1 1 1 0 0 1 0

8 1 0 0 0 0 0 0 1

9 1 0 0 1 0 0 0 0

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 SIMPLIFICATION:

m
er as
co
eH w
o.
rs e
ou urc
o
aC s
vi y re
ed d
ar stu
is
Th
sh

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 LTSPICE STIMULATION :

m
er as
co
eH w
o.
rs e
ou urc
STIMULATION RESULT:
o
aC s
vi y re
ed d
ar stu
is
Th
sh

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 Comparing simulation with truth table:
In truth table
ABCD WXYZ
0001 1000
0111 0010
0100 0101

In simulation output :

ABCD WXYZ

m
er as
0001 1000

co
eH w
0111 0010

o.
0100 0101
rs e
ou urc
We can see that before and after stimulation the truth table is
o

same.Hence our results are accurate

aC s
vi y re

INFERENCE:
As the simulation output matches with the truth table, circuit
ed d

for 9’s complement of BCD digits is implemented successfully

ar stu

in LTspice.
is
Th
sh

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 EXP:3b
DATE:17-04-2021

8 X 1 MULTIPLEXER

AIM: To design a 8 × 1 multiplexer in LTSpice and verify its working

by validating from the truth table.
TRUTH TABLE:
DATA SELECT LINES OUTPUT

m
er as
S1 S2 S3 Z

co
eH w
1 1 1 D0

o.
1 1
rs e
0 D1
ou urc
1 0 1 D2
o

1 0 0 D3
aC s
vi y re

0 1 1 D4
0 1 0 D5
ed d

0 0 1 D6
ar stu

0 0 0 D7
is

2n number of input channels are handled by n-number of control lines.

Th

Therefore, for a 8 × 1 multiplexer, there will be 3 (log2n = log28 = 3 )data select

lines.
sh

THE BOOLEAN EXPRESSION OF Z:

Z=S1S2S3D0+ S1S2S’3D1+S1S’2S3D2+S1S’2 S’3 D3+ S1S’2S’3D4+S’1S2S’3D5+
S’1S’2S3D6+S’1S’2S’3D7

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 IMPLEMENTATION OF CIRCUIT :

m
er as
co
eH w
o.
rs e
ou urc
OUTPUT OF CIRCUIT:
o
aC s
vi y re
ed d
ar stu
is
Th
sh

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 COMPARITION OF STIMULATION WITH TRUTH TABLE:
As per the truth table, for input 000, output should be
D7. In this case, D7 is 0 and output is also 0. Therefore,
this is in accordance with the LT Spice output graph.
This is the same for all conditions. Hence, the
stimulation graph is correct.

INFERENCE:

m
The circuit for 8 × 1 multiplexer has been implemented in

er as
LTSPICE and the results of simulation have been verified with

co
eH w
the truth table.

o.
rs e
ou urc
o
aC s
vi y re
ed d
ar stu
is
Th
sh

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