High Speed, Dual,

4 A MOSFET Driver
Data Sheet ADP3654
FEATURES GENERAL DESCRIPTION
Industry-standard-compatible pinout The ADP3654 high current and dual high speed driver is capable
High current drive capability of driving two independent N-channel power MOSFETs. The
Precise UVLO comparator with hysteresis driver uses the industry-standard footprint but adds high speed
3.3 V-compatible inputs switching performance.
10 ns typical rise time and fall time at 2.2 nF load
The wide input voltage range allows the driver to be compatible
Matched propagation delays between channels
with both analog and digital PWM controllers.
Fast propagation delay
4.5 V to 18 V supply voltage Digital power controllers are powered from a low voltage
Parallelable dual outputs supply, and the driver is powered from a higher voltage supply.
Rated from −40°C to +125°C junction temperature The ADP3654 driver adds UVLO and hysteresis functions,
Thermally enhanced packages, 8-lead SOIC_N_EP and 8-lead allowing safe startup and shutdown of the higher voltage supply
MINI_SO_EP when used with low voltage digital controllers.

APPLICATIONS The driver is available in thermally enhanced SOIC_N_EP and

MINI_SO_EP packaging to maximize high frequency and
AC-to-dc switch mode power supplies current switching in a small printed circuit board (PCB) area.
DC-to-dc power supplies
Synchronous rectification
Motor drives

FUNCTIONAL BLOCK DIAGRAM

NC 1 8 NC
ADP3654 VDD

INA 2
7 OUTA

PGND 3
UVLO 6 VDD

INB 4
5 OUTB
09054-001

Figure 1.

Rev. A Document Feedback

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ADP3654 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Test Circuit .........................................................................................8
Applications ....................................................................................... 1 Theory of Operation .........................................................................9
General Description ......................................................................... 1 Input Drive Requirements (INA and INB) ................................9
Functional Block Diagram .............................................................. 1 Low-Side Drivers (OUTA, OUTB) .............................................9
Revision History ............................................................................... 2 Supply Capacitor Selection ..........................................................9
Specifications..................................................................................... 3 PCB Layout Considerations .........................................................9
Timing Diagrams.......................................................................... 3 Parallel Operation ...................................................................... 10
Absolute Maximum Ratings ............................................................ 4 Thermal Considerations............................................................ 10
ESD Caution .................................................................................. 4 Outline Dimensions ....................................................................... 12
Pin Configuration and Function Descriptions ............................. 5 Ordering Guide .......................................................................... 13
Typical Performance Characteristics ............................................. 6

REVISION HISTORY
8/15—Rev. 0 to Rev. A
Changes to Figure 5 .......................................................................... 6
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 13

8/10—Revision 0: Initial Version

Rev. A | Page 2 of 13
Data Sheet ADP3654

SPECIFICATIONS
VDD = 12 V, TJ = −40°C to +125°C, unless otherwise noted.1

Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SUPPLY
Supply Voltage Range VDD 4.5 18 V
Supply Current IDD No switching 1.2 3 mA
UVLO
Turn-On Threshold Voltage VUVLO_ON VDD rising, TJ = 25°C, see Figure 3 3.8 4.2 4.5 V
Turn-Off Threshold Voltage VUVLO_OFF VDD falling, TJ = 25°C, see Figure 3 3.5 3.9 4.3 V
Hysteresis 0.3 V
DIGITAL INPUTS (INA, INB)
Input Voltage High VIH See Figure 2 2.0 V
Input Voltage Low VIL See Figure 2 0.8 V
Input Current IIN 0 V < VIN < VDD −20 +20 µA
Internal Pull-Up/Pull-Down Current 6 µA
OUTPUTS (OUTA, OUTB)
Output Resistance, Unbiased VDD = PGND 80 kΩ
Peak Source Current See Figure 14 4 A
Peak Sink Current See Figure 14 −4 A
SWITCHING TIME
OUTA and OUTB Rise Time tRISE CLOAD = 2.2 nF, see Figure 2 10 25 ns
OUTA and OUTB Fall Time tFALL CLOAD = 2.2 nF, see Figure 2 10 25 ns
OUTA and OUTB Rising Propagation Delay tD1 CLOAD = 2.2 nF, see Figure 2 14 30 ns
OUTA and OUTB Falling Propagation Delay tD2 CLOAD = 2.2 nF, see Figure 2 22 35 ns
Delay Matching Between Channels 2 ns
1
All limits at temperature extremes guaranteed via correlation using standard statistical quality control (SQC) methods.

TIMING DIAGRAMS

INA, VIH VIL

INB

tD1 tRISE tD2 tFALL

90% 90%
OUTA,
OUTB
10% 10%
09054-002

Figure 2. Output Timing Diagram

VUVLO_ON

VUVLO_OFF

VDD
09054-003

UVLO MODE NORMAL OPERATION UVLO MODE

OUTPUTS DISABLED OUTPUTS DISABLED

Figure 3. UVLO Function

Rev. A | Page 3 of 13
ADP3654 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 2. Stresses at or above those listed under Absolute Maximum
Parameter Rating Ratings may cause permanent damage to the product. This is a
VDD −0.3 V to +20 V stress rating only; functional operation of the product at these
OUTA, OUTB or any other conditions above those indicated in the operational
DC −0.3 V to VDD + 0.3 V section of this specification is not implied. Operation beyond
<200 ns −2 V to VDD + 0.3 V the maximum operating conditions for extended periods may
INA, INB −0.3 V to VDD + 0.3 V affect product reliability.
ESD
Human Body Model (HBM) 3.5 kV
Field Induced Charged Device Model
ESD CAUTION
(FICDM)
SOIC_N_EP 1.5 kV
MINI_SO_EP 1.0 kV
θJA, JEDEC 4-Layer Board
SOIC_N_EP1 59°C/W
MINI_SO_EP1 43°C/W
Junction Temperature Range −40°C to +150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature
Soldering (10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 260°C
1
θJA is measured per JEDEC standards, JESD51-2, JESD51-5, and JESD51-7, as
appropriate with the exposed pad soldered to the PCB.

Rev. A | Page 4 of 13
Data Sheet ADP3654

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NC 1 8 NC
INA 2
ADP3654 7 OUTA
TOP VIEW
PGND 3 (Not to Scale) 6 VDD
INB 4 5 OUTB

NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD OF THE PACKAGE IS NOT DIRECTLY
CONNECTED TO ANY PIN OF THE PACKAGE, BUT IT IS
ELECTRICALLY AND THERMALLY CONNECTED TO THE DIE
SUBSTRATE, WHICH IS THE GROUND OF THE DEVICE. IT IS

09054-004
RECOMMENDED TO HAVE THE EXPOSED PAD AND THE
PGND PIN CONNECTED ON THE PCB.

Figure 4. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description
1 NC No Connect.
2 INA Input Pin for Channel A Gate Driver.
3 PGND Ground. This pin should be closely connected to the source of the power MOSFET.
4 INB Input Pin for Channel B Gate Driver.
5 OUTB Output Pin for Channel B Gate Driver.
6 VDD Power Supply Voltage. Bypass this pin to PGND with a ~1 µF to 5 µF ceramic capacitor.
7 OUTA Output Pin for Channel A Gate Driver.
8 NC No Connect.
9 EPAD Exposed Pad. The exposed pad of the package is not directly connected to any pin of the package, but it is
electrically and thermally connected to the die substrate, which is the ground of the device. It is recommended
to have the exposed pad and the PGND pin connected on the PCB.

Rev. A | Page 5 of 13
ADP3654 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

VDD = 12 V, TJ = 25°C, unless otherwise noted.
9 25

8
20

7
15

TIME (ns)
UVLO (V)

6 tFALL

10
tRISE
5

V UVLO_ON
5
4
V UVLO_OFF

3 0
09054-005

09054-008
–50 –30 –10 10 30 50 70 90 110 130 0 5 10 15 20
TEMPERATURE (°C) VDD (V)

Figure 5. UVLO vs. Temperature Figure 8. Rise and Fall Times vs. VDD

14 70

12 60
tFALL
10 50
tRISE
TIME (ns)
TIME (ns)

8 40

6 30

tD2
4 20
tD1
2 10

0 0
09054-006

09054-009
–50 –30 –10 10 30 50 70 90 110 130 0 5 10 15 20
TEMPERATURE (°C) VDD (V)

Figure 6. Rise and Fall Times vs. Temperature Figure 9. Propagation Delay vs. VDD

60
VDD = 12V

50

OUTA/OUTB
40
TIME (ns)

30
tD2
2
20
tD1
INA/INB
10

0 1 VDD = 12V
09054-007

09054-010

–50 –30 –10 10 30 50 70 90 110 130 TIME = 20ns/DIV

TEMPERATURE (°C)

Figure 7. Propagation Delay vs. Temperature Figure 10. Typical Rise Propagation Delay

Rev. A | Page 6 of 13
Data Sheet ADP3654

OUTA/OUTB OUTA/OUTB
2 2

INA/INB INA/INB
1 VDD = 12V 1 VDD = 12V

09054-011

09054-013
TIME = 20ns/DIV TIME = 20ns/DIV

Figure 11. Typical Fall Propagation Delay Figure 13. Typical Fall Time

OUTA/OUTB

INA/INB

1 VDD = 12V
09054-012

TIME = 20ns/DIV

Figure 12. Typical Rise Time

Rev. A | Page 7 of 13
ADP3654 Data Sheet

TEST CIRCUIT
1 NC NC 8
SCOPE
ADP3654 PROBE

INA OUTA
2 A 7

VDD

3 PGND VDD 6
4.7µF 100nF
CERAMIC CERAMIC CLOAD

INB OUTB
4 B 5

09054-014
Figure 14. Test Circuit

Rev. A | Page 8 of 13
Data Sheet ADP3654

THEORY OF OPERATION
The ADP3654 dual driver is optimized for driving two LOW-SIDE DRIVERS (OUTA, OUTB)
independent enhancement N-channel MOSFETs or insulated The ADP3654 dual drivers are designed to drive ground
gate bipolar transistors (IGBTs) in high switching frequency referenced N-channel MOSFETs. The bias is internally
applications. connected to the VDD supply and PGND.
These applications require high speed, fast rise and fall times, as When ADP3654 is disabled, both low-side gates are held low.
well as short propagation delays. The capacitive nature of the Internal impedance is present between the OUTA pin and GND
aforementioned gated devices requires high peak current and between the OUTB pin and GND; this feature ensures that
capability as well. the power MOSFET is normally off when bias voltage is not
1 NC NC 8 present.
ADP3654 VDS
When interfacing ADP3654 to external MOSFETs, the designer
2
INA
A
OUTA
7 should consider ways to make a robust design that minimizes
stresses on both the driver and the MOSFETs. These stresses
VDD include exceeding the short time duration voltage ratings on the
3 PGND VDD 6
OUTA and OUTB pins, as well as the external MOSFET.
VDS
Power MOSFETs are usually selected to have a low on resistance
4
INB
B
OUTB
5
to minimize conduction losses, which usually implies a large
input gate capacitance and gate charge.
SUPPLY CAPACITOR SELECTION
09054-015

For the supply input (VDD) of the ADP3654, a local bypass

Figure 15. Typical Application Circuit
capacitor is recommended to reduce the noise and to supply
INPUT DRIVE REQUIREMENTS (INA AND INB) some of the peak currents that are drawn.
The ADP3654 is designed to meet the requirements of modern An improper decoupling can dramatically increase the rise
digital power controllers; the signals are compatible with 3.3 V times because excessive resonance on the OUTA and OUTB
logic levels. At the same time, the input structure allows for pins can, in some extreme cases, damage the device, due to
input voltages as high as VDD. inductive overvoltage on the VDD, OUTA, or OUTB pin.
An internal pull-down resistor is present at the input, which The minimum capacitance required is determined by the size
guarantees that the power device is off in the event that the of the gate capacitances being driven, but as a general rule, a
input is left floating. 4.7 µF, low ESR capacitor should be used. Multilayer ceramic
chip (MLCC) capacitors provide the best combination of low
ESR and small size. Use a smaller ceramic capacitor (100 nF)
with a better high frequency characteristic in parallel to the
main capacitor to further reduce noise.
Keep the ceramic capacitor as close as possible to the ADP3654
device and minimize the length of the traces going from the
capacitor to the power pins of the device.
PCB LAYOUT CONSIDERATIONS
Use the following general guidelines when designing PCBs:
• Trace out the high current paths and use short, wide
(>40 mil) traces to make these connections.
• Minimize trace inductance between the OUTA and OUTB
outputs and MOSFET gates.
• Connect the PGND pin of the ADP3654 device as closely
as possible to the source of the MOSFETs.
• Place the VDD bypass capacitor as close as possible to the
VDD and PGND pins.
• Use vias to other layers, when possible, to maximize
thermal conduction away from the IC.

Rev. A | Page 9 of 13
ADP3654 Data Sheet
Figure 16 shows an example of the typical layout based on the THERMAL CONSIDERATIONS
preceding guidelines. When designing a power MOSFET gate drive, the maximum
power dissipation in the driver must be considered to avoid
exceeding maximum junction temperature.
Data on package thermal resistance is provided in Table 2 to
help the designer with this task.
There are several equally important aspects that must be
considered, such as the following:
• Gate charge of the power MOSFET being driven
• Bias voltage value used to power the driver
• Maximum switching frequency of operation
09054-016

• Value of external gate resistance

Figure 16. External Component Placement Example • Maximum ambient (and PCB) temperature
• Type of package
Note that the exposed pad of the package is not directly con-
nected to any pin of the package, but it is electrically and All of these factors influence and limit the maximum allowable
thermally connected to the die substrate, which is the ground power dissipated in the driver.
of the device. The gate of a power MOSFET has a nonlinear capacitance
PARALLEL OPERATION characteristic. For this reason, although the input capacitance
The two driver channels present in the ADP3654 device can be is usually reported in the MOSFET data sheet as CISS, it is not
combined to operate in parallel to increase drive capability and useful to calculate power losses.
minimize power dissipation in the driver. The total gate charge necessary to turn on a power MOSFET
The connection scheme is shown in Figure 17. In this configura- device is usually reported on the device data sheet under QG.
tion, INA and INB are connected together, and OUTA and This parameter varies from a few nanocoulombs (nC) to several
OUTB are connected together. hundred nC, and is specified at a specific VGS value (10 V
or 4.5 V).
Particular attention must be paid to the layout in this case to
optimize load sharing between the two drivers. The power necessary to charge and then discharge the gate of a
power MOSFET can be calculated as:
1 NC NC 8

ADP3654 PGATE = VGS × QG × fSW

INA OUTA where:
2 A 7
VGS is the bias voltage powering the driver (VDD).
VDD QG is the total gate charge.
3 PGND VDD 6 fSW is the maximum switching frequency.
VDS The power dissipated for each gate (PGATE) still needs to be
multiplied by the number of drivers (in this case, 1 or 2) being
INB OUTB
4 B 5
used in each package, and it represents the total power dissi-
pated in charging and discharging the gates of the power
MOSFETs.
09054-017

Not all of this power is dissipated in the gate driver because part
Figure 17. Parallel Operation of it is actually dissipated in the external gate resistor, RG. The
larger the external gate resistor is, the smaller the amount of
power that is dissipated in the gate driver.
In modern switching power applications, the value of the gate
resistor is kept at a minimum to increase switching speed and
minimize switching losses.
In all practical applications where the external resistor is in the
order of a few ohms, the contribution of the external resistor
can be neglected, and the extra loss is assumed in the driver,
providing a good guard band to the power loss calculations.

Rev. A | Page 10 of 13
Data Sheet ADP3654
In addition to the gate charge losses, there are also dc bias The SOIC_N_EP thermal resistance is 59°C/W.
losses, due to the bias current of the driver. This current is ΔTJ = 878.4 mW × 59°C/W = 51.8°C
present regardless of the switching.
TJ = TA + ΔTJ = 136.8°C ≤ TJMAX
PDC = VDD × IDD
This estimated junction temperature does not factor in the
The total estimated loss is the sum of PDC and PGATE. power dissipated in the external gate resistor and, therefore,
PLOSS = PDC + (n × PGATE) provides a certain guard band.
where n is the number of gates driven. If a lower junction temperature is required by the design,
When the total power loss is calculated, the temperature the MINI_SO_EP package can be used, which provides a
increase can be calculated as thermal resistance of 43°C/W, so that the maximum junction
temperature is
ΔTJ = PLOSS × θJA
ΔTJ = 878.4 mW × 43°C/W = 37.7°C
Design Example
TJ = TA + ΔTJ = 122.7°C ≤ TJMAX
For example, consider driving two IRFS4310Z MOSFETs with a
VDD of 12 V at a switching frequency of 300 kHz, using an Other options to reduce power dissipation in the driver include
ADP3654 in the SOIC_N_EP package. reducing the value of the VDD bias voltage, reducing switching fre-
quency, and choosing a power MOSFET with smaller gate charge.
The maximum PCB temperature considered for this design is 85°C.
From the MOSFET data sheet, the total gate charge is QG = 120 nC.
PGATE = 12 V × 120 nC × 300 kHz = 432 mW
PDC = 12 V × 1.2 mA = 14.4 mW
PLOSS = 14.4 mW + (2 × 432 mW) = 878.4 mW

Rev. A | Page 11 of 13
ADP3654 Data Sheet

OUTLINE DIMENSIONS
5.00
4.90 2.29
4.80 0.356

8 5 6.20
4.00 6.00
3.90 5.80 2.29
3.80 0.457
1 4

FOR PROPER CONNECTION OF

1.27 BSC BOTTOM VIEW THE EXPOSED PAD, REFER TO
3.81 REF THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
TOP VIEW SECTION OF THIS DATA SHEET.
1.75 1.65 0.50 45°
1.35 1.25 0.25
0.25
0.17
0.10 MAX
SEATING
PLANE 0.51 0.05 NOM 8°
1.04 REF
COPLANARITY 0° 1.27
0.31 0.10 0.40

06-02-2011-B
COMPLIANT TO JEDEC STANDARDS MS-012-A A

Figure 18. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body (RD-8-1)
Dimensions shown in millimeters

3.10 2.26
3.00 2.16
2.90 2.06

8 5
3.10 5.05 1.83
3.00 TOP 4.90 EXPOSED 1.73
VIEW 4.75
PAD
2.90 1 1.63
4
FOR PROPER CONNECTION OF
PIN 1 THE EXPOSED PAD, REFER TO
INDICATOR 0.525 BSC BOTTOM VIEW THE PIN CONFIGURATION AND
0.65 BSC FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.94 0.23
0.86 1.10 MAX 0.18
0.78 0.13
0.15 0.70
0.40 SEATING 8° 0.55
0.10 PLANE 0°
0.33 0.40
0.05
0.25
COPLANARITY
071008-A

0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA-T

Figure 19. 8-Lead Mini Small Outline Package with Exposed Pad [MINI_SO_EP]
(RH-8-1)
Dimensions shown in millimeters

Rev. A | Page 12 of 13
Data Sheet ADP3654
ORDERING GUIDE
UVLO Temperature Package Ordering
Model1 Option Range Package Description Option Quantity Branding
ADP3654ARDZ 4.5 V −40°C to +125°C 8-Lead Standard Small Outline Package RD-8-1 98
(SOIC_N_EP), Tube
ADP3654ARDZ-R7 4.5 V −40°C to +125°C 8-Lead Standard Small Outline Package RD-8-1 1,000
(SOIC_N_EP), 7“ Tape and Reel
ADP3654ARDZ-RL 4.5 V −40°C to +125°C 8-Lead Standard Small Outline Package RD-8-1 2,500
(SOIC_N_EP), 13“ Tape and Reel
ADP3654ARHZ 4.5 V −40°C to +125°C 8-Lead Mini Small Outline Package RH-8-1 50 78
(MINI_SO_EP), Tube
ADP3654ARHZ-R7 4.5 V −40°C to +125°C 8-Lead Mini Small Outline Package RH-8-1 1,000 78
(MINI_SO_EP), 7“ Tape and Reel)
ADP3654ARHZ-RL 4.5 V −40°C to +125°C 8-Lead Mini Small Outline Package RH-8-1 3,000 78
(MINI_SO_EP), 13” Tape and Reel
1
Z = RoHS Compliant Part.

©2010–2015 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D09054-0-8/15(A)

Rev. A | Page 13 of 13