TPS40077 4.5-V To 28-V Input, Voltage Mode, Synchronous Buck Controller With Voltage Feed Forward

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TPS40077
SLUS714E – JANUARY 2007 – REVISED JUNE 2019
TPS40077 4.5-V to 28-V Input, Voltage Mode, Synchronous Buck Controller

With Voltage Feed Forward
1 Features 3 Description
•
1 Operation Over 4.5-V to 28-V Input Range The TPS40077 is a mid-voltage, wide-input (4.5-V to
28-V), synchronous, step-down controller, offering
• Programmable, Fixed-Frequency, up to 1-MHz, design flexibility for a variety of user-programmable
Voltage-Mode Controller functions, including soft start, undervoltage lockout
• Predictive Gate-Drive Anti-Cross-Conduction (UVLO), operating frequency, voltage feed-forward,
Circuitry and high-side, FET-sensed, short-circuit protection.
• <1% Internal 700-mV Reference The TPS40077 drives external N-channel MOSFETs
• Internal Gate-Drive Outputs for High-Side and using second-generation, predictive-gate drive to
Synchronous N-Channel MOSFETs minimize conduction in the body diode of the low-side
FET and maximize efficiency. Pre-biased outputs are
• 16-Pin PowerPAD™ Package
supported by not allowing the low-side FET to turn on
• Thermal Shutdown Protection until the voltage commanded by the closed-loop soft
• Pre-Bias Compatible start is greater than the pre-bias voltage. Voltage
• Power-Stage Shutdown Capability feed-forward provides good response to input
transients and provides a constant PWM gain over a
• Programmable High-Side Sense Short-Circuit wide input-voltage operating range to ease
Protection compensation requirements. Programmable short-
circuit protection provides fault-current limiting and
2 Applications hiccup recovery to minimize power dissipation with a
• Power Modules shorted output. The 16-pin PowerPAD package gives
good thermal performance and a compact footprint.
• Networking/Telecom
• PCI Express Device Information(1)
• Industrial PART NUMBER PACKAGE BODY SIZE (NOM)
• Servers TPS40077 HTSSOP (16) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
TPS40077PWP
VDD 1 KFF ILIM 16 VDD
2 15
RT VDD
3 LVPB BOOST 14
Powergood
4 PGD HDRV 13
VOUT
5 SGND SW 12
VOUT
6 SS DBP 11
7 FB LDRV 10
8 COMP PGND 9
UDG-09041
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS40077
SLUS714E – JANUARY 2007 – REVISED JUNE 2019 www.ti.com
Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 21
2 Applications ........................................................... 1 8.1 Application Information............................................ 21
3 Description ............................................................. 1 8.2 Typical Applications ................................................ 21
4 Revision History..................................................... 2 8.3 Additional System Examples .................................. 32
5 Pin Configuration and Functions ......................... 3 9 Layout ................................................................... 34
9.1 Layout Guidelines ................................................... 34
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5 10 Device and Documentation Support ................. 35
6.2 ESD Ratings.............................................................. 5 10.1 Device Support...................................................... 35
6.3 Recommended Operating Conditions....................... 5 10.2 Documentation Support ........................................ 35
6.4 Electrical Characteristics........................................... 6 10.3 Receiving Notification of Documentation Updates 35
6.5 Typical Characteristics .............................................. 8 10.4 Community Resources.......................................... 35
10.5 Trademarks ........................................................... 35
7 Detailed Description ............................................ 12
10.6 Electrostatic Discharge Caution ............................ 35
7.1 Overview ................................................................. 12
10.7 Glossary ................................................................ 35
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13 11 Mechanical, Packaging, and Orderable
7.4 Programming........................................................... 17
Information ........................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (April 2009) to Revision E Page
• Added Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section; editorial changes ......................................................................................... 1
• Deleted Ordering Information table ........................................................................................................................................ 3
• Moved Package Dissipation Ratings table to Power Dissipation ........................................................................................ 16
2 Submit Documentation Feedback Copyright © 2007–2019, Texas Instruments Incorporated
Product Folder Links: TPS40077

TPS40077
www.ti.com SLUS714E – JANUARY 2007 – REVISED JUNE 2019
5 Pin Configuration and Functions

16-Pin HTSSOP with PowerPAD
(1)
PWP PACKAGE
(TOP VIEW)
KFF 1 16 ILIM
RT 2 15 VDD
LVBP 3 14 BOOST
PGD 4 Thermal 13 HDRV
SGND 5 Pad 12 SW
SS 6 11 DBP
FB 7 10 LDRV
COMP 8 9 PGND
P0047-01
(1) For more information on the PWP package, see the PowerPAD Thermally Enhanced Package technical brief
(SLMA002).
Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
A resistor connected from this pin to VIN programs the amount of feed-forward voltage. The current fed
1 KFF I into this pin is internally divided by 25 and used to control the slope of the PWM ramp and program
UVLO. Nominal voltage at this pin is maintained at 400 mV.
2 RT I A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.
4.2-V reference used for internal device logic only. This pin should be bypassed by a 0.1-μF ceramic
3 LVBP O
capacitor. External loads that are less than 1 mA and electrically quiet may be applied.
This is an open-drain output that pulls to ground when soft start is active, or when the FB pin is outside
4 PGD O
a ±10% band around VREF.
Signal ground reference for the device. Low-level quiet circuitry around the IC should connect to this pin.
This pin should be connected to the thermal pad under the IC, and that thermal pad should connect to
5 SGND —
the PGND pin. Do not allow power currents to flow in the thermal pad or in the SGND part of the ground
for best results.
Soft-start programming pin. A capacitor connected from this pin to GND programs the soft-start time.
The capacitor is charged with an internal current source of 12 μA. The resulting voltage ramp on the SS
pin is used as a second noninverting input to the error amplifier. The voltage at this error amplifier input
is approximately 1 V less than that on the SS pin. Output voltage regulation is controlled by the SS
6 SS I voltage ramp until the voltage on the SS pin reaches the internal offset voltage of 1 V plus the internal
reference voltage of 700 mV. If SS is pulled below 225 mV, the device goes into a shutdown state
where the power FETSs are turned off and the prebias circuitry is reset. If the programmed UVLO
voltage is below 6 V, connect a 330-kΩ resistor in parallel with the SS capacitor. Also provides timing for
fault recovery attempts.
Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal
7 FB I
reference voltage, 0.7 V.
Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this
8 COMP O
pin to the FB pin to compensate the overall loop. The COMP pin is internally clamped to 3.4 V.
Power ground reference for the device. There should be a low-impedance path from this pin to the
9 PGND —
source(s) of the lower MOSFET(s).
Gate drive for the N-channel synchronous rectifier. This pin switches from DBP (MOSFET on) to ground
10 LDRV O (MOSFET off). For proper operation, the total gate charge of the MOSFET connected to LDRV should
be less than 50 nC.
8-V reference used for the gate drive of the N-channel synchronous rectifier. This pin should be
11 DBP O
bypassed to ground with a 1-μF ceramic capacitor.
This pin is connected to the switched node of the converter. It is used for short-circuit sensing and gate-
12 SW I drive timing information and is the return for the high-side driver. A 1.5-Ω resistor is required in series
with this pin for protection against substrate current issues.
Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on)
13 HDRV O
to SW (MOSFET off).
Copyright © 2007–2019, Texas Instruments Incorporated Submit Documentation Feedback 3

TPS40077
Pin Functions (continued)

PIN
I/O DESCRIPTION
NO. NAME
The peak voltage on BOOST is equal to the SW node voltage plus the voltage present at DBP less the
bootstrap diode drop. This drop can be 1.4 V for the internal bootstrap diode or 300 mV for an external
14 BOOST I
Schottky diode. The voltage differential between this pin and SW is the available drive voltage for the
high-side FET.
15 VDD I Supply voltage for the device.
Short-circuit-protection programming pin. This pin is used to set the short circuit detection threshold. An
internal current sink from this pin to ground sets a voltage drop across an external resistor connected
from this pin to VDD. The voltage on this pin is compared to the voltage drop (VVDD – VSW) across the
high side N-channel MOSFET during conduction. Just prior to the beginning of a switching cycle, this pin
16 ILIM I
is pulled to approximately VDD/2 and released when SW is within 2 V of VDD or after a timeout (the
precondition time), whichever occurs first. Placing a capacitor across the resistor from ILIM to VDD
allows the ILIM threshold to decrease during the switch-on time, effectively programming the ILIM
blanking time. See Application Information.

TPS40077
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VDD, ILIM 30
COMP, FB, KFF, PGD, LVBP –0.3 6
Input voltage, VVDD V
SW –0.3 40
SW, transient (<50 ns) –2.5
COMP, KFF, RT, SS –0.3 6
VBOOST 50
Output voltage, VOUT V
DBP 10.5
LVBP 6
Output current source, IOUT (LDRV, HDRV) 1.5 A
LDRV, HDRV 2
Output current sink, IOUT A
KFF 10
RT 1
Output current mA
LVBP 1.5
Lead temperature, 1.6 mm (1/16 inch) from case (10 s) 260 °C
Operating junction temperature, TJ –40 125 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Input voltage 4.5 28 V
TA Operating free-air temperature –40 85 °C

TPS40077
6.4 Electrical Characteristics

TA = –40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, IKFF = 300 μA, fSW = 500 kHz, and all parameters at zero power dissipation
(unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VVDD Input voltage range, VIN 4.5 28 V
IVDD Quiescent current Output drivers not switching 2.5 3.5 mA
VLVBP Output voltage TA = TJ = 25°C 3.9 4.2 4.5 V
OSCILLATOR/RAMP GENERATOR
fOSC Accuracy 450 500 550 kHz
(1)
VRAMP PWM ramp voltage VPEAK – VVAL 2 V
VRT RT voltage 2.23 2.4 2.58 V
tON Minimum output pulse time (1) CHDRV = 0 nF 150 ns
VFB = 0 V, 100 kHz ≤ fSW ≤ 500 kHz 84% 93%
Maximum duty cycle
VFB = 0 V, fSW = 1 MHz 76% 93%
VKFF Feed-forward voltage 0.35 0.4 0.45 V
(1)
IKFF Feed-forward current operating range 20 1100 μA
SOFT START
ISS Charge current 7 12 17 μA
tDSCH Discharge time CSS = 3.9 nF 25 75 μs
CSS = 3.9 nF, VSS rising from 0.7 V to
tSS Soft-start time 210 290 500 μs
1.6 V
Turnon threshold 310 365 420
VSSSD mV
Shutdown threshold 225 275 325
VSSSDH Shutdown threshold hysteresis 35 150 mV
VDD > 10 V 7 8 9
VDBP Output voltage V
VDD = 4.5 V, IOUT = 25 mA 4 4.3
ERROR AMPLIFIER
TJ = 25°C 0.698 0.7 0.704
VFB Feedback regulation voltage total variation 0°C ≤ TJ ≤ 85°C 0.69 0.7 0.707 V
–40°C ≤ TJ ≤ 85°C 0.69 0.7 0.715
VSS Soft-start offset from VSS (1) Offset from VSS to error amplifier 1 V
GBW Gain bandwidth (1) 5 10 MHz
AVOL Open-loop gain 50 dB
ISRC Output source current 2.5 4.5 mA
ISINK Output sink current 2.5 6 mA
IBIAS Input bias current VFB = 0.7 V –250 0 nA
SHORT-CIRCUIT CURRENT PROTECTION
IILIM Current sink into current limit 80 105 125 μA
VILIM(ofst) Current limit offset voltage (VSW – VILIM) VILIM = 11.5 V, VVDD = 12 V –75 –50 –30 mV
tHSC Minimum HDRV pulse duration During short circuit 135 225 ns
Propagation delay to output (1) 50 ns
tBLANK Blanking time (1) 50 ns
tOFF Off time during a fault (SS cycle times) 7 Cycles
Switching level to end precondition
VSW 2 V
(VVDD – VSW) (1)
tPC Precondition time (1) 100 ns
(1)
VILIM Current limit precondition voltage threshold 6.8 V
(1) Ensured by design. Not production tested.

TPS40077
Electrical Characteristics (continued)

TA = –40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, IKFF = 300 μA, fSW = 500 kHz, and all parameters at zero power dissipation
(unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT DRIVERS
tHFALL High-side driver fall time (HDRV – SW) (1) 36 ns
CHDRV = 2200 pF
tHRISE High-side driver rise time (HDRV – SW) (1) 48 ns
tHFALL High-side driver fall time (HDRV – SW) (1) CHDRV = 2200 pF, VVDD = 4.5 V, 72 ns
tHRISE High-side driver rise time (HDRV – SW) (1) 0.2 V ≤ VSS ≤ 4 V 96 ns
tLFALL Low-side driver fall time (1) 24 ns
CLDRV = 2200 pF
tLRISE Low-side driver rise time (1) 48 ns
tLFALL Low-side driver fall time (1) CLDRV = 2200 pF, VVDD = 4.5 V, 48 ns
tLRISE Low-side driver rise time (1) 0.2 V ≤ VSS ≤ 4 V 96 ns
High-level output voltage, HDRV IHDRV = –0.01 A 0.7 1
VOH V
(VBOOST – VHDRV) IHDRV = –0.1 A 0.95 1.3
IHDRV = 0.01A 0.06 0.1
VOL Low-level output voltage, HDRV (VHDRV – VSW) V
IHDRV = 0.1 A 0.65 1
High-level output voltage, LDRV ILDRV= –0.01A 0.65 1
VOH V
(VDBP – VLDRV) ILDRV = –0.1 A 0.875 1.2
ILDRV = 0.01 A 0.03 0.05
VOL Low-level output voltage, LDRV V
ILDRV = 0.1 A 0.3 0.5
VBOOST Output voltage VDD = 12 V 15.2 17 V
UVLO
VUVLO Programmable UVLO threshold voltage RKFF = 90.9 kΩ, turn-on, VVDD rising 6.2 7.2 8.2 V
Programmable UVLO hysteresis RKFF = 90.9 kΩ 1.1 1.55 2 V
Fixed UVLO threshold voltage Turn-on, VVDD rising 4.15 4.3 4.45 V
Fixed UVLO hysteresis 275 365 mV
POWER GOOD
VPG Power-good voltage IPG = 1 mA 370 500 mV
VOH High-level output voltage, FB 770 mV
VOL Low-level output voltage, FB 630 mV
THERMAL SHUTDOWN
Shutdown temperature threshold (1) 165 °C
Hysteresis (1) 15 °C

TPS40077
6.5 Typical Characteristics
4.30 8.15
8.10
4.25 VDD = 28 V
VDD = 28 V
VLVPP − LVBP Voltage − V
8.05
VDBP − DBP Voltage − V

4.20
8.00
4.15 VDD = 12 V VDD = 12 V
7.95
4.10
7.90
4.05
7.85
4.00 7.80
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ − Junction Temperature − °C TJ − Junction Temperature − °C
Figure 1. LVBP Voltage vs Junction Temperature Figure 2. DBP Voltage vs Junction Temperature
4.50 2.0
VDD = 4.5 V
4.49 ILOAD = 25 mA 1.9
VDROP − Bootstrap Diode Voltage Drop − V

4.48 1.8
VDBP − DBP Voltage − V
4.47 1.7
4.46 1.6
4.45 1.5
4.44 1.4
4.43 1.3
4.42 1.2
4.41 1.1
4.40 1.0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
Figure 3. DBP Voltage vs Junction Temperature Figure 4. Bootstrap Diode Voltage
vs Junction Temperature
0 150
VILIM(offst) – Current Limit Offset Voltage Drop – mV
145
−10
IILIM − Current Limit Sink Current − µA
+3 S 140
135
−20
Average 130
−30 125
120
−40
115
VDD
−3 S 28 V
110 12 V
−50
4.5 V
105
−60 100
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ – Junction Temperature – °C TJ − Junction Temperature − °C
Figure 5. Current Limit Offset Voltage Figure 6. Current Limit Sink Current
vs Junction Temperature vs Junction Temperature

TPS40077
Typical Characteristics (continued)

704 500
VDD RRT = 90.1kΩ
28 V 499
703 4.5 V
12 V 498
fSW − Switching Frequency − kHz

VFB − Feedback Voltage − V
702 497
496
701
495
700
494
493
699
492
698
491
697 490
−50 −25 0 25 50 75 100 125 4 8 12 16 20 24 28
TJ − Junction Temperature − °C VVDD − Input Voltage − V
Figure 7. Feedback Regulation Voltage Figure 8. Switching Frequency vs Input Voltage

93 4.35
VUVLO − Undervoltage Lockout Threshold − V

92 4.30
DMAX − Maximum Duty Cycle − %
91 VUVLO(on)
4.25
fSW = 100 kHZ
90
4.20
89
4.15
88
4.10
fSW = 500 kHZ
87
4.05
86
4.00 VUVLO(off)
85 fSW = 1 MHZ
84 3.95
83 3.90
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
Figure 9. Maximum Duty Cycle Figure 10. Undervoltage Lockout

1.10 14.0
VUVLO − Relative Programmable UVLO Threshold − %
1.08
VUVLO(off) 13.5
ISS − Soft−Start Charging Current − µA
1.06 VUVLO(on)
13.0
1.04
12.5
1.02
1.00 12.0
0.98
11.5
0.96
11.0
0.94
10.5
0.92
0.90 10.0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
Figure 11. Programmable UVLO Threshold Figure 12. Soft-Start Charging Current

TPS40077

0 5.0
VIN = 28 V
IBIAS − Error Amplifier Input Bias Current − nA
−10 4.5
VIN = 24 V
−20 4.0 VIN = 18 V
VOUT − Output Voltage − V

VIN = 15 V
−30 3.5 VIN = 12 V
VIN = 10 V
−40 3.0
VIN = 8 V
−50 2.5
VIN = 5 V
−60 2.0
−70 1.5
−80 1.0
−90 0.5
−50 −25 0 25 50 75 100 125 100 200 300 400 500 600 700 800 900 1000
TJ − Junction Temperature − °C fOSC − Oscillator Frequency − kHz
Figure 13. Error Amplifier Input Bias Current Figure 14. Minimum Output Voltage vs Frequency
600 20
fSW = 300 kHz
UVLOVON
18
VUVLO − Programmable UVLO Threshold − V

500
16
RT − Timing Resistance − kΩ
400 14
12 UVLOVOFF
300
10
200 8
100
4
0 2
100 150 200 250 300 350 400 450
0 200 400 600 800 1000
RKFF − Feedforward Impedance − kΩ
fSW − Switching Frequency − kHz G017
Figure 16. Undervoltage Lockout Threshold
Figure 15. Switching Frequency
vs Feed-Forward Impedance
vs Timing Resistance
20 20
fSW = 500 kHz UVLOVON fSW = 750 kHz
UVLOVON
18 18
16 16
14 14
12 UVLOVOFF 12 UVLOVOFF
10 10
8 8
6 6
4 4
2 2
60 90 120 150 180 210 240 270 40 60 80 100 120 140 160 180
RKFF − Feedforward Impedance − kΩ RKFF − Feedforward Impedance − kΩ
Figure 17. Undervoltage Lockout Threshold Figure 18. Undervoltage Lockout Threshold
vs Feed-Forward Impedance vs Feed-Forward Impedance

TPS40077

100 10
UVLO(on) = 15 V
90
9
VDBP − Driver Bypass Voltage − V

80
UVLO(on) = 8 V
UVLO(on) = 12 V 8
Duty Cycle − %
70
60 7
UVLO(on) = 4.5 V
50
6
40
5
30
20 4
4 8 12 16 20 24 28 0 5 10 15 20 25
VIN − Input Voltage − V VDD − Input Voltage − V
G023 G024
Figure 19. Typical Maximum Duty Cycle Figure 20. DBP Voltage vs Input Voltage
vs Input Voltage
4.50
4.45
VDBP − Low Voltage Bypass Voltage − V
4.40
4.35
4.30
4.25
4.20
4.15
4.10
4.05
4.00
5 10 15 20 25 30
VDD − Input Voltage − V
G025
Figure 21. Input Voltage vs Low-Voltage Bypass Voltage

TPS40077
7 Detailed Description
7.1 Overview
The TPS40077 allows the user to construct synchronous voltage-mode buck converters with inputs ranging from
4.5 V to 28 V and outputs as low as 700 mV. Predictive Gate Drive circuitry optimizes switching delays for
increased efficiency and improved converter output-power capability. Voltage feed forward is employed to ease
loop compensation for wide-input-range designs and provide better line transient response.
The TPS40077 incorporates circuitry to allow start-up into a preexisting output voltage without sinking current
from the source of the preexisting output voltage. This avoids damaging sensitive loads at start-up. An integrated
power-good indicator is available for logic (open-drain) output of the condition of the output of the converter.
7.2 Functional Block Diagram
11 DBP
VDD
Reference
VDD 15 UVLO 16 ILIM
Regulator UVLO
Controller
LVBP 3
Ramp
RT 2 Oscillator Generator SW Pulse
CLK Control
9 PGND
KFF 1 RAMP
PGD 4
770 mV
Power
Good FB
12 SW
SGND 5 Logic 630 mV
SS Active
Short-Circuit
ILIM Comparator OC
SS Active CLK and Control
LVBP
Soft Start OC
and
Fault Control CLK DBP 14 BOOST
OC Predictive 13 HDRV
FB 7 Gate Drive
CLK PWM Control SW
700 mV + Logic
+
UVLO 10 LDRV
SS 6
PGND
COMP 8 FAULT
B0150-01

TPS40077
7.3 Feature Description

7.3.1 Minimum Pulse Duration
The TPS40077 devices have limitations on the minimum pulse duration that can be used to design a converter.
Reliable operation is assured for nominal pulse durations of 150 ns and above. This places some restrictions on
the conversion ratio that can be achieved at a given switching frequency. Figure 14 shows minimum output
voltage for a given input voltage and frequency.
7.3.2 Slew Rate Limit On VDD

The regulator that supplies power for the drivers on the TPS40077 requires a limited rising slew rate on VDD for
proper operation if the input voltage is above 10 V. If the slew rate is too great, this regulator can overshoot and
damage to the part can occur. To ensure that the part operates properly, limit the slew rate to no more than
0.12 V/μs as the voltage at VDD crosses 8 V. If necessary, an R-C filter can be used on the VDD pin of the
device. Connect the resistor from the VDD pin to the input supply of the converter. Connect the capacitor from
the VDD pin to PGND. There should not be excessive (more than a 200-mV) voltage drop across the resistor in
normal operation. This places some constraints on the R-C values that can be used. Figure 22 is a schematic
fragment that shows the connection of the R-C slew rate limit circuit. Equation 1 and Equation 2 give values for R
and C that limit the slew rate in the worst-case condition.
R TPS40077
ILIM 16
VIN 15 VDD
+ C HDRV 13
_
SW 12
9 PGND
LDRV 10
S0203-01
Figure 22. Limiting the Slew Rate

V IN * 8 V
Cu
R SR (1)
Rt 0.2 V
f SW Q g(TOT) ) I DD
where
• VVIN is the final value of the input voltage ramp
• fSW is the switching frequency
• Qg(TOT) is the combined total gate charge for both upper and lower MOSFETs (from MOSFET data sheet)
• IDD is the TPS40077 input current (3.5 mA maximum)
• SR is the maximum allowed slew rate [12 ×104] (V/s) (2)

TPS40077
Feature Description (continued)

7.3.3 Setting The Switching Frequency (Programming The Clock Oscillator)
The TPS40077 has independent clock oscillator and PWM ramp generator circuits. The clock oscillator serves as
the master clock to the ramp generator circuit. Connecting a single resistor from RT to ground sets the switching
frequency of the clock oscillator. The clock frequency is related to RT with Equation 3.
RT + ǒ f SW(kHz)
1
17.82 10 *6
* 23Ǔ kW
(3)
7.3.4 Loop Compensation

Voltage-mode, buck-type converters are typically compensated using Type III networks. Because the TPS40077
uses voltage feed-forward control, the gain of the voltage feed-forward circuit must be included in the PWM gain.
The gain of the voltage feed-forward circuit, combined with the PWM circuit and power stage for the TPS40077 is
Equation 4.
KPWM ≅ VUVLO(on) (4)

The remainder of the loop compensation is performed as in a normal buck converter. Note that the voltage feed-
forward circuitry removes the input voltage term from the expression for PWM gain. PWM gain is strictly a
function of the programmed start-up voltage.
7.3.5 Shutdown and Sequencing

The TPS40077 can be shut down by pulling the SS pin below 250 mV. In this state, both of the output drivers are
in the low-output state, turning off both of the power FETs. This places the output of the converter in a high-
impedance state. When shutting down the converter, a crisp pulldown of the SS pin is preferred to a slow
pulldown. A slow pulldown could allow the output to be pulled low, possibly sinking current from the load. As a
general rule of thumb, the fall time of SS when shutting down the converter should be no more than 1/10th of the
control loop crossover frequency. An example of a shutdown interface is shown in Figure 23.
TPS40077
6 SS
Shutdown
S0204-01
Figure 23. TPS40077 Shutdown
In a similar manner, power supplies based on the TPS40077 can be sequenced by connecting the PGD pin of
the first supply to come up to the SS pin of the second supply as shown in Figure 24.

TPS40077
TPS40077 TPS40077
6 SS PGD 4 6 SS PGD 4 To System Power Good
S0205-01
Figure 24. TPS40077 Sequencing
7.3.6 Boost and LVBP Bypass Capacitance

The BOOST capacitance provides a local, low-impedance flying source for the high-side driver. The BOOST
capacitor should be a good-quality, high-frequency capacitor. A capacitor with a minimum value of 100-nF is
suggested.
The LVBP pin must provide energy for both the synchronous MOSFET and the high-side MOSFET (via the
BOOST capacitor). The suggested value for this capacitor is 1-μF ceramic, minimum.
7.3.7 Internal Regulators

The internal regulators are linear regulators that provide controlled voltages from which the drivers and the
internal circuitry operate. The DBP pin is connected to a nominal 8-V regulator that provides power for the driver
circuits. This regulator has two modes of operation. At VDD voltages below 8.5 V, the regulator is in a low-dropout
mode of operation and tries to provide as little impedance as possible from VDD to DBP. Above 10 V at VDD, the
regulator regulates DBP to 8 V. Between these two voltages, the regulator remains in the state it was in when
VDD entered this region (see Figure 20). Small amounts of current can be drawn from this pin for other circuit
functions, as long as power dissipation in the controller device remains at acceptable levels and junction
temperature does not exceed 125°C.
The LVBP pin is connected to another internal regulator that provides 4.2 V (nom) for the operation of low-
voltage circuitry in the controller. This pin can be used for other circuit purposes, but extreme care must be taken
to ensure that no extra noise is coupled onto this pin; otherwise, controller performance suffers. Current draw is
not to exceed 1 mA. See Figure 21 for typical output voltage at this pin.
7.3.8 Power Dissipation

The power dissipation in the TPS40077 is largely dependent on the MOSFET driver currents and the input
voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver power
(neglecting external gate resistance) can be calculated with Equation 5.
PD = Qg × VDR × fSW (Watts/driver)
where
VDR is the driver output voltage (5)
The total power dissipation in the TPS40077, assuming the same MOSFET is selected for both the high-side and
synchronous rectifier, is described in Equation 6 or Equation 7.
PT + ǒ
2 PD
V DR
) IQ Ǔ
V IN (Watts)
(6)

TPS40077

or
P T + ǒ2 Qg f SW ) I QǓ V IN (Watts)
where IQ is the quiescent operating current (neglecting drivers) (7)

The maximum power capability of the TPS40077 PowerPAD package is dependent on the layout as well as air
flow. The thermal impedance from junction to air, assuming 2-oz. copper trace and thermal pad with solder and
no air flow, is 37°C/W. See the application report titled PowerPAD Thermally Enhanced Package (SLMA002) for
detailed information on PowerPAD package mounting and usage.
The maximum allowable package power dissipation is related to ambient temperature by Equation 8. For θJA, see
Table 1.
T * TA
PT + J (Watts)
q JA (8)
Table 1. Package Dissipation Ratings

THERMAL IMPEDANCE,
TA = 25°C POWER RATING TA = 85°C POWER RATING
JUNCTION-TO-AMBIENT (1)
Natural convection 37°C/W 2.7 W 1.08 W
150 LFM airflow 30°C/W 3.33 W 1.33 W
250 LFM airflow 28°C/W 3.57 W 1.42 W
500 LFM airflow 26°C/W 3.84 W 1.52 W
(1) For more information on the board and the methods used to determine ratings, see the PowerPAD Thermally Enhanced Package
application report (SLMA002).
Substituting Equation 8 into Equation 7 and solving for fSW yields the maximum operating frequency for the
TPS40077. The result is described in Equation 9.
ǒƪ ǒT J*T AǓ
ǒq JA V DDǓ
* IQƫ Ǔ
f SW + (Hz)
ǒ2 Q gǓ (9)
7.3.9 Boost Diode

The TPS40077 series has internal diodes to charge the boost capacitor connected from SW to BOOST. The drop
across these diodes is rather large, 1.4 V nominal, at room temperature. If this drop is too large for a particular
application, an external diode may be connected from DBP (anode) to BOOST (cathode). This provides
significantly improved gate drive for the high-side FET, especially at lower input voltages.
7.3.10 Synchronous Rectifier Control

Table 2 describes the state of the rectifier MOSFET control under various operating conditions.
Table 2. Synchronous Rectifier MOSFET States

SYNCHRONOUS RECTIFIER OPERATION DURING
FAULT
SOFT-START NORMAL (FAULT RECOVERY IS SAME AS OVERVOLTAGE
SOFT-START)
Turns OFF only at start of next cycle
Off until first high-side pulse is Turns off at the start of a new cycle.
only if the pulse width modulator duty
detected, then on when high-side Turns on when the high-side OFF
cycle is greater than zero. Otherwise,
MOSFET is off MOSFET is turned off
stays ON

TPS40077
For proper operation, the total gate charge of the MOSFET connected to LDRV must be less than 50 nC.
7.4 Programming
7.4.1 Programming The Ramp Generator Circuit and UVLO
The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides
voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp
magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations,
because the PWM is not required to wait for loop delays before changing the duty cycle. (See Figure 25).
The PWM ramp must reach approximately 1 V in amplitude during a clock cycle, or the PWM is not allowed to
start. The PWM ramp time is programmed via a single resistor (RKFF) connected from KFF VDD. RKFF, VSTART,
and RT are related by (approximately) Equation 10.
2
R KFF + 0.131 RT V UVLO(on) * 1.61 10*3 V UVLO(on) ) 1.886 V UVLO * 1.363 * 0.02 R T * 4.87 10*5 R 2T
where
• RT and RKFF are in kΩ
• VUVLO(on) is in V (10)
This yields typical numbers for the programmed start-up voltage. The minimum and maximum values may vary
up to ±15% from this number. Figure 16 through Figure 18 show the typical relationship of VUVLO(on), VUVLO(off)
and RKFF at three common frequencies.
The programmable UVLO circuit incorporates 20% hysteresis from the start voltage to the shutdown voltage. For
example, if the start-up voltage is programmed to be 10 V, the controller starts when VDD reaches 10 V and shuts
down when VDD falls below 8 V. The maximum duty cycle begins to decrease as the input voltage rises to twice
the start-up voltage. Below this point, the maximum duty cycle is as specified in the Electrical Characteristics.
Note that with this scheme, the theoretical maximum output voltage that the converter can produce is
approximately two times the programmed start-up voltage. For design, set the programmed start-up voltage
equal to or greater than the desired output voltage divided by maximum duty cycle (85% for frequencies 500 kHz
and below). For example, a 5-V output converter should not have a programmed start-up voltage below 5.9 V.
Figure 25 shows the theoretical maximum duty cycle (typical) for various programmed start-up voltages.
VIN
VIN
SW SW
VPEAK RAMP
COMP COMP
RAMP VVALLEY
T1 T2
tON1 tON2
t
d + ON tON1 > tON2 and d1 > d2
T
VDG−03172
Figure 25. Voltage Feed-Forward and PWM Duty Cycle Waveforms

TPS40077
Programming (continued)
7.4.2 Programming Soft Start
TPS40077 uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft start is
programmed by connecting an external capacitor (CSS) from the SS pin to GND. This capacitor is charged by a
fixed current, generating a ramp signal. The voltage on SS is level-shifted down approximately 1 V and fed into a
separate noninverting input to the error amplifier. The loop is closed on the lower of the level-shifted SS voltage
or the 700-mV internal reference voltage. Once the level-shifted SS voltage rises above the internal reference
voltage, output-voltage regulation is based on the internal reference. To ensure a controlled ramp-up of the
output voltage, the soft-start time should be greater than the L-COUT time constant or Equation 11.
t START w 2p ǸL COUT
(11)
Note that there is a direct correlation between tSTART and the input current required during start-up. The lower
tSTART is, the higher the input current required during start-up, because the output capacitance must be charged
faster. For a desired soft-start time, the soft-start capacitance, CSS, can be found from Equation 12.
I SS
C SS + t SS
VFB (12)
7.4.3 Programming Short-Circuit Protection

The TPS40077 uses a two-tier approach for short-circuit protection. The first tier is a pulse-by-pulse protection
scheme. Short-circuit protection is implemented on the high-side MOSFET by sensing the voltage drop across
the MOSFET when its gate is driven high. The MOSFET voltage is compared to the voltage dropped across a
resistor (RILIM) connected from VVDD to the ILIM pin when driven by a constant-current sink. If the voltage drop
across the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately
terminated. The MOSFET remains off until the next switching cycle is initiated. This is illustrated in Figure 26.
ILIM
ILIM Threshold
(A)
Overcurrent
VIN − 2V
SW
T2
ILIM ILIM Threshold

T1 VIN − 2V
(B)
SW
T1
T3 UDG−03173
Figure 26. Switching and Current-Limit Waveforms and Timing Relationship

TPS40077
In addition, just prior to the high-side MOSFET turning on, the ILIM pin is pulled down to approximately half of
VVDD. The ILIM pin is allowed to return to its nominal value after one of two events occurs. If the SW node rises
to within approximately 2 V of VVDD, the device allows ILIM to go back to its nominal value. This is illustrated in
Figure 26(A). T1 is the delay time from the internal PWM signal being asserted and the rise of SW. This includes
a driver delay of 50 ns, typical. T2 is the reaction time of the sensing circuit that allows ILIM to start to return to
its nominal value, typically 20 ns. The second event that can cause ILIM to return to its nominal value is for an
internal timeout to expire. This is illustrated in Figure 26(B) as T3. Here SW never rises to VVDD – 2 V, for
whatever reason, and the internal timer times out, releasing the ILIM pin.
Prior to ILIM starting back to its nominal value, overcurrent sensing is not enabled. In normal operation, this
ensures that the SW node is at a higher voltage than ILIM when overcurrent sensing starts, avoiding false trips
while allowing for a quicker blanking delay than would ordinarily be possible. Placing a capacitor across RILIM
sets an exponential approach to the normal voltage at the ILIM pin. This exponential decay of the overcurrent
threshold can be used to compensate for ringing on the SW node after its rising edge and to help compensate
for slower-turnon FETs. Choosing the proper capacitance requires care. If the capacitance is too large, the
voltage at ILIM does not approach the desired overcurrent level quickly enough, resulting in an apparent shift in
overcurrent threshold as pulse duration changes. As a general rule, it is best to make the time constant of the R-
C at the ILIM pin 0.2 times or less of the nominal pulse duration of the converter as shown in Equation 17.
Also, the comparator that uses ILIM and SW to determine if an overcurrent condition exists has a clamp on its
SW input. This clamp makes the SW node never appear to fall more than 1.4 V (approximately, could be as
much as 2 V at –40°C) below VVDD. When ILIM is more than 1.4 V below VVDD, the overcurrent circuit is
effectively disabled.
The second-tier protection incorporates a fault counter. The fault counter is incremented on each cycle with an
overcurrent pulse and decremented on a clock cycle without an overcurrent pulse. When the counter reaches
seven (7), a fault condition is declared by the controller. When this happens, the outputs are placed in a state
defined in Table 2. Seven soft-start cycles are initiated (without activity on the HDRV and LDRV outputs) and the
PWM is disabled during this period. The counter is decremented on each soft-start cycle. When the counter is
decremented to zero, the PWM is re-enabled and the controller attempts to restart. If the fault has been
removed, the output starts up normally. If the output is still present, the counter counts seven overcurrent pulses
and re-enters the second-tier fault mode. Refer to Figure 27 for typical fault-protection waveforms.
In Equation 13, the minimum short-circuit limit setpoint (ISCP(min)) depends on tSTART, COUT, VOUT, ripple current in
the inductor (IRIPPLE), and the load current at turnon (ILOAD).
I SCP(min) u ǒ
COUT VOUT
t START
Ǔ I
) I LOAD ) RIPPLE
2
ǒ Ǔ
(13)
The short-circuit limit programming resistor (RILIM) is calculated from Equation 14.
I SCP RDS(onMAX) ) VILIM (offset)
R ILIM + W
I ILIM
where
• IILIM is the current into the ILIM pin (110 μA, typical)
• VILIM(offset) is the offset voltage of the ILIM comparator (–50 mV, typical)
• ISCP is the short-circuit protection current (14)
To find the range of the overcurrent values, use Equation 15 and Equation 16.
1.09 I ILIM(max) R ILIM * 0.09 RVDD I R * 0.045 V ) 75 mV
VDD
I SCP(max) + (A)
R DS(ON)min
(15)
1.09 I ILIM(min) R ILIM * 0.09 RVDD IR * 0.045 V ) 30 mV
VDD
I SCP(min) + (A)
R DS(ON)max
(16)

TPS40077
The TPS40077 provides short-circuit protection only. Therefore, it is recommended that the minimum short-circuit
protection level be placed at least 20% above the maximum output current required from the converter. The
maximum output of the converter should be the steady state maximum output plus any transient specification
that may exist.
The ILIM capacitor maximum value can be found from Equation 17.
V OUT 0.2
C ILIM(max) + (Farads)
VIN RILIM f SW (17)
Note that this is a recommended maximum value. If a smaller value can be used, it should be. For most
applications, consider using half the maximum value above.
HDRV
Clock
tBLANKING
VILIM
VVIN − VSW
SS
7 Current-Limit Trips
(HDRV Cycle Terminated by Current-Limit Trip)
7
Soft-Start
Cycles VDG−03174
Figure 27. Typical Fault Protection Waveforms

TPS40077
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information

The TPS40077 allows the user to construct synchronous voltage-mode buck converters with inputs ranging from
4.5 V to 28 V and outputs as low as 700 mV. Predictive Gate Drive circuitry optimizes switching delays for
increased efficiency and improved converter output-power capability. Voltage feed-forward is employed to ease
loop compensation for wide-input-range designs and provide better line transient response.
The TPS40077 incorporates circuitry to allow startup into a preexisting output voltage without sinking current
from the source of the preexisting output voltage. This avoids damaging sensitive loads at start-up. An integrated
power-good indicator is available for logic (open-drain) output of the condition of the output of the converter.
8.2 Typical Applications

8.2.1 Buck Regulator 8-V to 16-V Input, 1.8-V Output at 10 A
VIN
CIN +
ELCO RKFF CDELAY RLIM
RT
U1
TPS40077PWP QSW
CBP5
1 16 VOUT = 1.8 V
KFF ILIM LOUT
2 15 CBOOST IOUT up to 10 A
RPGD RT VDD
3 14
BP5 BOOST VOUT
4 13 CVDD
PGD HDRV
5 12 C_IN
SGND SW
6 11 MLCC
SS DBP
CSS 7 10 R4
FB LDRV + COUT C_OUT
0W
8 9 ELCO MLCC
R10 COMP PGND QSR
330 kW PWP
C13
CDBP 2.2nF
RPZ2 CZ2
CP2
0V
RZ1
RSET CPZ1 RP1 C11

0.1 mF
S0239-01
Figure 28. Schematic Diagram
8.2.1.1 Design Requirements

Table 3 lists the design specifications and Table 4 lists the bill of materials for this buck regulator application
example.
TPS40077
Typical Applications (continued)

Table 3. Characteristics
PARAMETER NOTES AND CONDITIONS MIN NOM MAX UNITS
INPUT CHARACTERSTICS
VIN Input voltage 8 12 16 V
IIN Input current VIN = NOM, IOUT = MAX 1.8 2 A
No-load input current VIN = NOM, IOUT = 0 A 62.6 3.6 mA
VIN_UVLO Input UVLO IOUT = MIN to MAX 5.4 6 6.6 V
VIN_ONV Input ONV IOUT = MIN to MAX 6.3 7 7.7 V
OUTPUT CHARACTERSTICS
VOUT Output voltage VIN = NOM, IOUT = NOM 1.75 1.8 1.85 V
Line regulation (1) VIN = MIN to MAX, IOUT = NOM 0.5%
Load regulation (1) VIN = NOM, IOUT = MIN to MAX 0.5%
VOUT_ripple Output voltage ripple VIN = NOM, IOUT = MAX 100 mVpp
IOUT Output current VIN = MIN to MAX 0 5 10 A
Output overcurrent
IOCP VIN = NOM, VOUT = VOUT – 5% 12.25 19.4 34 A
inception point
VOVP Output OVP IOUT = MIN to MAX NA NA NA
Transient response
ΔI Load step IOUT_Max to 0.2 × IOUT _Max 8 A
Load slew rate 10 A/μs
Overshoot 200 mV
Settling time 1 ms
SYSTEM CHARACTERSTICS
fSW Switching frequency 240 300 360 kHz
ηpk Peak efficiency VIN = NOM, IOUT = MIN to MAX 90%
η Full-load efficiency VIN = NOM, IOUT = MAX 90%
Operating temperature
Top VIN = MIN to MAX, IOUT = MIN to MAX –40 25 85 °C
range
MECHANICAL CHARACTERSTICS
2 Inches
L Width
5.08 cm
3 Inches
W Length
7.62 cm
0.41 Inch
h Component height
1.04 cm
(1) Voltage accuracy is dependent on resistor tolerance and reference accuracy. Line and load regulation are calculated with respect to the
actual set point voltage.
Table 4. Bill of Materials

REFDES COUNT VALUE DESCRIPTION SIZE PART NUMBER MFR
C1 1 470 μF Capacitor, aluminum, 470-μF, 25-V, 0.457 x 0.406 EEVFK1E471P Panasonic
20%
C2, C10 2 0.1 μF Capacitor, ceramic, 25-V, X7R, 20% 0603 Std Vishay
C3 1 15 nF Capacitor, ceramic, 25-V, X7R 20% 0603 Std Vishay
C4 1 47 pF Capacitor, ceramic, 25-V, X7R, 20% 0603 Std Vishay
C5 1 1.8 nF Capacitor, ceramic, 25-V, X7R 20% 0603 Std Vishay
C6 1 680 pF Capacitor, ceramic, 25-V, X7R 20% 0603 Std Vishay
C7 1 51 pF Capacitor, ceramic, 25-V, COG 20% 0603 Std Vishay
C8, C11 2 0.1 μF Capacitor, ceramic, 25-V, X7R, 20% 0603 Std Vishay

TPS40077
Table 4. Bill of Materials (continued)

REFDES COUNT VALUE DESCRIPTION SIZE PART NUMBER MFR
C9 1 1 μF Capacitor, ceramic, 25-V, X7R, 20% 0805 Std Vishay
C12, C14, 3 22 μF Capacitor, ceramic, 22-μF, 16-V, 1812 C4532X5R1C226MT TDK
C15 X5R, 20%
C13 1 2.2 nF Capacitor, ceramic, 25-V, X7R, 20% 0603 Std Vishay
C16 1 470 μF Capacitor, aluminum, SM, 6.3-V, 8 × 10 Std Panasonic
300-mΩ (FC series)
C17 1 47 μF Capacitor, ceramic, 47-uF, 6.3-V, 1812 C4532X5R0J476MT TDK
X5R, 20%
D1 1 BAT54 Diode, Schottky, 200-mA, 30-V SOT23 BAT54 Vishay
J1, J2 2 ED1609-ND Terminal block, 2-pin, 15-A, 5,1-mm 0.40 × 0.35 ED1609 OST
J3 1 PTC36SAAN Header, 2-pin, 100-mil spacing, (36- 0.100 × 2 PTC36SAAN Sullins
pin strip)
L1 1 2.5 μH Inductor, SMT, 2.5 μH, 16.5-A, 3.4- 0.515 × 0.516 MLC1550-252ML Coilcraft
mΩ
Q1 1 Si7860DP MOSFET, N-channel, 30-V, 18-A, PWRPAK S0-8 Si7860DP Vishay
8.0-mΩ
Q2 1 Si7336ADP MOSFET, N-channel, 30-V, 18-A, 40- PWRPAK S0-8 Si7886ADP Vishay
mΩ
Q3 1 FDV301N MOSFET, N-channel, 25-V, 220-mA, SOT23 FDV301N Fairchild
5-Ω
R1 1 10 kΩ Resistor, chip, 1/16-W, 20% 0603 Std Std
R2, R6 2 165 kΩ Resistor, Chip, 1/16-W, 20% 0603 Std Std
R3 1 32.4 kΩ Resistor, chip, 1/16-W, 20% 0603 Std Std
R4, R11 2 0Ω Resistor, chip, 1/16-W, 20% 0603 Std Std
R12 1 51 Ω Resistor, chip, 1/16-W, 20% 0603 Std Std
U1 1 TPS40077PWP IC, Texas Instruments PWP16 TPS40077PWP TI
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Power Train Components
8.2.1.2.1.1 Output Inductor, LOUT

The output inductor is one of the most important components to select. It stores the energy necessary to keep
the output regulated when the switch FET is turned off. The value of the output inductor dictates the peak and
RMS currents in the converter. These currents are important when selecting other components. Equation 18 can
be used to calculate a value for LOUT for this module which operates at a switching frequency (f) of 300 kHz.
VOUT V IN(max) * V OUT
LOUT +
V IN(max) f s I RIPPLE
(18)
IRIPPLE is the allowable ripple in the inductor. Select IRIPPLE to be between 20% and 30% of maximum IOUT. For
this design, IRIPPLE of 2.5 A was selected. Calculated LOUT is 2.13 μH. A standard inductor with value of 2.5 μH
was chosen. This will reduce IRIPPLE by about 17% to 2.07 A.
This IRIPPLE value can be used calculate the rms and peak current flowing in LOUT with Equation 19. Note that
this peak current is also seen by the switching FET and synchronous rectifier.

TPS40077
I LOUT_RMS + Ǹ I OUT
2 I
2
) RIPPLE + 10.02 A
12 (19)
The power loss from the selected inductor DCR is 357 mW. The ac core loss for this Coilcraft inductor may be
found from the Coilcraft Web site, where there is a loss calculator. The loss is 179 mW calculated with
Equation 20.
I
I PK + I OUT ) RIPPLE + 11.03 A
2 (20)
The inductor is selected with a saturation current higher than this current plus the current that is developed
charging the output capacitance during the soft-start interval.
8.2.1.2.1.2 Output Capacitor, COUT, ELCO and MLCC

Several parameters must be considered when selecting the output capacitor. The capacitance value should be
selected based on the output overshoot, VOVER, and undershoot, VUNDER, during a transient load, ISTEP, on the
converter. The equivalent series resistance (ESR) is chosen to allow the converter to meet the output ripple
specification, VRIPPLE. The voltage rating must be greater than the maximum output voltage. Another parameter
to consider is equivalent series inductance, which is important in fast-transient load situations. Also, size and
technology can be factors when choosing the output capacitor. In this design, a large-capacitance electrolytic
type capacitor, COUT ELCO, is used to meet the overshoot and undershoot specifications. Its ESR is chosen to
meet the output ripple specification. Smaller multiple-layer ceramic capacitors, COUT MLCC, are used to filter
high-frequency noise.
The minimum required capacitance and maximum ESR can be calculated using Equation 21, Equation 22, and
Equation 23.
2
LOUT I STEP
COUT +
2 VUNDER Dmax (VIN * VOUT) (21)
2
LOUT I STEP
COUT +
2 VOVER VOUT (22)
V
ESR + RIPPLE
I RIPPLE (23)
The capacitance for COUT should be greater than 444 μF, and its ESR should be less than 12 mΩ. The 470-
μF/6.3-V capacitor from Panasonic's FC series was chosen. Its ESR is 160 mΩ. MLCCs of 47 μF and 22 μF/16 V
are also added in parallel to achieve the required ESR and to reduce high-frequency noise.
8.2.1.2.1.3 Input Capacitor, CIN ELCO and MLCC

The input capacitor is selected to handle the ripple current of the buck stage. Also, a relatively large capacitance
is used to keep the ripple voltage on the supply line low. This is especially important where the supply line has
high impedance. It is recommended however, that the supply-line impedance be kept as low as possible.
The input-capacitor ripple current can be calculated using Equation 24.
I CAP(RMS) + Ǹƪ ǒIOUT * IIN(AVG)Ǔ

2 I
) RIPPLE
12
2
ƫ D ) I IN(AVG)
2
(1 * D)
(24)
IIN(AVG) is the average input current. This is calculated simply by multiplying the output dc current by the duty
cycle. The ripple current in the input capacitor is 3.3 A. An 1812 MLCC using X5R material has a typical
dissipation factor of 5%. For a 22-μF capacitor at 300 kHz, the ESR is approximately 4 mΩ. Two capacitors are
used in parallel, so the power dissipation in each capacitor is less than 11 mW.
A 470-μF/16-V electrolytic is added to maintain the voltage on the input rail.

TPS40077
8.2.1.2.1.4 Switching MOSFET, QSW

The following key parameters must be met by the selected MOSFET.
• Drain source voltage, Vds, must be able to withstand the input voltage plus spikes that may be on the
switching node. For this design a Vds rating of 30 volts is recommended.
• Drain current, ID, at 25°C, must be greater than that calculated using Equation 25.
I QSW(RMS) + Ǹ V OUT
VIN(MIN)
ƪ 2
I OUT(MAX) )
I RIPPLE
12
ƫ
2
(25)
• With the parameters specified, the calculation of IQSW(RMS) should be greater than 5 A.
• Gate source voltage, Vgs, must be able to withstand the gate voltage from the control IC. For the TPS40077,
this is 11 V.
Once the above boundary parameters are defined, the next step in selecting the switching MOSFET is to select
the key performance parameters. Efficiency is the performance characteristic which drives the other selection
criteria. Target efficiency for this design is 90%. Based on 1.8-V output and 10 A, this equates to a power loss in
the converter of 1.8 W. Based on this figure, a target of 0.6 W dissipated in the switching FET was chosen.
Equation 26 through Equation 29 can be used to calculate the power loss, PQSW, in the switching MOSFET.
P QSW + PCON ) PSW ) PGATE (26)
P CON + RDS(on)
2
I QSW(RMS) + R DS(on)
V OUT
VIN
ƪ 2
I out )
I RIPPLE
12
ƫ
2
(27)
ȱǒI ) IRIPPLEǓ ǒQ ) Q Ǔ ȳ
ȧ OUT 2 gs1 gd
Q OSS(SW) ) Q OSS(SR)ȧ
P SW + VIN fS ȧ ) ȧ
ȧ Ig 12
ȧ
Ȳ ȴ (28)
P GATE + Q g(TOT) Vg f SW
(29)
where
PCON = conduction losses
PSW = switching losses
PGATE = gate-drive losses
Qgd = drain-source charge or Miller charge
Qgs1 = gate-source post-threshold charge
Ig = gate-drive current
QOSS(SW) = switching MOSFET output charge
QOSS(SR) = synchronous MOSFET output charge
Qg(TOT) = total gate charge from zero volts to the gate voltage
Vg = gate voltage
If the total estimated loss is split evenly between conduction and switching losses, Equation 27 and Equation 28
yield preliminary values for RDS(on) and (Qgs1 + Qgd). Note output losses due to QOSS and gate losses have been
ignored here. Once a MOSFET is selected, these parameters can be added.
The switching MOSFET for this design should have an RDS(on) of less than 8 mΩ. The sum of Qgd and Qgs should
be approximately 4 nC.

TPS40077
It may not always be possible to get a MOSFET which meets both these criteria, so a compromise may be
necessary. Also, by selecting different MOSFETs close to these criteria and calculating power loss, the final
selection can be made. It was found that the Si7860DP MOSFET from Vishay semiconductor gave reasonable
results. This device has an RDS(on) of 8 mΩ and a (Qgs1 + Qgd) of 5 nC. The estimated conduction losses are
0.115 W and the switching losses are 0.276 W. This gives a total estimated power loss of 0.391 W versus 0.6 W
for our initial boundary condition. Note this does not include gate losses of approximately 71 mW and output
losses of 20 mW.
8.2.1.2.1.5 Rectifier MOSFET, QSR

Similar criteria to the foregoing can be used for the rectifier MOSFET. There is one significant difference: due to
the body diode conducting, the rectifier MOSFET switches with zero voltage across its drain and source, so
effectively with zero switching losses. However, there are some losses in the body diode. These are minimized
by reducing the delay time between the transition from the switching MOSFET turnoff to rectifier MOSFET turnon
and vice-versa. The TPS40077 incorporates TI's proprietary Predictive Gate Drive circuitry (PGD), which helps
reduce these delays to around 10 ns.
To calculate the losses in the rectifier MOSFET, use Equation 30 through Equation 33.
P QSR + PCON ) PBD ) PGATE (30)
P CON + RDS(on) ƪ1*

V OUT
VIN
* ǒt 1 ) t 2Ǔ fSƫ ƪ 2
I out )
I RIPPLE
12
ƫ
2
(31)
P BD + Vf I OUT ǒt1 ) t 2Ǔ fS (32)
P GATE + Q g(TOTAL) Vg fS
where
• PBD = body diode losses
• t1 = body diode conduction prior to turnon of channel = 12 ns for PGD
• t2 = body diode conduction after turnoff of channel = 12 ns for PGD
• Vf = body diode forward voltage (33)
Estimating the body diode losses based on a forward voltage of 1 V gives 0.072 W. The gate losses are
unknown at this time, so assume 0.1-W gate losses. This leaves 0.428 W for conduction losses. Using this
figure, a target RDS(on) of 5 mΩ was calculated.
The Si7336ADP from Vishay was chosen. Using the parameters from its data sheet, the actual expected power
losses are calculated. Conduction loss is 0.317 W, body diode loss is 0.072 W, and the gate loss is 0.136W. This
totals 0.525 W associated with the rectifier MOSFET.
Two other criteria should be verified before finalizing on the rectifier MOSFET. One is the requirement to ensure
that predictive gate drive functions correctly. The turnoff delay of the Si7336ADP is 97 ns. The minimum turnoff
delay of the Si7860DP is 25 ns. Together these devices meet the 130-ns requirement.
Secondly, the ratio between Cgs and Cgd should be greater than 1. The Si7336ADP easily meets this criterion.
This helps reduce the risk of dv/dt-induced turnon of the rectifier MOSFET. If this is likely to be a problem, a
small resistor may be added in series with the boost capacitor, CBOOST.
8.2.1.2.1.6 Timing Resistor, RT

The timing resistor is calculated using Equation 34.
RT + 1 * 23
f S 17.82 10 *6 (34)
This gives a resistor value of 165 kΩ. The nominal frequency using this resistor is 300 kHz.
8.2.1.2.1.7 Feed-Forward and UVLO Resistor, RKFF

A resistor connected to the KFF pin of the IC feeds into the ramp generator. This resistor provides current into
the ramp generator proportional to the input voltage. The ramp is then adjusted to compensate for different input
voltages. This provides the voltage feed-forward feature of the TPS40077.

TPS40077
The same resistor also sets the undervoltage lockout point. The input start voltage should be used to calculate a
value for RKFF. For this module, the minimum input voltage is 8 V; however, due to tolerances in the IC, a start
voltage of 10% less than the minimum input voltage is selected. The start voltage for RKFF calculation is 7.2 V.
Using Equation 35, RKFF can be selected.
2
R KFF + 0.131 RT V UVLO(on) * 1.61 10*3 V UVLO(on) ) 1.886 V UVLO * 1.363 * 0.02 RT
2
* 4.87 10*5 RT
where
• RKFF and RT are in kΩ (35)
Equation 35 gives an RKFF value of 156 kΩ. The closest lower standard value of 154 kΩ should be selected. This
gives a minimum start voltage of 7.1 V.
8.2.1.2.1.8 Soft-Start Capacitor, CSS

It is good practice to limit the rise time of the output voltage. This helps prevent output overshoot and possible
damage to the load. The selection of the soft-start time is arbitrary. It must meet one condition: it should be
greater than the time constant of the output filter, LOUT and COUT. This time is given by Equation 36.
tSTARTw 2p ǸLOUT COUT (36)
The soft-start time must be greater than 0.23 ms. A time of 0.75 ms was chosen. This time also helps limit the
initial input current during start-up so that the peak current plus the capacitor start-up current is less than the
minimum short-circuit current. The value of CSS can be calculated using Equation 37.
I
C SS + SS t START
VFB (37)
A standard 15-nF MLCC capacitor was chosen. The calculated start time using this capacitor is 0.875 ms.
8.2.1.2.1.9 Short-Circuit Protection, RILIM and CILIM

Short-circuit protection is programmed using the RILIM resistor. Selection of this resistor depends on the RDS(on) of
the switching MOSFET selected and the required short-circuit current trip point, ISCP. The minimum ISCP is limited
by the inductor peak current, the output voltage, the output capacitor, and the soft-start time. Their relationship is
given by Equation 38. A short-circuit current trip point greater than that calculated by Equation 38 should be
used.
COUT V OUT
I SCP w ) I PK
t START (38)
The minimum short-circuit current trip point for this design is 12.25 A. This value is used in Equation 39 to
calculate the minimum RILIM value.
I SCP RDS(on)MAX ) VILIM(Max)
R ILIM +
I LIM(Min)
(39)
RILIM is calculated to be 1.17 kΩ, and a 1.2-kΩ resistor is used to verify that the short-circuit current requirements
are met. The minimum and maximum short-circuit current can be calculated using Equation 40 and Equation 41.
I ILIM(MIN) RILIM(MIN) * VILIM(MAX)
I SCP(MIN) +
R DS(on)MAX
(40)
I ILIM(MAX) RILIM(MAX) * VILIM(MIN)
I SCP(MAX) +
R DS(on)MIN
(41)
where: VILIM(MAX) and VILIM(MIN) are maximum and minimum voltages across the high side FET when it is turned
on, taking into account temperature variations.
The minimum ISCP is 12.25 A, and the maximum is 34 A.

TPS40077
It is also recommended to add a small capacitor, CILIM, across RILIM. The value of this capacitor should be about
half the value calculated in Equation 42.
VOUT 0.2
C ILIM(Max) +
VIN RILIM f S (42)
This equation yields a maximum CILIM as 55 pF. A smaller value of 27 pF is chosen is chosen.
8.2.1.2.1.10 Boost Voltage, CBOOST and DBOOST (Optional)

To be able to drive an N-channel MOSFET in the switch location of a buck converter, a capacitor charge pump
or boost circuit is required. The TPS40077 contains the elements for this boost circuit. The designer must only
add a capacitor, CBOOST, from the switch node of the buck power stage to the BOOST pin of the IC. Selection
of this capacitor is based on the total gate charge of the switching MOSFET and the allowable ripple on the
boost voltage, ΔVBOOST. A ripple of 0.2 V is assumed for this design. Using these two parameters and
Equation 43, the minimum value for CBOOST can be calculated.
Q g(TOTAL)
CBOOST u
DV BOOST (43)
The total gate charge of the switching MOSFET is 23 nC. A minimum CBOOST of 0.092 μF is required. A 0.1 μF
capacitor was chosen. This capacitor must be able to withstand the maximum input voltage plus the maximum
voltage on DBP. This is 13.2 V plus 9.0 V, which is 22.2 V. A 50-V capacitor is used.
To reduce losses in the TPS40077 and to increase the available gate voltage for the switching MOSFET, an
external diode can be added between the DBP pin and the BOOST pin of the IC. A small-signal Schottky diode
should be used here, such as the BAT54.
8.2.1.2.1.11 Closing the Feedback Loop, RZ1, RP1, RPZ2, RSET1, RSET2, CZ2, CP2, and CPZ1
A graphical method is used to select the compensation components. This is a standard feed-forward buck
converter. Its PWM gain is given by Equation 44.
V
K PWM ^ UVLO
1V (44)
The ramp voltage is 1 V at the UVLO voltage. Because of the feed-forward compensation, the programmed
UVLO voltage is the voltage that sets the PWM gain.
The gain of the output LC filter is given by Equation 45.
K LC + 1 ) s ESR COUT
1)s LOUT ) s 2 LOUT COUT
ROUT (45)
The PWM and LC gain is Equation 46.
VUVLO 1 ) s ESR COUT
G c(s) + KPWM KLC
1V 1)s LOUT ) s 2 LOUT COUT
ROUT (46)
To plot this on a Bode plot, the dc gain must be expressed in dB. The dc gain is equal to KPWM. To express this
in dB, take its logarithm and multiply by 20. For this converter, the dc gain is Equation 47.
DCGAIN + 20 logƪ V UVLO

VRAMP
ƫ+ 20 log(7) + 16.9 dB
(47)
Also, the pole and zero frequencies should be calculated. A double pole is associated with the LC and a zero is
associated with the ESR of the output capacitor. The frequencies where these occur can be calculated using
Equation 48 and Equation 49.
f LC_Pole + 1 + 4.3 kHz
2p ǸLOUT COUT (48)
f ESR_Zero + 1 + 2.1 kHz
2p ESR COUT (49)

TPS40077
These are shown in the Bode plot of Figure 29.

30
20
Double Pole
10
ESR Zero
0
Gain − dB
−10
−20 ESR = 0.16 Ω

Slope = –20 dB/Decade
−30
−40
−50
−60
0.1 1 10 100 1k
f − Frequency − kHz
G028
Figure 29. PWM and LC Filter Gain
The next step is to establish the required compensation gain to achieve the desired overall system response.
The target response is to have the crossover frequency between 1/9 and 1/5 times the switching frequency, in
order to have a phase margin greater than 45° and a gain margin greater than 6 dB.
A type-III compensation network, shown in Figure 30, was used for this design. This network gives the best
overall flexibility for compensating the converter.
RP1 CPZ1 TPS40077

VOUT
6 SS
RZ1
CZ2
7 FB
CP2
RPZ2
8 COMP
RSET
S0240-01
Figure 30. Type-III Compensation With the TPS40077
A typical Bode plot for this type of compensation network is shown in Figure 31.

TPS40077
40
30
20 High-Frequency Gain
Gain − dB
10
−10
fZ1 fZ2 fP1 fP2

−20
0.1 1 10 100 1k
f − Frequency − kHz
G029
Figure 31. Type-III Compensation Typical Bode Plot
The high-frequency gain and the break (pole and zero) frequencies are calculated using Equation 50 through
Equation 55.
RZ1 ) RSET
VOUT + VREF
RSET (50)
R Z1 ) R P1
GAIN + R PZ2
R Z1 R P1 (51)
f P1 + 1
2p R P1 C PZ1 (52)
C P2 ) CZ2 1
f P2 + [
2p R PZ2 C P2 C Z2 2p R PZ2 CP2 (53)
f Z1 + 1
2p R Z1 C PZ1 (54)
f Z2 + 1 [ 1
2p ǒR PZ2 ) R P1Ǔ C Z2 2p R PZ2 CZ2
(55)
Looking at the PWM and LC bode plot, there are a few things which must be done to achieve stability.
1. Place two zeros close to the double pole, e.g., fZ1 = fZ2 = 4.3 kHz
2. Place both poles well above the crossover frequency. The crossover frequency was selected as one sixth the
switching frequency, fco1 = 50 kHz, fP1 = 66 kHz
3. Place the second pole at three times fco1. This ensures that the overall system gain falls off quickly to give
good gain margin, fp2 = 150 kHz
4. The high-frequency gain should be sufficient to ensure 0 dB at the required crossover frequency, GAIN = –1
× gain of PWM and LC at the crossover frequency, GAIN = 16.9 dB
Using these values and Equation 50 through Equation 55, the Rs and Cs around the compensation network can
be calculated.
1. Set RZ1 = 51 kΩ
2. Calculate RSET using Equation 50, RSET = 32.4 kΩ
3. Using Equation 54 and fz1 = 4.3 kHz, CPZ1 can be calculated to be 726 pF, CPZ1= 680 pF

TPS40077
4. fP1 and Equation 52 yields RP1 to be a standard value of 3.3 kΩ.

5. The required gain of 16.9 dB and Equation 51 sets the value for RPZ2. RPZ2 = 21.5 kΩ.
6. CZ2 is calculated using Equation 55 and the desired frequency for the second zero, CZ2 = 1.7 nF, or using
standard values, 1.8 nF.
7. Finally, CP2 is calculated using the second pole frequency and Equation 53; CP2 = 47 pF.
Using these values, the simulated results are 57° of phase margin at 54 kHz.
8.2.1.3 Application Curves
100 50 200
90 45 180
80 Phase
40 160
8V
70 12 V 35 140
η − Efficiency − %
16 V
60
30 120
Gain − dB
Phase − °
50
25 100
40
20 80
30
15 Gain 60
20
10 40
10
5 20
0
0 1 2 3 4 5 6 7 8 9 10
0 0
IOUT − Load Current − A 100 1k 10k 100k 1M
G026
Figure 32. Module Efficiency, f − Frequency − Hz

G027
8 V, 12 V, and 16 V In, 0 to 10 A Out Figure 33. Bode Plot Showing 57° Phase Margin
at Crossover Frequency of 54 kHz

TPS40077
8.3 Additional System Examples

+
VDD
12 V R6
– 165 kW
TPS40077PWP R9 C7
2 kW 10 pF
1 KFF ILIM 16
R2 C12 C14
165 kW 22 mF 22 mF
2 RT VDD 15 C8
0.1 mF
C2 0.1 mF C10 0.1 mF
L1
3 LVBP BOOST 14
Pulse
Q1 PG0077.202
Si7840BDP 2 mH
4 PGD HDRV 13
D1
BAT54 +
5 SGND SW 12
C3 22 nF C9 1 mF Q2
6 SS DBP 11 Si7856ADP + + VOUT
C13 1.8 V
4.7 nF C15 C16 C17 C18 10 A
7 FB LDRV 10
R5 C5 47 mF 470 mF 470 mF 0.1 mF
10 kW 5.6 nF
8 COMP PGND 9
–
C4 470 pF PWP
R7 8.66 kW
R3 C6 R8
5.49 kW 4.7 nF 226 W
S0209-01
Figure 34. 300 kHz, 12 V to 1.8 V

TPS40077
Additional System Examples (continued)
+
VDD
12 V R6
– 165 kW
TPS40077PWP R9 C7
2 kW 10 pF
1 KFF ILIM 16
R2 C12 C14
165 kW 22 mF 22 mF
2 RT VDD 15 C8
0.1 mF
C2 0.1 mF C10 0.1 mF
L1
3 LVBP BOOST 14
Pulse
Q1 PG0077.202
Si7840BDP 2 mH
4 PGD HDRV 13
D1
BAT54 +
5 SGND SW 12
C3 22 nF C9 1 mF Q2
6 SS DBP 11 Si7856ADP + + VOUT
C13 1.8 V
4.7 nF C15 C16 C17 C18 10 A
7 FB LDRV 10
R5 C5 47 mF 470 mF 470 mF 0.1 mF
10 kW 5.6 nF
8 COMP PGND 9
–
C4 470 pF PWP
R7 8.66 kW
R3 C6 R8
5.49 kW 4.7 nF 226 W
S0210-01
See Boost Diode.
Figure 35. 300 kHz, 12 V to 1.8 V With Improved High-Side Gate Drive

TPS40077
Additional System Examples (continued)
+
VDD
5V R6
– 47 kW
TPS40077PWP R9 C7
2 kW 10 pF
1 KFF ILIM 16
R2 C12 C14
90.1 kW 22 mF 22 mF
2 RT VDD 15 C8
0.1 mF
C2 0.1 mF C10 0.1 mF
L1
3 LVBP BOOST 14
Pulse
Q1 PG0077.202
Si7860DP 2 mH
4 PGD HDRV 13
D1
BAT54 +
5 SGND SW 12
C3 22 nF
C9 1 mF Q2
R4 330 kW 6 SS DBP 11 Si7860DP + + VOUT
C13 1.2 V
4.7 nF C15 C16 C17 C18 10 A
7 FB LDRV 10
R5 C5 47 mF 470 mF 470 mF 0.1 mF
10 kW 5.6 nF
8 COMP PGND 9
–
C4 470 pF PWP
R7 8.66 kW
R3 C6 R8
12.1 kW 4.7 nF 226 W
Note: Resistor across soft start capacitor.

S0211-01
See Boost Diode.
Figure 36. 500 kHz, 5 V to 1.2 V With Improved High-Side Gate Drive
9 Layout
9.1 Layout Guidelines

The TPS40077 provides separate signal ground (SGND) and power ground (PGND) pins. Take care to properly
separation of the circuit grounds. Each ground must consist of a plane to minimize its impedance, if possible.
The high-power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor
(DBP), and the input capacitor should be connected to PGND plane.
Connect sensitive nodes such as the FB resistor divider and RT to the SGND plane. The SGND plane must only
make a single-point connection to the PGND plane. TI recommends that the SGND pin be tied to the copper
area for the thermal pad underneath the chip. Tie the PGND to the thermal-pad copper area as well, and make
the connection to the power circuit ground from the PGND pin. Reference the output voltage divider to the SGND
pin.
Component placement must ensure that bypass capacitors (LVPB and DBP) are located as close as possible to
their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located
near high-dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW). Failure to follow careful layout
practices results in suboptimal operation. More detailed information can be found in the TPS40077EVM user's
guide (SLVU192).

TPS40077
10 Device and Documentation Support
10.1 Device Support

10.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
10.2 Documentation Support

10.2.1 Related Documentation
For related documentation see the following:
• PowerPAD Thermally Enhanced Package, SLMA002
• TPS40190 Low Pin Count Synchronous Buck Controller, SLUS658
• TPS40100 Midrange Input Synchronous Buck Controller With Advanced Sequencing and Output Margining,
SLUS601
• TPS40075 Midrange Input Synchronous Buck Controller With Voltage Feed-Forward, SLUS676
• TPS40057 Wide-Input Synchronous Buck Controller, SLUS593
• Using the TPS40077EVM 12-V Input, 1.8-V Output, 10-A Synchronous Buck Converter, SLVU192
10.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
10.5 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
10.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
10.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

TPS40077
11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 13-Aug-2021
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TPS40077PWP ACTIVE HTSSOP PWP 16 90 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 40077
TPS40077PWPR ACTIVE HTSSOP PWP 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 40077
TPS40077PWPRG4 ACTIVE HTSSOP PWP 16 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 40077
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 13-Aug-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS40077PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Feb-2019
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS40077PWPR HTSSOP PWP 16 2000 350.0 350.0 43.0
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0016C SCALE 2.500
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
6.6 C
TYP
A 6.2
PIN 1 INDEX 0.1 C
AREA 14X 0.65 SEATING
16 PLANE
1
2X
5.1
4.55
4.9
NOTE 3
8
9
0.30
4.5 16X
B 0.19
4.3
0.1 C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5 4X (0.3)
8 9
2X 0.23 MAX
NOTE 5
2.31 17
0.25
1.75
GAGE PLANE 1.2 MAX
0.75 0.15
1 16 0 -8 0.50 0.05
DETAIL A
A 20
THERMAL 2.46 TYPICAL

PAD 1.75
4224559/B 01/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016C TM
(3.4)
NOTE 9
(2.46)
16X (1.5)
SYMM METAL COVERED
BY SOLDER MASK
1
16X (0.45) 16 (1.2) TYP
(R0.05) TYP
SYMM 17 (2.31)
(5)
(0.6) NOTE 9
14X (0.65)
( 0.2) TYP
VIA 8 9
SOLDER MASK (1) TYP

DEFINED PAD SEE DETAILS
(5.8)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING
EXPOSED METAL EXPOSED METAL
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
15.000
4224559/B 01/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016C TM
(2.46)
BASED ON
16X (1.5) METAL COVERED
0.125 THICK
STENCIL BY SOLDER MASK
1
16X (0.45) 16
(R0.05) TYP
(2.31)
SYMM 17 BASED ON
0.125 THICK
STENCIL
14X (0.65)
8 9
SYMM SEE TABLE FOR

DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.8) THICKNESSES
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.75 X 2.58
0.125 2.46 X 2.31 (SHOWN)
0.15 2.25 X 2.11
0.175 2.08 X 1.95
4224559/B 01/2019
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated

TPS40077 4.5-V To 28-V Input, Voltage Mode, Synchronous Buck Controller With Voltage Feed Forward

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TPS40077 4.5-V to 28-V Input, Voltage Mode, Synchronous Buck Controller

Simplified Application Diagram

Changes from Revision D (April 2009) to Revision E Page

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5 Pin Configuration and Functions

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Pin Functions (continued)

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6.2 ESD Ratings

6.3 Recommended Operating Conditions

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6.4 Electrical Characteristics

(1) Ensured by design. Not production tested.

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Electrical Characteristics (continued)

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6.5 Typical Characteristics

VDBP − DBP Voltage − V

VDROP − Bootstrap Diode Voltage Drop − V

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Typical Characteristics (continued)

fSW − Switching Frequency − kHz

Figure 7. Feedback Regulation Voltage Figure 8. Switching Frequency vs Input Voltage

VUVLO − Undervoltage Lockout Threshold − V

Figure 9. Maximum Duty Cycle Figure 10. Undervoltage Lockout

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Typical Characteristics (continued)

VOUT − Output Voltage − V

VUVLO − Programmable UVLO Threshold − V

VUVLO − Programmable UVLO Threshold − V

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Typical Characteristics (continued)

VDBP − Driver Bypass Voltage − V

Figure 21. Input Voltage vs Low-Voltage Bypass Voltage

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7.2 Functional Block Diagram

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7.3 Feature Description

7.3.2 Slew Rate Limit On VDD

Figure 22. Limiting the Slew Rate

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Feature Description (continued)

7.3.4 Loop Compensation

KPWM ≅ VUVLO(on) (4)

7.3.5 Shutdown and Sequencing

Figure 23. TPS40077 Shutdown

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Feature Description (continued)

6 SS PGD 4 6 SS PGD 4 To System Power Good

Figure 24. TPS40077 Sequencing