Islamic University of Technology (IUT)

Organisation of Islamic Cooperation (OIC)

Department of Electrical and Electronic Engineering
Electronics Laboratory

Name:………………………………….……Student No ……..……..…… Section….... Group……

Course: EEE 4604 (Measurement and Instrumentation Lab)

Experiment no.: 04

Name of the experiment: To study the response of a Sample-and-Hold (S/H) Circuit.

Objective:

Sample-and-Hold (S/H) circuit is used to sample an analog input voltage for a very short period (several
milliseconds to microseconds) and to hold on its last sampled value until the input is sampled again.
The period may be from a few milliseconds to several seconds. The sample-and-hold ( S/H ) circuit has
a third terminal for the logic S/H command in addition to the terminal for Vs and Vo .This command is
issued to the circuit in the form of a pulse.

The block diagram and the idealized response of the S/H circuit are show below:
The circuit has two mode of operation depending on the logic level of the S/H command. Upon
receiving the S/H pulse circuit swing Vo toward Vin and then forces Vo to follow or track Vin for the
reminder of the pulse. This is called the track mode. After the S/H pulse is removed, the circuit holds
Vo at the value of Vin at the instant of pulse deactivation. This is called the hold mode.

A periodic array S/H pulse train allows the entire analog signal to be sampled and a discrete version of
analog signal to be produced at the output of the S/H circuit. For the replication of the analog signal
without distortion or interference known as aliasing, the sampling frequency fs of the S/H pulse train
should be twice or more than the bandwidth fm of the input analog signal.

S/H circuits are used in the following applications:

(i) In connection with A/D converts (analog signal de-multiplexers), especially the successive
approximation type, to hold the signal constant while the A/D conversion is taking place.
(ii) As D/A convert output deglitches in CRT displays.
(iii) Applications requiring fast acquisition-very low drop rate S/h circuit.

2. Equipments and required components:

a) Trainer/project board.
b) Function generator.
c) Oscilloscope.
d) Resistor 1 kΩ (2 pieces), 100 KΩ (2 pieces).
e) Potentiometer 10 KΩ (2 pieces).
f) Diodes ( 2 pieces )
g) 555 Timer.
h) Capacitor 0.01 µF 0.047 µF ( 2 pieces )
i) 741-OpAmp chip ( Pieces )
j) MOSFET IFR 540.

3. Experiment setup:

In experiment the response of two basic S/H circuit configuration will be studied and evaluated. These
two circuit are sketched on the following page. The 555 Timer used in the astable mode produced the
sampling pulse train to the gate of the MOSFET which act as a switch. During the sample MOSFET
switch is turned on and the holding capacitor CH charges up to the level of the analog input voltage. At
the end of this short sampling pulse, The MOSFET is switched off. This isolates the holding capacitor
CH and the voltage across CH and therefore Vo will essentially remain at the value of the input voltage
sampled at the trailing edge of the sampling pulse. The acquisition time tac, of a S/H circuit is the time
required for the holding capacitor to charge up to a level close to the input voltage during the sampling
time. For the circuit configuration, there are three principal factors that will control the acquisition time.
a) The RC time constant resulting from the resistance rds (on) of the MOSFET switch and
the holding capacitor CH .
b) Maximum output current which can be sourced and sunk by the first Op-Amp in the
S/H circuit
c) The slew rate capability of the Op-Amp.
For the circuit chosen in the experiment, there is an added advantage that in this circuit the acquisition
time will not be limited by the rds(on) of the MOSFET but by the maximum output current capability of
the first Op-Amp does not provide high input impedance. The second Op-Amp used in the circuit
isolates CH from the load to prevent rapid discharge. Due to the high input impedance of this second
Op-Amp, the value charged by the holding capacitor cannot discharge and its held constant during the
time MOSFET is off. The use of resistances in the feedback path of the second circuit are two limit the
current flow and provide gain if required.

-Vcc(-15V)
-Vcc(-15V)

U1
U1

4
1
5
5V

4
1
5
Q1 2
2 IRF540 6
6 3
3

7
R3 741

7
U1 741
1k
4
8

+Vcc(+15V)
R
VCC

+Vcc(+15V)
RV3
50%

100k

DC
7

1k

3
Q
28%

100k

KABIR_555_IUT

2
TR

TH
6
GND

CV
1

C1 C2
1nF 1nF

Figure 1: Basic S/H circuit configuration.

 100k

-Vcc(-15V)
-Vcc(-15V)

U1
U1

4
1
5
5V

4
1
5
Q1 2
2 IRF540 6
100k 6 3
3

7
R3 741

7
U1 741
1k

4
8
+Vcc(+15V)

R
VCC
+Vcc(+15V)
50% RV3
100k

DC
7

1k

3
Q
28%

100k

KABIR_555_IUT

2
TR

TH
6
GND

CV
1

C1 C2
1nF 1nF

Figure 2: Basic S/H circuit configuration with gain.

4. Produce:

1. Make the connection of 555 timers as shown in the figure 1.

2. Observe the output wave shape at pin 3 of 555 timers and vary the duty cycle with the tuning of
potentiometer. Chose a sampling frequency of 2 KHz.
3. Complete connection for the whole circuit diagram of figure 1.
4. Apply a sinusoidal voltage of 5 Vp-p at the non-inverting input pin 3 of first Op-Amp of Figure
1. Use a charging capacitor value off o.1 µF in the circuit.
5. Observe the input sinusoidal signal on the oscilloscope at CH1 and output at pin 6 of the second
Op-Amp on CH2, respectively. Choose an operating frequency of 1 KHz, 500 Hz and 100 Hz
for the input signal using the function generator and observe their effect of output signal.
Comment on the difference.
6. Now set the operating frequency of the input signal at 100 Hz vary duty cycle of the 555 Timer
output and observe their effect on the acquisition time and hold time of the output signal.
7. Now change the holding capacitor value to 0.033 µF and 0.047 µF and observe their effect on
the output signal comment on your observation.
8. Now construct the circuit of Figure 2. Use 100 KΩ resistances in the feedback path. Repeat
steps 1-7 above for the response of this circuit does the gain obtained from the circuit make the
output response better in terms of acquisition time and hold time?

Report:

1. What is the function of MOSFET in this experiment?

2. Describe the sampling and holding situations.
3. Discuss on the results obtained and any discrepancies among the experimental and calculated
outputs.