MM74HC4046 CMOS Phase Lock Loop

February 1984
Revised October 2003

MM74HC4046
CMOS Phase Lock Loop
General Description them. This comparator is more susceptible to noise throw-
ing the loop out of lock, but is less likely to lock onto har-
The MM74HC4046 is a low power phase lock loop utilizing monics than the other two comparators.
advanced silicon-gate CMOS technology to obtain high fre-
In a typical application any one of the three comparators
quency operation both in the phase comparator and VCO
feed an external filter network which in turn feeds the VCO
sections. This device contains a low power linear voltage
input. This input is a very high impedance CMOS input
controlled oscillator (VCO), a source follower, and three
which also drives the source follower. The VCO’s operating
phase comparators. The three phase comparators have a
frequency is set by three external components connected
common signal input and a common comparator input. The
to the C1A, C1B, R1 and R2 pins. An inhibit pin is provided
signal input has a self biasing amplifier allowing signals to
to disable the VCO and the source follower, providing a
be either capacitively coupled to the phase comparators
method of putting the IC in a low power state.
with a small signal or directly coupled with standard input
logic levels. This device is similar to the CD4046 except The source follower is a MOS transistor whose gate is con-
that the Zener diode of the metal gate CMOS device has nected to the VCO input and whose drain connects the
been replaced with a third phase comparator. Demodulator output. This output normally is used by tying
a resistor from pin 10 to ground, and provides a means of
Phase Comparator I is an exclusive OR (XOR) gate. It pro-
looking at the VCO input without loading down modifying
vides a digital error signal that maintains a 90 phase shift
the characteristics of the PLL filter.
between the VCO’s center frequency and the input signal
(50% duty cycle input waveforms). This phase detector is
more susceptible to locking onto harmonics of the input fre- Features
quency than phase comparator I, but provides better noise ■ Low dynamic power consumption: (VCC = 4.5V)
rejection.
■ Maximum VCO operating frequency:
Phase comparator III is an SR flip-flop gate. It can be used 12 MHz (VCC = 4.5V)
to provide the phase comparator functions and is similar to
the first comparator in performance. ■ Fast comparator response time (VCC = 4.5V)
Phase comparator II is an edge sensitive digital sequential Comparator I: 25 ns
network. Two signal outputs are provided, a comparator Comparator II: 30 ns
output and a phase pulse output. The comparator output is Comparator III: 25 ns
a 3-STATE output that provides a signal that locks the VCO
■ VCO has high linearity and high temperature stability
output signal to the input signal with 0 phase shift between

Ordering Code:
Order Number Package Number Package Description
MM74HC4046M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC4046SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4046MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC4046N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

© 2003 Fairchild Semiconductor Corporation DS005352 www.fairchildsemi.com

MM74HC4046
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP

Block Diagram

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 MM74HC4046
Absolute Maximum Ratings(Note 1) Recommended Operating
(Note 2) Conditions
Supply Voltage (VCC) −0.5 to + 7.0V Min Max Units
DC Input Voltage (VIN) −1.5 to VCC +1.5V Supply Voltage (VCC) 2 6 V
DC Output Voltage (VOUT) −0.5 to VCC + 0.5V DC Input or Output Voltage
Clamp Diode Current (IIK, IOK) ±20 mA (VIN, VOUT) 0 VCC V
DC Output Current per pin (IOUT) ±25 mA Operating Temperature Range (TA) −40 +85 °C
DC VCC or GND Current, per pin (ICC) ±50 mA Input Rise or Fall Times
Storage Temperature Range (TSTG) −65°C +150°C (tr, tf) VCC = 2.0V 1000 ns
Power Dissipation (PD) VCC = 4.5V 500 ns
(Note 3) 600 mW VCC = 6.0V 400 ns
S.O. Package only 500 mW Note 1: Maximum Ratings are those values beyond which damage to the
device may occur.
Lead Temperature (TL)
Note 2: Unless otherwise specified all voltages are referenced to ground.
(Soldering 10 seconds) 260°C
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics (Note 4)

TA = 25°C TA = −40 to 85°C TA = −55 to 125°C

Symbol Parameter Conditions VCC Units
Typ Guaranteed Limits
VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V
Input Voltage 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum HIGH Level VIN = VIH or VIL
Output Voltage |IOUT | ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VIN = VIH or VIL
|IOUT | ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|IOUT | ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum Low Level VIN = VIHor VIL
Output Voltage |IOUT | ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VIN = VIH or VIL
|IOUT | ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
|IOUT | ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maximum Input Current (Pins 3,5,9) VIN = VCCor GND 6.0V ±0.1 ±1.0 ±1.0 µA
IIN Maximum Input Current (Pin 14) VIN = VCC or GND 6.0V 20 50 80 100 µA
IOZ Maximum 3-STATE Output VOUT = VCC or GND 6.0V ±0.5 ±5.0 ±10 µA
Leakage Current (Pin 13)
ICC Maximum Quiescent VIN = VCC or GND 6.0V 30 80 130 160 µA
Supply Current IOUT = 0 µA
VIN = VCC or GND 6.0V 600 1500 2400 3000 µA
Pin 14 Open
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

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MM74HC4046
AC Electrical Characteristics VCC = 2.0 to 6.0V, CL = 50 pF, tr = tr = 6 ns (unless otherwise specified.)
TA=25C TA = −40 to 85°C TA = −55 to 125°C
Symbol Parameters Conditions VCC Units
Typ Guaranteed Limits
AC Coupled C (series) = 100 pF 2.0V 25 100 150 200 mV
Input Sensitivity, fIN = 500 kHz 4.5V 50 150 200 250 mV
Signal In 6.0V 135 250 300 350 mV
tr , tf Maximum Output 2.0V 30 75 95 110 ns
Rise and Fall Time 4.5V 9 15 19 22 ns
6.0V 8 12 15 19 ns
CIN Maximum Input Capacitance 7 pF
Phase Comparator I
tPHL, tPLH Maximum 2.0V 65 200 250 300 ns
Propagation Delay 4.5V 25 40 50 60 ns
6.0V 20 34 43 51 ns
Phase Comparator II
tPZL Maximum 3-STATE 2.0V 75 225 280 340 ns
Enable Time 4.5V 25 45 56 68 ns
6.0V 22 38 48 57 ns
tPZH, tPHZ Maximum 3-STATE 2.0V 88 240 300 360 ns
Enable Time 4.5V 30 48 60 72 ns
6.0V 25 41 51 61 ns
tPLZ Maximum 3-STATE 2.0V 90 240 300 360 ns
Disable Time 4.5V 32 48 60 72 ns
6.0V 28 41 51 61 ns
tPHL, tPLH Maximum 2.0V 100 250 310 380 ns
Propagation Delay 4.5V 34 50 63 75 ns
HIGH-to-LOW to Phase Pulses 6.0V 27 43 53 64 ns
Phase Comparator III
tPHL, tPLH Maximum 2.0V 75 200 250 300 ns
Propagation Delay 4.5V 25 40 50 60 ns
6.0V 22 34 43 51 ns
CPD Maximum Power All Comparators 130 pF
Dissipation Capacitance VIN = VCC and GND

Voltage Controlled Oscillator (Specified to operate from VCC= 3.0V to 6.0V)

fMAX Maximum C1 = 50 pF
Operating R1 = 100Ω 4.5V 7 4.5 MHz
Frequency R2 = ∞ 6.0V 11 7 MHz
VCOin = VCC
C1 = 0 pF 4.5V 12 MHz
R1 = 100Ω 6.0 14 MHz
VCOin = VCC
Duty Cycle 50 %
Demodulator Output
Offset Voltage Rs = 20 kΩ 4.5V 0.75 1.3 1.5 1.6 V
VCOin–Vdem
Offset Rs = 20 kΩ 4.5V
Variation VCOin = 1.75V 0.65 V
2.25V 0.1
2.75V 0.75

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 MM74HC4046
Typical Performance Characteristics

Typical Center Frequency Typical Center Frequency

vs R1, C1 VCC = 4.5V vs R1, C1 VCC = 6V

Typical Offset Frequency Typical Offset Frequency

vs R2, C1 VCC = 4.5V vs R2, C1 VCC = 6V

Typical VCO Power Dissipation Typical VCO Power

@ Center Frequency vs R1 Dissipation @ fMIN vs R2

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MM74HC4046
Typical Performance Characteristics (Continued)
VCOin vs fout VCC = 4.5V VCOin vs fout VCC = 4.5V

VCOout vs VCOout vs
Temperature VCC = 4.5V Temperature VCC = 6V

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 MM74HC4046
Typical Performance Characteristics (Continued)

HC4046 Typical Source Follower Typical fMAX/fMIN vs R2/R1

Power Dissipation vs RS VCC = 4.5V & 6V fMAX/fMIN

Typical VCO Linaearity vs R1 & C1 Typical VCO Linearity vs R1 & C1

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MM74HC4046
Detailed Circuit Description
VOLTAGE CONTROLLED OSCILLATOR/SOURCE
FOLLOWER
The VCO requires two or three external components to the value of R2 the lock range of the PLL is offset above
operate. These are R1, R2, C1. Resistor R1 and capacitor 0Hz and the gain (Hz/Volt) does not change. In general,
C1 are selected to determine the center frequency of the when offset is desired, R2 and C1 should be chosen first,
VCO. R1 controls the lock range. As R1’s resistance and then R1 should be chosen to obtain the proper center
decreases the range of fMIN to fMAX increases. Thus the frequency.
VCO’s gain increases. As C1 is changed the offset (if used) Internally the resistors set a current in a current mirror as
of R2, and the center frequency is changed. (See typical shown in Figure 1. The mirrored current drives one side of
performance curves) R2 can be used to set the offset fre- the capacitor once the capacitor charges up to the thresh-
quency with 0V at VCO input. If R2 is omitted the VCO old of the schmitt trigger the oscillator logic flips the capaci-
range is from 0Hz. As R2 is decreased the offset frequency tor over and causes the mirror to charge the opposite side
is increased. The effect of R2 is shown in the design infor- of the capacitor. The output from the internal logic is then
mation table and typical performance curves. By increasing taken to pin 4.

VCO WITHOUT OFFSET VCO WITH OFFSET

R2 = ∞

Comparator I Comparator II & III

R2= ∞ R2≠∞ R2 = ∞ R2≠∞
•Given: f0 •Given: f0 and fL •Given: fMAX •Given: fMIN and fMAX
•Use f0 with curve titled •Calculate fMIN from the •Calculate f0 from the •Use fMIN with curve titled
center frequency vs R1, C equation fMIN = fo − fL equation fo = fMAX/2 offset frequency vs R2,
to determine R1 and C1 •Use fMIN with curve titled •Use f0 with curve titled C to determine R2 and C1
offset frequency vs R2, C center frequency vs R1, C •Calculate fMAX/fMIN
to determine R2 and C1 to determine R1 and C1 •Use fMAX/fMIN with curve
•Calculate fMAX/fMIN from titled fMAX/fMIN vs R2/R1
the equation fMAX/fMIN = to determine ratio R2/R1
fo + fL/fo − fL to obtain R1
•Use fMAX/fMIN with curve
titled fMAX/fMIN vs R2/R1
to determine ratio R2/R1
to obtain R1
FIGURE 1.

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 MM74HC4046
Detailed Circuit Description (Continued)

FIGURE 2. Logic Diagram for VCO

The input to the VCO is a very high impedance CMOS not being used. A logic high on inhibit disables the VCO
input and so it will not load down the loop filter, easing the and source follower.
filters design. In order to make signals at the VCO input The output of the VCO is a standard high speed CMOS
accessible without degrading the loop performance a output with an equivalent LSTTL fanout of 10. The VCO
source follower transistor is provided. This transistor can output is approximately a square wave. This output can
be used by connecting a resistor to ground and its drain either directly feed the comparator input of the phase com-
output will follow the VCO input signal. parators or feed external prescalers (counters) to enable
An inhibit signal is provided to allow disabling of the VCO frequency synthesis.
and the source follower. This is useful if the internal VCO is

PHASE COMPARATORS
All three phase comparators share two inputs, Signal In is a standard digital input. Both input structures are shown
and Comparator In. The Signal In has a special DC bias in Figure 3.
network that enables AC coupling of input signals. If the The outputs of these comparators are essentially standard
signals are not AC coupled then this input requires logic 74HC voltage outputs. (Comparator II is 3-STATE.)
levels the same as standard 74HC. The Comparator input

FIGURE 3. Logic Diagram for Phase Comparator I and the common input circuit for all three comparators

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MM74HC4046
Detailed Circuit Description (Continued)

FIGURE 4. Typical Phase Comparator I. Waveforms

Thus in normal operation VCC and ground voltage levels quency is fMAX then the VCO input must be VCC and the
are fed to the loop filter. This differs from some phase phase detector inputs must be 180° out of phase.
detectors which supply a current output to the loop filter The XOR is more susceptible to locking onto harmonics of
and this should be considered in the design. (The CD4046 the signal input than the digital phase detector II. This can
also provides a voltage.) be seen by noticing that a signal 2 times the VCO fre-
Figure 5 shows the state tables for all three comparators. quency results in the same output duty cycle as a signal
equal the VCO frequency. The difference is that the output
PHASE COMPARATOR I frequency of the 2f example is twice that of the other exam-
This comparator is a simple XOR gate similar to the ple. The loop filter and the VCO range should be designed
74HC86, and its operation is similar to an overdriven bal- to prevent locking on to harmonics.
anced modulator. To maximize lock range the input fre-
quencies must have a 50% duty cycle. Typical input and PHASE COMPARATOR II
output waveforms are shown in Figure 4. The output of the This detector is a digital memory network. It consists of four
phase detector feeds the loop filter which averages the out- flip-flops and some gating logic, a three state output and a
put voltage. The frequency range upon which the PLL will phase pulse output as shown in Figure 6. This comparator
lock onto if initially out of lock is defined as the capture acts only on the positive edges of the input signals and is
range. The capture range for phase detector I is dependent thus independent of signal duty cycle.
on the loop filter employed. The capture range can be as Phase comparator II operates in such a way as to force the
large as the lock range which is equal to the VCO fre- PLL into lock with 0 phase difference between the VCO
quency range. output and the signal input positive waveform edges. Fig-
To see how the detector operates refer to Figure 4. When ure 7 shows some typical loop waveforms. First assume
two square wave inputs are applied to this comparator, an that the signal input phase is leading the comparator input.
output waveform whose duty cycle is dependent on the This means that the VCO’s frequency must be increased to
phase difference between the two signals results. As the bring its leading edge into proper phase alignment. Thus
phase difference increases the output duty cycle increases the phase detector II output is set high. This will cause the
and the voltage after the loop filter increases. Thus in order loop filter to charge up the VCO input increasing the VCO
to achieve lock, when the PLL input frequency increases frequency. Once the leading edge of the comparator input
the VCO input voltage must increase and the phase differ- is detected the output goes 3-STATE holding the VCO
ence between comparator in and signal in will increase. At input at the loop filter voltage. If the VCO still lags the sig-
an input frequency equal fMIN, the VCO input is at 0V and nal then the phase detector will again charge up to VCO
this requires the phase detector output to be ground hence input for the time between the leading edges of both wave-
the two input signals must be in phase. When the input fre- forms.

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 MM74HC4046
Detailed Circuit Description (Continued)
Phase Comparator State Diagrams

FIGURE 5. PLL State Tables

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MM74HC4046
Detailed Circuit Description (Continued)

FIGURE 6. Logic Diagram for Phase Comparator II

FIGURE 7. Typical Phase Comparator II Output Waveforms

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 MM74HC4046
Detailed Circuit Description (Continued)
If the VCO leads the signal then when the leading edge of Phase comparator II is more susceptible to noise causing
the VCO is seen the output of the phase comparator goes the phase lock loop to unlock. If a noise pulse is seen on
LOW. This discharges the loop filter until the leading edge the signal input, the comparator treats it as another positive
of the signal is detected at which time the output 3-STATE edge of the signal and will cause the output to go HIGH
itself again. This has the effect of slowing down the VCO to until the VCO leading edge is seen, potentially for a whole
again make the rising edges of both waveform coincident. signal input period. This would cause the VCO to speed up
When the PLL is out of lock the VCO will be running either during that time. When using the phase comparator I the
slower or faster than the signal input. If it is running slower output of that phase detector would be disturbed for only
the phase detector will see more signal rising edges and so the short duration of the noise spike and would cause less
the output of the phase comparator will be HIGH a majority upset.
of the time, raising the VCO’s frequency. Conversely, if the
VCO is running faster than the signal the output of the PHASE COMPARATOR III
detector will be LOW most of the time and the VCO’s out- This comparator is a simple S-R Flip-Flop which can func-
put frequency will be decreased. tion as a phase comparator Figure 8. It has some similar
As one can see when the PLL is locked the output of phase characteristics to the edge sensitive comparator. To see
comparator II will be almost always 3-STATE except for how this detector works assume input pulses are applied to
minor corrections at the leading edge of the waveforms. the signal and comparator inputs as shown in Figure 9.
When the detector is 3-STATE the phase pulse output is When the signal input leads the comparator input the flop is
HIGH. This output can be used to determine when the PLL set. This will charge up the loop filter and cause the VCO to
is in the locked condition. speed up, bringing the comparator into phase with the sig-
nal input. When using short pulses as input this comparator
This detector has several interesting characteristics. Over
behaves very similar to the second comparator. But one
the entire VCO frequency range there is no phase differ-
can see that if the signal input is a long pulse, the output of
ence between the comparator input and the signal input.
the comparator will be forced to a one no matter how many
The lock range of the PLL is the same as the capture
comparator input pulses are received. Also if the VCO input
range. Minimal power is consumed in the loop filter since in
is a square wave (as it is) and the signal input is pulse then
lock the detector output is a high impedance. Also when no
the VCO will force the comparator output LOW much of the
signal is present the detector will see only VCO leading
time. Therefore it is ideal to condition the signal and com-
edges, and so the comparator output will stay LOW forcing
parator input to short pulses. This is most easily done by
the VCO to fMIN operating frequency.
using a series capacitor.

FIGURE 8. Phase Comparator III Logic Diagram

FIGURE 9. Typical Waveforms for Phase Comparator III

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MM74HC4046
Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A

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 MM74HC4046
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D

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MM74HC4046
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16

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 MM74HC4046 CMOS Phase Lock Loop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N16E

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Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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