Department of Computer Science & Engineering

Course Title: Digital Logic Design Lab

Course Code: CSE-206

Submitted to:
KAZI MAHMUDUL HASSAN
Assistant Professor

Dept. of Computer Science & Engineering

Jatiya Kabi Kazi Nazrul Islam University

Submitted by:
Name: Md.Ismail Hossen
Roll: 19102002
Reg. NO: 7722
Session: 2018-19
Dept. of Computer Science & Engineering
Jatiya Kabi Kazi Nazrul Islam University

Submission Date: 16.11.2021

 INDEX
S.N. Experiment Name Page
Number

1 n-bit binary to Gray converter 01-02

2 n-bit decimal to BCD converter 03-06

3 Boolean expression to circuit implementation using algebraic 07-10

simplification

4 Truth table to circuit implementation using k-map simplification . 11-12

5 Half adder 13-15

6 Full adder 16-18

7 n-bit parity bit generator 19-22

8 n-bit parity bit checker 23-26

9 Clocked S-R flip-flop (using NAND/NOR gate) 27-28

10 Clocked J-K flip-flop (using NAND/NOR gate) 29-30

11 Clocked D Latch 31-32

12 n-bit asynchronous (up/down) counter triggered with (PGT/NGT) 33

13 n-bit synchronous (up/down) counter triggered with (PGT/NGT) 34-35

14 n-bit binary to decimal decoder 36-38

15 n-bit decimal to binary decoder 39-40

16 N-input multiplexer 41-42

17 1 Line to 8 Line demultiplexer 43-46

Page | 2
Experiment No: 01
Experiment Name: N-Bit Binary to Gray converter.
Objectives:The main objectives is to learn the mechanism how to convert binary number to gray
code.To know how to logic circuit work on it.
Theory:
The logical circuit which converts the binary code to equivalent gray code is known as binary to
gray code converter. An n-bit gray code can be obtained by reflecting an n-1 bit code about an
axis after 2n-1 rows and putting the MSB (Most Significant Bit) of 0 above the axis and the MSB
of 1 below the axis. Reflection of Gray codes is shown below.

The 4 bit binary to gray code conversion table is given below:

Table-1

Page | 1
Binary Numbers is default way to store numbers, but in many applications binary numbers are
difficult to use and a variation of binary numbers is needed.When multiple input conditions are
changing at the same time ,the situation can be misinterpreted and cause an enormous
reaction.Consider when the three bit binary number for 3 changes to 4 ,all three bits must change
state . This is where Gray codes are very useful.
Gray code has property that two successive numbers differ in only one bit because of this
property gray code does the cycling through various states with minimal effort and used in K-
maps, error correction, communication etc

Circuit Diagram Input Output circuit

Discussion:The MSB of the binary will be 0 as the MSB of gray is 0. Now move to the next gray
bit. As it is 1 the previous binary bit will alter i.e it will be 1, thus the second binary bit will be 1.
Next look at the third bit of the gray code.In the circuit diagram I made it in dsch3 software and
input output circuit gives an example for input binary 10110 and the output gray 11101.

Page | 2
Experiment no : 02
Experiment name : n-bit decimal to BCD converter
Objective : The main objectives is to design a decimal to BCD Encoder .To know how to
convert decimal numbers into binary number using logical circuit.
Theory :
When calculations are carried out electronically they will usually be in binary or twos
complementnotation, but the result will very probably need to be displayed in decimal form. A
binary number withits bits representing values of 1, 2, 4, 8, 16 etc. presents problems. It would
be better if a particular number of binary bits could represent the numbers 0 to 9, but this doesn’t
happen in pure binary, a 3 bitbinary number represents the values 0 to 7 and 4 bit represents 0 to
15. What is needed is a system where a group of binary digits can represent the decimal numbers
0-9, and the next group 10-90 etc.
To make this possible, binary codes are used that have ten values, but where each value is
representedby the 1s and 0s of a binary code. These special ‘half way’ codes are called BINARY
CODED DECIMAL or BCD. There are several different BCD codes, but they have a basic
similarity. Each of the ten decimaldigits 0 to 9 is represented by a group of 4 binary bits, but in
codes the binary equivalents of the 10 decimal numbers do not necessarily need to be in a
consecutive order. Any group of 4 bits can represent any decimal value, so long as the
relationship for that particular code is known.
In fact any ten of the 16 available four bit combinations could be used to represent 10
decimalnumbers,and this is where different BCD codes vary. There can be advantages in some
specialist applications inusing some particular variation of BCD. For example it may be useful to
have a BCD code that can be used for calculations, which means having positive and negative
values, similar to the twos complement system, but BCD codes are most often used for the
display of decimal digits. The most commonly encountered version of BCD binary code is the
BCD(8421) code. In this version the numbers 0 to 9 are represented by their pure binary
equivalents, 4 bits per decimal number, in consecutive order.

The process of converting from familiar symbols or numbers to a coded format is called
encoding. This type of encoder has ten inputs--one for each decimal digit-and four outputs
corresponding to the BCD code, as shown. This is a basic 10-line-to-4-line encoder. The
BCD(8421) code is listed in this Table.

Page | 3
Decimal BCD
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001

From this table you can determine the relationship between each BCD bit and the decimal digits
in order to analyze the logic. For instance, the most significant bit(MSB) of the BCD code is
always a 1 for decimal digit8 or 9. An OR expression for bit in terms of the decimal digits can
therefore be written as
= 8+9
Bit is always a 1 for decimal digit 4, 5, 6, or 7 and can be expressed as an OR function as
= 4+5+6+7
Bit is always a 1 for decimal digit 2, 3, 6, or 7 and can be expressed as
= 2+3+6+7
Finally,LSB is always a 1 for decimal digit 1, 3, 5, 7, or 9. The expression for is
= 1+3+5+7+9
Now let's implement the logic circuitry required for encoding each decimal digit to a BCD
code by using the logic expressions just developed. It is simply a matter of ORing the
appropriate decimal digit input lines to form each BCD output.

Page | 4
The basic encoder logic resulting from these expressions is shown in Figure :

When a HIGH appears on one of the decimal digit input lines, the appropriate levels occur on the
four BCD output lines. For instance, if input line 9 is HIGH, assuming all other input lines are
LOW, this condition will produce a HIGH on outputs and LOWs on outputs and , which is the
BCD code, 1001 for decimal 9 as shown below:

Page | 5
Limitations With Decimal To BCD Encoder
A decimal to bcd encoder has limitations similar to octal to binary encoder.
1. For 10 bits input, there can be 210 possible combinations, out of which only 10 are used using
4 output lines.
2. The discrepancy of 0 output due to all inputs being 0 or D0 being 0 is resolved by using
additional input known as Enable
3. Only one input can be active at any given time.

Discussion: In the circuit diagram I made it in dsch3 software and input output circuit.Use
decimal number as input and binary number as output .We have successfully run this circuit.

Page | 6
Experiment no : 03
Experiment Name: Boolean expression to circuit implementation using algebraic simplification.
Objective : The main objectives is to simplify a given Boolean expression using algebraic
simplification and design a circuit.To know how to use simplification law to simplify a equation
and design a simplified circuit.
Theory :
Boolean algebra, a logic algebra, allows the rules used in the algebra of numbers to be applied to
logic. It formalizes the rules of logic. Boolean algebra is used to simplify Boolean expressions
which represent combinational logic circuits. It reduces the original expression to an equivalent
expression that has fewer terms which means that less logic gates are needed to implement the
combinational logic circuit.
Laws of Boolean Algebra:
Boolean Algebra Laws are used to simplify boolean expressions :
Basic Boolean Laws
1. Idempotent Law
A*A=A
A+A=A
2. Associative Law
(A * B) * C = A * (B * C)
(A + B) + C = A + (B + C)
3. Commutative Law
A*B=B*A
A+B=B+A
4. Distributive Law
A * (B + C) = A * B + A * C
A + (B * C) = (A + B) * (A + C)
5. Identity Law
A*0=0 A*1=A
A+1=1 A+0=A
6. Complement Law

Page | 7
 A*=0
A+=1
7. Involution Law
o=A
8. DeMorgan's Law
o=+
o=*
Redundancy Laws
9. Absorption
A + (A * B) = A
A * (A + B) = A
10.
(A * B) + (A * ) = A
(A + B) * (A + ) = A
11.
A + ( * B) = A + B
A * ( + B) = A * B

Boolean expression for simplification :

Z = ABC+AB
= AB(C+1)
=AB*1
=AB

Page | 8
Truth table:
A B C ABC+AB AB
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 0 1 0 0
1 1 0 1 1
1 1 1 1 1

With simplification :

AB

Page | 9
Without simplification :

ABC+AB

Discussion: In the circuit diagram I made it in dsch3 software and input output circuit.We have used the
simplification law to simplify a logical equationand check the output with the truth table.We have
successfully run this circuit.

Page | 10
Experiment No:04

Experiment Name : Truth table to circuit implementation using K-map simplification.

Objectives :The main objectives is to design a circuit using k map from truth table.To know how
to loop in a K-map.

Theory :
The Karnaugh map (KM or K-map) is a method of simplifying Boolean algebra expressions.The
Karnaugh map reduces the need for extensive calculations by taking advantage of humans'
pattern-recognition capability.It also permits the rapid identification and elimination of
potential race conditions.
The required Boolean results are transferred from a truth table onto a two-dimensional grid
where, in Karnaugh maps, the cells are ordered in Gray code,[6][4] and each cell position
represents one combination of input conditions, while each cell value represents the
corresponding output value.
Optimal groups of 1s or 0s are identified, which represent the terms of a canonical form of the
logic in the original truth table.These terms can be used to write a minimal Boolean expression
representing the required logic.
Karnaugh maps are used to simplify real-world logic requirements so that they can be implement
edusing a minimum number of physical logic gates. A sum-of-products expression can always be
implemented using AND gates feeding into an OR gate, and a product-of-sums expression leads
to OR gates feeding an AND gate.Karnaugh maps can also be used to simplify logic expressions
in software design. Boolean conditions, as used for example in conditional statements, can get
very complicated, which makes the code difficult to read and to maintain. Once minimised,
canonical sum-of-products and product-of-sums expressions can be implemented directly using
AND and OR logic operators.
There is some variation like pair ,quads ,octets.Construct a K map and place 1s in those squares
according to truth table.place 0s in other squares.

Page | 11
The simplify form of expression from this karnaugh map is C .
Because A ,B, are in pairs.

Discussion: In the circuit diagram I made it in dsch3 software and input output circuit.Using K-map we
can find the simpliest form of a logical equation as well as we can design a simpliest logic circuit.We
have successfully run this circuit.

Page | 12
Experiment No: 05
Experiment Name: Half Adder.
Objectives: The main objectives is to design a half adder .To know how the half adder adds two
single binary digits .We will able to learn about half adder.
Theory:
The half adder adds two single binary digits A and B. It has two outputs, sum (S)
and carry . The carry signal represents an overflow into the next digit of a multi-digit
addition. The value of the sum is 2C + S. The simplest half-adder design, pictured on the
right, incorporates an XOR gate for S and an AND gate for C.

The simplified Boolean functions for the two outputs can be obtained directly from
the truth table. The simplified sum-of-products expressions are
S = AB’+A’B
C = AB

Page | 13
Truth Table :

Half Adder using Gates:

Some gates are required in order to design a half adder. The circuit to realize half
adder using gates is shown below.

Normal Circuit:

Page | 14
Input & Outout :

If A and B are the input bits, then sum bit (S) is the NOT,AND of A and B ,and
the carry bit (C) will be the AND of A and B. From this it is clear that a half adder circuit
can be easily constructed using one gate and one AND gate. Half adder is the simplest
of all adder circuit, but it has a major disadvantage. The half adder can add only two input
bits (A and B) and has nothing to do with the carry if there is any in the input. So if the
input to a half adder have a carry, then it will be neglected it and adds only the A and B bits.
That means the binary addition process is not complete and that‟s why it is called a half
adder.

Discussion: In the circuit diagram I made it in dsch3 software and input output circuit.We add two
binary single bit using by Hlaf adder .Major disadvantage is carry value is neglected . We have
successfully run this circuit.

Page | 15
Experiment No: 06
Experiment Name: Full Adder.
Objectives: The main objectives is to design a full adder .To know how the Full adder adds three
bits binary digits .We will able to learn about full adder.
Theory:
A full adder is a combinational circuit that forms the arithmetic sum of three bits. It consists of
three inputs and two outputs. Two of the input variables, denoted by A and B ,represent the two
significant bits to be added. The third input,represents the carryfrom the previous lower
significant position.
The block diagram of a full adder with A, B and cIN as inputs and S, cOUTut as outputs is
shown below:

Truth Table:

Page | 16
The simplified equation for sum is S = A’B’Cin + A’BcIN’ +AB’cIN’+ ABcIN.
The simplified equation for cOUT is cOUT = AB + AcIN + BcIN.Full Adder using NAND
GatesTem NAND gates are required in order to design a full adder. The circuit to realize full
adder using NAND gates is shown below:

Circuit:

Page | 17
Input Output circuit:

Full adder is a simple 1 – bit adder. If we want to perform n – bit addition, then
n number of 1 – bit full adders should be used in the form of a cascade connection.

Discussion: In the circuit diagram I made it in dsch3 software and input output circuit.Here we
use 2 bit binary value with a carry bit from previous function thats why there is three inputs. We
have successfully run this circuit.

Page | 18
Experiment No: 07
Experiment Name: n- bit parity bit generator.
Objectives: The main objectives is to learn the mechanism n- bit parity bit generator.To know
how parity bit create for required desire.
Theory:
Parity evaluates whether the number of “1” bits in a binary code is odd or even. This provides a
simple means of error checking. There are two types of parity with opposite results.:Even parity
results in a “1” if there are an odd number of “1” bits in the original code, and “0” if there are an
even number. The even parity bit can be appended to the code to make the number of “1” bits
even.Odd parity results in a “0” if there are an odd number of “1” bits, and “1” if there are an
even number. The odd parity bit can be appended to the code to make the number of “1” bits
odd.

Truth table of Even and Odd parity Generator:

Page | 19
n bit parity generator:

Page | 20
• Even Paraity Generator:Circuit:

• Odd Paraity Generator,Circuit:

Page | 21
 • Even Paraity Generator:

• Odd Paraity Generator:

Discussion: In the circuit diagram I made it in dsch3 software and input output circuit.In even parity
generator creat 1 if code group contain odd number of 1s .Odd parity generator do the reverse
function.We have successfully run this circuit.

Page | 22
Experiment No: 08
Experiment Name: n- bit parity bit Checker.
Objectives: The main objectives is to learn the mechanism n- bit parity bit Checker.To know
how to check the code group including parity bit that has there any error or not.
Theory:
A parity check is the process that ensures accurate data transmission between nodes during
communication. A parity bit is appended to the original data bits to create an even or odd bit
number; the number of bits with value one.
It is a logic circuit that checks for possible errors in the transmission. This circuit can be an even
parity checker or odd parity checker depending on the type of parity generated at the
transmission end. When this circuit is used as even parity checker, the number of input bits must
always be even.

When a parity error occurs, the ‘sum even’ output goes low and ‘sum odd’ output goes high. If
this logic circuit is used as an odd parity checker, the number of input bits should be odd, but if
an error occurs the ‘sum odd’ output goes low and ‘sum even’ output goes high.

Even Parity Checker:

Page | 23
Odd Parity Checker:

Page | 24
Even parity checker Circuit:

Input & Output:

Page | 25
Odd parity checker Circuit:

Input & Output:

Discussion: In the circuit diagram I made it in dsch3 software and input output circuit.Parity Checker
check

Page | 26
Experiment No:09
Experiment Name: Clocked S-R flip-flop using NAND Gate.
Objective: To learn how to implement clocked S-R flip-flop using NAND Gate.
Theory:
SR flip flop can also be designed by cross coupling of two NAND gates. It is an active high input
SR flip – flop. The circuit of SR flip – flop using NAND gates is shown in below figure.

Case 1: When both the SET and RESET inputs are low, then the output remains in previous state
i.e. it holds the previous data Case 2: When SET input is low and RESET input is high, then the
flip flop will be in RESET state. Because the high input of NAND gate with R input drives the
other NAND gate with 0, as its output is 0. So both the inputs of the NAND gate with S input are
0. This will cause the output of the flip – flop to settle in RESET state.

When SET input is high and RESET input is low, then the flip flop will be in SET state. Because
the low input of NAND gate with S input drives the other NAND gate with 1, as its output is 1.
So both the inputs of the NAND gate with R input are 1. This will cause the output of the flip
flop to settle in SET state. Case 4: When both the SET and RESET inputs are high, then the flip

Page | 27
flop will be undefined state. Because the high inputs of S and R, violates the rule of flip flop that
the outputs should complement to each other.

So the flip flop is in undefined state (or forbidden state). The table below summarizes above
explained working of SR Flip Flop designed with the
help of a NAND gate. Even though simple SR flip – flops and simple SR latches are same, both
the terms are used in their respective contexts.

Circuit of SR Flip Flop:

Input & Output:

Discussion: In the circuit diagram I made it in dsch3 software and input output circuit.Flip Flop used to
store a binary bit.We have successfully run this circuit.

Page | 28
Experiment No: 10
Experiment Name: Clocked J-K flip-flop using NAND Gate.
Objective: To learn how to implement clocked J-K flip-flop using NAND Gate.To know how to
break forbidden state of sr flip flop.

Theory: The clock has to be high for the inputs to get active. Thus, JK flip-flop is a controlled
Bi-stable latch where the clock signal is the control signal. Thus, the output has two stable states
based on the inputs which have been discussed below. The J (Jack) and K (Kilby) are the input
states for the JK flip-flop.
JK flip-flop is a controlled Bi-stable latch where the clock signal is the control signal. Thus, the
output has two stable states based on the inputs which have been discussed below.

Circuit Diagram:

In JK FF, two bypass line used as input to break the state of forbidden state.After using bypass
line there happen a toggle mode.That means alter the output result as previous output.

Page | 29
Prectical circuit:

Discussion: In the circuit diagram I made it in dsch3 software and input output circuit. In JK FF, two
bypass line used as input to break the state of forbidden state. After using bypass line there
happen a toggle mode.That means alter the output result as previous output..We have successfully
run this circuit.

Page | 30
Experiment No: 11
Experiment Name: Clocled D Latch.
Objective: The main objectives is to learn how to implement clocked D using NOR Gate.
Theory:
D-LATCH. Latch is an electronic device that can be used to store one bit of information. ... If the
data on the D line changes state while the clock pulse is high, then the output, Q, follows the
input, D. When the CLK input falls to logic 0, the last state of the D input is trapped and held in
the latch.

The operation of the D type delays any input by exactly one clock cycle (given an instantanious
response time i.e. a perfect flip-flop). Cascading several D type flip-flops together can produce
delaying circuits, possible applications could be for matching time delays in digital television
systems.

Page | 31
Circuit Diagram:

Input & Output:

Discussion: In the circuit diagram I made it in dsch3 software and input output circuit.We have
successfully run this circuit.

Page | 32
Experiment No: 12
Experiment Name: n-bit asynchronous (up/down) counter triggered with (PGT/NGT).
Objectives: we will able to learn the n bit asynchronous up or down counter triggered with PGT
or NGT.
Theory:
1. The clock pulses are applied only to
the CLKinput of flip-flop
A.Thus,flipflop A will toggle (change
to its opposite state) each time the
clock pulses make a negative (HIGH-
to-LOW) transition.Note that JK1 for
all FFs.
2. The normal output of flip-flop A acts as the CLK input for flip-flop B, and so flip-
flop B will toggle each time the A output goes from 1 to 0. Similarly, flip-flop C will
toggle when B goes from 1 to 0, and flip-flop D will toggle when C goes from 1 to 0.
3. FF outputs D, C, B, and A represent a four-bit binary number, with D as the MSB.
Let’s assume that all FFs have been cleared to the 0 state (CLEAR inputs are not
shown).The waveforms in Figure 7-1 show that a binary counting sequence from
0000 to 1111 is followed as clock pulses are continuously applied.
4. After the NGT of the fifteenth
clock pulse has occurred, the
counter FFs are in the 1111
condition. On the sixteenth
NGT, flip-flop A goes from 1
to 0, which causes flip-flop B
to go from 1 to 0, and so on,
until the counter is in the 0000 state. In other words, the counter has gone through one
complete cycle (0000 through 1111) and has recycled back to 0000. From this point,
it will begin a new counting cycle as subsequent clock pulses are applied.
In this counter, each FF output drives the CLK input of the next FF. This type of counter
arrangement is called an asynchronous counter because the FFs do not change states in exact
synchronism with the applied clock pulses; only flip-flop A responds to the clock pulses. FF B
must wait for FF A to change states before it can toggle; FF C must wait for FF B, and so on.
Thus, there is a delay between the responses of successive FFs. This delay is typically 5–20 ns
per FF. In some cases, as we shall see, this delay can be troublesome. This type of counter is also
often referred to as a ripple counter because of the way the FFs respond one after another in a
kind of rippling effect. We will use the terms asynchronous counter and ripple counter
interchangeably.

Discussion:There are shown 4 bit asynchronous down counter which is triggered with NGT.1st
flip flop’s output puts onto the 2nd plip flop as a clock signal and so on.

Page | 33
Experiment No:13
Experiment Name: n-bit synchronous (up/down) counter triggered with (PGT/NGT)
Objectives: we will able to learn the n bit synchronous up or down counter triggered with PGT
or NGT.

Theory:A synchronous down counter is constructed in a similar manner except that we use the
inverted FF outputs to control the higher-order J, K inputs. Comparing the synchronous, MOD-
16, down counter in bellows Figure with the up counter in others Figure shows that we need only
to substitute the corresponding inverted FF output in place of the A, B, and C outputs. For a
down count sequence, the LSB FF (A) still needs to toggle with each NGT of the clock input
signal. Flip-flop B must change states on the next NGT of the clock when A = 0. Flip-flop C
changes states when A = B = 0 (A’. B’ = 1) and flip-flop D changes states when A = B = C = 0
(A’B’C’ = 1). This circuit configuration will produce the count sequence: 15,
14,13,12,...,3,2,1,0,15,14,and so on, as shown in the timing diagram.

Circuit Diagram of Syncronous Counter:

Page | 34
Truth Table of Synchronous Counter:

Discussion:In the logic circuit, there are shown a circuit named synchronous counter. For n bit
synchronous counter, I used here bit, so here n=4. MOD=2^n=2^4=16.

Page | 35
Experiment No:14
Experiment Name : N-bit Binary to Decimal decoder.
Objective : To learn the implementation of N-bit Binary to Decimal decoder.
Theory :The name “Decoder” means to translate or decode coded information from one format
into another, so a binary decoder transforms “n” binary input signals into an equivalent code
using 2n outputs.
Binary Decoders are another type of digital logic device that has inputs of 2-bit, 3-bit or 4-bit
codes depending upon the number of data input lines, so a decoder that has a set of two or more
bits will be defined as having an n-bit code, and therefore it will be possible to represent
2n possible values. Thus, a decoder generally decodes a binary value into a non-binary one by
setting exactly one of its n outputs to logic “1”.
If a binary decoder receives n inputs (usually grouped as a single Binary or Boolean number) it
activates one and only one of its 2n outputs based on that input with all other outputs deactivated.
2-to-4 Binary Decoder :
The 2-to-4 line binary decoder depicted above consists of an array of four AND gates. The 2
binary inputs labelled A and B are decoded into one of 4 outputs, hence the description of 2-to-4
binary decoder. Each output represents one of the minterms of the 2 input variables, (each output
= a minterm)
The binary inputs A and B determine which output line from Q0 to Q3 is “HIGH” at logic level
“1” while the remaining outputs are held “LOW” at logic “0” so only one output can be active
(HIGH) at any one time. Therefore, whichever output line is “HIGH” identifies the binary code
present at the input, in other words it “decodes” the binary input.
Truth Table:

Page | 36
Circuit:

Page | 37
Input & Output:

Discussion: In the circuit diagram I made it in dsch3 software and input output circuit.We have
successfully run this circuit.

Page | 38
Experiment No:15
Experiment Name: n-bit decimal to binary decoder.
Objective: To learn how to implement n-bit decimal to binary decoder.
Theory: A BCD to decimal decoder has ten output bits. It accepts an input value consisting of a binary-
coded decimal integer value and activates one specific, unique output for every input value in the range
[0,9]. All outputs are held inactive when a non-decimal value is applied to the inputs.

Binary decoder is a combination logic circuit that converts binary information from the n coded
inputs to a maximum of 2n unique outputs. They are used in a wide variety of applications,
including data demultiplexing, seven segment displays, and memory address decoding.
There are several types of binary decoders, but in all cases a decoder is an electronic
circuit with multiple input and multiple output signals, which converts every unique combination
of input states to a specific combination of output states. In addition to integer data inputs, some
decoders also have one or more "enable" inputs. When the enable input is negated (disabled), all
decoder outputs are forced to their inactive states.
For one bit binary decoder, the input of decimal can be 0 to 1. For two bit output, the
decimal can be 0 to 3 and for the 3 bit binary number the decimal can be 0 to 7. By this similar
type of information, the logic circuit will make of n bit’s max decimal values input.

Circuit Diagram:

Page | 39
Input Output Circuit:

Discussion:As a example, I used here, 3bit decimal to binary decoder. For 3 bit maximum
output, the maximum value of the decimal number is 7, so the input will be 8 numbers, from 0 to
7. But here, we can turn on one input from the logic circuit.

Page | 40
Experiment No:16
Experiment Name: Implement n-input multiplexer.
Objective: The main objectives is to learn how to implement n-input multiplexer.To know how
to accept many inputs and provide one output.
Theory: A multiplexer is a circuit that accept many input but give only one output. A multiplexer is
a circuit used to select and route any one of the several input signals to a signal output. An simple
example of an non electronic circuit of a multiplexer is a single pole multiposition switch. Few types
of multiplexer are 2-to-1, 4-to-1, 8-to-1, 16-to-1 multiplexer.

The block diagram of Multiplexer is below:

For example we take 4 to 1 multiplexer:

Truth table

Page | 41
Circuit diagram:

Input & output:

Discussion: In the circuit diagram I made it in dsch3 software and input output circuit.By controlling the
selection line we can pass the input to output line one by one .We have successfully run this circuit.

Page | 42
Experiment no : 17
Experiment name : 1 Line to 8 Line Demultiplexer.
Objective : The main objectives is to design a 1 Line to 8 Line Demultiplexer.
Theory :
A Demultiplexer is a data distributor read as DEMUX. It is quite opposite to multiplexer or
MUX. It is a process of taking information from one input and transmitting over one of many
outputs. With the use of a demultiplexer , the binary data can be bypassed to one of its many
output data lines..

INPUT Outputs
DEMUX

SELECT

DEMUX are used to implement general-purpose logic systems. A demultiplexer takes one single
input data line and distributes it to any one of a number of individual output lines one at a time.
Demultiplexing is the process of converting a signal containing multiple analog or digital signals
backs into the original and separate signals. A demultiplexer of 2n outputs has n select lines.
1 Line to 8 Line Demultiplexer :

A 1 to 8 demultiplexer consists of one input line, 8 output lines and 3 select lines. Let the input
be I, 𝑆0 , 𝑆1 and 𝑆2 are three select lines and eight outputs from 𝑂0 to 𝑂7. It is also called as 3 to 8
DEMUX because of the 3 selection lines. Below is the block diagram of 1 to 8 DEMUX.

Page | 43
Truth Table :

The below is the truth table for 1 to 8 demultiplexer. It tells the functionality of the DEMUX.

Data Select Input Outputs

Input
I 𝑆2 𝑆1 𝑆0 𝑂7 𝑂6 𝑂5 𝑂4 𝑂3 𝑂2 𝑂1 𝑂0
I 0 0 0 0 0 0 0 0 0 0 1
I 0 0 1 0 0 0 0 0 0 1 0
I 0 1 0 0 0 0 0 0 1 0 0
I 0 1 1 0 0 0 0 1 0 0 0
I 1 0 0 0 0 0 1 0 0 0 0
I 1 0 1 0 0 1 0 0 0 0 0
I 1 1 0 0 1 0 0 0 0 0 0
I 1 1 1 1 0 0 0 0 0 0 0

From this truth table, the Boolean expressions for all the outputs can be written as follows.
O0 =I. ̅̅̅
S2 S̅1 ̅̅̅
S0
O1 =I. ̅̅̅̅
S2 S̅1 S0
O2 =I.̅̅̅̅
S2 S1 ̅̅̅
S0
O3 =I. ̅̅̅̅
S2 S1 S0
O4 =I. S2 S̅1 ̅̅̅
S0
O5 =I. S2 S̅1 S0
O6 =I. S2 S1 ̅̅̅
S0
O7 =I. S2 S1 S0
From these obtained equations, the logic diagram of this demultiplexer can be implemented by
using eight AND gates and three NOT gates. However we used 16 AND gates as shown in below
figure. The different combinations of the select lines , select one AND gate at given time , such
that data input will appear at a particular output.

Page | 44
Circuit:

1 Line to 8 Line demultiplexer circuit

Page | 45
Input & output Circuit:

Discussion: In the circuit diagram I made it in dsch3 software and input output circuit.We have
successfully run this circuit.

Page | 46
Page | 47