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    1) The document describes experiments to study latches and flip-flops built with discrete gates. It involves constructing a gated SR latch using NAND gates and observing its behavior under different input conditions. It also involves constructing a master-slave JK flip-flop using NAND gates and observing its behavior. 2) The gated SR latch experiment aims to study the effect of selectively adding propagation delay to one of the NAND gates. Observations are reported in the timing diagram and behavior is explained. 3) For the JK flip-flop, logic values are recorded for its outputs Q, Q, Qm, and Qm under different input conditions. A timing diagram is drawn and its behavior

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    Expt3 Directions

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    1) The document describes experiments to study latches and flip-flops built with discrete gates. It involves constructing a gated SR latch using NAND gates and observing its behavior under different input conditions. It also involves constructing a master-slave JK flip-flop using NAND gates and observing its behavior. 2) The gated SR latch experiment aims to study the effect of selectively adding propagation delay to one of the NAND gates. Observations are reported in the timing diagram and behavior is explained. 3) For the JK flip-flop, logic values are recorded for its outputs Q, Q, Qm, and Qm under different input conditions. A timing diagram is drawn and its behavior

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    1) The document describes experiments to study latches and flip-flops built with discrete gates. It involves constructing a gated SR latch using NAND gates and observing its behavior under different input conditions. It also involves constructing a master-slave JK flip-flop using NAND gates and observing its behavior. 2) The gated SR latch experiment aims to study the effect of selectively adding propagation delay to one of the NAND gates. Observations are reported in the timing diagram and behavior is explained. 3) For the JK flip-flop, logic values are recorded for its outputs Q, Q, Qm, and Qm under different input conditions. A timing diagram is drawn and its behavior

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    28 views3 pages

    Expt3 Directions

    Uploaded by

    lsu225
    1) The document describes experiments to study latches and flip-flops built with discrete gates. It involves constructing a gated SR latch using NAND gates and observing its behavior under different input conditions. It also involves constructing a master-slave JK flip-flop using NAND gates and observing its behavior. 2) The gated SR latch experiment aims to study the effect of selectively adding propagation delay to one of the NAND gates. Observations are reported in the timing diagram and behavior is explained. 3) For the JK flip-flop, logic values are recorded for its outputs Q, Q, Qm, and Qm under different input conditions. A timing diagram is drawn and its behavior

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    EE 2731 Experiment 3 February 8 or 10, 2011

    Latches and Flip-Flops


    In this experiment we will study the behavior of flip-flops built with discrete gates. The following
    experiments are to be performed on the trainer kit. For each experiment, use the description of
    gates used to select the appropriate chips and connect them in a manner that allows you to input
    logic values through the logic switches and the debounced switch for the clock, and to read flip-flop
    outputs though the built-in logic monitor.

    1 Gated SR-Latch
    1.1 Normal Behavior
    Use 2-input NAND gates to construct the gated SR latch shown below. Use the debounced switch
    to control (normally at 1) for the Clk input.

    S
    1 Q

    Clk

    2 Q
    R

    Record the response of the circuit (at outputs Q and Q and at times T1 –T7 ) for the input shown
    below.
    T1 T2 T3 T4 T5 T6 T7

    Briefly, explain the recorded behavior in your report.

    1.2 Behavior at the Clk = S = R = 11 to Clk = 0 Transition


    Baseline Experiment: Apply the following input sequence and record the circuit’s output (Q
    and Q) at time T2 . The two transitions at time T1 can occur in any order.

    1
    EE 2731 (Spring 2011)—Experiment 3 2

    T1 T2

    Clk

    Repeat this input sequence 10 times and record the outputs as before. The outputs (Q or Q)
    at time T should exhibit more or less consistent values over these 10 times.

    Induced-Delay Experiment: The idea of this experiment is to selectively add a delay to one
    of the NAND gates numbered 1 and 2 in the latch and then check the behavior exhibited in the
    baseline Experiment. This delay will be in terms of two inverters (built out of NAND gates) added
    in series with the original gate.
    Suppose that in the 10 trials of the Baseline Experiment, most (or all) of the time you get
    Q = 0 and Q = 1. Change the circuit by connecting two inverters to Gate 1 as shown below.

    S
    1 Q

    Clk

    2 Q
    R

    This change does not alter the functionality of Gate 1 (see the part enclosed in the red rectangle).
    It just increases the propagation delay of Gate 1. Now apply the input sequence described above
    another 10 times. Record the output and describe any changes in the output.
    If the Baseline Experiment resulted in Q = 1 and Q = 0 most (or all) of the time, do the
    Induced-Delay Experiment with the delay added to NOR gate 2 and leave Gate 1 unchanged.

    Include all of the above logic value measurements in your report. Explain the SR-Latch’s behavior in terms of your
    measured results.
    EE 2731 (Spring 2011)—Experiment 3 3

    2 JK Flip-Flop
    The block diagram of a Master-Slave JK flip-flop (in terms of Gated SR-Latches) is shown below.
    The logic diagram of the Gated SR-Latch is shown earlier in the context of the previous experiment.

    Qm
    S Q S Q Q
    J
    clock Clk Clk
    K Qm
    R Q R Q Q

    Use 2- and 3-input NAND gates to build a Master-Slave JK Flip-Flop on the trainer kit. Connect
    the JK inputs to regular logic switches and the clock input to a debounced switch (that is normally
    low). Connect signals Q, Q, Qm and Qm to the built-in monitor.
    Record the values of Q, Q, Qm and Qm for the following inputs.

    clock

    In your report, draw the complete timing diagram (for signals Q, Q, Qm and Qm that you measured in your experiment.
    Briefly explain the Master-Slave JK flip-flop’s behavior in terms of your measured logic values. In particular, determine
    whether the flip-flop you constructed is positive or negative edge-triggered.

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