3070 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO.

9, SEPTEMBER 2015

A Compact Virtual-Source Model for Carbon

Nanotube FETs in the Sub-10-nm Regime—Part II:
Extrinsic Elements, Performance Assessment,
and Design Optimization
Chi-Shuen Lee, Eric Pop, Senior Member, IEEE, Aaron D. Franklin, Senior Member, IEEE,
Wilfried Haensch, Fellow, IEEE, and Hon-Sum Philip Wong, Fellow, IEEE

Abstract— We present a data-calibrated compact model of technology nodes [1]–[3] owing to CNTs’ near-ballistic carrier
carbon nanotube (CNT) FETs (CNFETs), including contact transport [4], [5] and ultrathin body (1–2 nm), which provides
resistance, direct source-to-drain, and band-to-band tunneling a superior electrostatic control over the channel and enables
currents. The model captures the effects of dimensional scaling
and performance degradations due to parasitic effects, and is further scaling of the gate length (L g ) below 10 nm [3], [6].
used to study the tradeoffs between the drive current and While CNFETs have superior intrinsic electronic properties,
the leakage current of CNFETs according to the selection of they suffer from imperfections, such as the difficulty of
CNT diameter, CNT density, contact length, and gate length acquiring extremely high-purity semiconducting CNTs [7],
for a target contacted gate pitch. We describe a co-optimization hysteresis of the current–voltage (I –V ) characteristics [8],
study of CNFET device parameters near the limits of scaling with
physical insight, and project the CNFET performance at the 5-nm and variations of material and devices [9]. Techniques to
technology node with an estimated contacted gate pitch of 31 nm. overcome these imperfections at the system level have
Based on the analysis, including parasitic resistance, capacitance, been reported in [10] at modest cost of area and energy
and tunneling leakage current, a CNT density of 180 CNTs/µm consumption.
will enable the CNFET technology to meet the International In this paper, we focus on two specific issues: 1) parasitic
Technology Roadmap for Semiconductors target of drive current
(1.33 mA/µm), which is within reach of modern experimental metal-CNT contact resistance (Rc ) and 2) direct source-to-
capabilities. drain tunneling (SDT) current (ISDT ).1 Obtaining low Rc
between metals and low-dimensional materials has been recog-
Index Terms— Carbon nanotube (CNT), carbon-nanotube
FET (CNFET), compact model, contact, technology assessment, nized as one of the most challenging yet critical requirements
tunneling. for high-performance transistors [11], [12]. Furthermore, as L g
scales below 10 nm, ISDT may become significant and cause
high leakage power [2], [13], [14]. While previous works
I. I NTRODUCTION employed rigorous yet computationally intensive modeling
methods to study these issues [2], [15], here, we develop
S EMICONDUCTING single-walled carbon-nanotube
(CNT) FETs (CNFETs) have shown promise for
extending the CMOS technology scaling into the sub-10-nm
analytical models for Rc and ISDT in CNFETs and study their
impacts on the device performance. This paper is organized as
follows: models for Rc and ISDT calibrated to the experiments
Manuscript received March 17, 2015; revised June 13, 2015; accepted and numerical simulations are described in Sections II and III,
July 8, 2015. Date of current version August 19, 2015. This work was
supported in part by the Network for Computational Nanotechnology–Nano- respectively. These extrinsic elements are then integrated with
Engineered Electronic Device Simulation Program funded by the National the intrinsic model developed in [16] based on the virtual-
Science Foundation under Contract 1227020-EEC and by the Semiconductor source (VS) approach to arrive at a complete VS-CNFET
Research Corporation, in part by the Systems on Nanoscale Information
Fabrics (SONIC), one of the six Semiconductor Research Corporation STAR- model; in Section IV, the CNFET performance is evaluated
net Centers through the Microelectronics Advanced Research COrporation at the 5-nm technology node corresponding to a contacted
and Defense Advanced Research Projects Agency, in part by the member gate pitch L pitch = 31 nm and metal-1 pitch L M1 = 25.2 nm.
companies of the Initiative for Nanoscale Materials and Processes (INMP)
through Stanford University, Stanford, CA, USA, and in part by IBM through By comparing the drive current against the 2013 International
the SystemX Alliance and the Center for Integrated Systems, Stanford Technology Roadmap for Semiconductors (ITRS) target [17],
University. The review of this paper was arranged by Editor G. L. Snider. the requirements of the CNT density for CNFETs are
C.-S. Lee, E. Pop, and H.-S. P. Wong are with the Department of
Electrical Engineering, Stanford University, Stanford, CA 94305 USA (e-mail: presented as a guide for technology development; in
chishuen@stanford.edu; epop@stanford.edu; hspwong@stanford.edu). Section V, we discuss the assumptions of the model and
A. D. Franklin is with the Department of Electrical and Computer analysis as well as suggestions for future experimental works.
Engineering, Duke University, Durham, NC 27708 USA (e-mail:
aaron.franklin@duke.edu). The models presented in this paper are calibrated to the data
W. Haensch is with the IBM Thomas J. Watson Research Center, Yorktown
Heights, NY 10598 USA (e-mail: whaensch@us.ibm.com). 1 These two challenges are not unique to CNFETs, but are also challenges
Color versions of one or more of the figures in this paper are available for all scaled FETs. The simplicity of the CNT band structure makes this a
online at http://ieeexplore.ieee.org. model system for gaining insight into these challenges for other materials as
Digital Object Identifier 10.1109/TED.2015.2457424 well.
0018-9383 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
LEE et al.: COMPACT VS MODEL FOR CNFETs IN THE SUB-10-nm REGIME 3071

Fig. 2. Parameter extraction for the metal-CNT contact resistance model.

Fig. 1. Representative GAA CNFET structure used in the VS-CNFET model (a) ION versus 1/d from [20] to extract E 00 in (3a). (b) Rc versus L c from [23]
with the critical dimensions, parasitic resistances, and capacitances labeled. to extract λc and gc in (2).

from the experiments and numerical simulations based on

nonequilibrium Green’s function (NEGF) quantum transport. where L T is the current transfer length, R Q = h/(4q 2 ) ≈
Therefore, this paper aims to provide realistic insight into the 6.5 k is the quantum resistance of the CNT (lowest band,
potentials and challenges of the CNFET technology. Due to doubly degenerate with two spins), q is the elementary charge,
the limited space, the complete derivation of all the equations h is Planck’s constant, λc is the charge carrier mean-free-
is detailed in [31]; here, we only discuss the physics and key path (MFP) in the CNT under the metal contact, and gc is
results. the coupling conductance between the CNT and the metal
contact. Note that in (2a), R Q is subtracted on the right-hand
II. PARASITIC R ESISTANCE side because R Q is considered the intrinsic property associated
The CNFET parasitic resistance considered in this paper with the interfaces between the 1-D CNT channel with the
consists of two components: 1) the parasitic metal-CNT metal S/D contacts [24]. As a result, Rc is a parasitic com-
contact resistance (Rc ) and 2) the resistance in the source/ ponent. In [25], λc and gc are constant empirical parameters;
drain (S/D) extensions (Rext ), as shown in Fig. 1. In general, whereas, in this paper, gc is related to φb so as to account
the metal-CNT Rc is determined by three factors: 1) Schottky for the experimental observation of the increase in Rc as d
barrier height (φb ); 2) interface quality (i.e., metal-CNT decreases [20] by
adhesion); and 3) physical contact length (L c ). In [18], the
gc = gco exp (−φb /E 00 ) (3a)
Fermi-level pinning is predicted to be insignificant in the
metal-CNT contacts, and thus φb is proportional to the CNT φb = E g /2 − (φm − φs ) (3b)
bandgap (E g ) [19] where φm and φs are work functions of the contact metal
2E p acc and the CNT, respectively, and gco and E 00 are empirical
Eg = (1)
d parameters. In analogy to the calculation of transmission
where E p = 3 eV is the tight-binding parameter, coefficient through a metal-to-bulk-semiconductor Schottky
acc = 0.142 nm is the carbon–carbon distance in CNTs, contact [26], the E 00 value in (3a) characterizes the width
and d is the CNT diameter. Corrections to (1) could be of the energy barrier at metal-to-bulk-semiconductor interface:
made due to bandgap renormalization as discussed in [16], 1) the smaller the E 00 value; 2) the wider the barrier; and 3) the
but they do not alter the core of the model presented here. more sensitive the gc value to the φb value. Note that (3b) is for
Chen et al. [20] experimentally demonstrated an exponential p-type contacts. For n-type contacts, (3b) should be modified
increase in Rc with 1/d, attributed to the increase in φb ; other to φb = E g /2 + (φm − φs ).
authors showed that lower Rc can be achieved with Pd rather There are three empirical parameters to be determined
than Au contacts, despite their similar work functions [4], [21]. in (2) and (3): 1) λc ; 2) gco ; and 3) E 00 . The extraction of
This advantage is attributed to better wettability at the these three parameters goes as follows.
Pd-CNT interface, the importance of which was also clarified 1) The Rc value calculated by (2) and (3) is included
by a recent study with several contact metals [22]. In the into the intrinsic current model described in [16] to
models presented here, we include the dependence of Rc on d, generate the ON-state current (ION ) compared against
but not that of the interface wettability or adhesion (which the data from [20] in Fig. 2(a). From the slope of ION
could also be influenced by polymer residue from fabrication); versus 1/d, E 00 = 32 meV is extracted.
the dependence of Rc on L c was experimentally studied 2) Equation (2) is fitted to the Rc versus L c data from [23]
in [22] and [23], and can be phenomenologically modeled by in Fig. 2(b), where λc = 380 nm and gc = 2 μS/nm are
the transmission line model [25] extracted (same as the result in [25]) for d = 1.2 nm
   with Pd as the contact metal.
4 Lc
2Rc = R Q 1 + coth − RQ (2a) 3) Substituting φm = 5.1 eV for Pd, φs = 4.7 eV for
λc gc R Q LT intrinsic CNTs, E g = 0.71 eV for d = 1.2 nm, and
   −1/2 gc = 2 μS/nm into (3a) and (3b), gco = 0.49 μS/nm is
gc R Q gc R Q 2
LT = + (2b) obtained. In Fig. 2(a), we observe that the ION drops
λc 2 even faster as 1/d increases beyond a certain point
3072 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 9, SEPTEMBER 2015

Fig. 3. Contact resistance versus (a) CNT diameter for different contact Fig. 4. Comparison of the extension resistances versus the doping density.
lengths and (b) contact lengths for different CNT diameters. The symbols are calculated by (4) numerically. Lines: analytical approxima-
tion of (5). The dashed lines are generated by assuming λi in (4) is constant.

(for the Al contact as example, the ION decreases more

to the Drude model and 2) λi is proportional to d according
rapidly as 1/d > 1 nm−1 ).
to [27]. Equation (5) is then fitted to the numerical results
This accelerated downturn can be explained as follows: given by (4), as shown in Fig. 4, where Rext0 = 35 ,
when 1/d is small and gc is large, L T  L c in (2) and αd = 2, and αn = 2.1 are extracted. Equation (5) agrees well
coth(L c /L T ) ≈ 1. Therefore, Rc increases with (1/gc )1/2 ∝ with (4) at low n sd region but underestimates Rext at high
exp[1/(2d)]; as 1/d increases and gc becomes small, L T  L c n sd region. However, when n sd is large, Rext  Rc , so the
and coth(L c /L T ) ≈ L T /L c , and Rc increases with discrepancy is negligible. The dashed lines in Fig. 4 represent
1/gc ∝ exp(1/d). This accelerated downturn is observed in the results when λi is a constant instead of being dependent
both the experimental data and the model (2) and (3), which on energy and CNT diameter. In such a case, Rext exhibits
strengthens the validity of the Rc model. As shown in Fig. 3, less sensitivity to d and higher sensitivity to n sd .
in the region where L c and/or d are small, Rc increases
drastically, which severely degrades the drive current and can III. T UNNELING L EAKAGE C URRENT
cause large variation in the presence of variations in L c and d.
According to the 2013 ITRS projections [17], the L g values
The impact of L c and d on the CNFET performance is
of MOSFETs should eventually scale below 10 nm. At such
discussed in Section IV.
a small L g , quantum mechanical tunneling from the source
The other component Rext is derived from the 1-D Landauer
to drain becomes appreciable. Several simulation works
formula [24]
predicted that at L g ≈ 5–10 nm, ISDT will become promi-
Rext = 1/G − R Q (4a) nent and severely degrade the subthreshold swing (SS) of
  MOSFETs [2], [13], [14]. Nonetheless, observation of
4q 2 ∞ λi (E) ∂ f (E, E F )
G = − dE (4b) SDT has been reported only in a few experiments, e.g.,
h L ext + λi (E) ∂E
 ∞ Ec a Si MOSFET with L g = 8 nm, using temperature-dependent
n sd = g(E) f (E, E F )d E (4c) measurements [28]. Whether the ultimate scaling limit of L g is
Ec set by ISDT is still not clear because of the lack of experimental
where G is the CNT conductance at low fields, L ext is the evidence, and because the answer also depends on the precise
length of the S/D extensions (see Fig. 1), E c is the conduction geometry of the FET. However, to fully exploit the excellent
band (CB) edge, E F is the Fermi level, E is the energy electrostatic control of the ultrathin CNTs, the L g value of
of free electrons referenced to E c , f is the Fermi–Dirac CNFETs is likely to be aggressively scaled down until the
distribution function, g(E) is the CNT density of states, leakage current becomes intolerable. It is thus important to
n sd is the doping density in the S/D extensions, and λi is develop a model that consider the impact of ISDT in the
the carrier MFP in CNTs representing the aggregate effect sub-10-nm technology nodes.
of optical phonon and acoustic phonon scattering as intro- Two tunneling mechanisms are considered here: 1) SDT
duced in [27]. R Q is subtracted from 1/G in (4a) because and 2) band-to-band tunneling (BTBT) at the drain side. The
G is the total conductance including the contact resistance, SDT can be further divided into two parts: 1) the intraband
which has already been considered in the Rc model. Because SDT (intra-SDT), the tunneling from CB to CB, and 2) the
λi has a complex expression [27], (4b) cannot be integrated inter-band SDT (inter-SDT), the tunneling from CB to valence
analytically. Therefore, an empirical expression of Rext is band (VB) to CB. The BTBT is the tunneling from source
employed here VB to drain CB, as shown in Fig. 5. While n-type FETs are
used as examples throughout this paper, the model can be
L ext
Rext = Rext0 (5) easily applied to p-FETs by properly changing the polarity
d αd n αsdn of the terminal voltages, due to the symmetry of the CNT
where Rext0 , αd , and αn are the empirical fitting parameters. CB and VB. All tunneling currents are computed by the
The form of (5) is inspired by the observations that: 1) for 1-D Landauer formula [24]

heavily doped CNTs, the carrier transport becomes more 4q
diffusive, and thus Rext ∝ L ext /n sd in a manner analogous I = Te (E)[ f (E, E fs ) − f (E, E fd )]d E (6)
h
LEE et al.: COMPACT VS MODEL FOR CNFETs IN THE SUB-10-nm REGIME 3073

top of E c (x) (named EXPS in Fig. 6)


E cs (x) = u s e−x/λ + vs , −L g /2 − L of < x < 0
E c (x) =
E cd (x) = u d e x/λ + vd , 0 < x < L g /2 + L of
(9)
where u’s and v’s are fitting coefficients, λ is the electrostatic
length scale discussed in [16], and L of is an empirical
parameter functioning like an extension of the L g that
captures the finite Debye length and the gate fringing field
Fig. 5. Illustration of the direct SDT and the BTBT mechanisms. xi and xo (see Fig. 6); and 3) a piecewise function to describe both the
are the positions where the electrons tunnel in and out the energy barrier. curvy top and the tails of E c (x) (named PIECE in Fig. 6)
⎧
⎪
⎪ E cs (x) = bs e(x+L g /2)/λs + cs , x < −L g /2
⎪
⎨ E cg (x) = a1 e−x/λ + a2 e x/λ + a3
E c (x) = (10)
⎪
⎪ − L g /2 < x < L g /2
⎪
⎩
E cd (x) = bd e−(x−L g /2)/λd + cd , x > L g /2
where a’s, b’s, c’s, λs , and λd are fitting coefficients.
By substituting (9) and (10) into (8), Te can be calculated
analytically. The derivation of the coefficients in (9) and (10)
as well as the analytical expressions of Te in (8) are detailed in
[31, eq. (28)–(36)]. ISDT is then calculated by (6) numerically.
Fig. 6. CB profile calculated by the numerical simulation (circles) [30]. The ISDT calculated by the numerical simulation [30] is
three analytical models. RECT: rectangular E c profile. EXPS: two connected compared against the three different E c (x) models individually
exponential functions given by (9). PIECE: piecewise function given by (10).
in Fig. 7(a)–(c). As shown in Fig. 7(a), the RECT model
does not fit the data well in the high Vgs region (i.e., near-
where Te is the tunneling probability and E fs and E fd are threshold), because it fails to capture the characteristic of the
Fermi levels at the source and the drain, respectively. Te is curvy top of E c , resulting in an underestimate of ISDT ; in
calculated by the Wentzel–Kramers–Brillouin approxima- the low Vgs region (i.e., deep subthreshold region), the RECT
tion [29] model overestimates ISDT due to the disregard of the tails of
  xo  the E c profile; in Fig. 7(b), the EXPS model fits the data well
Te (E) = exp −2 κd x at high Vgs but overestimates ISDT at low Vgs because it also
xi fails to capture the tails; finally, in Fig. 7(c), the PIECE model
π Eg
gives the best fitting result because it considers both the curvy
κ = 1 − {1 − 2[E c (x) − E]/E g }2 (7) top and the tails. However, the use of a piecewise function
hυ F
in (10) could potentially result in convergence issues when
where κ is the imaginary wave vector in CNTs, υ F ≈ 106 m/s implemented in Verilog-A [32], because when a large-scale
is the Fermi velocity, x is the position along the CNFET circuit is simulated in an environment like SPICE, extraordi-
channel, and x i and x o are the positions where the electrons narily large biases may be applied on the device terminals,
tunnel in and out the energy barrier, respectively (see Fig. 5). which can potentially lead to discontinuities in (10). As a
Equation (7) is then recast as follows for the convenience of result, the EXPS model will be used to calculate ISDT in the
calculations: following analysis. Although the EXPS model overestimates

2π E g ISDT in the deep subthreshold region, it can still give accurate
Te (E) = exp − tb (E) results in the subthreshold region and warn the user of an
hυ F
 xo
imminent significant impact of ISDT when the L g becomes
tb (E) = 1 − {1 − 2[E c (x) − E]/E g }2 d x. (8) too short. Besides, the EXPS model is more computationally
xi
efficient.
To calculate Te , analytical models for E c (x) are first discussed. As shown in [33], the presence of ISDT significantly
The circles in Fig. 6 are the E c profile calculated by degrades the SS and increases the leakage power of CNFETs.
the numerical simulation based on the NEGF quantum To explore potential ways to lower ISDT , Fig. 8(a) and (b)
transport [30], which simulates a CNFET with a cylindrical shows how ISDT is affected by d, n sd , and the dielectric
gate-all-around (GAA) device structure and heavily doped constant of the sidewall spacer kspa (see Fig. 1). As shown
S/D extensions. Two features are observed in the simulated in Fig. 8(a), ISDT increases exponentially with d, because
E c profile: 1) a curvy profile around the top of E c (x) κ in (7) is proportional to E g . By utilizing small-diameter
and 2) gradual tails extending into the S/D extensions. CNTs, tunneling leakage can be effectively mitigated, but it
Three different analytical models of E c (x) are examined also leads to lower drive current due to larger Rc , and lower
here: 1) a rectangular profile (named RECT in Fig. 6); carrier mobility and velocity [16]. A decrease of n sd from
2) two connected exponential functions to model the curvy 1 nm−1 to 0.6 nm−1 can reduce ISDT by a factor of 3.5,
3074 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 9, SEPTEMBER 2015

Fig. 7. Comparison of direct source-to-drain tunneling current between the numerical simulation [30] and the three models. (a) RECT: rectangular E c profile.
(b) EXPS: E c profile given by (9). (c) PIECE: E c profile given by (10) for different gate lengths. d = 1 nm is used.

Fig. 9. Calibration of the BTBT current model to the numerical simula-

tion [30] for different CNT diameters and spacer dielectric constants kspa .
(a) IBTBT versus Vds for different diameters. (b) IBTBT versus kspa for
different values of Vds s.

by fitting the ISDT model to the numerical simulation based

on a GAA cylindrical structure [30] for different values of
kspa and tox . While (11) could be changed for different device
geometries, the trend should remain the same.
The BTBT current (IBTBT ) is modeled in a similar approach
Fig. 8. (a) Direct SDT current ISDT versus CNT diameters for different
to ISDT , except that the E c value is modeled differently
E c (x) = ue−x/λBTBT
doping densities in the S/D extensions. Inset: source CB is raised
as n sd decreases. (b) ISDT versus Vgs for different spacer dielectric con- (12)
stants (kspa ). Symbol: numerical simulation. Line: model. Inset: higher kspa
results in stronger gate-to-extension fringe field, wider energy barrier, and where u and λBTBT are fitting parameters. Equation (12) is
lower ISDT . employed to model the decaying E c profile at the gate-drain
junction (see Fig. 5). Substituting (12) into (8) gives
because as n sd decreases, the CB edge at the source is raised  xo

relative to the Fermi level, and thus less carriers are available tb (E) = 1 − {1 − 2(ue−x/λBTBT − E)/E g }2 d x
xi
to tunnel from the source through the barrier to the drain    
E + Eg E
[see Fig. 8(a) (inset)]. However, lower n sd gives higher Rext . x i = λBTBT ln , x o = λBTBT ln . (13)
As shown in the inset of Fig. 8(b), higher kspa results in u u
stronger gate-to-extension fringe field and leads to a wider By changing variables, a closed-form expression of tb is
energy barrier. To model the effect of the fringe field caused by obtained
different kspa ’s, L of in (9) and implicitly in (10) are empirically 
tb = λBTBT π(ζ + ζ 2 − 1) (14)
related to kspa and the gate oxide thickness tox
where ζ = −2E/E g − 1 (see [31] for detailed derivation).
L of = (0.0263kspa + 0.056) · tox . (11)
IBTBT is then obtained by integrating (6) numerically. The
As shown in Fig. 8(b), increasing kspa from 2 to 16 can modeled IBTBT is compared against the numerical simulation
reduce ISDT by a factor of 12 for L g = 10 nm and in Fig. 9(a) and (b). Similar to the discussion of the effect
d = 1 nm. However, increasing kspa also causes larger of gate-to-drain fringe fields when modeling ISDT , IBTBT is
parasitic capacitances and degrades the circuit speed [34]. also a function of kspa . The higher the kspa value, the stronger
These results indicate that lowering ISDT may degrade the the fringe fields, the more gradual the E c profile at the
speed performance (i.e., increase delay), a manifestation of gate-drain junction, and the smaller the IBTBT value. Empir-
the energy-delay tradeoffs. Note that (11) is a first-order ically, λBTBT (nm) = 0.092kspa + 2.13 is determined by
approximation, and the empirical coefficients are determined fitting the IBTBT model to the numerical simulation result.
LEE et al.: COMPACT VS MODEL FOR CNFETs IN THE SUB-10-nm REGIME 3075

Fig. 10. Representative Id versus Vgs of a CNFET with L g = 8 nm and

d = 1.3 nm, showing that the tunneling currents dominate over the thermionic
emission current in the subthreshold region.

Note that phonon-assisted and trap-assisted tunneling [35] are

not considered in this model, so IBTBT = 0 when Vds < E g .
In addition, since the tunneling model presented in this paper
is calibrated to the NEGF-based numerical simulation with Fig. 11. Dimensional scaling trend of major foundries collected from the
a relatively simple GAA cylindrical device structure [30] published data (unit in nm). The geometric pitch is defined as (metal-1 pitch
× contacted gate pitch)1/2 . The dashed lines beyond the 16/14-nm node are
assuming ballistic transport, the model aims to provide a trend projections by linearly extrapolation from the nodes over the last 10 years.
instead of accurate results.
IV. CNFET P ERFORMANCE A SSESSMENT
The intrinsic elements of the VS-CNFET model introduced
in [16] are then combined with the extrinsic elements
described in Sections II and III to assess the CNFET design
space and performance. A representative Id versus Vgs
curve given by the complete VS-CNFET model separately
identifying the current components—thermionic emission,
direct SDT, and BTBT currents—is shown in Fig. 10. It can
be seen that the tunneling currents can dominate over the
thermionic emission current in the subthreshold region of a Fig. 12. Optimization of the CNFET dimensions (L g , L c , and L ext )
short-channel CNFET. to minimize the gate delay under the constraints of L pitch = 31 nm and
In this section, we demonstrate the capability of the IOFF = 100 nA/μm. ρcnt = 100 CNTs/μm and d = 1.2 nm are used.
VS-CNFET model by optimizing L g , L c , L ext , and
CNT diameter to minimize the CNFET gate delay (τgate )
and estimating the requirement for CNT density (ρcnt ≡ 1/s, helps to improve the device speed because of lower intrinsic
where s is the spacing between CNTs, see Fig. 1) to meet the capacitance and higher drive current, but also increases the
ITRS targets of drive current. For advanced CMOS technology, OFF -state current (I OFF , defined as the Id at Vgs = 0 and
the dimensional scaling is no longer simply the scaling of L g Vds = Vdd ) and thus the static power. Hence, there exists
but a multivariable optimization that targets a technology an optimal L g to balance the speed and power consumption.
pacing objective. Fig. 11 shows the dimensional scaling L c is preferred to be as long as possible in order to lower the
trend of major foundries as well as the projections down to Rc value (ignoring the possible increase in the parasitic capac-
the so-called 5-nm technology node by linear extrapolation. itance at the circuit level). Scaling down L ext helps to reduce
While foundries tend to scale the metal-1 pitch (L M1 ) and Rext but drastically increase the parasitic capacitance (Cpar ).
the contacted gate pitch (L pitch , as shown in Fig. 1) at For CNFETs, Rext is negligible compared with Rc in general,
different paces, the geometric pitch L GP ≡ (L M1 · L pitch )1/2 so L ext is preferred to be large.
scales at a relatively consistent pace. Here, we use this L GP In Fig. 12, L g , L c , and L ext are optimized under the
to pace the advancement of logic technology. The CNFET constraints of L pitch = 31 nm and IOFF = 100 nA/μm (by
performance is evaluated at the 5-nm node corresponding to adjusting the flat-band voltage Vfb ) to minimize τgate ≡
L GP = 28.1 nm, L M1 = 25.2 nm, and L pitch = 31.1 nm. (L g Cinv + Cpar ) · Vdd /ION , where Cpar is calculated by the
The 2023 node of the 2013 ITRS projections [17] is used analytical models of [36], in which the gate-to-extension fringe
as a reference point, which also predicts L M1 will be capacitance (Cof ) and gate-to-contact capacitances (Cgtc ) are
scaled down to 25.2 nm in 2023 for high-performance considered (see Fig. 1). ρcnt = 100 CNTs/μm is assumed. The
logic. The corresponding ITRS parameters—supply voltage optimal design is arrived at L g = 11.7 nm, L c = 12.9 nm, and
Vdd = 0.71 V and EOT = 0.51 nm—are used as the inputs to L ext = 3.2 nm. Because the optimization goal is to minimize
the VS-CNFET model. Furthermore, a GAA device structure τgate and Rc is the major limiter of the drive current, L g is
is assumed (see Fig. 1) in the following analysis. scaled down until IOFF becomes intolerable, and L ext is scaled
Under the constraint of a fixed L pitch , tradeoffs exist down until Cpar becomes too large, in order to save space
between L g , L c , and L ext at the device-level. Scaling down L g for L c . It is worthwhile noting that while the optimal design
3076 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 9, SEPTEMBER 2015

Fig. 13. (a) ION versus IOFF for different diameters. The symbols are Fig. 14. Projection of the requirement for the CNT density to meet the
generated by sweeping Vfb from −0.1 to 0.1 V. CNTs with smaller d have 2013 ITRS target of ION = 1.33 mA/μm with fixed IOFF = 100 nA/μm
smaller ION mainly due to larger Rc . (b) Optimized gate delay (see Fig. 12) corresponding to metal-1 pitch = 25.2 nm. 2Rc ≈ 70 k per CNT is
versus diameter under different constraints of IOFF . ρcnt = 100 CNTs/μm is calculated by (2) with L c = 12.9 nm and d = 1.2 nm.
assumed.

experiments that the model is calibrated to [16]; L g = 11.7 nm

may vary as different parameters (e.g., CNT diameter) are and L c = 12.9 nm are used according to the optimization
used, the shape of the contour in Fig. 12 remains the same. result from Fig. 12. At L c = 12.9 nm, 2Rc ≈ 70 k per CNT,
It appears in Fig. 12 here that L g cannot scale below and ρcnt ≈ 180 CNTs/μm is needed in order to meet the
11 nm in order to keep IOFF ≤ 100 nA/μm, mainly due 2013 ITRS target of ION = 1.33 mA/μm (corresponding to
to SDT. Since SDT highly depends on the CNT diameter, L M1 = 25.2 nm); whereas when Rc can be reduced to zero,
the impact of the CNT diameter is studied in Fig. 13. the required ρcnt can be lowered to 40 CNTs/μm.
Fig. 13(a) shows ION versus IOFF for different diameters.
A minimum IOFF for each d is observed by sweeping Vfb : as V. D ISCUSSION
Vfb starts increasing, IOFF decreases exponentially because The analysis in Section IV exhibits the potential of
both thermionic emission and intra-SDT currents decrease; as scalability of CNFETs down to L pitch = 31 nm and capability
Vfb further increases beyond a certain point, inter-SDT starts of delivering high drive current with ON/OFF ratio >104. It is
to increase and becomes dominant, so IOFF increases. The important to review the assumptions made in the analysis. The
larger the diameter, the higher the IOFF value. In addition, interface between the gate dielectric and the CNTs is assumed
for small-diameter CNTs, reducing Vfb does not improve to be perfect, i.e., hysteresis of the I –V characteristics [8] is
ION effectively, because the Rc value is so large that the ION negligible, and the short-channel effect (e.g., SS degradation
value is dominated by the resistance of contacts rather than and Drain-Induced Barrier Lowering) is determined purely by
the channel. In Fig. 13(b), we co-optimize the CNT diameter, electrostatics. Recent progress in the CNT-dielectric interface
L g , L c , and L ext to minimize τgate under different constraints includes the use of Y2 O3 and LaO3 as gate dielectrics to
of IOFF . Each point along the curves has different optimized reduce the interface traps [40], [41] and interface passivation
L g , L c , and L ext . The optimal diameter increases as the to alleviate the hysteresis [8], [42]. The CNTs are assumed
constraint of IOFF increases, indicating that large-diameter to be perfectly aligned and equally spaced. The imperfect
CNTs are suitable for high-performance applications while alignment and variation in the CNT spacing result in delay
small-diameter CNTs are suitable for low-power applications. variations and potential functional failures. Process techniques
In the discussion above, the CNTs are assumed to be per- to achieve a good CNT alignment have been improved over
fectly aligned and equally spaced, and ρcnt = 100 CNTs/μm the years [43]. Design techniques can be employed to
is assumed. This CNT density is within reach experimentally overcome these imperfections at the modest cost of area and
as suggested in recent reports. The highest ρcnt to date energy consumption [10]. Nonetheless, improvement in the
through chemical vapor deposition is ≈30 CNTs/μm [37]. material is still strongly desired. The CNTs in a single device
By using multiple CNT transfers, ρcnt ≈ 100 CNTs/μm was are assumed to be identical in diameter, carrier mobility, and
achieved [38]. Although ρcnt > 500 CNTs/μm has been velocity. However, Cao et al. [9] measured the distribution
reported in [39] by assembling solution-based CNTs using the of CNT diameter and mobility, showing that the variations
Langmuir–Schaefer method on a target substrate, the CNTs are not negligible. As these imperfections are considered,
were not well aligned and the measured Rc ≈ 3 M/CNT, the projections described in Section IV need to be adjusted,
about 100× the value reported in [23]. While high ρcnt has but the general conclusion should remain unchanged (e.g.,
been reported in these works, the control of CNT pitch still tradeoff between contact resistance and tunneling currents
remains to be a challenge. Variations in the CNT pitch can due to the selection of CNT diameter).
degrade CNFET performance and reduce circuit yield. The Since the CNT diameter is shown to have a great impact
issue of CNT variations has been discussed in [10], and is out on Rc , ISDT , and thus the CNFET performance, we next revisit
of the scope of this paper. the model and discuss its validity. The dependence of Rc on d
To estimate the ρcnt required for CNFETs to deliver is characterized in (3) by E 00 , which can be viewed (loosely)
enough drive current (assuming no variations), Fig. 14 shows as the inverse of the Schottky barrier width at the metal-CNT
ION versus ρcnt with a fixed IOFF = 100 nA/μm; d = 1.2 nm is contacts. Smaller E 00 leads to higher sensitivity of Rc to the
used for the analysis, because it is the diameter measured in the CNT diameter. In this paper, E 00 = 32 meV is extracted
LEE et al.: COMPACT VS MODEL FOR CNFETs IN THE SUB-10-nm REGIME 3077

from [20]. However, the detailed experimental studies on the [2] M. Luisier, M. Lundstrom, D. A. Antoniadis, and J. Bokor,
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[28] H. Kawaura, T. Sakamoto, and T. Baba, “Observation of source-to- Eric Pop (M’99–SM’11) received the B.S. and
drain direct tunneling current in 8 nm gate electrically variable shallow M.S. degrees from the Massachusetts Institute
junction metal–oxide–semiconductor field-effect transistors,” Appl. Phys. of Technology, Cambridge, MA, USA, and the
Lett., vol. 76, no. 25, pp. 3810–3812, Apr. 2000. Ph.D. degree from Stanford University, Stanford,
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semiconducting nanotube and graphene nanoribbon p-n junctions,” Appl. He was with the University of Illinois at
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(2010). Cylindrical CNT MOSFET Simulator. [Online]. Available: Professor of Electrical Engineering with Stanford
https://nanohub.org/resources/moscntr University. His current research interests include
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Nanotube Field-Effect Transistors Model, Technical User’s Manual. 2-D and 1-D devices and materials, and energy conversion and harvesting.
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device footprint scaling on high-performance CMOS logic technology,” Ph.D. degree in electrical engineering from Purdue
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[35] S. O. Koswatta, M. S. Lundstrom, and D. E. Nikonov, “Band-to-band He is currently an Associate Professor with the
tunneling in a carbon nanotube metal-oxide-semiconductor field-effect Department of Electrical and Computer Engineering,
transistor is dominated by phonon-assisted tunneling,” Nano Lett., vol. 7, Duke University, Durham, NC, USA. His current
no. 5, pp. 1160–1164, Mar. 2007. research interests include nanomaterials in nanoelec-
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conducting channels,” IEEE Trans. Electron Devices, vol. 54, no. 9,
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S. Mitra, “High-performance carbon nanotube field-effect transistors,”
Wilfried Haensch (F’12) received the Ph.D. degree
in IEDM Tech. Dig, Dec. 2014, pp. 33.6.1–33.6.4.
from the Technical University of Berlin, Berlin,
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Germany, in 1981.
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He joined the IBM T. J. Watson Research, in
for high-performance electronics,” Nature Nanotechnol., vol. 8, no. 3,
2001, and is currently responsible for post CMOS
pp. 180–186, Jan. 2013.
device solution and Si technology extensions. He
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has authored has authored or co-authored over
subthreshold swing in carbon nanotube transistors using lanthanum
175 publications.
oxide,” Appl. Phys. Lett., vol. 102, no. 1, p. 013108, 2013.
He was awarded the Otto Hahn Medal for out-
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pp. 498–504, Jul. 2009.

Chi-Shuen Lee received the B.S. degree in Hon-Sum Philip Wong (F’01) received the
electrical engineering from National Taiwan Univer- B.Sc. (Hons.) degree from The University of Hong
sity, Taipei, Taiwan, in 2011, and the M.S. degree Kong, Hong Kong, the M.S. degree from Stony
in electrical engineering from Stanford University, Brook University, Stony Brook, NY, USA, and the
Stanford, CA, USA, in 2014, where he is currently Ph.D. degree from Lehigh University, Bethlehem,
pursuing the Ph.D. degree. PA, USA.
His current research interests include modeling He joined Stanford University, Stanford, CA,
and simulation of nanoscale MOSFETs and CMOS USA, in 2004, as a Professor of Electrical Engi-
technology assessment and benchmarking. neering, where he is currently the Willard R. and
Inez Kerr Bell Professor.