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Laboratory Manual
Electronic Devices and Technology (EET-224L)
Third Semester Electronic Engineering Technology

Electronic Engineering Department

Sir Syed University Of Engineering and Technology
University Road Karachi - 75300
http://www.ssuet.edu.pk
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Electronic Devices and Technology (EET-224L) Lab Manual

Electronic Devices and Technology

(ELT-224L)
Table of Contents

Lab # List of Experiments Page # Signature Remarks

To follow the process to identify the type of
1 transistor (NPN & PNP) & find its correct
pin configuration

2 To reproduce BJT circuit as a switch

To follow common emitter configuration of

3 BJT

Reproduce the BJT Fixed biased

configuration in order to perform DC
4
analysis

Reproduce the BJT emitter feedback biased

5 configuration in order to perform DC
analysis
Reproduce the BJT feedback biased
6 configuration in order to perform DC
analysis
7 Open – Ended Lab

Sketch Transfer Characteristic of N-channel

8
JFET
Display the output of DC analysis of self-
9
bias configuration of N-channel JFET
Measure the quantities ID, VGS, VDS be able
10 to do DC analysis of common source,
voltage divider bias JFET amplifier.
11 Measure the quantities ID, VGS, VDS be able

to do DC analysis of common drain (source

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Electronic Devices and Technology (EET-224L) Lab Manual

follower) N-channel JFET amplifier

Follow the circuit of common emitter BJT

12 amplifier to find the frequency response.

Trace the Lower critical frequency and
Upper critical frequency
Reproduce two stage BJT transistor
13 amplifiers and trace the AC analysis at both
stages of cascaded transistor.
14 Open – Ended Lab
Electronic Devices and Technology (EET-224L) Lab Manual

Electronic Devices & Technology (ELT-224L), 3rd Semester, Batch 2020F

Name of Student: Roll No.

Criteria Exceeds Expectations Meets Developing Unsatisfactory

(>=90%) Expectations (50%-69%) (<50%)
(70%-89%)
Able to setup Able to setup Can setup major part Can’t set up the
experiment experiment of the experiment experiment even
Experimental
independently with independently with with assistance with assistance
Setup
complete understanding adequate
(1)
of each step understanding of
each step
Able to follow the Able to follow the Able to follow major Unable to follow
procedure completely procedure part of the procedure the procedure
Procedure
with simplification or completely with errors or
(5)
develop alternate omissions
procedure
Able to achieve all the Able to achieve all Able to achieve Unable to achieve
Experimental
desired results with the desired results most of the desired the desired results
Results
alternate ways to results with errors
(2)
improve measurements
Extremely alert to Fairly alert to Rarely alert to Poorly alert about
practice safety measures practice safety practice safety safety measures in
Safety
in laboratory procedures measures in measures in laboratory
(1)
laboratory laboratory procedures
procedures procedures
Laboratory manual has Laboratory manual Laboratory manual Laboratory
no grammatical and/ or has very few has multiple manual has several
spelling errors. grammatical/ grammatical/ grammatical/
All sections of the spelling errors. spelling errors. spelling errors and
Laboratory
report are very well All sections of the Few sections of the sentence
Manual
written and technically report are report contain construction is
(1) accurate. technically accurate. technical errors. poor. All sections
of the report
contains multiple
technical errors.
Electronic Devices and Technology (EET-224L) Lab Manual
Rubric -Laboratory Manual

Electronic Devices & Technology (ELT-224L), 3rd Semester, Batch 2020F

Name of Student: Roll No.
Lab Description & Score

1. Experimental Procedur Results Safety Lab Report

Setup ( )/1 e( )/5 ( )/2 ( )/1 ( )/1

2. Experimental Procedur Results Safety Lab Report

Setup ( )/1 e( )/5 ( )/2 ( )/1 ( )/1

3. Experimental Procedur Results Safety Lab Report

Setup ( )/1 e( )/5 ( )/2 ( )/1 ( )/1

4. Experimental Procedur Results Safety Lab Report

Setup ( )/1 e( )/5 ( )/2 ( )/1 ( )/1

5. Experimental Procedur Results Safety Lab Report

Setup ( )/1 e( )/5 ( )/2 ( )/1 ( )/1

6. Experimental Procedur Results Safety Lab Report

Setup ( )/1 e( )/5 ( )/2 ( )/1 ( )/1

7. Experimental Procedur Results Safety Lab Report

Setup ( )/1. e( )/5 ( )/2 ( )/1 ( )/1

8. Experimental Procedur Results Safety Lab Report

Setup ( )/1 e( )/5 ( )/2 ( )/1 ( )/1

9. Experimental Procedur Results Safety Lab Report

Setup ( )/1 e( )/5 ( )/2 ( )/1 ( )/1

10. Experimental Procedur Results Safety Lab Report

Setup ( )/1 e( )/5 ( )/2 ( )/1 ( )/1

11. Experimental Procedur Results Safety Lab Report

Setup ( )/1 e( )/5 ( )/2 ( )/1 ( )/1

12. Experimental Procedur Results Safety Lab Report

Setup ( )/1. e( )/5 ( )/2 ( )/1 ( )/1

13. Experimental Procedur Results Safety Lab Report

Setup ( )/1. e( )/5 ( )/2 ( )/1 ( )/1

14. Experimental Procedur Results Safety Lab Report

Setup ( )/1 e( )/5 ( )/2 ( )/1 ( )/1
TOTAL SCORE
Overall Score: out of 15 Examined by:
(Obtained Score / Total Score) x 15 (Name and Signature of concerned
lab instructor)
Electronic Devices and Technology (EET-224L) Lab Manual

Rubric for Subject Project

Electronic Devices & Technology (ELT-224L),3rd Semester, Batch 2020F

Name of Student: Roll No.

Criteria Exceeds Meets Developin Unsatisfactor Score
Expectation Expectations g (50%- y (<50%) Obtained
s (70%-89%) 69%)
(>=90%)

Able to Able to demonstrate Able to Able to

demonstrate the the project with demonstrate the demonstrate the
project with achievement of project with project with
achievement of required objectives achievement of achievement of
required but understanding a*t least 50% less than 50%
objectives having of project required required
Project clear limitations and objectives and objectives and
Demonstration understanding of future insufficient lacks in
(5) Marks project limitations enhancements is understanding of understanding of
and future insufficient. project limitations project
enhancements. Hardware and/or and future limitations and
Hardware and/or Software enhancements. future
Software modules are Hardware and/or enhancements.
modules are fully functional, if Software Hardware and/or
functional, if applicable. modules are Software
applicable. partially modules are not
functional, if functional, if
applicable. applicable.

Able to achieve all Able to achieve Able to achieve Unable to

Project results the desired results all the desired most of the achieve the
with alternate results desired results desired results
( 3 ) Marks
ways to improve with errors
measurements

Project report has Project report Project report Project report has
no grammatical has very few has multiple several
Project Report and/ or spelling grammatical/ grammatical/ grammatical/
errors. spelling errors. spelling errors. spelling errors
( 5 ) Marks
All sections of the All sections of the Few sections of and sentence
report are very report are the report contain construction is
well- written and technically technical errors. poor.
technically accurate.
accurate.

Viva Able to answer the Able to answer the Able to answer Unable to
(2) Marks questions easily questions related the questions but answer the
and
to the project with mistakes questions
correctly across
the project.

Total Marks (Out of 15)

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Electronic Devices and Technology (EET-224L) Lab Manual

Electronic Devices & Technology (ELT-224L),3rd Semester, Batch 2020F

Name of Student: Roll No.

Criteria Exceeds Meets Developing Unsatisfacto Score

Expectations Expectations (50%- ry Obtained
(>=90%) (70%-89%) 69%) (<50%)
Perform
ance Able to present full Able to present Able to present No or very
knowledge of both adequate knowledge sufficient less
( 10 ) problem and solution. of both problem and knowledge of both knowledge
Marks solution problem and of both
solution problem
and solution
Viva
( 5 ) Marks Able to answer the Able to answer Able to Unable
questions easily and the questions answer the to
correctly questions but answer
with mistakes the
question
s
Total Marks (Out
of __)

Final Lab Assessment

CLO Criteria Score

No Bloom's Obtaine
Taxonomy d
Laboratory Manual
Marks( 15 )  
Subject Project (if
( 1 ) ( P4 )
any) Marks( 15 )  
Lab Performance
Marks( 15 )  
( 2 ) ( A4 ) Viva
Marks( 5 )  
Total
( 50 ) Marks  

Examined by:

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(Name and Signature of concerned lab instructor)

Laboratory Exercise 1
Objective: To follow the process to identify the type of transistor
(NPN & PNP) & find its correct pin configuration.

Apparatus/Component:
 Breadboard (for testing)
 6 PNP & NPN transistors available in lab
 Multimeter

Description/Theory:
The BJT (bipolar junction transistor) is constructed with three doped semiconductor regions
separated by two pn junctions. The three regions are called emitter, base, and collector. One type
consists of two n regions separated by a p region (npn), and the other type consists of two p regions
separated by an n region (pnp). The pn junction joining the base region and the emitter region is
called the base-emitter junction. The pn junction joining the base region and the collector region is
called the base-collector junction. A wire lead connects to each of the three regions. These leads are
labeled E, B, and C for emitter, base, and collector, respectively. The base region is lightly doped
and very thin compared to the heavily doped emitter and the moderately doped collector regions.

Identifying BJT Types:

Both NPN and PNP transistor looks similar in physical appearance. We cannot differentiate by
seeing them. We need a multimeter to identify the type of BJT.
Remember the following points:
1. The transistor internally has two diodes (NPN ≡ N - P - N ≡ NP Junction + PN Junction and
PNP ≡ P - N - P ≡ PN Junction + NP Junction).
i.e.,Emitterto base is one PN junction (diode) and Base to collector another PN junction (diode).
2. In the diode mode, the multimeter will show the voltage when we keep the positive probe of
the multimeter to the anode of the diode and negative probe to the cathode.
3. If the multimeter positive probe is connected to the cathode of the diode and the negative
probe to the anode, then it will not give any voltage (showing zero).

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Fig 8-1: BJT Transistor Circuit Symbols

Identifying NPN terminals:

In NPN bipolar transistor, there is a PN junction formed from base to collector, and another PN
junction formed from base to emitter. So, by testing each "diode candidate", you can determine
which pin is the base. diode test function can determine whether a diode is forward biased.  The
common "P" will be the base. The other two pins will be the collector and emitter. A "diode test"
function gives the voltage drop across the forward-biased diode being tested, you can compare the
voltage drop across the two diode candidates. The one with the higher voltage drop will correspond
with the emitter of the transistor.

Circuit Diagram:

Fig 8-2: NPN and PNP Transistor Biasing

Observation:

Table 8-1: Identify the type of transistor

S. No. Transistor Name Type(NPN/PNP) Pin Configuration

Result/conclusion:

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Exercise:

1. Write the in-detail process to identify PNP terminals

_____________________________________________________________________________

_____________________________________________________________________________

2. Write the process to determine ß

_____________________________________________________________________________

_____________________________________________________________________________

Date: ______________ Teacher’s Sign_____________________

Laboratory Exercise 2

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Objective: To reproduce BJT circuit as a switch

Apparatus/Component:

 Resistors 1k, 360k

 Transistor 2N1904 Cor 2N2222 or any general purpose NPN transistor
 LED
 Switch push button)
 DC supply
 Multimeter

Description/Theory:

The term transistor comes from the words Transfer and resistor, meaning that it changes resistance.
As an active device, the transistor can be used as an electronic switch. It changes between very low
resistance (Short circuit) and very high resistance (Open circuit).

Circuit Diagram:

Fig 8-3: BJT transistor as a switch

Exercise:

Write the in-detail the step by process through which you determined BJT working as switch

_________________________________________________________________________________

_________________________________________________________________________________

Date: ______________ Teacher’s Sign_____________________

Laboratory Exercise 3
Objective: To follow common emitter configuration of BJT.
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Apparatus/Component:
 Power supply (adjustable From 0 to 15V)
 Transistor (2N3904 or any NPN silicon transistor)
 Resistor 1/2W (100Ω, 1kΩ, 470kΩ)
 VOM (Analog or Digital Multimeter)

Description/Theory:
A Bipolar Junction Transistor or BJT is a three terminal device having two PN- junctions
connected together in series. Each terminal is given a name to identify it and these are known as the
Emitter (E), Base (B) and Collector (C). There are two basic types of bipolar transistor construction,
NPN and PNP, which basically describes the physical arrangement of the P-type and N-type
semiconductor materials from which they are made. Bipolar Transistors are "CURRENT"
Amplifying or current regulating devices that control the amount of current flowing through them in
proportion to the amount of biasing current applied to their base terminal.
The principle of operation of the two transistors types NPN and PNP, is exactly the same the
only difference being in the biasing (base current) and the polarity of the power supply for each type.
The symbols for both the NPN and PNP bipolar transistor are shown above along with the direction
of conventional current flow. The direction of the arrow in the symbol shows current flow between
the base and emitter terminal, pointing from the positive P-type region to the negative N-type region,
exactly the same as for the standard diode symbol. For normal operation, the emitter-base junction is
forward-biased and the collector-base junction is reverse-biased. As an approximation of transistor
behavior, we use the Ebers-Moll model.
The emitter diode acts like a controlled current source. The voltage across the emitter diode
of a small signal transistor is typically 0.6 to 0.7V. For most troubleshooting & design, we will use
0.7V for the VBE drop. In this experiment, you will get data for calculating the αdc, βdc & the VBE drop.

Circuit Diagram:

Fig 8-3: Fixed Biased Configuration Circuit.

Observation:
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Table 8-2: NPN Transistors Parameters

Transistor VBE VCE IB IC
1.
2.
3.

Table 8-3: PNP Transistors Parameters

Transistor VCB IE άDC ßDC
1.
2.
3.

Result/Conclusion:

Date: ______________ Teacher’s Sign_____________________

Laboratory Exercise 4
Objective: Reproduce the BJT Fixed biased configuration in order to perform DC analysis

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Description/Theory:
Before we can use a transistor to amplify an ac signal, we have to setup a Q point of operation,
typically near the middle of the dc load line. Then the incoming ac signal can produce fluctuation
above and below this Q point. The three most primitive forms of bias are Base bias, Emitter-
feedback bias and Collector-feedback. But these are not the best ways to bias a transistor if a stable
Q point is required. Voltage divider bias configuration is such a network in which effect of beta
variation is virtually eliminated so that it will provide a stable Q point.

Apparatus/Components:
 Transistor C828, 2N3904
 ½-w Resistors: 820kΩ, 56 kΩ, 2.2kΩ & 1kΩ
 Adjustable Power Supply
 Multi-meter

Circuit Diagram:
Fixed biased:

Fig 9-1: Fixed Biased Configuration Circuit.

Formulas:

 IB=VCC-VBE
RB
 IC = β × IB
 V CE =V CC - I CR C
Observations:

Table 9-1: Fixed Biased Parameters of Transistor.

Measured Calculated
Transistor 
IB IC VCE IB IC VCE

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Result/Conclusion:

Date: ______________ Teacher’s Sign_____________________

Laboratory Exercise 5
Objective: Reproduce the BJT emitter feedback biased configuration in order to perform DC
analysis
Description/Theory:

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Before we can use a transistor to amplify an ac signal, we have to setup a Q point of operation,
typically near the middle of the dc load line. Then the incoming ac signal can produce fluctuation
above and below this Q point. The three most primitive forms of bias are Base bias, Emitter-
feedback bias and Collector-feedback. But these are not the best ways to bias a transistor if a stable
Q point is required. Voltage divider bias configuration is such a network in which effect of beta
variation is virtually eliminated so that it will provide a stable Q point.

Apparatus/Components:
 Transistor C828, 2N3904
 ½-w Resistors: 820kΩ, 56 kΩ, 2.2kΩ & 1kΩ
 Adjustable Power Supply
 Multi-meter

Emitter Feedback Bias:

Fig 9-2: Emitter Feedback Bias Configuration Circuit.

Formulas:

 IB=VCC-VBE-VE
RB
 IC = β × IB
 V CE =V CC - IC(R C + RE)

Observations:
Table 9-2: Emitter Feedback Bias Configuration Circuit.
Measured Calculated
Transistor 
IB IC VCE IB IC VCE

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Result/Conclusion:

Date: ______________ Teacher’s Sign_____________________

Laboratory Exercise 6

Objective: Reproduce the BJT collector feedback biased configuration in order to perform DC
analysis
Description/Theory:

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Before we can use a transistor to amplify an ac signal, we have to setup a Q point of operation,
typically near the middle of the dc load line. Then the incoming ac signal can produce fluctuation
above and below this Q point. The three most primitive forms of bias are Base bias, Emitter-
feedback bias and Collector-feedback. But these are not the best ways to bias a transistor if a stable
Q point is required. Voltage divider bias configuration is such a network in which effect of beta
variation is virtually eliminated so that it will provide a stable Q point.

Apparatus/Components:
 Transistor C828, 2N3904
 ½-w Resistors: 820kΩ, 56 kΩ, 2.2kΩ & 1kΩ
 Adjustable Power Supply
 Multi-meter

Collector Feedback Bias:

Fig 9-3: Collector Feedback Bias Configuration Circuit.

Formulas:

 IB=VC-VBE
RB
 I C = VC-VBE
RC + RB/β
 V CE =V CC - I CR C

Observations:

Table 9-3: Collector Feedback Bias Configuration Circuit.

Measured Calculated
Transistor 
IB IC VCE IB IC VCE

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Result/Conclusion:

Date: ______________ Teacher’s Sign_____________________

Laboratory Exercise 7
Name: ___________________________ Roll No: ______________________

Open-Ended LAB

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Title:

1. Objective:

2. Hardware/Software required:

3. Diagram:

4. Methodology:

5. Observation:

6. Results and Discussions:

7. Conclusion:

Date: ______________ Teacher’s Sign_____________________

Laboratory Exercise 8
Objective: Sketch Transfer Characteristic of N-channel JFET.

Apparatus/Components:
 Transistor: K105 (n-channel)
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 ½-w Resistors: 1MΩ, 3.3kΩ &1kΩ

 Adjustable Power Supply
 Multi-meter

Transfer Characteristic of N-channel JFET

Description/Theory:
The transfer characteristics are plot of an output (drain) current versus an input controlling quantity
(VGS). The transfer characteristics are useful in evaluating the operating conditions of a FET. To
determine these characteristics VDS is kept at a constant voltage level and VGS is varied while ID is
measured. The resulting graph is non linear i.e., it grows exponentially with increasing values of
VGS. It is also called a square law curve because of the squared term in the equation (Shockley’s)
from which ID is determined.

 ID = IDSS (1- VGS/VP)2

Circuit Diagram:

Fig 10-1: JFET Configuration Circuit.

Observation:
Table 10-1: JFET Parameters.
S.no VGS (volts) ID (mA)

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VP = ______________

IDSS = _______________

Graph:
Plot the JFET transfer characteristic curve of VGS against ID on separate graph sheet and attach here.

Result/Conclusion:

Date: ______________ Teacher’s Sign_____________________

Laboratory Exercise 9
Objective: Display the output of DC analysis of Self-Bias configuration of N-channel
JFET.

Theory:
In self-bias configuration only one dc supply is required. Gate terminal is at zero volt (0V) because
gate resistor is grounded .The controlling gate to source voltage depend on the voltage develop
across source resistance.

Circuit Diagram:

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Fig 10-2: JFET Self-Bias Configuration Circuit.

Observation:
Table 10-2: DC Voltages of JFET Self-Bias Configuration
VD VG VS VDS VGS
Quantity
(volts) (volts) (volts) (volts) (volts)
Measured
Calculated

Table 10-3: DC Currents of JFET Self-Bias Configuration

ID IS IG
(mA) (mA) (mA)
Measured
Calculated

Result/Conclusion:
_________

Date: ______________ Teacher’s Sign_____________________

Laboratory Exercise 10
Objective: Measure the quantities ID, VGS, VDS be able to do DC analysis of common
source, voltage divider bias JFET amplifier.

Description/Theory:

In voltage divider bias configuration when large supply voltages are available it gives relatively
stable Q-point. The voltage divider bias arrangement applied to the BJT transistor amplifiers is also
applied to FET amplifiers. The basic construction is exactly the same, but the DC analysis of each is
quite different. The voltage gain of a common-source amplifier is determined largely by trans-
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conductance, gm and drain resistance RD. There is 1800 phase inversion between gate and drain
voltages.

Apparatus/Components:
 Transistor K105 (N-Channel JFET)
 ½-w Resistors: 4.7Ω, 1MΩ, 3.3kΩ & 2.2kΩ
 Capacitors: 47F (one), 10F (two)
 Adjustable Power Supply
 Frequency generator
 Multi-meter
 Oscilloscope

Circuit Diagram:

Fig 11-1: JFET Voltage Divider Configuration Circuit.

Observation:

Table 11-1: DC Analysis of JFET Voltage Divider Configuration

Quantity VGS VDS VS ID

(volts) (volts) (volts) (mA)

Measured
Calculated

Result/Conclusion:
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Date: ______________ Teacher’s Sign_____________________

Laboratory Exercise 11
Objective: Measure the quantities ID, VGS, VDS be able to do DC analysis of common
drain (source follower) N-channel JFET amplifier.

Description/Theory:
The common drain amplifier, better known as the source follower, is analogous to the emitter
follower. The voltage gain approaches unity and the input impedance approaches infinity, limited
only by the external biasing resistors connected to the gate. The source follower is a popular circuit
often found near the front end of measuring instruments.

 AV = (gmRs)
1+gmRs

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 gm= gm0 (1- VGS/VP)

 gm0 = 2 IDSS / |VP|

Apparatus/Components:
 Transistor K105 (N-Channel JFET)
 ½-w Resistors: 220kΩ, 100kΩ & 2.2kΩ
 Capacitors:10F (two)
 Adjustable Power Supply
 Frequency generator
 Multi-meter
 Oscilloscope

Circuit Diagram:

220kΩ

Fig 11-2: JFET Common Drain Configuration Circuit.

Observation:
Table 11-2: DC Analysis of JFET Common Drain Configuration

Quantity VGS VDS VS ID

(volts) (volts) (volts) (mA)

Measured
Calculated

Table 11-3: AC Analysis of JFET Common Drain Configuration

Vi (p-p) Vo (p-p) Av (measured) Av (calculated)

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Result/Conclusion:

Date: ______________ Teacher’s Sign_____________________

Laboratory Exercise 12
(a) Follow the circuit of common emitter BJT amplifier to find the frequency response.
(b) Trace the Lower critical frequency and Upper critical frequency

Description/Theory:
A perfect amplifier with an amplification of times 10, as shown below, would give an output 10
times greater than the input. If the input was 10 mV then the output would be 100 mV, no matter the
frequency of the input signal, as seen in the graph below. This graph is known as a FREQUENCY
RESPONSE diagram.

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Fig 12-1: Ideal Frequency Response of Amplifier

In a practical amplifier it is not possible to obtain a perfectly flat response curve.

This is due to limitations of electronic components and circuitry. The two points on the response
curve mark where the output of the amplifier has fallen to 70.7 % of the maximum output. This
means that that the 100mV output has fallen to 70.7 mV at these frequencies. These are called the -3
dB points.

Fig 12-2: Practical Frequency Response of Amplifier

Dominant Critical Frequency for Low Frequency Response:

It will be highest value of all (three) low frequencies

Dominant Critical Frequency for High Frequency Response:

It will be lowest value of all (two) low frequencies

Bandwidth of the Amplifier:

Total bandwidth of the amplifier will be the difference of both dominant critical frequencies.

Apparatus/Components:

Transistor C828
½-w Resistors: 68kΩ, two 10kΩ, 5.6kΩ& 1kΩ
Capacitors two 0.1uf , 10uf.
Frequency generator
Adjustable Power Supply
Multi-meter
Oscilloscope

Circuit Diagram:

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Fig 12-3: Common Emitter BJT Amplifier

Observations:
Table 12-1: BJT Common Emitter Amplifier Parameters
Sr # Frequency Log (f) Vo(p-p) Av = Vo/Vin Av(dB)
(Hz) (volts)

Vi(p-p) =
Lower critical frequency (f )
CL = ____________________
Upper critical frequency (f )
CU = ____________________
Band Width (BW) = ____________________

Graph:
Draw frequency response curve on Bode Plot on graph sheet and attach here.

Result/Conclusion:
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Date: ______________ Teacher’s Sign_____________________

Laboratory Exercise 13
Objective: Reproduce two stage BJT transistor amplifiers and trace the AC analysis at both
stages of cascaded transistor.

Description/Theory:
Transistors are usually connected in various configuration or stages to perform different
tasks. By connecting two transistor amplifiers in the common-emitter configuration, more gain can
be obtained from one supply voltage. To accomplish this, the output signal from the first stage is
input or coupled into the next stage. This type of amplifier is called a cascaded amplifier because it
uses more than one transistor.

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All the concepts that applied to the single stage transistor amplifier are applicable in this
experiment. This transistor must be a properly biased in each stages, and both transistor will have
same polarity: NPN or PNP. In the circuit shown in Fig. 45-1, note the bias resistors on Q1, the first
stage transistor. Here Ra and Rb provide voltage divider bias and Rc is the collector resistor, and Re
is the emitter resistor. The bias resistors on Q2 act exactly the same as those used for Q1. In fact they
can be the same exact values.

Notice also that capacitor that keeps the DC current isolated between stages and passes or couples
the AC output signal from stage 1 into stage 2.

 AV1 = RC1 // Zin2

RE1 + re1
 Zin2 = RB2 // RB2 // β (RE2 + re2)
 AV2 = RC2 // RL
RE2
 AVT = AV1X AV2

Apparatus/Components:

 Transistor C828
 ½-w Resistors: 68kΩ, 10kΩ, 5.6kΩ & 1kΩ
 Capacitors: 10F (three)
 Adjustable Power Supply
 Frequency generator
 Multi-meter
 Oscilloscope

Circuit Diagram:

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Fig 13-1: Cascaded BJT Amplifier Circuit.

Observation:

Table 12-1: DC Biasing of Cascaded BJT Amplifier

Measured Calculated
Measured
Nominal values Voltages with Currents with
Stage # Voltages with stages
(Ohms) stages stages
disconnected
connected connected
1 68kΩ
1 10kΩ
1 5.6kΩ
1 1kΩ
2 68kΩ
2 10kΩ
2 5.6kΩ
2 1kΩ

Calculations

Two Stages (Overall Gain):

Vin = ___20 mV__

Vout = ___________
Av (Measured) = ___________
Av (Calculated) = ___________

Note, Vout = stage 2 output

Single Stages (Individual Gain):

Stage 1:

Vin = ___20 mV__

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Vout = ___________
Av (Measured) = ___________
Av (Calculated) = ___________

Stage 2:

Vin = ___20 mV__

Vout = ___________
Av (Measured) = ___________
Av (Calculated) = ___________

Result/Conclusion:

Date: ______________ Teacher’s Sign_____________________

Laboratory Exercise 14
Name: ___________________________ Roll No: ______________________

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Open-Ended LAB

Title:

8. Objective:

9. Hardware/Software required:

10.Diagram:

11.Methodology:

12.Observation:

13.Results and Discussions:

14. Conclusion:

Date: ______________ Teacher’s Sign_____________________

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