SPAD P IXELS F OR UV I MAGING

by

ZHENJIE WANG

1300723

MASTER OF SCIENCE

IN

MIKROSYSTEMTECHNIK

Analogue Circuits and Image Sensors

University of Siegen

Siegen, Germany

December, 2021
 Candidate’s Declaration

This is to certify that the work presented in this thesis entitled, “SPAD Pixels For UV
Imaging”, is the outcome of the research carried out by ZHENJIE WANG under the
supervision of Prof. Dr. Bhaskar Choubey, University of Siegen, Germany.

It is also declared that neither this thesis nor any part thereof has been submitted any-
where else for the award of any degree, diploma, or other qualifications.

Signature of the Candidate

ZHENJIE WANG
1300723

ii
 Dedication

I must express my very profound gratitude to my parents for supporting me every way
possible and continuous encouragement throughout my years of study.

iii
Contents

Candidate’s Declaration ii

Dedication iii

List of Figures vii

List of Tables x

Acknowledgement xi

Abstract xii

1 Introduction 1
1.1 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Why CMOS SPADs? . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Why UV Imaging? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Objectives of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Background 5
2.1 Single-Photon Avalanche Diode . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.2 Breakdown Voltage and Excess Bias . . . . . . . . . . . . . . . 7
2.2 Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1 The Guard Ring . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2 Planar SPADs . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

iv
 2.3 Schemes for Quenching and Recharge . . . . . . . . . . . . . . . . . . 11
2.3.1 Passive Quenching . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.2 Active Quenching . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.3 Active Recharge . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 A Simple, Quantitative SPAD Model . . . . . . . . . . . . . . . . . . . 14
2.5 Definition of SPAD Figures of Merit . . . . . . . . . . . . . . . . . . . 14
2.5.1 Photon Detection Efficiency . . . . . . . . . . . . . . . . . . . 14
2.5.2 After-pulsing Probability . . . . . . . . . . . . . . . . . . . . . 15
2.5.3 SPAD Dead Time . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.4 Dark Count Rate . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.5 Fill-factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5.6 Spectral Range . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3 Proposed Pixel Architecture in XS018 17

3.1 Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Quenching Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Switch to XH018 Process . . . . . . . . . . . . . . . . . . . . . . . . . 21

4 Proposed Pixel Architecture in XH018 23

4.1 Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 NAND, AND, OR Gates . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3 Delay elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.4 D-flip-flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.5 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.6 Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.7 Quenching Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5 Results Discussion 37
5.1 Single Photon Avalanche Diode Array . . . . . . . . . . . . . . . . . . 37

v
 5.2 Pixel Layout Optimization . . . . . . . . . . . . . . . . . . . . . . . . 39
5.3 Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6 Conclusions 44

References 47

vi
List of Figures

2.1 Current-voltage characteristics for a p-n junction. . . . . . . . . . . . . 6

2.2 Illustration of guard ring and PEB prevention mechanisms in planer SPAD 9
2.3 SPAD structure with STI-based guard rings . . . . . . . . . . . . . . . 9
2.4 Cross-sections of planar SPADs [1] . . . . . . . . . . . . . . . . . . . . 10
2.5 Illustration of passive quenching circuits [2] . . . . . . . . . . . . . . . 12
2.6 Illustration of active quenching/recharge circuits . . . . . . . . . . . . . 13
2.7 The traditional SPAD model. The ideal switch is used to simulate the
occurrence of an avalanche. . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Proposed SPAD cross-section. . . . . . . . . . . . . . . . . . . . . . . 18

3.2 SPAD layout. UV window is inserted as a top opening. All regions
except the active region are covered with metal. DRC clean. . . . . . . 18
3.3 Schematic of quenching/recharge circuits . . . . . . . . . . . . . . . . 19
3.4 Simulation results of the quenching/recharge circuits. 1 ns = 1 Gbits PDR. 20
3.5 Quenching/recharge layout . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1 Principle application of SPAD dspb . . . . . . . . . . . . . . . . . . . . 24

4.2 Schematics, symbols and layouts of the digital elements. (a) NAND,
(b) inverter, (c) TG (d) AND, and (e) OR . . . . . . . . . . . . . . . . . 24
4.3 Simulation of the NAND, AND, OR, INV. The first line is AnandB, the
second line is AandB, the third line is AorB, the fourth line is -B, the
fifth line A and the sixth line B are the inputs. A has twice the period of
B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

vii
4.4 Simulation of 12u/5u inverter driving a 1.5 pF load. The first line is the
input and the second line is the output. . . . . . . . . . . . . . . . . . . 27
4.5 Delay elements: buffer, current-starved inverter (CSI) and switched ca-
pacitance. [3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.6 An edge-triggered D-flip-flop with a reset. Transistor count: 20 . . . . . 28
4.7 Proposed D-flip-flop schematic. Transistor count: 24 . . . . . . . . . . 28
4.8 Simulation of the flip-flops. The two flip flop results match. The first
line is the clock, the second line is clear, the third line is Din, and the
last four lines are the output of two Dffs. Each dff contains two outputs.
One is Q, and one is QB. . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.9 Proposed D-flip-flop layout. Length 11um, width 5um. DRC, LVS
clean. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.10 Schematics and symbols of the counters with row select. (a) 1-bit counter
schematic, (b) 1-bit counter symbol, (c) 2-bit counter schematic, (d) 2-
bit counter symbol and (e) 8-bit counter schematic . . . . . . . . . . . . 31
4.11 Simulation of a 9-bit digital counter. The first line is the clock signal.
The second line is the reset signal. The third line is the row select signal.
The rest are the outputs Q1 to Q9. . . . . . . . . . . . . . . . . . . . . 32
4.12 Counters layout. (a) 1-bit counter layout, (b) 2-bit counter layout and (c)
8-bit counter layout. Reset and row select are the common bus signals.
The 2-bit is the foundation and can be extended from 2-bit to higher
bits. The bottom flip-flop is flipped. Open the 8-bit counter layout view
to ensure that the CI, CIB, reset, and row select signals are at the right
position. The 9th bit counter is added separately. . . . . . . . . . . . . . 33
4.13 Shift register schematics. (a) 2-bit shift register schematic, (b) 2-bit
shift register symbol and (c) 8-bit shift register schematic . . . . . . . . 34
4.14 Simulation of an 8-bit shift register. 2-bit is the base and can be easily
expanded to 50-bits, corresponding to the activation of 50 rows of pixels. 35

viii
4.15 2-bit shift register layout. A 2-bit is the foundation unit. . . . . . . . . . 35
4.16 Schematic of quenching/recharge circuits. The width of the used tran-
sistors has been marked on the figure. Length remains unchanged and
is the default value. The output are directly readable digital pulses. The
sizes of the transistors have been marked on the diagram. . . . . . . . . 36
4.17 Quenching/recharge layout. Guard rings are to prevent latch-up. The
shared Nwell and ISOPW fix the vertical length. . . . . . . . . . . . . . 36

5.1 Simulation results of the SPAD pixel. A full pixel contains the diode,
the AQC and the 9-bit counter. . . . . . . . . . . . . . . . . . . . . . . 38
5.2 The layout of one pixel. (a) the basic block of each SPAD pixel and (b)
one pixel layout. Diode feature size = 12um.. . . . . . . . . . . . . . . 39
5.3 The layout of fully parallel 2×2 array. 2×2 array is the basic units.
With the addition of high voltage isolation, it is DRC and LVS clean. . . 40
5.4 The layout of 50×50 array and the zoom in on the top left. It contains
only a 50 by 50 array of pixels and does not contain a row selector or
readout unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.5 The low fill factor (FF) challenges of SPAD can be mitigated by making
the layout more compact, using micro-lens(not with UV range) and 3D
integration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.1 Simplified 50×50 array’s block diagram and the layout. (a) block dia-
gram (b) layout and the zoom in on the top left. The size of the 50×50
array is 1.8mm×2mm, and one pixel is 35um×40um. . . . . . . . . . . 46

ix
List of Tables

6.1 Performance comparison . . . . . . . . . . . . . . . . . . . . . . . . . 45

x
 Acknowledgement

I want to thank my supervisor Prof. Dr. Bhaskar Choubey, for his very patient guidance
and assistance. He is very knowledgeable and good at conveying knowledge, and I have
learnt a lot from him. His teaching style and enthusiasm made a strong impression on
me and I have always carried positive memories of his classes with me.

I want also to acknowledge Dr Andreas Bablich as the second reader of this thesis. I
want to thank him for taking the time to review my thesis.

Finally, I want to thank my school friends for their support and help. Thank you.

xi
 Abstract

SPAD operates in Geiger mode, is biased above its breakdown voltage, can be triggered
by generated carriers that ignite a self-sustaining avalanche multiplication process.

This report presents a compact 2D CMOS single-photon avalanche diode (SPAD) array
of 50×50 pixels, which is able to detect single photons in the UV wavelength range. A
quenching/recharge circuit is proposed to increase the speed and reliability of avalanche
quenching and recharge. Meanwhile, a compact 9-bit digital counter is applied to per-
form photo-counting operations for further processing.

The minimal quenching/recharge time is 1.5ns. The global pixel size is 35um×40um.
The feature size of the diode is 12um, giving a fill factor of 8%. The size of 50×50
array is 1.8mm ×2mm. The photon-detection probability at 405nm wavelengh is about
42%.

xii
CHAPTER 1. INTRODUCTION 1

Chapter 1

Introduction

In the past few years, with the popularity of smartphones, the research and design of
CMOS image sensors have developed rapidly. Many IDMs and fabless companies are
now developing a new generation of image sensors to fit the demands of new situations,
such as automobiles, medical care, security, etc. Some image sensors even need to
detect photons.

1.1 Problem Statement

Photons have wave-particle duality. It sometimes acts as waves and sometimes as parti-
cles. This property makes photons extremely versatile ranging from 3D-vision to health
care. When photons interact with semiconductors, photons act like particles and have
packetized energy. Photon energy absorbed in the depletion layer generates electrons
and holes, drifting in opposite directions and inducing current. These interactions allow
us to exploit the properties of photon detectors.

Photon detection requires sensors to detect photon arrival times and energies with rel-
atively low cost and low noise. However, conventional detectors are not suitable for
all situations, mainly because they are slow or don’t work in low light conditions, for
CHAPTER 1. INTRODUCTION 2

example, cars trying to detect people or objects in the dark. The speed and sensitivity
are often in contradiction with each other.

In Lidar autonomous vehicles, the surrounding scene is illuminated by a short pulse

laser and imaged by detectors. Based on the round trip time, we get the depth informa-
tion of the scene. But the reflected light may be too far away or feeble to receive. Many
pixels share the reflected light, and some may only receive less than one photon. The
high-end Lidar systems can be expensive and consume colossal power.

The SPADs provide a solution. Single-photon avalanche diode (SPAD), also known
as Geiger-mode avalanche photodiode, is biased slightly above its breakdown voltage.
A single electron-hole pair generates by light (or non-light) is sufficient to cause an
avalanche breakdown. The avalanche current increases exponentially and is digitally
detectable at the output. SPAD pixels have real single-photon sensitivity.

The current pulse will be sensed and controlled by active quenching circuits (AQC).
When the SPAD detects a photon, the AQC lowers the voltage across the SPAD to stop
the avalanche and subsequently resets the SPAD. So, each photon arrival is recorded
digitally by the pixel circuit. Digitization is achieved within the pixel, which offers
many advantages. For example, an analogue-to-digital converter (ADC) is unnecessary,
and the frame rate is very high.

1.2 Why CMOS SPADs?

SPAD fabricated in standard complementary metal-oxide-semiconductor (CMOS) tech-

nologies have many advantages. For example, the technology is mature, and fabrica-
tions are highly cost-effective, making large detector arrays feasible. Thanks to Moore’s
Law scaling, digital circuits (e.g., counters) can be integrated into each pixel to achieve
in-pixel digitization, enabling high-frame-rate imaging. Due to this, high-performance,
high-resolution 3D-vision chips will become a reality. As 3D integration continues to
CHAPTER 1. INTRODUCTION 3

mature, the low fill factor (FF) problem will be solved.

1.3 Why UV Imaging?

Visible light is only a tiny part of the spectrum. There is some invisible light that carries
a lot of valuable and exciting information. Machine vision is now being used in almost
every field, such as automotive Lidar, fluorescent imaging in life sciences, oil remote
sensing in the ocean, etc. The main reason for this is the increasingly cheap computing
power and numerous RGB images available for training models.

However, machine vision generally uses traditional RGB image sensors and ML algo-
rithms and focuses on the visible range of light (400nm - 750nm). It provides some
disadvantages. For example, it is difficult for machines to identify it is oil or water on
the road in the visible range. The car may mistakenly believe that this is water instead
of oil, which may lead to traffic accidents that endanger the lives and property of pas-
sengers. Another example in low light is when a car is driving fast into a tunnel. At
this point, there is no visible light, and the camera will not distinguish the texture of the
road.

UV Light offers a solution. UV light can detect more minor features more precisely
because UV wavelengths are much shorter, ranging from 10nm to 400nm. However,
ultraviolet light is generally challenging to capture because it reacts with pretty much
other matters, thus substantially reducing the intensity of the reflected UV light. This
situation requires that the detector be able to amplify the UV signal. Luckily SPAD is
naturally suitable for this case because it has a virtually infinite gain via carrier multi-
plication. So, it does not require additional amplifier circuits or particular components,
thus reducing the cost.

Modern CMOS technologies are well suited for UV imaging. As feature size shrinks,
the doping profiles become higher, the junctions become shallower, and the multiplica-
CHAPTER 1. INTRODUCTION 4

tion region becomes thinner, which leads to higher photon detection probability (PDP)
in the UV regions.

1.4 Objectives of the Thesis

This work aimed to develop SPAD pixels for UV imaging in CMOS technology for
large arrays. This new-generation image sensor will have real single-photon sensitivity,
in-pixel digitization, super high frame rate and work in low light. It will significantly
enhance the capabilities and reduce the cost of Lidar imaging.

1.5 Thesis Outline

The rest of this thesis is organized as follows. An introduction to the SPAD basics,
theory of operations and fabrications are given in Chapter (2). In Chapter (3) are the
circuits and layouts in XS018. The implementations of the proposed pixels, simulations
and layouts in XH018 are presented in Chapter (4). Chapter (5) discussed the simulation
results and pixel layout optimisations. Chapter (6) concluded the whole project.
CHAPTER 2. BACKGROUND 5

Chapter 2

Background

2.1 Single-Photon Avalanche Diode

This section will discuss the diode’s IV characteristic curve, the characteristics of the
Geiger mode, the development of the avalanche, quenching, and reset, and the diode’s
breakdown voltage and excess bias voltage that controls the overall operation of the
system.

2.1.1 Theory of Operation

The p-n junctions consist of p-type and n-type semiconductors, which are the funda-
mentals for almost all modern electronic circuits. The majority carriers of the p-type
region are holes, and the majority carriers of the n-type region are electrons. Electrons
diffuse from the n-region into the p-region, and holes diffuse from the p-region to the
n-region. As a result, a narrow region called the depletion region is formed between the
junction.

The built-in potential, which points from the n-side toward the p-side, obstructs the
further diffusion and hence no net current flow across the junction in equilibrium con-
CHAPTER 2. BACKGROUND 6

dition.

By applying a voltage will alter the built-in potential and cause a departure from equi-
librium. If the junction is forwarded biased or reverse biased, the Fermi levels are
misaligned, and electrons and holes start to move.
i

VBD + VEX i = is[exp(eV/KT) - 1]

Photon Recharge
is

VEX+VBD VBD V

Avalanche Quenching

Excess bias

Geiger Linear Forward

Mode Mode biased

Figure 2.1: Current-voltage characteristics for a p-n junction.

The current-voltage (i-V) characteristic of a p-n junction acts as a diode is as shown

in Figure (2.1). By applying a positive voltage V to the p-side, the junction is forward
biased. The current increases exponentially by the factor exp(eV/kT). In reverse biased
condition, the exponential term approaches zero, and the current is −I0 , a tiny reverse
saturation current.

Continuing to increase the reverse voltage to a certain point will trigger an avalanche
effect. If the voltage applied to the junction is above the breakdown voltage (VBD ), the
electric field across the depletion layer is so high that impact ionization occurs.

When carriers are injected (photon generated or non-photon generated), an avalanche

effect is immediately triggered, resulting in a sharp increase in current. The exponen-
tially increasing avalanche current is self-sustaining.
CHAPTER 2. BACKGROUND 7

The avalanche must be quenched. As long as the onset of avalanche current is detected,
external circuits immediately bring the bias voltage below the breakdown voltage.

Quenching circuits as external interference stop the avalanche. After a period of delay,
the external circuits raise the voltage to the breakdown voltage again. The SPAD is now
recharged back to avalanche state again to detect the next incoming photon. The current
pulse is digitally detectable at the output.

Diodes are safe in this mode. It may seem destructive because the breakdown current is
too high, and the diode will heat up and be damaged. However, if the current is limited
to a reasonable value by the external circuits, the p-n junction can operate as safely as
in the forward region. [4].

Diodes designed to operate in this mode of operation are known as Geiger mode
avalanche diode, also as single-photon avalanche diode (SPAD). Such diodes are
extremely sensitive to photon generated carriers (or non-photon generated) and have
virtually infinite gain via carrier multiplication.

2.1.2 Breakdown Voltage and Excess Bias

The breakdown voltage of a diode depends on the width of its depletion region. The
lighter the doping, the greater the width of the depletion region and the higher the
breakdown voltage. The breakdown voltages between the different wells are very high
and, as described in section (2.2.1), we use well for isolation.

If both sides are heavily doped, the depletion region is narrow, and the breakdown
voltage becomes smaller. If one side is heavily doped and one side is lightly doped,
then the lightly doped side determines the breakdown voltage.

Excess bias voltage VEX is the key parameter controlling the operation of SPAD. The
three states of the SPAD, i.e. avalanche, quenching, and recharge, are all related to the
excess bias voltage.
CHAPTER 2. BACKGROUND 8

By adding the extra bias voltage, the diode enters the avalanche state. By subtracting
the extra bias voltage, quenching occurs, and the avalanche stops. By adding the extra
bias voltage again, the diode is reset.

The SPAD transits from these three states back and forth. We can see that the entire
operation is to manipulate excess bias voltage. A typical value of VEX is 2 to 6 volts.

2.2 Fabrication

The fabrication of SPADs can significantly affect the performance parameters of SPADs.
Conventional SPADs are generally manufactured on a planar process. It usually has a
heavily doped p-type substrate and a lightly doped p-type epitaxial layer. Ion implanta-
tion determines the doping profile of the SPADs.

2.2.1 The Guard Ring

The guard ring is used to protect a core area in a chip and is essential in analogue lay-
out. Many places require guard rings, for example, between critical transistors, outside
the active area of diodes, between different modules and between digital and analogue
circuits.

Guard ring usually surrounds that area and is shown on the layout as a series of contacts
with the well. The majority carriers guard ring P+ diffusion is used to connect the p-sub,
and n+ diffusion is used to connect the well. Some high voltage processes also require
high voltage isolation at the periphery.

Guard ring is required outside the active region of SPADs. The active region of the
SPAD is the region where the photons are incident. It is the most crucial region for each
pixel and should always be separated from the other areas.

Guard ring around the active area has the following roles. Firstly, it prevents carri-
CHAPTER 2. BACKGROUND 9

N+ P+

NWELL NWELL PWELL PWELL

Multiplication Multiplication
region region

DNWELL
Guard ring
P-epi

Figure 2.2: Illustration of guard ring and PEB prevention mechanisms in planer SPAD

ers from other regions from diffusing into the active region and causing a spurious
avalanche. Secondly, the electrical fields at the active region’s edge are stronger. The
guard ring creates a constant breakdown voltage in the active area and prevents prema-
ture edge breakdown (PEB).

Figure (2.2) shows the cross-section of the SPADs with guard rings implemented by n-
well or p-well. The WELL has a higher breakdown voltage, so there are no avalanches
at the edge.

In addition to Well-based guard rings, STI-based guarding ring is another type of guard
ring. As feature size keeps shrinking, STI plays a more and more critical role in the
guard ring. The implementation of a shallow-trench-isolation (STI) guard ring is re-
ported to have 30 times larger breakdown voltage than silicon [5]. However, STI con-
tributes a lot of noise. Due to the lattice mismatch, there are many traps on the sur-
face of the STI. Free carriers may be trapped and then released, triggering a spurious
avalanche. By using STI-Nwell guard ring and virtual guard rings can alleviate this
noise problem [6].

STI N+ STI STI Cathode Dope STI

Avalanche
NWELL NWELL Multiplication region
Multiplication
region Special layers
used in XH018

STI-NWELL guard ring STI- "Virtual" guard ring

P-epi P-epi

Figure 2.3: SPAD structure with STI-based guard rings

CHAPTER 2. BACKGROUND 10

2.2.2 Planar SPADs

There are various approaches to design the layout of a planar process SPAD, and they
may have different features and be suitable for different situations. Figure (2.4) shows
the most used SPAD structures.

All the structures can be divided into two categories: n+/pwell or p+/nwell junction.
The p-n junction can be round, square, rounded square, octagons.

Different processes have different breakdown voltages. Some techniques use particular
layers for a more controlled breakdown voltage. The depth of the junction also affects
the sensitivity to different wavelengths of light.

P+ N+
DNWELL Wide spectrum
Shallow junction
blue or green sensitive Deep junction
IR or visible sensitive
NWELL or DNWELL Less sensitive to UV

P-epi P-sub
(a) (b) (c)

Figure 2.4: Cross-sections of planar SPADs [1]

Figure 2.4 (a) has p-type diffusion (P+) as a anode and a n-well or deep n-well as a
cathode. The p+/nwell junction is shallow, with a shallow p-well forming the guard ring.
This structure is usually blue or green-sensitive because of the shallow multiplication
region.

By burying the multiplication region, Figure 2.4 (b) depicts an IR or visible light sensi-
tive SPAD. Because the p-n junction is deep, this structure is less susceptible to light in
the UV range (UV light is absorbed in the surface).

The structure in Figure 2.4 (c) has the potential to be sensitive to a broad spectrum.
Modern CMOS presses usually use heavily doped p-substrates. An N+ diffusion forms
an intuitive n-p junction with the substrate, and the well around it creates a guard ring.
The main drawback of this structure is the generally poor photon detection probability
CHAPTER 2. BACKGROUND 11

(PDP). Because the p-substrate is heavily doped and the n+/p-sub junction will result in
a thin depletion layer [1].

2.3 Schemes for Quenching and Recharge

The avalanche must be quenched to sense the next photon. Passive quenching (PQ) and
active quenching (AQ) circuits are the two types of quenching circuits.

Passive quenching is simple, but the refresh rate is poor. Active quenching is fast but
has the disadvantage of increasing the design difficulty.

2.3.1 Passive Quenching

The simplest quenching method is to use a resistor. As illustrated in Figure 2.5, the
SPAD is biased at (VBD +VEX ). The operations of the PQ are as follows.

When there is no avalanche, the current is zero, and the voltage across the resistor is
zero (VR = 0). When photons come, and an avalanche is triggered, IR will rise sharply.

As current increases, VR rises to VEX . The voltage difference across the SPAD is re-
duced to VBD . Hence, the avalanche is quenched. The rise time is swift. Rising time
depends on the SPAD resistance and capacitance (junction capacitance and diffusion ca-
pacitance). The fall time can be hundreds of nanoseconds, depending on the quenching
resistance and SPAD capacitance.

Finally, the diode is reset, enters the avalanche state again, and waits for the next photon
to arrive.
CHAPTER 2. BACKGROUND 12

I
Vspad=VBD+VEX

hv

Diode

V
VBD VEX
Avalanche VRq
VRq Avalanche quenching
Current
VEX

Rq
Recharge

t
Photon arrival Hold-off time

Figure 2.5: Illustration of passive quenching circuits [2]

2.3.2 Active Quenching

The principle of active quenching is to use a quenching transistor to rapidly charge the
parasitic capacitance and discharge the SPAD junction capacitance, as can be seen in
Figure 2.6 [7].

AQC senses the avalanche and raises the anode voltage, reducing the voltage difference
across the SPAD. Thus, the avalanche process is stopped.

The AQC can be super fast (around 1-2 ns), depending on the circuit’s sensitivity to
detect avalanche onset. The sooner the avalanche is sensed, the quicker the operations
of the quenching circuits. It leaves less charge in the depletion region, thus reducing the
after-pulse probability.

The MOS transistor is very suitable for quenching/recharge circuits. The reasons are
as follows. First of all, a transistor can be used as a resistor by controlling the gate
voltage. Secondly, drain current ID remains constant in the saturation region (as seen in
Equation 2.1). λ represents here the channel-length modulation (λ=0 in long-channel).
This saturation current limits the avalanche current and prevents device damage.
CHAPTER 2. BACKGROUND 13

Vspad=VBD+VEX Pixel

hv

Diode
AQ transistor
In-pixel
Vanode digitization
Avalanche Sensing
Current Buf Counter
unit Digital
pulse

AR transistor
Recharge

Externally tunable delay

Figure 2.6: Illustration of active quenching/recharge circuits

1
ID,sat = β(VGS − VT H )2 [1 + λ(VDS − VDS,sat )] (2.1)
2

2.3.3 Active Recharge

The switching of a transistor connected in series with the SPAD achieves the recharge
of the SPAD (See Figure 2.6). When the recharge transistor is switched on, the SPAD
is recharged above breakdown.

A feedback loop controls the timing of the gate switch, and the exact delay time is
determined by the delay elements on the feedback loop. This period is called hold-off
because the SPAD cannot detect photons (also called dead time). The SPAD is ready
for the next photon after the dead time.

Depending on the delay circuity, the dead time can vary from a few nanoseconds to
hundreds of nanoseconds. The maximum count rate is limited by the dead time, but the
dead time is sometimes intentionally extended to reduce the possibility of after-pulsing.
CHAPTER 2. BACKGROUND 14

2.4 A Simple, Quantitative SPAD Model

A conventional SPAD model is used to simulate the behaviour of quenching/recharge

of a diode. The ideal switch is used to simulate the initiation of an avalanche. The CAC
is the junction capacitance between anode and cathode (See Figure 2.7). The other two
are stray capacitance from anode to substrate and cathode to substrate. Rd is the reverse
resistance during an avalanche. VBD is the breakdown voltage.
Vcathode

CAS
RAC

Vphoton VBD Breakdown Anode to Cathode

voltage CAC capacitance

Ideal switch
CCS

Vanode

Figure 2.7: The traditional SPAD model. The ideal switch is used to simulate the occurrence
of an avalanche.

2.5 Definition of SPAD Figures of Merit

2.5.1 Photon Detection Efficiency

Photon detection efficiency η is defined as the fraction of incoming photons that gen-
erate a detected pulse in the output. η is wavelength-dependent because the absorption
coefficient is wavelength dependent. Only the photons that reach the active area and are
absorbed can produce electron-hole pairs.
CHAPTER 2. BACKGROUND 15

2.5.2 After-pulsing Probability

During the avalanche, some of the carriers may be trapped by the lattice. If the release
occurs before the SPAD is reset to alert state, and the SPAD voltage is less than Vbd ,
these carriers cannot trigger an avalanche. This is the dead time of the SPAD.

However, if the carriers are released after the SPAD is quenched and recharged to the
Geiger mode, these carriers can trigger a spurious avalanche. This will lead to false
detection, and this event is called the after-pulsing effect [7].

Increasing the dead time will reduce the after-pulsing probability. By using an active
circuit (active reset (AR)) or by a resistor (passive reset (PR)), the dead time is con-
trollable. But increasing the dead time will lead to a reduction of the photon count
rate.

2.5.3 SPAD Dead Time

After the absorption of a photon, the SPAD is ignited. Then it must be quenched and
recharged. During this time, SPAD cannot detect other photons. Deadtime = Quenching
time + Recharging time. This time interval is called dead time τ . A feedback loop
regulates the length of τ to reduce the after-pulsing probability. τ limits the maximum
count rate.

2.5.4 Dark Count Rate

Not only the photogenerated carriers can trigger an avalanche, but in practice, some
SPAD intrinsic noises can cause some ignitions and get false counts, such as thermally
excited charge carriers, tunnelling and trapping centres. These are called dark counts,
dark currents. Hence SPAD requires process quality of wafer and low working temper-
ature to reduce the dark count.
CHAPTER 2. BACKGROUND 16

2.5.5 Fill-factor

Only the active area is sensitive to light in each pixel. Other circuits are not sensitive but
occupy additional chip areas. The Fill factor (FF) defines the ratio of the active area and
the total chip area. By using micro-lens and 3D integration will solve the low fill-factor
problem.

2.5.6 Spectral Range

The sensitive spectral range is determined by the materials used in the active area. For
example, some are sensitive to visible spectrum or IR, and some are sensitive to UV
(wavelength less than 400nm).
CHAPTER 3. PROPOSED PIXEL ARCHITECTURE IN XS018 17

Chapter 3

Proposed Pixel Architecture in XS018

In this chapter, we discuss the proposed SPAD pixel in the 180nm image sensor process
XS018. Section (3.1) illustrates the layout design of the diode. Section (3.2) discusses
the quenching/recharge circuits design, simulation and layout. Section (3.4) explains
the reasons why we changed the process to XH018.

3.1 Diode

The proposed CMOS SPAD structure is as shown in Figure (3.1). It consists of an

n+ diffusion layer as cathode and a p-well layer as an anode. The feature size of the
active region is 10um. The STI/Nwell guard ring around the active area is to prevent
premature-edge-breakdown (PEB). It ensures that the voltage in the multiplication re-
gion is maximized. The photons absorption and carriers multiplication occur below
n+ [6].

The top nitride passivation layer is a glass layer that protects the chip from the outside
world. But this layer will reduce overall light sensitivity in the UV range by more than
50%.
CHAPTER 3. PROPOSED PIXEL ARCHITECTURE IN XS018 18

Passivation (glass) Passivation

hv
MET2(metal shield) MET2

Anode Cathode UV window Cathode Anode VIA1

MET1 MET1 MET1 MET1
CONT
STI P+ N+ P+ STI

PWELL NWELL PWELL NWELL PWELL

Multiplication
region
STI-NWELL guard ring
P-epi layer

Figure 3.1: Proposed SPAD cross-section.

Figure 3.2: SPAD layout. UV window is inserted as a top opening. All regions except the
active region are covered with metal. DRC clean.

XS018 or XH018 provides the UV window. It is inserted as an opening in the top

passivation layer. As shown in the cross-section (see Figure 3.1), the top opening is
placed directly above the active area.

All regions except the active area are covered with metal, thus preventing photon ab-
sorption from occurring outside and lowering the noise and after-pulsing probability.

The poly ring surrounds the active area to match the device and the UV window layer.
Poly has a high absorption coefficient in the UV range ( below 400nm), so poly can
block UV light from entering outside the active area. The layout view in cadence virtu-
CHAPTER 3. PROPOSED PIXEL ARCHITECTURE IN XS018 19

oso shows in Figure (3.2).

3.2 Quenching Circuit

Vspad=VBD+VEX

hv
VDD
Diode AQ transistor

Digital Clock input of

pulse digital counter
Inv Vout
Vanode
VDD
Pixel
reset Vref
PQ Externally tunable
delay

Current-star
inverter (CS
Switched
capacitance
AR transistor

Figure 3.3: Schematic of quenching/recharge circuits

As shown in Figure (3.3), a mixed-quenching circuit is implemented. A PMOS acts

as the active quenching transistor. The operations are as follows. When an avalanche
happens, passive quenching occurs first, and the Vanode voltage increases sharply.

After reaching the threshold voltage of the sensing electronics, the active quenching
transistor turns on, followed by active quenching, which raises the voltage of the anode
to VDD [8] immediately.

The circuit used to sense avalanche is an inverter. By increasing the gate width of the
inverter, we can reduce the threshold voltage of the inverter. Some technology provides
body bias, which will also make the threshold voltage hugely reduced.

A lower threshold voltage will increase the sensitivity of the quenching circuit. It will
CHAPTER 3. PROPOSED PIXEL ARCHITECTURE IN XS018 20

detect avalanches earlier, allowing the circuits to be quenched faster. Because fewer
charges are trapped in the depletion region, the after-pulsing iprobability s reduced. [7].
Transient Response
Name V (V)
/Vpho 1.1

Photon arrival
0.3
-0.1
/Pix_Rst 3.2

1.4 Pixel reset signal

-0.2
/CSI_Vb 2.8

1.4 Externaly tunable bias voltage

-0.2 AQPQ
/I4/Va 3.4
AR

1.4
35ns
-0.2 Photon Next
1ns
/I4/net0193.6
arrival photon

Output
1.4 of QR
-0.2

0.0 50.0 100.0 150.0 200.0 250.0 300.0 350.0 400.0 450.0 500.0
time (ns)

Figure 3.4: Simulation results of the quenching/recharge circuits. 1 ns = 1 Gbits PDR.

The simulation results of the mixed-quenching and recharge circuits can be seen in
Figure (3.4). The minimal recovery period can be 1 ns, which translates to a frequency
of 1G bits photon detection rate (PDR). But we usually intentionally make it longer
to reduce the APE. After about 40 ns of hold-off time, the active recharge transistor
recharges the diode in the feedback loop.

The hold-off time is externally tunable by a current-starved inverter (CSI) and a switched
capacitance. Increasing the reference voltage of the CSI will make the hold-off time
longer. All operations that increase the capacitance in the loop will increase the hold-
off time. But only CSI provides flexibility for much longer hold-off time. During the
hold-off time, the SPAD cannot detect the next photon.

If the hold-off time is too short, then the charges trapped in the trap cannot all be re-
leased, which will cause a spurious avalanche. If the hold-off time is too long, the
frame rate of the sensor will be significantly reduced. In the worst case, it will not be
CHAPTER 3. PROPOSED PIXEL ARCHITECTURE IN XS018 21

able to complete the AR before the next photon arrives [8]. The output pulse is directly
detectable by the digital counter.

VDD

NDIFF
Guard Ring

Quenching
Quenching
Out
In

PDIFF
Guard Ring

VSS

Figure 3.5: Quenching/recharge layout

3.3 Counter

The counter design in XS018 can be seen in Section (4.5). The digital circuit is very
similar in XS018 and XH018 technologies. The transistors in XH018 has a deep nwell.
The difference between the layout is that XH018 has two more layers, ISOPW and
DNWELLMV. The rest of the layout remains the same.

3.4 Switch to XH018 Process

In our design, we found that the XH018 is a better process than XS018. The reasons
are as follows.

First of all, XH018 also provides a UV window (works in UV range by opening a

slot on the passivation layer). Also, the breakdown voltage of the XH018 is easier to
measure and control because the XH018 offers particular layers and new types of guard
CHAPTER 3. PROPOSED PIXEL ARCHITECTURE IN XS018 22

rings (STI-based guard rings). Additionally, because XH018 is a high-voltage process,

it is more suited for SPAD. DNWELL and HV isolation are employed for this purpose.
Furthermore, the XH018 process directly offers a set of guard rings, so we don’t have
to draw them by hand layer by layer during the layout design.

In summary, we switch to the XH018 process. The circuitry for the following chapters
will be designed in the XH018.
CHAPTER 4. PROPOSED PIXEL ARCHITECTURE IN XH018 23

Chapter 4

Proposed Pixel Architecture in XH018

In this chapter, we discuss the proposed pixel architecture in XH018. Section (4.1)
briefly introduces the diode ”dspb”. Section (4.2) explains the design of the basic digital
elements. Section (4.3) explains the design of delay elements. Section (4.4) illustrates
the circuits design, simulation and layout of the d-flip-flop. Section (4.5) presents the
design of counters. Section (4.6) illustrates the design of shift registers. Section (4.7)
presents the design of the quenching circuits.

4.1 Diode

The diode used here is the ”dspb” provided by XH018. SPAD dspb provides a CATDOP
layer as cathode and AML layer as avalanche multiplication region. The dspb requires
the anode to be connected to the substrate, and the readout circuit can only read the
SPAD avalanche current at the cathode. The principal application of dspb can be seen
in Figure (4.1). The quenching and counter circuits are realized in the high voltage
domain, and the DNWELL with HV isolation at the periphery is required.
CHAPTER 4. PROPOSED PIXEL ARCHITECTURE IN XH018 24

VDD:3.3V

dspb Q/R Counter OUT

VSS:0V
DNWELL with HV isolation

Vsub

Figure 4.1: Principle application of SPAD dspb

4.2 NAND, AND, OR Gates

B
A Clk_b A A&B
-A&B A -A
In Out
A AorB
B Clk B

Clk_b
A 940n/420n
A A
-A&B A&B AorB
B Nand A -A In Out And B Or
B

Clk

(a) (b) (c) (d) (e)

Figure 4.2: Schematics, symbols and layouts of the digital elements. (a) NAND, (b) inverter,
(c) TG (d) AND, and (e) OR

Schematics, symbols and layouts of the digital elements can be seen in Figure (4.2).
Figure (a) is the NAND gate. The output goes low when both inputs are high. Figure
(b) is a 0.94u/0.42u (0.94um W 0.3um L PMOS and 0.42um W 0.35um L NMOS)
inverter. Figure (c) is a Transmission gate (TG). TG is made up of an n-type and a
p-type transistor in parallel. The input and output of TG are exchangeable. Figure (d)
is a AND gate. It consists of a NAND gate and an inverter. The output goes high when
both inputs are high. Figure (e) is an OR gate. It consists of a NOR gate and an inverter.
The output goes low when both inputs are low.
CHAPTER 4. PROPOSED PIXEL ARCHITECTURE IN XH018 25

Each layout is DRC clean, LVSed, and shows that the netlists match and zero error ex-
ists. TG layout is modified from an inverter layout. All the inputs, outputs are labelled,
all heights are constant, and all the VDD and GND are aligned.

These layouts are standard-cell custom designs. Standard cells, including gates, flip-
flops are available in a cell library provided by the foundry. The designer creates circuits
by using standard cells, modifying the layouts, and connecting wires between cells.

The figure (4.3) shows the simulation results. The first line is AnandB, the second line is
AandB, the third line is AorB and the fourth line is -B. The inverter here is a 0.94u/0.42u
(0.94um W 0.3um L PMOS and 0.42um W 0.35um L NMOS) inverter. The fifth line
A and the sixth line B are the inputs. Both A and B are pulsed signals, where A has
twice the period of B. As can be seen from the simulation results, all circuits are free of
errors, and the results are as expected.

Figure (4.4) illustrates the simulation of 12u/5u inverter driving a 1.5pF load.

4.3 Delay elements

There are several elements used to achieve the delay (See Figure 4.5). The simplest is
to use multiple inverters on the path, and the delay is achieved by modifying its gate
width. The current-starved inverters (CSI) use an external bias voltage, so the delay can
be controlled externally and achieve a much longer delay (from several nanoseconds to
hundreds of nanoseconds). The user can adjust the camera frame rate externally.

4.4 D-flip-flop

Figure (4.6) shows the schematic of the flip-flop with a reset. The operation of this flip-
flop is as follows. When Clk is low, the first stage tracks and the second stage holds.
CHAPTER 4. PROPOSED PIXEL ARCHITECTURE IN XH018 26

Transient Response
Name V (V)
/AnandB3.6

1.4

-0.2
/AandB 3.6

1.4

-0.2
/AorB 3.6

1.4

-0.2
/-B 3.6

1.4

-0.2
/A 3.4

1.4

-0.2
/B 3.4

1.4

-0.2

0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0
time (ns)

Figure 4.3: Simulation of the NAND, AND, OR, INV. The first line is AnandB, the second
line is AandB, the third line is AorB, the fourth line is -B, the fifth line A and the sixth line B
are the inputs. A has twice the period of B.

When Clk goes high, the first stage captures the input and transfers it to the the second
stage. When ResetN goes low, all outputs are reset to low.

For CMOS imager design, pixel size and fill factor is crucial. The flip-flop above uses
only 20 transistors, and the simulation is correct. The author tried to draw his flip-flop
version, but the layout is hardly smaller than that provided by the digital library. Experts
designed the flip-flop in the digital library with many years of experience in the field. A
student could never design a smaller size than them.

This project optimised the flip-flop provided by the digital library to achieve a smaller
area and increase fill-factor. Although the flip-flop in the digital library is smaller and
uses only poly and one layer of metal to make all the connections, this flip-flop uses 30
transistors and has a layout area of 15.5um. After careful inspection, we think there is
CHAPTER 4. PROPOSED PIXEL ARCHITECTURE IN XH018 27

Transient Response
Name

/in 3.4

3.0

2.6

2.2

1.8

V (V)
1.4

1.0

0.6

0.2

-0.2
/out 3.4

3.0

2.6

2.2

1.8
V (V)

1.4

1.0

0.6

0.2

-0.2

0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0
time (ns)

Figure 4.4: Simulation of 12u/5u inverter driving a 1.5 pF load. The first line is the input and
the second line is the output.

In Out
In
Out
In Out Vref
Vref

Buffer Current-starved inverter Switched capacitance

Figure 4.5: Delay elements: buffer, current-starved inverter (CSI) and switched
capacitance. [3]

still much room for layout size optimisation here. These optimisations will be discussed
in section (5.2). The final schematic can be seen in Figure (4.7)

Figure (4.8) shows the simulation results for the two D-flip-flops. The first line is the
clock, the second line is clear, the third line is Din, and the last four lines are the output
of two Dffs. Each dff contains two outputs. One is Q, and one is QB. Two flip-flops
behave in the same way, and both are correct.

Figure (4.9) shows the layout of the proposed D-flip-flop with a reset. The length is
11um, and the width is 5um. It’s DRC and LVS clean.
CHAPTER 4. PROPOSED PIXEL ARCHITECTURE IN XH018 28

Clk_b Clk_b

TG Inv TG Qb

Clk Clk

Nand
Clk_b
Clk_b

In A

A
B
TG
Nand TG Inv Q
B

Clk
Clk
ResetN

Figure 4.6: An edge-triggered D-flip-flop with a reset. Transistor count: 20

Qb
CI CIB CIB CI

Din
Q
CIB CI CI CIB

RN RN

Figure 4.7: Proposed D-flip-flop schematic. Transistor count: 24

4.5 Counter

Digital circuits widely use counters. It counts the pulses received at the clock input.
Each time a rising or falling edge is detected, the count is added by one. N D-flip-flops
construct an n-bit counter. Counters should always support some features, e.g. reset. If
reset is activated, all counter outputs are reset to 0.

In our pixel design, each pixel contains a 9-bit asynchronous (ripple) counter, which
is used to count the number of incoming photons (as well as dark counts). The output
lines of a 9-bit counter represent the values 29 or 512.

The output of the quenching circuits provides the counter clock inputs of the first stage.
The counters previous stages’ output Q and Q bar provide the input clocks of the fol-
CHAPTER 4. PROPOSED PIXEL ARCHITECTURE IN XH018 29

Transient Response
Name V (V)
/Clock 3.4

-0.2
/Clear 3.4

-0.2
/Din 3.4

-0.2
/Clock_B3.6

-0.2
/Dff2_Q 3.6

-0.2
/Dff2_Qb3.6

-0.2
/Dff1_Q 3.6

-0.2
/Dff1_Qb3.6

-0.2

0.0 40.0 80.0 120.0 160.0 200.0 240.0 280.0 320.0 360.0 400.0 460.0
time (ns)

Figure 4.8: Simulation of the flip-flops. The two flip flop results match. The first line is the
clock, the second line is clear, the third line is Din, and the last four lines are the output of two
Dffs. Each dff contains two outputs. One is Q, and one is QB.

lowing stages.

Good arranging of the cell pins in the symbol view reduces the workload of connecting
wires. For example, VDD aligns VDD, clock aligns clock, reset aligns reset, etc.

Then, we can create an array simply by setting the number of rows and columns in the
Add Instance window and aligning the yellow boxes to align all the pins. This way of
making arrays is fast and accurate. For an 8-bit counter, the number of rows is 8, and
the number of columns is 1. The design of the counters with row select can be seen in
Figure (4.10).

The simulation results for the 9-bit counter can be seen in Figure (4.11). As can be seen
from the output curve, the circuit design is correct. At each falling edge of the clock,
the counter is added by one.
CHAPTER 4. PROPOSED PIXEL ARCHITECTURE IN XH018 30

11um

5um

Figure 4.9: Proposed D-flip-flop layout. Length 11um, width 5um. DRC, LVS clean.

The layout of the counters can be seen in Figure (4.12). The 2-bit is the foundation,
which can be extended from 2 to hundreds of bits. Open the 8-bit counter layout view
to ensure that the CI, CIB, reset, and row select signals are at the correct position. The
9th bit counter is added separately. The layout can be irregular, depending on the size
and position of flip-flops, diode, quenching circuits. It can be 8 or 10-bits as long as it
makes better use of the chip area.

XH018 provides guard ring directly. Here’s how to automatically generate a guard
ring. Select “Create” in the menu bar, then select “MPP Guard Ring” and choose
“DNWELL Guard” to create a high voltage guard ring (shortcut: Shift+G). Similarly,
PDIFF and NDIFF guard rings are available.

4.6 Shift Register

Shift registers are extremely useful digital circuits. They use a series of flip-flops to shift
the stored bits left or right. For example, an 8-bit shift register consists of 8 D-flip-flops.
All flip-flops share one clock and reset signal. The data is shifted one bit from input to
output at each rising edge of the clock signal. Hence, it can be used as a digital delay
line, and the speed depends on the clock frequency and the number of flip-flops. Shift
CHAPTER 4. PROPOSED PIXEL ARCHITECTURE IN XH018 31

1bit_OUT

RowSel
VDD OUT VDD
VDD
GND GND
D Q
Rst Counter Rst
Rst D-flip-flop 1-bit
Clk Qb
Clk
Qb ClkB Q
ClkB
RSel RSel
GND

(a) (b)

OUT OUT
VDD VDD VDD VDD VDD Out1 Out2 VDD
GND GND GND GND GND GND
Rst Counter Rst Rst Counter Rst Rst Counter Rst
Clk 1-bit Qb Clk 1-bit Qb Clk 2-bit Qb
ClkB Q ClkB Q ClkB Q
RSel RSel RSel RSel RSel RSel

(c) (d)

VDD Out1 Out2 VDD VDD Out1 Out2 VDD VDD Out1 Out2 VDD VDD Out1 Out2 VDD
GND GND GND GND GND GND GND GND
Rst Counter Rst Rst Counter Rst Rst Counter Rst Rst Counter Rst
Clk 2-bit Qb Clk 2-bit Qb Clk 2-bit Qb Clk 2-bit Qb
ClkB Q ClkB Q ClkB Q ClkB Q
RSel RSel RSel RSel RSel RSel RSel RSel

(e)

Figure 4.10: Schematics and symbols of the counters with row select. (a) 1-bit counter
schematic, (b) 1-bit counter symbol, (c) 2-bit counter schematic, (d) 2-bit counter symbol and
(e) 8-bit counter schematic

registers can be used as a row scan element in the design of the pixel. It will activate
the sensor array row by row, and after reaching the final line, it shifts the row activation
signal back to the first line.

Figure (4.13) shows the schematics, symbols of the shift registers. The output feed into
the Din of the next flip flop. Simulation results of an 8-bit shift register can be seen in
Figure (4.14). From the transient simulation results, the circuit is working correctly.

Figure (4.15) illustrates the 2-bit shift register layout. The bottom flip-flop is flipped up
and down. A 2-bit is the foundation unit. Align the VDDs, and it can be extended to
hundreds of bits. They share the column buses of clocks and reset signals.
CHAPTER 4. PROPOSED PIXEL ARCHITECTURE IN XH018 32

Transient Response
Name V (V)
/Clock 3.4

-0.2
/Reset 3.4

-0.2
/RowSel3.4

-0.2
/Q1 3.4

-0.2
/Q2 3.4

-0.2
/Q3 3.4

-0.2
/Q4 3.4

-0.2
/Q5 3.4

-0.2
/Q6 3.4

-0.2
/Q7 3.4

-0.2
/Q8 3.4

-0.2
/Q9 400.0
V (uV)
-700.0

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
time (us)

Figure 4.11: Simulation of a 9-bit digital counter. The first line is the clock signal. The second
line is the reset signal. The third line is the row select signal. The rest are the outputs Q1 to Q9.

4.7 Quenching Circuits

As shown in the Figure (4.16), a passive-quenching circuit is implemented. The p-mos

in the detection inverter (INV1) has a width of 2u, and n-mos has 500n. Increasing the
p-mos width is for lowering the threshold voltage. The size of the transistors has been
marked on the diagram.

The operation principle of the quenching circuits is described as follows. Before the
avalanche and the quenching, the pixel reset transistor (MG ) resets the pixel and gives
the diode an initial bias condition. The voltage across the diode after the reset operation
is VSU B +VDD. When photons arrive and an avalanche is ignited, the anode voltage
of the diode reduces sharply. The avalanche is quenched through a passive quenching
CHAPTER 4. PROPOSED PIXEL ARCHITECTURE IN XH018 33

VDD

Out
VSS
(a)
Row
VDD Rst
Select

C CB

VSS

VDD

(b) (c)

Figure 4.12: Counters layout. (a) 1-bit counter layout, (b) 2-bit counter layout and (c) 8-bit
counter layout. Reset and row select are the common bus signals. The 2-bit is the foundation
and can be extended from 2-bit to higher bits. The bottom flip-flop is flipped. Open the 8-bit
counter layout view to ensure that the CI, CIB, reset, and row select signals are at the right
position. The 9th bit counter is added separately.

transistor MQ . The detection inverter (IN1) senses the avalanche. After reaching the
threshold of the detection inverter (IN1), the passive quenching transistor MQ turns off.
VDD is now cut off from the diode, and the avalanche is quenched completely.

The output of the detection inverter (INV1) drives a current-starved inverter, which gen-
erates a user-tunable delay to recharge the diode and drives a second inverter (INV2),
which produces the clock signal for the digital counter. The bias voltage Vref regu-
lates the hold-off time by controlling the AR transistor MR . When Vref is low, the gate
voltage of MR slowly decreases to low, and the speed depends on the value of Vref .

The simulation results of the passive-quenching and recharge circuits can be seen in
Figure (5.1). The photon pulse has a period of 50ns and a pulse width of 20ps. The
CHAPTER 4. PROPOSED PIXEL ARCHITECTURE IN XH018 34

Out2 Out1

VDD VDD Out2 Out1

VDD VDD
Din D Q D Q GND GND
Rst Rst D-flip-flop Rst Rst D-flip-flop
Din Shift Out1

Clk Clk Clk Clk

Rst register Rst
Qb Qb 2-bit
ClkB ClkB Clk Clk
ClkB ClkB
GND GND ClkB ClkB

(a) (b)

Out2 Out1 Out2 Out1 Out2 Out1 Out2 Out1

VDD VDD VDD VDD VDD VDD VDD VDD
GND GND GND GND GND GND GND GND
Din Shift Out1 Din Shift Out1 Din Shift Out1 Din Shift Out1
Rst register Rst Rst register Rst Rst register Rst Rst register Rst

Clk
2-bit Clk Clk
2-bit Clk Clk
2-bit Clk Clk
2-bit Clk
ClkB ClkB ClkB ClkB ClkB ClkB ClkB ClkB

(c)

Figure 4.13: Shift register schematics. (a) 2-bit shift register schematic, (b) 2-bit shift register
symbol and (c) 8-bit shift register schematic

minimal recovery period can be 1.5 ns. After about 8 ns of dead time, the recharge
transistor recharges the diode in the feedback loop. The final output is an ideal digital
pulse signal.

The layout of AQC in XH018 can be seen in Figure (4.17). Guard rings surround the
transistors to prevent latch-up. The shared Nwell and ISOPW fix the vertical length.
With the addition of high voltage isolation, there are no DRC or LVS errors.
CHAPTER 4. PROPOSED PIXEL ARCHITECTURE IN XH018 35

Transient Response
Name V (V)

/clk 3.4

-0.2
/Din 3.4

-0.2
/Reset 3.4

-0.2
/Q1 3.4

-0.2
/Q2 3.4

-0.2
/Q3 3.4

-0.2
/Q4 3.4

-0.2
/Q5 3.4

-0.2
/Q6 3.4

-0.2
/Q7 3.4

-0.2
/Q8 3.6

-0.2

0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 100
time (ns)

Figure 4.14: Simulation of an 8-bit shift register. 2-bit is the base and can be easily expanded
to 50-bits, corresponding to the activation of 50 rows of pixels.

Rst C CB
VDD

VSS

VDD

Figure 4.15: 2-bit shift register layout. A 2-bit is the foundation unit.
CHAPTER 4. PROPOSED PIXEL ARCHITECTURE IN XH018 36

VDD=3.3V
MR

2u

Current-starved VDD
inverter (CSI)
VDD
Pixel 500n
MG MQ
reset ML0
1u 1u

Vref 2u
ML1
Inv
INV1 2u/500n 2u
ML2

INV2 1u/500n

Vsub=-18.2V Digital pulse

Inv VoutB

Vout

Figure 4.16: Schematic of quenching/recharge circuits. The width of the used transistors has
been marked on the figure. Length remains unchanged and is the default value. The output are
directly readable digital pulses. The sizes of the transistors have been marked on the diagram.

Pixel reset

Quenching Out
Quenching In

Guard Ring

Figure 4.17: Quenching/recharge layout. Guard rings are to prevent latch-up. The shared
Nwell and ISOPW fix the vertical length.
CHAPTER 5. RESULTS DISCUSSION 37

Chapter 5

Results Discussion

5.1 Single Photon Avalanche Diode Array

Each pixel consists of a diode, quenching/recharge circuits, as well as in-pixel digital

counters. The simulation of one complete pixel can be seen in Figure (5.1). Vpho simu-
lates the incoming photons, has a pulse width of 20ps and a period of 50ns. The dead
time is regulated by the reference voltage CSIvb . When the counter reset signal is high,
the counter counts the incoming photons. To better distinguish the output characteris-
tics, only the results from Q1 to Q3 are shown here (If Q1 to Q3 are working correctly,
Q4 to Q9 must also be working correctly).

The basic block of each SPAD pixel and the layout can be seen in Figure (5.2). The
left side of the counter should not exceed the left side of the diode, and the top side of
the AQC should not exceed the top side of the diode. The outputs connect to the 8-bit
column bus in the vertical direction. Output buffers are required at the readout module.
The feature size of the diode is 12um, and the pixel size is 35×40um, which gives us a
fill factor of about 8%.

After clearing all DRC and LVS errors of one pixel, we get a 2×2 array by flipping the
pixels twice, as shown in Figure (5.3). All the counters are aligned in the horizontal
CHAPTER 5. RESULTS DISCUSSION 38

direction. The length of the 8-bit counter fixes the size in the horizontal direction. To
better use the chip area, the 9th flip-flop is on the top of the 8th flip-flop.

The 4 pixels are the basic units that make up the 50×50 array, as shown in Figure (5.4).
All the outputs are aligned in the vertical direction. The 50×50 array has the size of
1.8×2mm. A DNWELL with high voltage isolation enclose the diodes, and all AQs
and Counters share a DNWELL with high voltage isolation.

With a system clock of 100MHz, each pixel is read out in 10ns, and hence, a complete
50×50 pixels array (2500 pixels) is read out in just about 25 us, giving a frame rate of
40000 frames/s.
Transient Response
Name V (V)
/Vpho 1.1
Photon Arrival
-0.1
/Pix_Rst 3.4
Low reset Pixel Reset
-0.2
/CSI_Vb 3.4
Reference voltage: change the dead time

0.6
3.4
/Coun_Rst High counts,
Counter Reset
low reset
-0.2
/RS 3.4
Row Select
-0.2
/P_Q1 3.4

-0.2
/P_Q2 3.4
Counter Out
-0.2
/P_Q3 3.4

-0.2 1.5ns 8ns

/I20/Vcath 3.4
Cathode Voltage Dead Time
0.4
3.4
/I20/QR_OUT
Quenching Out
-0.2

0.0 50.0 100.0 150.0 200.0 250.0 300.0 350.0 400.0 450.0 500.0
time (ns)

Figure 5.1: Simulation results of the SPAD pixel. A full pixel contains the diode, the AQC and
the 9-bit counter.
CHAPTER 5. RESULTS DISCUSSION 39

35um

Quenching
Diode
12um
Diode

40um
Q/R Counter
HV Isolation
One Pixel
(a)

9-bit Digital Counter

(b)

Figure 5.2: The layout of one pixel. (a) the basic block of each SPAD pixel and (b) one pixel
layout. Diode feature size = 12um..

5.2 Pixel Layout Optimization

The active area of each diode in a CMOS image sensor is the place where light is
collected. The other electronics don’t contribute to the photon detection ability but
occupy many areas and hugely reduce the fill factor. Large pixel size also minimises
the imager’s resolution and, most importantly, increases the fabrication costs. Hence,
optimising the pixel layout is essential in the CMOS imager.

One goal of this work is to reduce transistor count and sizes. D-flip-flop is one of the
most reused units in digital counter design, and hence, the Optimisation of the Dff area
is essential.

The optimisations are as follows. In the input stage, the clock needs to pass a two-stage
inverter first, and in the output stage, Q also needs to pass a two-stage inverter. The
inverters are necessary for digital design because they provide a higher quality clock
signal and improve the output signal’s ability to drive external circuits.

However, we can use an inverter to provide the clock signal in the first stage, and the
clock signals of the next stage are provided by outputs Q and QB from the previous
CHAPTER 5. RESULTS DISCUSSION 40

One Pixel One Pixel One Pixel

Q/R Q/R

Counter Counter

Counter Counter

Q/R Q/R

One Pixel One Pixel

(a)

(b)

Figure 5.3: The layout of fully parallel 2×2 array. 2×2 array is the basic units. With the
addition of high voltage isolation, it is DRC and LVS clean.

stage. Furthermore, all the pixels in one column share one buffer in the readout module.
Hence, we can remove the output buffer in the flip-flop.

Thus, the number of transistors used in each flip-flop has been reduced from 30 to 24.
The occupied area has been reduced from around 15.5 um to less than 11 um.

Another critical approach is to share areas. For example, in a counter design, VDD and
GND are shared. Each adjacent 1-bit counter is flipped up and down, suggesting that

1.8mm
2mm

Figure 5.4: The layout of 50×50 array and the zoom in on the top left. It contains only a 50 by
50 array of pixels and does not contain a row selector or readout unit.
CHAPTER 5. RESULTS DISCUSSION 41

VSS is on top and VDD is on the bottom. This achieves NWELL sharing and ISOPW
sharing. Similarly, other layers such as MV, PIMP and NIMP are shared.

The counter does not have to be regular either. For example, it is possible to place a
part of it next to it. The length of the camera chip in this project is precisely the length
of the 8-bit counter. Hence, 35um length fixed the minimum size of one pixel.

The minimum width of the counter and the width of the high voltage isolation fix the
width of the chip. In a 2×2 array, the top and bottom pixels’ outputs overlap because
the outputs Q are connected. They share one DIFF area and one CONT. What remains
to be optimised are the diodes and the AQC layouts.

Reducing the gate width of the transistor in the AQC reduces the chip width. However,
changing the gate width will affect the performance of the circuit. For example, in-
creasing the gate width will allow the AQC to complete quenching and recharge faster,
thus increasing the refresh rate and decreasing the after-pulsing probability. However,
increasing the chip size and fabrication cost is undesirable. In this project, the size
of some transistors was reduced appropriately, which increased the minimum recovery
time, but ultimately reduced the chip area. The final minimum recovery time is 1.5 ns.

The minimum recovery time has been increased to increase the fill factor, but the min-
imum time itself is not directly applicable as a minimum time. These circuits require a
specific hold-off time, which reduces the after-pulsing effect.

The gate voltage is more flexible compared to the gate width of the transistor. The
externally tunable delay, on or off of the transistor, is controlled by several factors such
as W/L ratio, VGS , Vth etc., and VGS has more control over the transistor as these operate
in the saturation region. They have a squared relationship: ID,sat = β(VGS − Vth )2 .

While keeping the area relatively minimal, avoiding routing wires over the transistors
and keeping the number of Vias to a minimum of two are also critical for increasing the
reliability.
CHAPTER 5. RESULTS DISCUSSION 42

In addition, the Vias and CONTs at the edge of the 2×2 array are shared with the
adjacent 2×2 array. Adjacent diodes share substrates, and in the layout, these diodes
link closely and share via strips.

In recent years, the research on SPAD has started shifting to 3D integration [9]. For
example, the top tier is the diode, the bottom is the control and processing circuitry, and
Cu-Cu connections connect them. In this case, the fill factor increases significantly.

5.3 Challenges

The main drawback of the SPAD pixels is the large pixel size and small fill factor. It
can be alleviated by reducing the size of digital circuits, for example, by using fewer
transistors, designing the digital circuits in 90nm or 28nm process, or using micro-lens
(with IR and visible range). 3D integration is also a recent research trend.

In addition, the carriers trapped in the lattice defects during the last avalanche may also
lead to another avalanche. Good process quality of the wafer will reduce the after-
pulsing effect.
hv

Diode
Diode AQAR Diode
Diode

Readout Circuits T
S
V
Active area Digital Circuits
Make it more compact SAPD Chip Quenching
Compact layout Microlens 3D integration

Figure 5.5: The low fill factor (FF) challenges of SPAD can be mitigated by making the layout
more compact, using micro-lens(not with UV range) and 3D integration.

SPAD image sensor still needs to continue to evolve to provide performance and reli-
ability. Autonomous driving requires many sensors and multiple systems to improve
safety, availability, maintainability and safety (RAMS). In addition, factors such as en-
CHAPTER 5. RESULTS DISCUSSION 43

ergy consumption and cost have to be considered. This work’s new-generation image
sensors cannot be used directly in a critical environment as a single sensor can not be
the core component to achieve RAMS.
CHAPTER 6. CONCLUSIONS 44

Chapter 6

Conclusions

This work presents an expandable SPAD pixel architecture for building large SPAD
arrays. It was designed in a 180nm high-voltage CMOS technology XH018 provided
by XFAB and is sensitive to UV range. The simplified array’s block diagram shows
in Figure (6.1). Each SPAD pixel contains a single-photon avalanche diode, quench-
ing/recharge circuits and a 9-bit digital counter. The functions of each component are
as follows.

The quenching circuits sense the avalanche onset, quench it swiftly, and then deliver
the pulse to the digital counter. The counter counts the number of photons detected by
the SPAD. After an externally tunable hold-off time, the SPAD is reset to the initial
state. The hold-off time is essential and user-selectable. The outputs of each pixel are
connected to a 9-bit column bus.

Each pixel has the size of 35×40um, and the active area of each diode is 12.3um, which
give us a fill factor of 8.2%. The minimal recovery time is 1.5ns. The 50×50 array
has the size of 1.8×2mm. Table (6.1) summarizes the performances of proposed SPAD
pixels.

The advantages of this camera are single-photon sensitivity, in-pixel-digitization, very

high and tunable frame rate. There are also challenges with the pixel: the global pixel
CHAPTER 6. CONCLUSIONS 45

size is too large, and the fill factor is relatively small.

Parameter This work ISSCC2013 [10] 2016 [8] 2020 [11]

Technology 180nm 180nm BSI 180nm 180nm
Pixel size 35×40um 21um 32×32um 1600um2
Feature size 12.3 um N/A 12um N/A
Array 50×50 202×96 N/A N/A
Fill factor 8.2% 70% 11% 21%
Dead time 1.5ns N/A 3.3ns 0.7ns
Diode dspb N/A N/A N/A
PDP 405nm 42% N/A N/A 23%
Counter 9-bit digital Analog Analog Analog
Quenching Passive Passive Active Active

Table 6.1: Performance comparison

CHAPTER 6. CONCLUSIONS 46

Diode Diode
R
o Q/R Counter Q/R Counter
w
One Pixel One Pixel
S Column bus
c
a Diode Diode
n Q/R Counter Q/R Counter
n
e One Pixel One Pixel
r

Output Buffer

Readout Circuits

(a)
35um

Quenching
Diode
40um

1.8mm
HV Isolation
2mm

9-bit Digital Counter

(b)

Figure 6.1: Simplified 50×50 array’s block diagram and the layout. (a) block diagram (b)
layout and the zoom in on the top left. The size of the 50×50 array is 1.8mm×2mm, and one
pixel is 35um×40um.
REFERENCES 47

References

[1] S. Mandai, M. W. Fishburn, Y. Maruyama, and E. Charbon, “A wide spectral range

single-photon avalanche diode fabricated in an advanced 180 nm cmos technol-
ogy,” Optics express, vol. 20, no. 6, pp. 5849–5857, 2012.

[2] S. Cova, M. Ghioni, A. Lacaita, C. Samori, and F. Zappa, “Avalanche photodi-

odes and quenching circuits for single-photon detection,” Applied optics, vol. 35,
no. 12, pp. 1956–1976, 1996.

[3] N. H. Weste and D. Harris, CMOS VLSI design: a circuits and systems perspective.
Pearson Education India, 2015.

[4] B. G. Streetman, S. Banerjee et al., Solid state electronic devices. Pearson/Pren-

tice Hall Upper Saddle River, NJ, 2006, vol. 10.

[5] H. Finkelstein, M. J. Hsu, S. Zlatanovic, and S. Esener, “Performance trade-offs in

single-photon avalanche diode miniaturization,” Review of scientific instruments,
vol. 78, no. 10, p. 103103, 2007.

[6] M. A. Karami, H.-J. Yoon, and E. Charbon, “Single-photon avalanche diodes in

sub-100nm standard cmos technologies,” in Proc. Intl. Image Sensor Workshop
(IISW), no. CONF, 2011.

[7] M. Dolatpoor Lakeh, J.-B. Kammerer, E. Aguenounon, D. Issartel, J.-B. Schell,

S. Rink, A. Cathelin, F. Calmon, and W. Uhring, “An ultrafast active quenching
REFERENCES 48

active reset circuit with 50% spad afterpulsing reduction in a 28 nm fd-soi cmos
technology using body biasing technique,” Sensors, vol. 21, no. 12, p. 4014, 2021.

[8] I. Vornicu, R. Carmona-Galán, B. Pérez-Verdú, and Á. Rodrı́guez-Vázquez,

“Compact cmos active quenching/recharge circuit for spad arrays,” International
Journal of Circuit Theory and Applications, vol. 44, no. 4, pp. 917–928, 2016.

[9] J. Ogi, T. Takatsuka, K. Hizu, Y. Inaoka, H. Zhu, Y. Tochigi, Y. Tashiro, F. Sano,

Y. Murakawa, M. Nakamura et al., “7.5 a 250fps 124db dynamic-range spad im-
age sensor stacked with pixel-parallel photon counter employing sub-frame ex-
trapolating architecture for motion artifact suppression,” in 2021 IEEE Interna-
tional Solid-State Circuits Conference (ISSCC), vol. 64. IEEE, 2021, pp. 113–
115.

[10] C. Niclass, M. Soga, H. Matsubara, M. Ogawa, and M. Kagami, “A 0.18- m

cmos soc for a 100-m-range 10-frame/s 200 ×96-pixel time-of-flight depth sen-
sor,” IEEE Journal of solid-state circuits, vol. 49, no. 1, pp. 315–330, 2013.

[11] Y. Xu, J. Lu, and Z. Wu, “A compact high-speed active quenching and recharging
circuit for spad detectors,” IEEE Photonics Journal, vol. 12, no. 5, pp. 1–8, 2020.