Outline

• Netlists
• Design flow
• What is a HDL?
EECS150 - Digital Design • Verilog
Lecture 6 - Hardware Description – history
– examples
Languages
February 6, 2003
John Wawrzynek

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Netlist Design Flow

• A key data structure (or Alternative format: Design
representation) in the design n1 g1.in1
Entry
process is the “netlist”: n2 g1.in2
n3 g2.in1
– Network List n4 g2.in2
• A netlist lists components and n5 g1.out g3.in1 High-level
connects them with nodes: n6 g2.out g3.in2
n7 g3.out Analysis
ex: g1 "and"
n1 n5 g2 "and"
g1 g3 "or"
n2
g3 n7
n3
n4
g2
n6 • Netlist is what is needed for simulation Technology
and implementation. Mapping
g1 "and" n1 n2 n5 • Could be at the transistor level, gate
g2 "and" n3 n4 n6 level, ...
g3 "or" n5 n6 n7 • Could be hierarchical or flat.
Low-level
• How do we generate a netlist?
Analysis

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 Design Flow Design Flow
Design • Circuit is described and Design • High-level Analysis is used to
Entry represented: Entry verify:
– Graphically (Schematics) – correct function
– Textually (HDL) – rough:
High-level • Result of circuit specification High-level • timing
Analysis (and compilation) is a netlist of: Analysis • power
– generic primitives - logic gates, • cost
flip-flops, or • Common tools used are:
– technology specific primitives - – simulator - check functional
Technology LUTs/CLBs, transistors, Technology correctness, and
discrete gates, or
Mapping Mapping – static timing analyzer
– higher level library elements -
• estimates circuit delays based
adders, ALUs, register files,
on timing model and delay
decoders, etc.
Low-level Low-level parameters for library elements
(or primitives).
Analysis Analysis

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Design Flow Design Flow

Design • Technology Mapping: Design
Entry – Converts netlist to Entry
implementation technology
dependent details
• Expands library elements,
High-level High-level
• performs:
Analysis Analysis
– partitioning, Netlist:
– placement, used between and
– routing internally for all steps.
Technology • Low-level Analysis Technology
Mapping – Simulation and Analysis Tools Mapping
perform low-level checks with:
• accurate timing models,
Low-level • wire delay Low-level
Analysis – For FPGAs this step could also Analysis
use the actual device.

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 Design Entry HDLs
• Schematic entry/editing used to • Basic Idea: • “Structural” example:
– Language constructs describe Decoder(output x0,x1,x2,x3;
be the standard method in inputs a,b)
industry circuits with two basic forms: {
– Structural descriptions similar to wire abar, bbar;
• Used in EECS150 until last year hierarchical netlist. inv(bbar, b);
☺ Schematics are intuitive. They – Behavioral descriptions use higher- inv(abar, a);
nand(x0, abar, bbar);
match our use of gate-level or level constructs (similar to
nand(x1, abar, b );
block diagrams. conventional programming). nand(x2, a, bbar);
☺ Somewhat physical. They imply • Originally designed to help in nand(x3, a, b );
abstraction and simulation. }
a physical implementation.
– Now “logic synthesis” tools exist to • “Behavioral” example:
Require a special tool (editor). automatically convert from behavioral Decoder(output x0,x1,x2,x3;
inputs a,b)
Unless hierarchy is carefully descriptions to gate netlist. {
designed, schematics can be • Hardware Description Languages – Greatly improves designer case [a b]
(HDLs) are the new standard productivity. 00: [x0 x1 x2 x3] = 0x0;
confusing and difficult to follow. 01: [x0 x1 x2 x3] = 0x2;
– except for PC board design, – However, this may lead you to falsely 10: [x0 x1 x2 x3] = 0x4;
where schematics are still used. believe that hardware design can be 11: [x0 x1 x2 x3] = 0x8;
reduced to writing programs! endcase;
}
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Verilog Basic Example: 2-to1 mux

• A brief history: //2-input multiplexor in gates • Notes:
– Originated at Automated Integrated Design Systems (renamed Gateway) in module mux2 (in0, in1, select, out);
– comments
1985. Acquired by Cadence in 1989. input in0,in1,select;
output out; – “module”
– Invented as simulation language. Synthesis was an afterthought. Many of the
basic techniques for synthesis were developed at Berkeley in the 80’s and wire s0,w0,w1; – port list
applied commercially in the 90’s. – declarations
– Around the same time as the origin of Verilog, the US Department of Defense not – wire type
developed VHDL. Because it was in the public domain it began to grow in (s0, select);
– primitive gates
popularity. and
– Afraid of losing market share, Cadence opened Verilog to the public in 1990. (w0, s0, in0),
– An IEEE working group was established in 1993, and ratified IEEE Standard (w1, select, in1);
1394 (Verilog) in 1995. or
– Verilog is the language of choice of Silicon Valley companies, initially because (out, w0, w1);
of high-quality tool support and its similarity to C-language syntax.
– VHDL is still popular within the government, in Europe and Japan, and some endmodule // mux2
Universities.
– Most major CAD frameworks now support both.
– Latest HDL: C++ based. OSCI (Open System C Initiative).

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 Announcements 2-to-1 mux behavioral description
// Behavioral model of 2-to-1
• Notes:
// multiplexor.
– behavioral descriptions use the
module mux2 (in0,in1,select,out);
keyword always followed by
input in0,in1,select; procedural assignments
output out; – Target output of procedural
// assignments must of of type reg
reg out; (not a real register)
always @ (in0 or in1 or select) – Unlike wire types where the
if (select) out=in1; target output of an assignment
else out=in0; may be continuously updated, a
reg type retains it value until a
endmodule // mux2
new value is assigned (the
assigning statement is executed).

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Hierarchy & Bit Vectors Behavioral 4-to1 mux

• Notes: • Notes:
//Assuming we have already – instantiation similar to primitives //Does not assume that we have – No instantiation
// defined a 2-input mux (either // defined a 2-input mux.
// structurally or behaviorally, – select is 2-bits wide – Case construct equivalent to
– named port assignment //4-input mux behavioral description nested if constructs.
//4-input mux built from 3 2-input muxes module mux4 (in0, in1, in2, in3, select, out);
module mux4 (in0, in1, in2, in3, select, out); input in0,in1,in2,in3; – Definition: A structural
input in0,in1,in2,in3; input [1:0] select; description is one where the
input [1:0] select; output out;
output out; reg out; function of the module is
wire w0,w1; defined by the instantiation and
always @ (in0 in1 in2 in3 select) interconnection of sub-modules.
case (select) – A behavioral description uses
mux2 2’b00: out=in0; higher level language
m0 (.select(select[0]), .in0(in0), .in1(in1), .out(w0)), 2’b01: out=in1; constructs and operators.
m1 (.select(select[0]), .in0(in2), .in1(in3), .out(w1)), 2’b10: out=in2;
m3 (.select(select[1]), .in0(w0), .in1(w1), .out(out)); 2’b11: out=in3; – Verilog allows modules to mix
endmodule // mux4 endcase both behavioral constructs and
endmodule // mux4 sub-module instantiation.

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 Behavioral with Bit Vectors “Dataflow” Descriptions of Logic
//Behavioral model of 32-bit
// wide 2-to-1 multiplexor. • Notes: //Dataflow description of mux • Notes:
module mux32 (in0,in1,select,out);– inputs, outputs 32-bits wide module mux2 in0, in1, select, out); – dataflow modeling provides a way
input [31:0] in0,in1; input in0,in1,select; to describe combinational logic by
input select; its function rather than gate
output [31:0] out; output out;
structure (similar to Boolean
// assign out = (~select & in0)
expressions).
reg [31:0] out; | (select & in1);
always @ (in0 or in1 or select) – The assign keyword is used to
if (select) out=in1; endmodule // mux2 indicate a continuous assignment.
else out=in0; Whenever anything on the RHS
endmodule // Mux Alternative: changes the LHS is updated.
//Behavioral model of 32-bit adder.
module add32 (S,A,B); assign out = select ? in1 : in0;
input [31:0] A,B;
output [31:0] S;
reg [31:0] S;
//
always @ (A or B)
S = A + B;
endmodule // Add
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Sequential Logic Testbench

//Parallel to Serial converter module testmux;
module ParToSer(LD, X, out, CLK); reg a, b, s; • Top-level modules written
wire f; specifically to test sub-modules.
input [3:0] X;
reg expected;
input LD, CLK; • Generally no ports.
output out; mux2 myMux (.select(s), .in0(a), .in1(b), .out(f));
reg out;
reg [3:0] Q; initial • Notes:
begin – initial block similar to always
assign out = Q[0]; s=0; a=0; b=1; expected=0;
• Notes: except only executes once (at
always @ (posedge CLK) #10 a=1; b=0; expected=1;
– “always @ (posedge CLK)” forces Q beginning of simulation)
if (LD) Q=X; #10 s=1; a=0; b=1; expected=1;
register to be rewritten every end – #n’s needed to advance time
else Q = Q>>1;
simulation cycle. initial – $monitor - prints output
endmodule // mux2 $monitor(
– “>>” operator does right shift (shifts in
a zero on the left). "select=%b in0=%b in1=%b out=%b, expected out=%b time=%d",
module FF (CLK,Q,D); s, a, b, f, expected, $time);
– Shifts on non-reg variables can be endmodule // testmux
input D, CLK; – A variety of other “system
done with concatenation:
output Q; reg Q; functions”, similar to monitor
wire [3:0] A, B; exist for displaying output and
always @ (posedge CLK) Q=D;
assign B = {1’b0, A[3:1]} controlling the simulation.
endmodule // FF
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 Verilog does not turn hardware design into More Verilog Help
writing programs! • The lecture notes only cover the very basics of Verilog and
mostly just the conceptual issues.
• The fact that Verilog looks similar to programming • The Mano textbook covers Verilog with many examples.
languages fools some people into thinking that they can • The Bhasker book is a good tutorial.
design hardware by writing programs. Not so. On reserve in the Engineering
• Verilog is a hardware description language. The best way library (starting Friday).
to use it is to first figure out the circuit you want, then figure
out how to express it in Verilog.
• The behavioral constructs hide a lot of the circuit details
but you as the designer must still manage the structure,
data-communication, parallelism, and timing of your • The complete language specification from the IEEE is
design. Not doing so leads to very inefficient designs. available on the class website under “Refs/Links”

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