NVIDIA Jetson TX1 System-on-Module: Data Sheet (Preliminary)

DATA SHEET [PRELIMINARY]
NVIDIA Jetson TX1 System-on-Module
NVIDIA Tegra Processors: TD580D, TD570D, CD580M, CD570M
Description
The NVIDIA® Jetson TX1 is a system-on-module (SoM) solution for visual computing applications. It combines the latest
NVIDIA Maxwell GPU architecture with an ARM® Cortex® -A57 MPCore (Quad-Core) CPU cluster to deliver the performance
and power efficiency required by industry-leading visual computing applications for next generation products.
Designed for use in power-limited environments, the Jetson TX1 SoM integrates:
 Advanced 3D graphics, video and image processing.

 Parallel computing, computer vision and machine learning capabilities.
 32-bit and 64-bit operating capability.
The combination of exceptional performance and power efficiency, integrated capabilities, rich I/O, and small-size enable new
classes of products while reducing complexity in system integration. The Jetson TX1 is ideal for many applications, including:
 Intelligent Video Analytics (IVA)

 Telepresence
 Drones
 Robotics
 Gaming Devices
 Virtual Reality (VR)
 Augmented Reality (AR)
 Portable Medical Devices
Ordering Information
Part Number Description
900-82180-0000-000 Jetson TX1 System-on-Module
JETSON | TX1 | DATASHEET | DS-07224-010_v0.9 | ADVANCE INFORMATION – SUBJECT TO CHANGE | © NVIDIA CORPORATION, ALL RIGHTS RESERVED 1
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Jetson TX1 System-on-Module
> Description Jetson TX1 System-on-Module
Maxwell GPU
256-core GPU | End-to-end lossless compression | Tile Caching | OpenGL® 4.5 | OpenGL ES 3.1 | CUDA® 7.0 | GPGPU | Android™ Extension Pack (AEP)
OpenGL ES Shader Performance (up to) GFLOPS (fp16) 1024
CPU Subsystem
ARM® Cortex® -A57 MPCore (Quad-Core) Processor with

1.9GHz
NEON Technology. Operating Frequency per Core (up to)
L1 Cache: 48KB L1 instruction cache (I-cache) per core; 32KB L1 data cache (D-cache) per core | L2 Unified Cache: 2MB
HD Video & JPEG
Decode †
H.265: Main10 2160p 60fps | 1080p 240fps

H.265: Main 2160p 60fps | 1080p 240fps
H.264: Baseline, Main, High, Stereo SEI (half-res) 2160p 60fps | 1080p 240fps
H.264: MVC Stereo (per view) 2160p 30fps | 1080p 120fps
WEBM VP9 2160p 60fps | 1080p 240fps

VC-1: Simple, Main, Advanced 1080p 120fps | 1080i 240fps
MPEG-2: Main 2160p 60fps | 1080p 240fps | 1080i 240fps
Encode †
H.265 (I and P frames) 2160p 30fps | 1080p 120fps

H.264: Baseline, Main, High 2160p 30fps | 1080p 120fps
H.264: MVC Stereo (per view) 1440p 30fps | 1080p 60fps
JPEG (Decode & Encode) 600 MP/sec
Audio Subsystem
Dedicated programmable audio processor | ARM Cortex A9 with NEON operating at up to 844MHz | 10-input/5-output 8-channel audio mixer | 4x Synchronous Sample Rate Converters
Display Controller Subsystem
Two independent display controllers with support for DSI with VESA link compression (VESA DSC), HDMI, and eDP
Captive Panel
Uncompressed: 24bpp
MIPI-DSI (1.5Gbps/lane) Support for Single x4 or Dual x4 links
VESA DSC Compression: 12bpp
eDP 1.4 (HBR2 5.4Gbps) 24bpp Single link (1x4) 4096x2160 at 60Hz
External Display
HDMI 2.0 (6Gbps) 24bpp 4096x2160 at 60Hz
Imaging System
Dedicated RAW to YUV processing engines process up to 1200Mpix/s | supports up to 128MP sensor
MIPI CSI 2.0 up to 1.5Gbps (per lane) Support for x4 and x2 configurations (up to 3 x4-lane or 6 x2-lane cameras)
Clocks
System clock: 38.4 MHz | Sleep clock: 32.768 KHz | Dynamic clock scaling and clock source selection
Boot Sources
eMMC and USB (recovery mode)

> Description Jetson TX1 System-on-Module
Security
Secure memory with video protection region for protection of intermediate results | Configurable secure DRAM regions for code and data protection | Hardware acceleration for AES
128/192/256 encryption and decryption to be used for secure boot and multimedia Digital Rights Management (DRM) | Hardware acceleration for AES CMAC, SHA-1 and SHA-256
algorithms | 2048-bit RSA HW for PKC boot| HW Random number generator (RNG) SP800-90 | TrustZone technology support for DRAM, peripherals | Dedicated HDCP HW
Memory
Dual Channel | Secure External Memory Access Using TrustZone Technology | System MMU
Memory Type 4ch x 16-bit LPDDR4
Maximum Memory Bus Frequency (up to)†† 1600MHz†
Memory Capacity 4GB
Storage
eMMC 5.1 Flash Storage
Bus Width 8-bit
Maximum Bus Frequency 200 MHz (HS400)
Storage Capacity 16 GB
Connectivity
WiFi
Radio type IEEE 802.11 ac 2x2
Maximum transfer rate 800 Mbps
Bluetooth
Version level 4.0
Maximum transfer rate 24Mbps
LAN
10/100/1000 BASE-T Ethernet
Peripheral Interfaces*
XHCI host controller with integrated PHY: 2 x USB 3.0, 3 x USB 2.0 | USB 3.0 device controller with integrated PHY | EHCI controller with embedded hub for USB 2.0 | 5-lane PCIe: one
x1 and one x4 controllers | SATA (1 port) | 2 x SD/MMC controllers (supporting eMMC 5.1, SD 4.0, SDHOST 4.0 and SDIO 3.0) | 3 x UART | 3 x SPI | 4 x I2C | 4 x I2S: support I2S, RJM,
LJM, PCM, TDM (multi-slot mode) | GPIOs
Temperature Specification
Storage Temperature Range -40C – 125C
Operation:
SoC Junction Temperature Range -25C – 105C
Thermal Transfer Plate Surface Range -25C – 80C**
Power Requirements
Maximum Total Module Power 6.5 – 15 W**
Applications
Embedded (Intelligent Video Analytics, Drones, Robotics, etc.), Automotive Research, Clamshells, Gaming, Internet TV, and more
†
Pending characterization.
††
Dependent on board layout. Refer to Interface Design Guide for layout guidelines.
* Refer to the Interface Design Guide and Technical Reference Manual to determine which peripheral interface options can be simultaneously exposed.
** Refer to the Product Design Guide and Thermal Design Guide for evaluating product power and thermal solution requirements

Revision History
Version Date Description
v0.8 JUN, 2015 PRELIMINARY Release
Updated CPU Complex: added CPU operating frequency limits.
v0.9 AUG, 2015 Updated Maxwell GPU: added GPU operating frequency limits.
Updated to show support for typical use case models.

Table of Contents
NVIDIA Jetson TX1 System-on-Module 1
1.0 Module Overview 7
Tegra X1 SoC .............................................................................................................................................. 8
Memory ........................................................................................................................................................ 9
Storage ........................................................................................................................................................ 9
Connectivity ................................................................................................................................................. 9
Networking ................................................................................................................................................... 9
Power (PMIC) .............................................................................................................................................. 9
Thermal Transfer Plate ................................................................................................................................ 9
Board-to-board Connector ......................................................................................................................... 10
WiFi/BT Antenna Connector ...................................................................................................................... 10
2.0 Power and System Management 11
Use Case Models ...................................................................................................................................... 11
Power Rails................................................................................................................................................ 11
2.2.1 VDD_IN ........................................................................................................................................ 11
2.2.2 VDD_RTC .................................................................................................................................... 12
2.2.3 IO Rail Voltages ........................................................................................................................... 12
Power Sequencing .................................................................................................................................... 12
2.3.1 Power Up ..................................................................................................................................... 12
2.3.2 Power Down ................................................................................................................................. 12
Power States ............................................................................................................................................. 13
2.4.1 ON State ...................................................................................................................................... 13
2.4.2 OFF State ..................................................................................................................................... 14
2.4.3 SLEEP State ................................................................................................................................ 14
Thermal Management ............................................................................................................................... 15
Clocks ........................................................................................................................................................ 15
WiFi Power States ..................................................................................................................................... 15
2.7.1 STA Mode .................................................................................................................................... 15
2.7.2 P2P Group-owner Powersave States .......................................................................................... 16
BlueTooth Power States ............................................................................................................................ 16
Ethernet ..................................................................................................................................................... 16
3.0 Interface and Signal Descriptions 17
SD/eMMC Controller ................................................................................................................................. 17
Serial ATA (SATA) Controller .................................................................................................................... 18
Display Interfaces ...................................................................................................................................... 18
3.3.1 MIPI Display Serial Interface (DSI) .............................................................................................. 18
3.3.2 High-Definition Multimedia Interface (HDMI) and DisplayPort (DP) Interfaces ........................... 19
3.3.3 Embedded DisplayPort (eDP) Interface ....................................................................................... 20
Audio Interfaces ......................................................................................................................................... 21
USB Interfaces........................................................................................................................................... 22
PCI Express (PCIe) Interface .................................................................................................................... 22
Serial Peripheral Interface ......................................................................................................................... 23
Inter-Chip Communication (I2C) Controller ............................................................................................... 25
UART Controller ........................................................................................................................................ 26
Video Input Interfaces .............................................................................................................................. 27
3.10.1 MIPI Camera Serial Interface (CSI) ........................................................................................... 27
3.10.2 Camera / VI (Video Input) .......................................................................................................... 28
Miscellaneous Interfaces ......................................................................................................................... 28
3.11.1 Debug ......................................................................................................................................... 28
3.11.2 Pulse Width/Frequency Modulation (PWFM)............................................................................. 28

4.0 Pin Definitions 30

Power-on Reset Behavior.......................................................................................................................... 31
Deep Sleep Behavior ................................................................................................................................. 31
GPIO Controller ......................................................................................................................................... 32
Pin Assignments ........................................................................................................................................ 33
Pin Descriptions ......................................................................................................................................... 34
5.0 Electrical Specification 41
Absolute Maximum Ratings ....................................................................................................................... 41
Recommended Operating Conditions ....................................................................................................... 42
Digital Logic Characteristics ...................................................................................................................... 43
6.0 Package and Thermal Specification 44
Thermal Characteristics ............................................................................................................................. 44
Package Drawing and Dimensions ........................................................................................................... 44

1.0 Module Overview

The Jetson TX1 System-on-Module (SoM) incorporates the following components and interfaces:
 NVIDIA Tegra X1 SoC

- NVIDIA Maxwell GPU
- Quad-core ARM Cortex-A57 CPU
 LPDDR4 memory
 eMMC 5.1 storage
 802.11ac 2x2 WiFi
 Gigabit Ethernet
 PMIC
 Thermal Transfer Plate (TTP) (primary thermal interface)
 400-pin board-to-board connector (exposes both high-speed and low-speed industry standard I/O)
 WiFi/BT antenna connectors
Table 1 Manufacturers and Part Numbers for 3rd Party Components Integrated on the Jetson TX1 Module
Component Manufacturer Part Number
WiFi 802.11ac Client/BT Broadcom Corp. BCM4354
Ethernet Controller 10/100/1000M Realtek Semiconductor Corp. RTL8153
PMIC Maxim Integrated MAX77620
400 pin Board-to-board connector Samtec SEAF-50-05-S-08-02-A-K
Figure 1 Jetson TX1 Block Diagram – General Application
Jetson TX1
USB 2.0
19V Jack VDD_IN 3.3V/5V Power USB0
Micro AB
Pre-Regs Subsystem
RJ45 w/Magnetics GBE_MDI PMIC USB1 USB 3.0
Gigabit CPU Reg uP1665P
Serial Port UART1 USB_SS0 Type A
Ethernet GPU Reg uP1665P
Bluetooth UART2 USB2
Thermal Power Monitors
Voltage Monitor PEX1
UART0 Sensor WiFi / Modem
Debug SDIO
JTAG
GPIOs/Control
I2C_GP0
SDMMC SD Card
Codec, Misc I2C_GP1
I2C_PM SATA SATA
SPI0 USB_SS1
PCIe x4
Display / Touch SPI2 Tegra X1 PEX0/2/3
GPIOs/Control
DSI[3:0] Display
SPI1 DP1 DSI – 2x4
Misc Expansion I2S1 DP0 DP/HDMI
GPIOs/Control GPIOs/Control eDP
I2S2 CSI[5:0]
WiFi/Modem
GPIOs/Control LPDDR4 eMMC 5.1 I2C_CAM Camera
4GB 16GB CAMx_MCLK Module(s)
AUDIO_MCLK
GPIOs/Control
Audio Codec I2S0
WiFi/BT
GPIOs/Control
Antenna Conn. #1 Antenna Conn. #2

Tegra X1 SoC
The NVIDIA Tegra® X1 series SoC couples the latest NVIDIA Maxwell™ GPU architecture with an ARM®v8 CPU cluster to
deliver high performance and power efficiency. The Maxwell GPU implements a number of architectural enhancements
designed to extract maximum performance per watt consumed. Designed for use in power-limited environments, Tegra X1
processors enable industry-leading visual computing capabilities, 32-bit and 64-bit operating capability, and integrate
advanced multi-function audio, video and image processing pipelines that exceed performance targets for next generation SFF
devices.
Refer to the Tegra X1 Embedded Datasheet for details and specifications.
Figure 2 Tegra X1 SoC Block Diagram
CPU COMPLEX
Color Legend:
Interrupt Controller
AVP Subsystem
NEON
NEON
NEON
NEON
CPU 0 CPU 1 CPU 2 CPU 3

Cortex-A57 Cortex-A57 Cortex-A57 Cortex-A57 Display Processor
PMC
Maxwell GPU Real Time Clock
D-cache I-cache D-cache I-cache D-cache I-cache D-cache I-cache Power Block
RTC
SCU (Snoop Control), BIU (Bus Interface) CPU Blocks
L2 Cache
VI & Associated
modules
AXI Demux Peripherals/External UART (x4)
Interfaces
CPU IF
Backplane Elements I2C Master/Slave
(x4)
AMBA PERIPHERIAL BUS (APB)

iRAM
MEMORY
CROSSBAR PROCESSOR DATA BUS
32-
bit
AXI/Xbar
MSelect Bus Bridge
SPI Master/Slave
PCIe (x3)
Dual Root
Port BPMP-L
Cache
APB Bridge
Maxw ell GPU AHB/APB
DMA Controller
AHB Security Engine

Data (SE) Audio Processing
Bridge
Engine (APE)
APB/AXI
MULTI-MASTER, AMBA HIGHSPEED BUS (AHB)

ADSP
Cortex-A9
GRAPHICS HOST
MEMORY Controller
ACONNECT
I2S/PCM Audio
(x4)
ISP Video Video TSEC Display
VI VIC JPEG
(x2) Encoder Decoder (x2) (x2)Display
AUDIO
HUB
EMC 0 EMC 1
Memory Interface
LPDDR4 LPDDR4
MIPI CSI
USB 2.0 crossbar
USB 2.0
(x3)
x4 x4 x4
Serial Camera Sensors

(x4 or 2x2) SATA XUSB
from PCIe HDMI DSI
x4 x1 eDP
DP (x2)
XUSB (4 ports)
SD/MMC
Controller
(x4)
port mux x8
USB 2.0 PHYs (x4)
USB3 / SATA x1 USB3 / PCIe x5 SD/SDIO/eMMC

Memory
On-board 4 GB of LPDDR4, over a 4 channel x 16 bit interface. The maximum frequency is 1600MHz. The theoretical peak
memory bandwidth is 25.6 GB/s.
Storage
On-board 16 GB of eMMC 5.1 flash storage. The theoretical peak bandwidth is 400 MB/s
Connectivity
Jetson TX1 integrates a 5G WiFi 802.11ac Client/combined BT module, which includes the following features:
 WiFi Ready
- Implements one- and two-stream IEEE 802.11 ac specification
- Transfer speeds up to 800 Mbps
- Backwards compatible with legacy 802.11b/g/a/n devices
 BlueTooth Ready
- Bluetooth 4.0 ready (can connect to Bluetooth 4.0 enabled devices)
- HIDP
- Audio – A2DP (advanced audio distribution profile)
- RFKILL
Refer to the manufacturer’s documentation for details and specifications.
Networking
Jetson TX1 integrates a 10/100/1000M Ethernet Controller, which includes the following features:
 10/100/1000M Ethernet controller

 IEEE 802.3u Media Access Controller
 Embedded memory
Refer to the manufacturer’s documentation for details and specifications.
Power (PMIC)
Power is provided by a single DC input, and supplied to the devices on board through a Power Management IC and dedicated
voltage regulators. More details can be found in section 2.0
Thermal Transfer Plate

Jetson TX1 is provided with a thermal transfer plate (TTP) to simplify integration with a system-level thermal solution. The TTP
mechanically isolates the Jetson TX1 board and components from external mechanical forces, standardizes the thermal and
mechanical interface, and allows for a modular system design.
Refer to the Jetson TX1 Thermal Design Guide for system-level thermal and mechanical requirements.

Board-to-board Connector
The primary interface to Jetson TX1 is via a 400-pin board-to-board connector. This connector exposes both high-speed and
low-speed industry standard I/O.
Refer to section 4.0 of this document for the individual pin descriptions and mapping.
Refer to the NVIDIA Jetson TX1 Product OEM Design Guide for details on integrating the TX1 module and mating
connector into product designs.
WiFi/BT Antenna Connector

Male I-PEX antenna connectors for WiFi and BT are located on the module. These support antennas with the following
characteristics:
 2x Female I-PEX connector

 Dual-band (x2)
 2.4 GHz and 5 GHz frequency bands
 50 Ω impedence

2.0 Power and System Management

Jetson TX1 is a complex system on a chip and contains features for ease of system integration. It can operate from a single
power source (VDD_IN). All internal module voltages and IO voltages are generated from this input. An optional back up
battery can be attached to the VDD_RTC module input. This will maintain the on system RTC, when VDD_IN is not present.
The Jetson TX1 is required to be powered on and off in a known sequence. Exact details are given in the following sections.
The sequencing is determined through a set of control signals. The signal CARRIER_PWR_ON is provided so that the carrier
board is powered on using this signal after the Jetson TX1 is fully powered.
Use Case Models

The Jetson TX1 module can be used in a wide variety of applications requiring varying performance metrics. To accommodate
these varying conditions, Tegra SoC frequencies and voltages are actively managed by Tegra Power and Thermal
Management Software and influenced by workload. To provide guidance, NVIDIA has modeled both partial use and full use
case models. Note that the operating frequencies for CPU and GPU may have different maximum limits in each model.
Use Case Models (UCM):
 UCM #1 (Partial Use)

- Operating time per day at max specification: 20%
- Operating Temperature Range (TJ): -25°C – 105°C
- Operating Lifetime: 5 years
 UCM #2 (Full Use)
- Operating time per day at max specification: 100%
- Operating Temperature Range (TJ): -25°C – 105°C
- Operating Lifetime: 5 years
Table 2 TM670D (UCM#1, UCM#2) Maximum GPU Operations
Guaranteed GPU Operations: GLOPS (fp16)

Use Case Model
Tj <= 50C Tj <= 90C Tj <= 105C
UCM: 1 1024 1024 942
UCM: 2 1024 1024 942
Table 3 TM670D (UCM #1, UCM #2) Maximum CPU Operating Frequency
Guaranteed CPU Operating Frequency

Use Case Model
Tj <= 50C Tj <= 90C Tj <= 105C
UCM: 1 1.9GHz 1.9GHz 1.53GHz
UCM: 2 1.9GHz 1.9GHz 1.42GHz
Power Rails
2.2.1 VDD_IN
VDD_IN should be supplied by the carrier board that the Jetson TX1 is designed to connect to. It must meet the required
electrical specifications detailed in section 5.

2.2.2 VDD_RTC
A back up battery can be connected to this input. It will be used to maintain the JETSON TX1 RTC when VDD_IN is not
present. This pin is connected directly to the onboard PMIC MAX77620. Details of the types of backup cells that optionally can
be connected are found in the MAX77620 datasheet. When a backup cell is connected the PMIC RTC will retain its contents
and also can be configured to charge the backup cell.
The following backup cells may be attached to this pin:

 Super Capacitor (gold cap, double layer electrolytic)
 Standard capacitors (tantalum)
 Rechargeable Lithium Manganese cells
The backup cells must provide a voltage in the range 2.5V to 3.5V. These will be charged with a constant current (CC) ,
constant voltage (CV) charger that can be configured between 2.5V and 3.5V CV output and 50uA to 800uA CC.
2.2.3 IO Rail Voltages

All of the signals on the Jetson TX1 interfaces are referenced to on-module voltage rails. No IO voltage is required to be
supplied to the module. Please consult the Jetson TX1 Product OEM Design Guide for details of connecting to each of the
interfaces.
Power Sequencing
2.3.1 Power Up
It is required that the Jetson TX1 and the product carrier board be power sequenced correctly to avoid potential damage to
components on either the Jetson TX1 or the carrier board system. The carrier board must wait until the signal
CARRIER_PWR_ON is asserted from the Jetson TX1, before enabling its power. Jetson TX1 will de-assert the RESET_OUT#
signal to enable the complete system to boot.
Figure 3 Power Up Sequence

1 2 3 4 5 6 7 8
VDD_IN (6V-19V)
VIN_PWR_BAD#
POWER_BTN#
Jetson TX1 System Power
CARRIER_PWR_ON
Carrier Board System Power
RESET_OUT#
2.3.2 Power Down

It is also required that the Jetson TX1 and the product carrier board be power down in the correct sequenced. On receiving a
Shutdown request the Jetson TX1 will assert the RESET_OUT# signal, allowing the carrier board to put any components into
a known state. The CARRIER_PWR_ON signal will then be de-asserted to indicate to the carrier board to power down. The
carrier board should disable its power at this point. The Jetson TX1 will then disable its power and shut down.

Figure 4 Power Down Sequence

1 2 3 4 5 6 7 8
RESET_OUT#
CARRIER_PWR_ON
Carrier Board System Power
Jetson TX1 System Power
VIN_PWR_BAD#
VDD_IN (6V-19V)
Power States
Jetson TX1 operates has 3 main power modes, OFF, SLEEP and ON. The module transitions between these states based on
various events from hardware or software. Figure x shows the transitions between these states.
Figure 5 Power State Diagram
OFF
OFF ON
EVENT EVENT
ON
WAKE SLEEP
EVENT EVENT
SLEEP
2.4.1 ON State
This power state is entered from either of OFF or SLEEP states.
In this state Jetson TX1 is fully functional and will operate at normal operating conditions.
An ON event has to occur for a transition between OFF and ON states. The only ON EVENT defined is a low to high transition
on the POWER_BTN# pin. This must occur with VDD_IN connected to a power rail, and VIN_PWR_BAD# at a logic1.
When in the ON power state, Jetson TX1 has various design features to minimize the power when possible. These include
such items as:
 Advanced Power Management IC (PMIC)

 On system Power Gating

 Advanced on chip Clock Gating

 Dynamic Voltage and Frequency Scaling (DVFS)
 Always on logic used to wake the system based on either a timer event or an external trigger (e.g., key press).
 Low power DRAM (LPDDR4)
2.4.2 OFF State

The OFF state is the default state when the system is not powered. It can only be entered from the ON state, through an OFF
event. OFF Events are listed in the table below.
Table 4 OFF State Events

Event Details Preconditions
Power Button (10 second Press) Keeping POWER_BTN# low for 7 seconds In ON State
will power down the Jetson TX1
SW Shutdown SW will initiate ON state, SW operational
Thermal Shutdown If the internal temperature of Jetson TX1 Any power state
reaches an unsafe temperature, the HW is
designed to initiate a shutdown
Voltage Brown out If VDD_IN drops below 5V then the onboard
system will shut Jetson TX1 down.
2.4.3 SLEEP State

The Sleep state can only be entered from the ON state. This state allows the Jetson TX1 to quickly resume to an operational
state without performing a full boot sequence. In this state Jetson TX1 operates in low power with enough circuitry powered to
allow the device to resume and re-enter the ON state. During this state the output signals from Jetson TX1 are maintained at
their logic level prior to entering the state (i.e. they do not change to a 0V level).
The SLEEP state can only be entered directly by SW. For example, operating within an OS, with no operations active for a
certain time can trigger the OS to initiate a transition to the SLEEP state.
To Exit the SLEEP state a WAKE event must occur. WAKE events can occur from within the Jetson TX1 or from external
devices through various pins on the JETSON TX1 connector. A full list is given in the table below.
Table 5 SLEEP State Events

Event Details
RTC WAKE up Timers within Jetson TX1 can be programmed, on SLEEP entry. When these expire they
will create a WAKE event to exit the SLEEP state.
Thermal Condition If the JETSON TX1 internal temperature exceeds programmed hot and cold limits the
system will be force to wake up, so it can report and take appropriate action (shut down for
example)
Low VDD_IN If VDD_IN voltage drops below 6V then the system can be woken up to initiate a graceful
shutdown.
USB VBUS detection If VBUS is applied to the system (USB cable attached) then the device can be configured to
Wake and enumerate
SD Card detect The Card detect pin may be configured to enable the system to wake.
On Jetson TX1 WIFI Wake Wifi can be configured to Wake up the system
On Jetson TX1 Bluetooth Wake Bluetooth events can also trigger a system Wake
Jetson TX1 connector Interface WAKE There are 16 signals on the Jetson TX1 connector. These are listed in the table below.
signal

Table 6 Programmable Interface Wake Event

Event Jetson TX1 Pin Assigned Wake #
Audio Interrupt GPIO20_AUD_INT 4
External BT Wake Request to AP GPIO13_BT_WAKE_AP 10
External WiFi Wake Request to AP GPIO10_WIFI_WAKE_AP 11
Modem to AP Ready GPIO17_MDM2AP_READY 14
Modem Coldboot Alert GPIO18_MDM_COLDBOOT 15
HDMI CEC HDMI_CEC 19
GPIO Exapander 0 Interrupt GPIO_EXP0_INT 21
Power Button On POWER_BTN# 24
Charging Interrupt CHARGING# 26
Sleep Request from Carrier Board SLEEP# 27
Ambient/Proximity Interrupt GPIO8_ALS_PROX_INT 32
HDMI Hot Plug Detect DP1_HPD 53
Battery Low Warning BATLOW# 57
Primary Modem Wake Request to AP GPIO16_MDM_WAKE_AP 61
Touch Controller Interrupt GPIO6_TOUCH_INT 62
Motion Sensor Interrupt GPIO9_MOTION_INT 63
Thermal Management
Jetson TX1 is designed to operate under various workloads, and environmental conditions. It has been design so that an
active or passive heat sinking solution can be attached. The module contains various methods through hardware and software
to limit the internal temperature to within operating limits. More details can be found in the Thermal design guide.
Clocks
Jetson TX1 requires no external clocks for operation. All Jetson TX system clocks are generated within the module. This
includes a low power 32.768 kHz clock for real-time operation.
The following clocks are provided by Jetson TX1 for use with the peripheral interfaces:
AUDIO_MCLK, TOUCH_CLK, SPI0_CLK, SPI1_CLK, SPI2_CLK, CAM0_MCLK, CAM1_MCLK.
WiFi Power States

Jetson TX1 integrates a 5G WiFi 802.11ac Client. The following power states are available
2.7.1 STA Mode

 PM0
No power save, always on.
 PM1
Legacy 802.11 powersave. STA must indicate to the AP that it is entering into powersave by setting the PM bit in a data packet.
Upon acknowledgement from the AP it can go into powersave. STA must wake up periodically (at period=DTIM) to check AID in the
TIM map. If AID is set, STA will use a PS-Poll packet to fetch buffered packets (one PS-Poll per buffered packet). This is an
inefficient mechanism as the traffic will tend to be bursty.
 PM2
Vendor implementation. In PM2 mode, whenever there is a traffic (either Tx or Rx), the DUT will come out of powersave and remain
there until packet exchanges have ceased for a minimum idle period (typically 200ms). When there is traffic, PM2 will operate nearly
as well as PM0 mode, with almost no PS related latency. When there is no traffic, PM2 will be similar to PM1 powersave.

2.7.2 P2P Group-owner Powersave States

 Opportunistic power save (OPS)
OPS allows the P2P Group Owner to save power when all associated clients are in a sleep state. P2P Power Management protocol
defines an availability period “CTWindow” (Client Traffic Window), during which a P2P Group Owner is present. P2P Clients are
allowed to transmit during CTWindow period. If at the end of the CTWindow all associated P2P Clients are in a sleep state, the P2P
Group Owner is permitted to sleep until the next Beacon time. However, if any P2P Client remains in active mode at the end of the
CTWindow the P2P Group Owner must remain awake until the next Beacon time.
To change OPS mode:
Use the wpa_cli utility to issue the command “p2p_set ctwindow <value>”
Where ‘value’ is CTwindow in ms
Use the wpa_cli utility to issue the command “p2p_set opps <value>”
Where ‘value’ 1/0 enables/disables OPS respectively (this must be issued every time the CTwindow is changed in order to be
reflected in the firmware)
 Notice-of-Absence
NoA is similar to the Opportunistic Power Save protocol. For NoA, GO deﬁnes absence periods with a signaling
element included in Beacon frames and Probe Responses containing
To configure NoA:
Use the wpa_cli ulility to issue the command “p2p_set noa <count, start, duration>”
Where duration is the length of each absence period, start time is the start time of the first absence period (after the
current beacon frame), and count is the number of absence periods to schedule during the current NoA.
BlueTooth Power States

Jetson TX1 integrates a BlueTooth controller. The following power states are available:
 Active
This is the default state. No power savings.
 LP
This is the power saving state. The BT chip will go into low power mode, and will wake on traffic.
To change the mode:
Assert/Deassert the ext_wake GPIO to put the chip in Active/LP mode.
The BT chip also includes a wake-on-BT function. When it receives data, the chip will assert Host_wake GPIO. The AP,
depending on its state, can treat it as a wake interrupt or info GPIO.
Ethernet
The Realtek RTL8153AI device used on the Jetson TX1 module contains many power saving features. Refer to the device
datasheet for more details. Please check the SW BSP for all features supported.

3.0 Interface and Signal Descriptions
SD/eMMC Controller
Standard Notes
SD Specifications Part A2 SD Host Controller

Standard Specification Version 4.00
SD Specifications Part 1 Physical Layer

Specification Version 4.00
SD Specifications Part E1 SDIO Specification Support for SD 4.0 Specification without UHS-II
Version 4.00
Embedded Multimedia Card (e•MMC), Electrical

Standard 5.1
The SecureDigital (SD)/Embedded MultiMediaCard (eMMC) controller is capable of interfacing to SD/eSD, SDIO cards, and
eMMC devices. It has a direct memory interface and is capable of initiating data transfers between memory and external card.
The SD/eMMC controller supports 2 different bus protocols: SD and eMMC bus protocol for eMMC. It has an APB Slave
interface to access configuration registers. To access the iRAM for Micro Boot, the SD/eMMC controller relies on the AHB
redirection arbiter in the Memory Controller.
Features:
 Supports of 8-bit data interface for eMMC/eSD cards

 Supports 4-bit data interface for SD cards
 Allows card to interrupt host in 1-bit, 4-bit, 8-bit SD modes.
 Supports Read wait Control, Suspend/Resume operation for SDIO cards
 Supports FIFO overrun and underrun condition by stopping SD clock
 Supports addressing larger capacity SD 3.0 or SD-XC cards up to 2 TB.
Jetson TX1 provides two instances of this controller: The SDCARD interface is intended for supporting an SD Card socket &
the SDIO interface is available to support various compatible peripherals, such as a secondary Wi-Fi/BT controller. The
SD/SDIO controllers support Default and High Speed modes as well as the High and Low voltage ranges.
Table 7 SD/MMC Controller I/O Capabilities

Controller Bus Width Supported I/O bus Maximum Notes
Voltages (V) clock (MHz) Bandwidth
(MBps)
SDCARD 4 3.3, 1.8 208 104
SDIO 4 3.3, 1.8 208 104
Table 8 SD/SDIO Signal Descriptions
Signal Name Type Description
SDCARD_CLK, SDIO_CLK Output SD/SDIO/MMC Clock
SDCARD_CMD, SDIO_CMD Bidirectional SD/SDIO/MMC Command
SDCARD_DAT[3:0], SDIO_DAT[3:0] Bidirectional SD/SDIO/MMC Data bus
SDCARD_WP Input SD Write Protect
SDCARD_CD# Input SD Card Detect

Serial ATA (SATA) Controller

Standard Notes
Serial ATA Revision 3.1 Including all errata, ENC, and TP, except DHU (direct head unload)
Serial ATA Advanced Host Controller Interface
(AHCI) Specification, Rev 1.3.1
The SATA controller enables a control path from Jetson TX1 to an external SATA device. A SSD / HDD / ODD drive can be
connected. Controller can support the maximum throughput of a Gen 2 drive.
Features:
 Port multiplier support

- Command based switching (CBS)
 Supported Cables and connectors
- Standard internal connector
- Internal micro connector
- Internal slimline connector
- mSATA connector
- BGA SSD interface
- Not supported: External connector (eSATA), USM, Internal LIF-SATA
Table 9 SATA Signal Descriptions
SATA_RX+/– Input Receive data, differential analog input
SATA_TX+/– Output Transmit data, differential analog output
Display Interfaces
The Jetson TX1 Display Controller Complex integrates two MIPI-DSI interfaces and two Serial Output Resources (SOR) to
collect pixels from the output of the display pipeline, format/encode them to desired format, and then streams to various output
devices. The SOR consists of several individual resources which can be used to interface with different display devices such
as HDMI, DP or eDP.
3.3.1 MIPI Display Serial Interface (DSI)

The Display Serial Interface (DSI) is a serial bit-stream replacement for the parallel MIPI DPI and DBI display interface
standards. DSI reduces package pin-count and I/O power consumption. DSI support enables both display controllers to
connect to an external display(s) with a MIPI DSI receiver. The DSI transfers pixel data from the internal display controller to
an external third-party LCD module.
Features:
 PHY Layer
- Start / End of Transmission. Other out-of-band signaling
- Per DSI interface: 1 Clock Lane; up to 4 Data Lanes
- Supports link configuration – 1x4, 2x4
- Supports dual link operation in 2x4 configurations for asymmetrical/symmetrical split in both left-right side or odd-
even group split schemes.

- DSC link compression

- Maximum link rate 1.5Gbps as per MIPI D-PHY 1.1v version
- Maximum 10MHz LP receive rate
 Lane Management Layer with Distributor
 Protocol Layer with Packet Constructor
 Supports MIPI DSI 1.0.1v version mandatory features
 Command Mode (One-shot) with Host and/or display controller as master
 Clocks
- Bit Clock : Serial data stream bit-rate clock
- Byte Clock : Lane Management Layer Byte-rate clock
- Application Clock: Protocol Layer Byte-rate clock.
 Error Detection / Correction
- ECC generation for packet Headers
- Checksum generation for Long Packets
 Error recovery
 High Speed Transmit timer
 Low Power Receive timer
 Turnaround Acknowledge Timeout
Table 10 DSI Signal Descriptions
Name Type Description
DSI_0_CLK_N, DSI_0_CLK_P Output Differential output clock for up to two 1x4 DSI interfaces
DSI_2_CLK_N, DSI_2_CLK_P
DSI_0_D[1:0]_N, DSI_0_D[1:0]_P Bidirectional Differential data lanes for DSI interfaces.

DSI_1_D[1:0]_N, DSI_1_D[1:0]_P DSI_0_D[1:0] & DSI_1_D[1:0] are associated with DSI_0_CLK.
DSI_2_D[1:0]_N, DSI_2_D[1:0]_P DSI_2_D[1:0] & DSI_3_D[1:0] are associated with DSI_2_CLK
DSI_3_D[1:0]_N, DSI_3_D[1:0]_P
3.3.2 High-Definition Multimedia Interface (HDMI) and DisplayPort (DP) Interfaces

Standard Notes
High-Definition Multimedia Interface (HDMI) > 340MHz pixel clock
Specification, version 2.0 Scrambling support
Clock/4 support (1/40 bit-rate clock)
High-bandwidth Digital Content Protection
(HDCP) System Specification, version 2.2
High-bandwidth Digital Content Protection
(HDCP) System Specification, version 1.3
The HDMI and DP interfaces share the same set of interface pins. A new transport mode was introduced in HDMI 2.0 to
enable link clock frequencies greater than 340MHz and up to 600MHz. For transfer rates above 340MHz, there are two main
requirements:
 All link data, including active pixel data, guard bands, data islands and control islands must be scrambled.
 The TMDS clock lane must toggle at CLK/4 instead of CLK. Below 340MHz, the clock lane toggles as normal
(independent of the state of scrambling).

Features:
 On-chip HDCP key storage, no external Secure ROM required

 Support for both HDCP 1.3 and HDCP 2.2
 HDMI
- HDMI 2.0 mode (3.4Gbps < data rate <= 6Gbps)
- HDMI 1.4 mode (data rate<=3.4Gbps)
- Multi-channel audio from HDA controller, up to 8 channels 192kHz 24-bit.
- Vendor Specific Info-frame (VSI) packet transmission
- 24-bit RGB and 24-bit YUV444 (HDMI) pixel formats
- Transition Minimized Differential Signaling (TMDS) functional up to 340MHz pixel clock rate
Table 11 HDMI Signal Descriptions
DP1_TX3+ Output HDMI Differential Clock. AC coupling & pull-downs (with disble) required on Carrier
DP1_TX3– board.
DP1_TX[2:0]+ Output HDMI/DP Differential Data. AC coupling & pull-downs (with disble) required on Carrier
DP1_TX[2:0]– board.
DP1_TX0 = HDMI TXD2
DP1_TX1 = HDMI TXD1
DP1_TX2 = HDMI TXD0
DP1_HPD Input Interrupt. Used for Hot Plug detection. Level shifter required as this pad is not 5V
tolerant
HDMI_CEC Bidirectional Consumer Electronics Control (CEC) one-wire serial bus.

NVIDIA provides low level CEC APIs (read/write). These are not supported in earlier
Android releases. For additional CEC support, 3rd party libraries need to be made
available.
DP1_AUX_CH+ (DDC_SCL) Output DDC Serial Clock. Level shifter required; pad is not 5V tolerant.
DP1_AUX_CH– (DDC_SDA) Bidirectional DDC Serial Data. Level shifter required; pad is not 5V tolerant.
Table 12 DP Signal Descriptions
DP1_TX[3:0]+ Output DP Differential Lanes. AC coupling required on Carrier board.

DP1_TX[3:0]–
DP1_HPD Input Interrupt. Used for Hot Plug detection.
DP1_AUX_CH+ Bidirectional DP auxiliary channel. AC coupling required on Carrier board.

DP1_AUX_CH–
3.3.3 Embedded DisplayPort (eDP) Interface

Standard Notes
Embedded DisplayPort 1.4 Supported eDP 1.4 features:
 Additional link rates
 Enhanced framing
 Power sequencing
 Reduced aux timing
 Reduced main voltage swing
eDP is a mixed-signal interface consisting of 4 differential serial output lanes and 1 PLL. This PLL is used to generate a high
frequency bit-clock from an input pixel clock enabling the ability to handle 10-bit parallel data per lane at the pixel rate for the

desired mode. Embedded DisplayPort (eDP) modes (1.6GHz for RBR, 2.16GHz, 2.43GHz, 2.7GHz for HBR, 3.42GHz,
4.32GHz and 5.4GHz for HBR2).
NOTE: eDP has been tested according to DP1.2b PHY CTS even though eDPv1.4 supports lower swing voltages and
additional intermediate bit rates. This means the following nominal voltage levels (400mV, 600mV, 800mV,
1200mV) and data rates (RBR, HBR, HBR2) are tested. This interface can be tuned to drive lower voltage swings
below 400mV and can be programmed to other intermediate bit rates as per the requirements of the panel and the
system designer.
The eDP block collects pixels from the output of the display pipeline, formats/encodes them to the eDP format, and then
streams them to various output devices. It drives local panels only (does not support an external DP port), includes a small test
pattern generator and CRC generator.
Table 13 eDP Signal Descriptions
DP0_TX[3:0]+ Output eDP Differential lanes

DP0_TX[3:0]–
DP0_HPD Input eDP hot-plug detect
DP0_AUX_CH+ Bidirectional eDP Auxiliary channel

DP0_AUX_CH–
Audio Interfaces
Jetson TX1 brings out four I2S interfaces. The I2S Controller transports streaming audio data between system memory and an
audio codec. The controller supports I2S format, Left-justified Mode format, Right-justified Mode format, and DSP mode format,
as defined in the Philips inter-IC-sound (I2S) bus specification. The timing in the following sections applies to any of these
interfaces depending on whether they are configured for I2S/PCM or TDM mode.
The I2S and PCM (master and slave modes) interfaces support clock rates up to 24.5760MHz.
The I2S controller supports point-to-point serial interfaces for the I2S digital audio streams. I2S-compatible products, such as
compact disc players, digital audio tape devices, digital sound processors, and those with digital TV sound may be directly
connected to the I2S controller. The controller also supports the PCM and telephony mode of data-transfer. Pulse-Code-
Modulation (PCM) is a standard method used to digitize audio (particularly voice) patterns for transmission over digital
communication channels. The Telephony mode is used to transmit and receive data to and from an external mono CODEC in
a slot-based scheme of time-division multiplexing. The I2S controller supports bidirectional audio streams and can operate in
half-duplex or full-duplex mode.
Features:
 Basic I2S modes to be supported (I2S, RJM, LJM and DSP) in both Master and Slave modes.
 PCM mode with short (one-bit-clock wide) and long-fsync (two bit-clocks wide) in both master and slave modes.
 NW-mode with independent slot-selection for both Tx and Rx
 TDM mode with flexibility in number of slots and slot(s) selection.
 Capability to drive-out a High-z outside the prescribed slot for transmission
 Flow control for the external input/output stream.
Table 14 I2S Signal Descriptions
I2S[3:0]_LRCK Bidirectional Frame Sync/Word Select. Supports I2S/PCM audio. Interface can be master or slave
I2S[3:0]_CLK Bidirectional Serial Clock/Bit Clock. Supports I2S/PCM audio. Interface can be master or slave

I2S[3:0]_SDIN Input Data In. Supports I2S/PCM audio. Interface can be master or slave.
I2S[3:0]_SDOUT Bidirectional Data Out. Supports I2S/PCM audio. Interface can be master or slave.
USB Interfaces
Standard Notes
Universal Serial Bus Specification Revision 3.0 Refer to specification for related interface timing details.
Universal Serial Bus Specification Revision 2.0 USB Battery Charging Specification, version 1.0; including Data Contact Detect protocol
Modes: Host and Device
Speeds: Low, Full, and High
Refer to specification for related interface timing details.
Enhanced Host Controller Interface Specification Refer to specification for related interface timing details.
for Universal Serial Bus revision 1.0
Table 15 USB Signals
Signal (Pin Name if different) Type Description
USB[2:0]_D– Analog USB Data Negative (USB 2.0 interfaces)
USB[2:0]_D+ Analog USB Data Positive (USB 2.0 interfaces)
USB_SS1_RX– Input USB 3.0 #1: Receive Data Negative input
USB_SS1_RX+ Input USB 3.0 #11: Receive Data Positive input
USB_SS1_TX– Output USB 3.0 #1: Transmit Data Negative output
USB_SS1_TX+ Output USB 3.0 #1: Transmit Data Positive output
USB_SS2_RX– (PEX1_RX– or PEX3_RX–) Input USB 3.0 #2 options: Receive Data Negative input
USB_SS2_RX+ (PEX1_RX+ or PEX3_RX+) Input USB 3.0 #2 options: Receive Data Positive input
USB_SS2_TX– (PEX1_TX– or PEX3_TX–) Output USB 3.0 #2 options: Transmit Data Negative output
USB_SS2_TX+ (PEX1_TX+ or PEX3_TX+) Output USB 3.0 #2 options: Transmit Data Positive output
USB_SS3_RX– (SATA_RX–) Input USB 3.0 #3 option: Receive Data Negative input
USB_SS3_RX+ (SATA_RX+) Input USB 3.0 #3 option: Receive Data Positive input
USB_SS3_TX– (SATA_TX–) Output USB 3.0 #3 option: Transmit Data Negative output
USB_SS3_TX+ (SATA_TX+) Output USB 3.0 #3 option: Transmit Data Positive output
Note: USB_SS0 interface is not available at the connector; it is used for the Gigabit Ethernet controller on Jetson TX1.
PCI Express (PCIe) Interface

Standard Notes
PCI Express Base Specification Revision 2.0 Jetson TX1 meets the timing requirements for the Gen2 (5.0 GT/s) data rates. Refer to
specification for complete interface timing details.
Although NVIDIA validates that the Jetson TX1 design complies with the PCIe
specification, PCIe software support may be limited.
Jetson TX1 integrates a x5 lane PCIe bridge to enable a control path from Jetson TX1 to external PCIe devices. Two PCIe
Gen2 controllers (one x4, one x1) support connections to one or two endpoints.

Table 16 PCIe Signal Descriptions
Signal Function (Pin Name) Type Description
PCI Express Wake

PEX_WAKE# Input This signal is used as the PCI Express defined WAKE# signal. When asserted by a PCI
Express device, it is a request that system power be restored. No interrupt or other
consequences result from the assertion of this signal.
PCIe Controller #0
PEX0_REFCLK+/– Output Differential Reference Clocks. PEX0_REFCLK is associated with PCIe Controller #0.
PEX2_RX+/– (Lane 3)
PEX_RFU_RX+/– (Lane 2)
Input Differential Receive Data Lanes, associated with PCIe Controller #0.
USB_SS1_RX+/– (Lane 1)
PEX0_RX+/– (Lane 0)
PEX2_TX+/– (Lane 3)
PEX_RFU_TX+/– (Lane 2)
Output Differential Transmit Data Lanes, associated with PCIe Controller #0.
USB_SS1_TX+/– (Lane 1)
PEX0_TX+/– (Lane 0)
PCI Express Reference Clock Request

PEX0_CLKREQ# Bidirectional This signal is used by a PCI Express device to indicate it needs the PEX_REFCLKP and
PEX_REFCLKN to actively drive reference clock. PEX0_CLKREQ# is associated with PCIe
Controller #0.
PCI Express Reset
This signal provides a reset signal to all the PCI Express links. It must be asserted 100 ms
PEX0_RST# Output
after the power to the PCI Express slots has stabilized. PEX0_RST# is associated with PCIe
Controller #0.
PCIe Controller #1
PEX1_REFCLK+/– Output Differential Reference Clocks. PEX1_REFCLK is associated with PCIe Controller #1.
PEX1_RX+/– Input Differential Receive Data Lane, associated with PCIe Controller #1.
PEX1_TX+/– Output Differential Transmit Data Lane, associated with PCIe Controller #1.
PCI Express Reference Clock Request

PEX1_CLKREQ# Bidirectional This signal is used by a PCI Express device to indicate it needs the PEX_REFCLKP and
PEX_REFCLKN to actively drive reference clock. PEX0_CLKREQ# is associated with PCIe
Controller #1.
PCI Express Reset

PEX1_RST# Output This signal provides a reset signal to all the PCI Express links. It must be asserted 100 ms
after the power to the PCI Express slots has stabilized. PEX0_RST# is associated with PCIe
Controller #1.
Serial Peripheral Interface

The SPI controllers operate up to 65 Mbps in master mode and 45 Mbps in slave mode. It allows a duplex, synchronous, serial
communication between the controller and external peripheral devices. It consists of 4 signals, SS_N (Chip select), SCK
(clock), MOSI (Master data out and Slave data in) and MISO (Slave data out and master data in). The data is transferred on
MOSI or MISO based on the data transfer direction on every SCK edge. The receiver always receives the data on the other
edge of SCK.
Features:
 Independent RX FIFO and TX FIFO.

 Software controlled bit-length supports packet sizes of 1 to 32 bits.
 Packed mode support for bit-length of 7 (8-bit packet size) and 15 (16-bit packet size).

 SS_N can be selected to be controlled by software, or it can be generated automatically by the hardware on packet
boundaries.
 Receive compare mode (controller listens for a specified pattern on the incoming data before receiving the data in the
FIFO).
 Simultaneous receive and transmit supported
 Supports Master mode. Slave mode has not been validated
Table 17 SPI Signal Descriptions
SPI[2:1]_CS[1:0]# Bidirectional Chip Select options for SPI[2:1]: Depending on pin multiplexing, there may be one or more
SPI0_CS0_N chip select options for each SPI interface. Multiple available chip selects can be used to
differentiate between two or more SPI slave devices
SPI[2:0]_MISO Bidirectional Master In / Slave Out.
SPI[2:0]_MOSI Bidirectional Master Out / Slave In.
SPI[2:0]_CLK Bidirectional Serial Clock: Clock phase and polarity is programmable.
Figure 5 SPI Master Timing Diagram
tCS
SPIx_CSx_N
tCSS tCSH tCSS tCSH
SPIx_SCK 0 n
tSU
SPIx_MOSI MSB IN LSB IN
tHD
SPIx_MISO
Table 18 SPI Master Timing Parameters

Symbol Parameter Min Typ Max Unit
Fsck SPIx_SCK clock frequency 65 MHz
Psck SPIx_SCK period 1/Fsck ns
50%Psck 50%Psck
tCH SPIx_SCK high time ns
-10% +10%
50%Psck 50%Psck
tCL SPIx_SCK low time ns
-10% +10%
tCRT SPIx_SCK rise time (slew rate) 0.1 V/ns
tCFT SPIx_SCK fall time (slew rate) 0.1 V/ns
tSU SPIx_MOSI setup to SPIx_SCK rising edge 2 ns
tHD SPIx_MOSI hold from SPIx_SCK rising edge 3 ns
tCSS SPIx_CSx_N setup time 2 ns
tCSH SPIx_CSx_N hold time 3 ns
tCS SPIx_CSx_N high time 10 ns
Note: Polarity of SCLK is programmable. Data can be driven or input relative to either the rising edge (shown above) or falling edge.

Figure 6 SPI Slave Timing Diagram
tCSH
SPIx_CSx_N
tCSU tSCP tCH tCL tCCS
SPIx_SCK 0 1 n
tDSU
SPIx_MOSI
tDH tDD
SPIx_MISO
Table 19 SPI Slave Timing Parameters

Symbol Parameter Min Typ Max Unit
tSCP SPIx_SCK period 2*(tSDD+ tMSU1) ns
tSCH SPIx_SCK high time tSDD + tMSU1 ns
tSCL SPIx_SCK low time tSDD + tMSU1 ns
tSCSU SPIx_CSx_n setup time 1 tSCP
tSCSH SPIx_CSx_n high time 1 tSCP
tSCCS SPIx_SCK rising edge to SPIx_CSx_n rising edge 1 1 tSCP
tSDSU SPIx_MOSI setup to SPIx_SCK rising edge 1 1 ns
tSDH SPIx_MOSI hold from SPIx_SCK rising edge 2 11 ns
tSDD SPIx_MISO delay from SPIx_SCLK falling edge (ALT12) 3.5 16 ns
2
tSDD SPIx_MISO delay from SPIx_SCLK falling edge (ALT2 ) 3 13 ns
tSDD SPIx_MISO delay from SPIx_SCLK falling edge (ALT32) 4 17 ns
1. tMSU is the setup time required by the external master
2. ALT1/2/3 refers to the position of the SPI pins in the Signal Pinout Multiplexing tables in Section 3.1, Signal List and Multiplexing Functions.
Note: Polarity of SCLK is programmable. Data can be driven or input relative to either the rising edge (shown above) or falling edge.
Inter-Chip Communication (I2C) Controller

Standard Notes
NXP inter-IC-bus (I2C) specification
The I2C controller implements an I2C-bus specification compliant I2C master and a slave controller. The I2C controller
supports multiple masters and slaves in: Standard-mode (up to 100Kbit/s), Fast-mode (up to 400 Kbit/s), Fast-mode plus
(Fm+, up to 1Mbit/s) and High-speed mode (up to 3.4Mbit/s) of operations. A general purpose I2C controller allows system
expansion for I2C-based devices, such as AM/FM radio, remote LCD display, serial ADC/DAC, and serial EPROMs, as
defined in the NXP inter-IC-bus (I2C) specification. The I2C bus supports serial device communications to multiple devices.
The I2C controller handles bus mastership with arbitration, clock source negotiation, speed negotiation for standard and fast
devices, and 7-bit and 10-bit slave address support according to the I2C protocol and supports master and slave mode of
operation.
Table 20 I2C Usage

Interface (Balls) name Target Application On-Jetson TX1 Termination
I2C_GP0_CLK/DAT Various 1KΩ on Jetson TX1 to 1.8V

I2C_GP1_CLK/DAT Power Monitors 1KΩ on Jetson TX1 to 3.3V
I2C_PM_CLK/DAT Camera 1KΩ on Jetson TX1 to 1.8V

Interface (Balls) name Target Application On-Jetson TX1 Termination

I2C_CAM_CLK/DAT Camera & Camera related functions 1KΩ on Jetson TX1 to 1.8V
DP1_AUX_CH+/- (see note) Display: HDMI/DP (DDC) None
DP0_AUX_CH+/- (see note) Display: eDP None
Note: See Display section for additional information for DP[1:0]_AUX_CH+/-
Table 21 I2C Signal Descriptions
I2C_GP[1:0]_CLK Bidirectional Serial Clock for I2C interfaces.

I2C_PM_CLK
I2C_CAM_CLK
I2C_GP[1:0]_DAT Bidirectional Serial Data for I2C interfaces.

I2C_PM_DAT
I2C_CAM_DAT
UART Controller
UART controller provides serial data synchronization and data conversion (parallel-to-serial and serial-to-parallel) for both
receiver and transmitter sections. Synchronization for serial data stream is accomplished by adding start and stop bits to the
transmit data to form a data character. Data integrity is accomplished by attaching a parity bit to the data character. The parity
bit can be checked by the receiver for any transmission bit errors.
Features:
 Synchronization for the serial data stream with start and stop bits to transmit data and form a data character
 Supports both 16450- and 16550-compatible modes. Default mode is 16450
 Device clock up to 200MHz, baud rate of 12.5Mbits/second
 Data integrity by attaching parity bit to the data character
 Support for word lengths from five to eight bits, an optional parity bit and one or two stop bits
 Support for modem control inputs
 DMA capability for both TX and RX
 8-bit x 36 deep TX FIFO
 11-bit x 36 deep RX FIFO. 3 bits of 11 bits per entry will log the RX errors in FIFO mode (break, framing and parity
errors as bits 10,9,8 of FIFO entry)
 Auto sense baud detection
 Timeout interrupts to indicate if the incoming stream stopped
 Priority interrupts mechanism
 Flow control support on RTS and CTS
 Internal loopback
 SIR encoding/decoding (3/16 or 4/16 baud pulse widths to transmit bit zero)
Table 22 UART Signal Descriptions
Function Type Description
UART[2:0]_TX Output UART Transmit

Function Type Description
UART[2:0]_RX Input UART Receive
UART[2:0]_CTS# Input UART Clear-to-send
UART[2:0]_RTS# Output UART Request-to-send
Video Input Interfaces

3.10.1 MIPI Camera Serial Interface (CSI)
Standard Notes
MIPI CSI 2.0 Receiver specification
Jetson TX1 incorporates three MIPI CSI x4 bricks supporting a variety of device types and camera configurations. The
Camera Serial Interface (CSI) is based on MIPI CSI 2.0 standard specification and implements the CSI receiver which
receives data from an external camera module with a CSI transmitter.
Features:
 Supported camera configurations:

- 1 x4: single camera with a 4 lane sensor using any one of three MIPI x4 bricks.
- 2 x4: stereo pair with 4 lanes for each camera using any pair of three MIPI x4 bricks.
- 2 x2: dual camera mode, breaking up any MIPI x4 brick to two x2 sub blocks; can support up to 6 camera
streams simultaneously.
 Supported input data formats:
- RGB: RGB888, RGB666, RGB565, RGB555, RGB444
- YUV: YUV422-8b, YUV420-8b (legacy), YUV420-8b, YUV444-8b
- RAW: RAW6, RAW7, RAW8, RAW10, RAW12, RAW14
- DPCM: user defined
- User defined: JPEG8
- Embedded: Embedded control information
 Supports single-shot mode
 D-PHY Modes of Operation
- High Speed Mode – High speed differential signaling up to 1.5Gbps; burst transmission for low power
- Low Power Control – Single-ended 1.2V CMOS level. Low speed signaling for handshaking.
- Low Power Escape –Low speed signaling for data, used for escape command entry only. 20Mbps
If the two streams come from a single source, then the streams are separated using a filter indexed on different virtual channel
numbers or data types. In case of separation using data types, the normal data type is separated from the embedded data
type. Since there are only two pixel parsers, virtual channel and embedded data capability cannot be used at the same time.
Table 23 CSI Signal Descriptions
CSI_[5:0]_CLK_N Input Differential CSI clock

CSI_[5:0]_CLK_P

CSI_[5:0]_D[1:0]_N Input Differential CSI data lanes. Each data pair can be associated with a different camera, or
CSI_[5:0]_D[1:0]_P CSI_[1:0]_D[1:0], CSI_[3:2]_D[1:0], CSI_[5:4]_D[1:0] can be used to interface with quad-
lane cameras.
3.10.2 Camera / VI (Video Input)

The Video Input (VI) is the cross bar unit for camera processing. It receives video from CSI and directs that data to either main
memory or ISP.
Table 24 Camera Clock & Control Signal Descriptions
I2C_CAM_CLK Bidirectional See I2C section
I2C_CAM_DAT Bidirectional See I2C section
CAM[1:0]_MCLK Output Video Input Master clocks for primary & secondary cameras
GPIO1_CAM1_PWR# Bidirectional Camera Power Control signals: Connect to powerdown pins on camera(s). Available
GPIO0_CAM0_PWR# for use as general purpose I/Os.
GPIO5_CAM_FLASH_EN Output Camera Flash Enable: Connect to enable of flash circuit. Available for use as
general purpose I/O.
GPIO3_CAM1_RST# Output Camera Resets: Used for camera module resets. If AutoFocus Enable is required,
GPIO2_CAM0_RST# GPIO3_CAM1_RST# to AF_EN pin on camera module & use GPIO2_CAM0_RST#
as common reset line. Available for use as general purpose I/Os.
Miscellaneous Interfaces
3.11.1 Debug
Jetson TX1 has an optional JTAG interface that can be used for SCAN testing or for communicating with either integrated
CPU.
Table 25 Debug Signal Descriptions
JTAG_RTCK Output Return Test Clock
JTAG_TCK Input Test Clock
JTAG_TDI Input Test Data In
JTAG_TDO Output Test Data Out
JTAG_TMS Input Test Mode Select
JTAG_TRST# Input Test Reset
3.11.2 Pulse Width/Frequency Modulation (PWFM)

The Pulse Width Frequency Modulator (PWFM) is a frequency divider with a varying pulse width. The PWFM runs off a device
clock programmed in the Clock and Reset controller, and can be any frequency up to the device clock maximum speed of
48MHz. The PWFM gets divided by 256 before being subdivided based on a programmable value. Two PWM signals are
available on Jetson TX1 pins. One is intended for LCD contrast and brightness control and another for fan speed control.

Table 26 PWFM Signal Descriptions
LCD0_BKLT_PWM LCD Backlight & FAN Pulse Width Frequency Modulation Signals. These output a
Output frequency divided down from the device clock source and output a pulse of programmed
FAN_PWM width.

4.0 Pin Definitions

Jetson TX1 has pins that are multi-purpose digital I/O pads (MPIO). Each MPIO can be configured to act as a GPIO or it can
be assigned for use by a particular I/O controller. Though each MPIO has up to 5 functions (GPIO function and up to 4 SFIO
functions), a given MPIO can only act as a single function at a given point in time. The functions for each pin on Jetson TX1 is
is fixed to a single SFIO function or as a GPIO. The different MPIO pins share a similar structure, but there are several
varieties of such pads. The varieties are designed to minimize the number of on-board components (such as level shifters or
pull-up resistors) required in Jetson TX1 designs.
Jetson TX1 employs the following MPIO pads:
 ST (standard) pads are the most common pads on the chip. They are used for typical General Purpose I/O.
 DD (dual-driver) pads are similar to the ST pads. A DD pad can tolerate its I/O pin being pulled up to 3.3V
(regardless of supply voltage) as long as the pad’s output-driver is set to open-drain mode. There are special power-
sequencing considerations when using this functionality.
NOTE: The output of DD pads cannot be pulled High during deep-power-down (DPD).
 CZ (controlled output impedance) pads are optimized for use in applications requiring tightly controlled output
impedance. They are similar to ST pads except for changes in the drive strength circuitry and in the weak pull-ups/-
downs. CZ pads are included on the VDDIO_SDMMC1 and VDDIO_SDDMC3 power rails. Each of those rails also
includes a pair of CZ_COMP pads. Circuitry within Jetson TX1 continually matches the output impedance of the CZ
pads to the on-board pull-up/-down resistors attached to the CZ_COMP pads.
 LV_CZ (low voltage controlled impedance) pads are similar to CZ pads but are optimized for use with a 1.2V supply
voltage (and signaling level). They support a 1.8V supply voltage (and signaling level) as a secondary mode. Jetson
TX1 uses LV_CZ pads for SPI interfaces operating at 1.8V.
 DP_AUX pad is used as an Auxiliary control channel for the Display Port which needs differential signaling. Because
the same I/O brick is used for the Display Port and HDMI to ensure the control path to the display interface is
minimized, the DP_AUX pads can operate in open-drain mode so that HDMI’s control path (i.e., DDC interface which
needs I2C) can also be used in the same pad.
Table 27 MPIO Pad Types
Pad Type
Pad Details
ST CZ DD LV_CZ ST_EMMC
IO rail voltage 1.8V 1.8V/3.3V 1.8V 1.8V 1.8V
Input Buffer Schmitt & CMOS Schmitt & CMOS Schmitt & CMOS Schmitt & CMOS Schmitt & CMOS
Push-pull & Open

Output Buffer Push-pull Push-pull Push-pull Push-pull
Drain
Open Drain: 3.3V

IO Voltage tolerance 1.8V VDDIO 1.8V 1.8V
Otherwise:VDDIO
Nominal Pull strength 100kΩ 18kΩ (PU) 100kΩ 15kΩ 15kΩ
“Slew Rate” control No 2-bits up/down No 2-bits up/down 3 bits up/down
Drive strength control 5-bits up/down 7-bits up/down 5-bits up/down 5-bits up/down 5 bits up/down
Per Pad Control
PUPD     
Tristate_control     
DPD_PARKING_CONTROL     
E_INPUT     

Pad Type
Pad Details
ST CZ DD LV_CZ ST_EMMC
E_LPDR  
E_OD  
E_IO_HV 
E_HSM 
SCHMT     
DRV_TYPE[1:0]  
Each MPIO pad consists of:
 An output driver with tristate capability, drive strength controls and push-pull mode, open-drain mode, or both
 An input receiver with either schmitt mode, CMOS mode, or both
 A weak pull-up and a weak pull-down
Power-on Reset Behavior

Each MPIO pad has a deterministic power-on reset (PoR) state. The particular reset state for each pad is chosen to minimize
the need of on-board components like pull-up resistors in a Jetson TX1-based system. For example, the on-chip weak pull-
ups are enabled during PoR for pads which are usually used to drive active-low chip selects.
The following list is a simplified description of the Jetson TX1 boot process focusing on those aspects which relate to the MPIO
pins.
1. System-level hardware executes the power-up sequence. This sequence ends when system-level hardware releases
SYS_RESET_N.
2. The boot ROM begins executing and programs the on-chip I/O controllers to access the secondary boot device.
3. The boot ROM fetches the Boot Configuration Table (BCT) and boot loader from the secondary boot device.
4. If the BCT and boot loader are fetched successfully, the boot ROM yields to the boot loader.
5. Otherwise, the boot ROM enters USB recovery mode.
Deep Sleep Behavior

Deep Sleep is an ultra-low-power standby state in which the Jetson TX1 maintains much of its I/O state while most of the chip
is powered off. The following lists offer a simplified description of the deep sleep entry and exit concentrating on those aspects
which relate to the MPIO pads. During deep sleep most of the pads are put in a state called Deep Power Down (DPD). The
sequence for entering to DPD is same across pads. Specific variations are there in some pads in terms of type of features that
are available in DPD.
NOTE: The output of DD pads cannot be pulled High during deep-power-down (DPD).
OD pads do NOT retain their output during DPD. OD pads should NOT be configured as GPIOs in a platform where they are
expected to hold a value during DPD.
ALL MPIO pads do NOT have identical behavior during deep sleep. They differ with regard to:
 Input buffer behavior during deep sleep
- Forcibly disabled OR
- Enabled for use as a “GPIO wake event” OR
- Enabled for some other purpose (e.g., a “clock request” pin)
 Output buffer behavior during deep sleep
- Maintain a static programmable (0, 1, or tristate) constant value OR

- Capable of changing state (i.e., dynamic while the chip is still in deep sleep)
 Weak pull-up/pull-down behavior during deep sleep
- Forcibly disabled OR
- Can be configured
 Pads that do not enter deep sleep
- Some of the pads whose outputs are dynamic during deep sleep are of special type and they do not enter deep sleep (e.g.,
pads that are associated with PMC logic do not enter deep sleep, pads that are associated with JTAG do not enter into deep
sleep any time.
Figure 7 DPD Wait Times
GPIO Controller
The Jetson TX1 has multiple dedicated GPIOs. Each GPIO can be individually configurable as Output/Input/Interrupt sources
with level/edge controls.

Pin Assignments
A B C D E F G H
1 VDD_IN VDD_IN VDD_IN RSVD FORCE_RECOV# AUDIO_MCLK I2S0_SDIN I2S0_LRCLK 1
2 VDD_IN VDD_IN VDD_IN RSVD SLEEP# GPIO19_AUD_RST I2S0_CLK I2S0_SDOUT 2
3 GND GND GND RSVD SPI0_CLK SPI0_CS0# GND GPIO20_AUD_INT 3
4 GND GND GND RSVD SPI0_MISO SPI0_MOSI RSVD RSVD 4
5 RSVD RSVD RSVD RSVD I2S3_SDIN I2S3_LRCLK I2S2_CLK I2S2_LRCLK 5
6 I2C_PM_CLK I2C_PM_DAT I2C_CAM_CLK I2C_CAM_DAT I2S3_CLK I2S3_SDOUT I2S2_SDIN I2S2_SDOUT 6
7 CHARGING# CARRIER_STBY# BATLOW# GPIO5_CAM_FLASH_ RSVD GPIO1_CAM1_PWR# GPIO4_CAM_STROB GPIO3_CAM1_RST# 7
EN E
8 GPIO14_AP_WAKE_ VIN_PWR_BAD# RSVD RSVD RSVD CAM1_MCLK GPIO0_CAM0_PWR# GPIO2_CAM0_RST# 8
MDM
9 GPIO15_AP2MDM_R GPIO17_MDM2AP_R RSVD UART1_TX UART1_RTS# CAM0_MCLK UART3_CTS# UART3_RX 9
EADY EADY
10 GPIO16_MDM_WAKE GPIO18_MDM_COLD RSVD UART1_RX UART1_CTS# GND UART3_RTS# UART3_TX 10
_AP BOOT
11 RSVD JTAG_TCK RSVD RSVD RSVD RSVD UART0_RTS# UART0_CTS# 11
12 JTAG_TMS JTAG_TDI RSVD RSVD RSVD RSVD UART0_RX UART0_TX 12
13 JTAG_TDO JTAG_GP0 RSVD I2S1_LRCLK SPI1_CS1# SPI1_MOSI SPI1_CLK GPIO8_ALS_PROX_I 13
NT
14 JTAG_RTCK GND I2S1_SDIN I2S1_SDOUT SPI1_CS0# SPI1_MISO GPIO9_MOTION_INT SPI2_CLK 14
15 UART2_CTS# UART2_RX I2S1_CLK I2C_GP0_DAT I2C_GP0_CLK GND SPI2_MOSI SPI2_MISO 15
16 UART2_RTS# UART2_TX FAN_PWM RSVD RSVD SPI2_CS1# SPI2_CS0# SDCARD_PWR_EN 16
17 USB0_EN_OC# FAN_TACH RSVD RSVD RSVD SDCARD_CD# GND SDCARD_D1 17
18 USB1_EN_OC# RSVD RSVD RSVD RSVD SDCARD_D3 SDCARD_CLK SDCARD_D0 18
19 RSVD GPIO11_AP_WAKE_ RSVD RSVD GND SDCARD_D2 SDCARD_CMD GND 19
BT
20 I2C_GP1_DAT GPIO10_WIFI_WAKE RSVD GND CSI5_D1- SDCARD_WP GND CSI4_D1- 20
_AP
21 I2C_GP1_CLK GPIO12_BT_EN GND CSI5_CLK- CSI5_D1+ GND CSI4_CLK- CSI4_D1+ 21
22 GPIO_EXP1_INT GPIO13_BT_WAKE_A CSI5_D0- CSI5_CLK+ GND CSI4_D0- CSI4_CLK+ GND 22
P
23 GPIO_EXP0_INT GPIO7_TOUCH_RST CSI5_D0+ GND CSI3_D1- CSI4_D0+ GND CSI2_D1- 23
24 RSVD TOUCH_CLK GND CSI3_CLK- CSI3_D1+ GND CSI2_CLK- CSI2_D1+ 24
25 LCD_TE GPIO6_TOUCH_INT CSI3_D0- CSI3_CLK+ GND CSI2_D0- CSI2_CLK+ GND 25
26 RSVD LCD_VDD_EN CSI3_D0+ GND CSI1_D1- CSI2_D0+ GND CSI0_D1- 26
27 RSVD LCD0_BKLT_PWM GND CSI1_CLK- CSI1_D1+ GND CSI0_CLK- CSI0_D1+ 27
28 GND LCD_BKLT_EN CSI1_D0- CSI1_CLK+ GND CSI0_D0- CSI0_CLK+ GND 28
29 SDIO_RST# SDIO_CMD CSI1_D0+ GND DSI3_D1+ CSI0_D0+ GND DSI2_D1+ 29
30 SDIO_D3 SDIO_CLK GND RSVD DSI3_D1- GND DSI2_CLK+ DSI2_D1- 30
31 SDIO_D2 GND DSI3_D0+ RSVD GND DSI2_D0+ DSI2_CLK- GND 31
32 SDIO_D1 SDIO_D0 DSI3_D0- GND DSI1_D1+ DSI2_D0- GND DSI0_D1+ 32
33 DP1_HPD HDMI_CEC GND RSVD DSI1_D1- GND DSI0_CLK+ DSI0_D1- 33
34 DP1_AUX_CH- DP0_AUX_CH- DSI1_D0+ RSVD GND DSI0_D0+ DSI0_CLK- GND 34
35 DP1_AUX_CH+ DP0_AUX_CH+ DSI1_D0- GND DP1_TX3- DSI0_D0- GND DP0_TX3- 35
36 USB0_OTG_ID DP0_HPD GND DP1_TX2- DP1_TX3+ GND DP0_TX2- DP0_TX3+ 36
37 GND USB0_VBUS_DET DP1_TX1- DP1_TX2+ GND DP0_TX1- DP0_TX2+ GND 37
38 USB1_D+ GND DP1_TX1+ GND DP1_TX0- DP0_TX1+ GND DP0_TX0- 38
39 USB1_D- USB0_D+ GND PEX_RFU_TX+ DP1_TX0+ GND PEX_RFU_RX+ DP0_TX0+ 39
40 GND USB0_D- PEX2_TX+ PEX_RFU_TX- GND PEX2_RX+ PEX_RFU_RX- GND 40
41 RSVD GND PEX2_TX- GND PEX1_TX+ PEX2_RX- GND PEX1_RX+ 41
42 RSVD USB2_D+ GND USB_SS1_TX+ PEX1_TX- GND USB_SS1_RX+ PEX1_RX- 42
43 GND USB2_D- USB_SS0_TX+ USB_SS1_TX- GND USB_SS0_RX+ USB_SS1_RX- GND 43
44 PEX0_REFCLK+ GND USB_SS0_TX- GND PEX0_TX+ USB_SS0_RX- GND PEX0_RX+ 44
45 PEX0_REFCLK- PEX1_REFCLK+ GND SATA_TX+ PEX0_TX- GND SATA_RX+ PEX0_RX- 45
46 RESET_OUT# PEX1_REFCLK- RSVD SATA_TX- GND GBE_LINK1000# SATA_RX- GND 46
47 RESET_IN# GND PEX1_CLKREQ# RSVD GBE_LINK_ACT# GBE_MDI1+ GND GBE_MDI3+ 47
48 CARRIER_PWR_ON RSVD PEX0_CLKREQ# PEX_WAKE# GBE_MDI0+ GBE_MDI1- GBE_MDI2+ GBE_MDI3- 48
49 CHARGER_PRSNT# RSVD PEX0_RST# RSVD GBE_MDI0- GND GBE_MDI2- GND 49
50 VDD_RTC POWER_BTN# RSVD RSVD PEX1_RST# GBE_LINK100# GND RSVD 50
A B C D E F G H

Pin Descriptions
In the following table, pins are categorized by functional block.
Table 28 MPIO Pin List

Pin Type
Pin # Jetson TX1 Pin Name Usage/Description Direction Pin Type
Code
Display
B34 DP0_AUX_CH- Display Port 0 Auxiliary Channel- Bidir AC-Coupled on Carrier Board DP_AUX
B35 DP0_AUX_CH+ Display Port 0 Auxiliary Channel+ Bidir AC-Coupled on Carrier Board DP_AUX
B36 DP0_HPD Display Port 0 Hot Plug Detect Input CMOS – 1.8V ST
H38 DP0_TX0- Display Port 0 Data Lane 0- Output AC-Coupled on Carrier Board DP
H39 DP0_TX0+ Display Port 0 Data Lane 0+ Output AC-Coupled on Carrier Board DP
F37 DP0_TX1- Display Port 0 Data Lane 1- Output AC-Coupled on Carrier Board DP
F38 DP0_TX1+ Display Port 0 Data Lane 1+ Output AC-Coupled on Carrier Board DP
G36 DP0_TX2- Display Port 0 Data Lane 2- Output AC-Coupled on Carrier Board DP
G37 DP0_TX2+ Display Port 0 Data Lane 2+ Output AC-Coupled on Carrier Board DP
H35 DP0_TX3- Display Port 0 Data Lane 3- Output AC-Coupled on Carrier Board DP
H36 DP0_TX3+ Display Port 0 Data Lane 3+ Output AC-Coupled on Carrier Board DP
A34 DP1_AUX_CH- Display Port 1 Aux- or HDMI DDC SDA Bidir AC-Coupled on Carrier Board DP_AUX
A35 DP1_AUX_CH+ Display Port 1 Aux+ or HDMI DDC SCL Bidir AC-Coupled on Carrier Board DP_AUX
A33 DP1_HPD Display Port 1 Hot Plug Detect Input CMOS – 1.8V ST
E38 DP1_TX0- DisplayPort 1 Lane 0- / HDMI Lane 2- Output AC-Coupled on Carrier Board DP
E39 DP1_TX0+ DisplayPort 1 Lane 0+ / HDMI Lane 2+ Output AC-Coupled on Carrier Board DP
C37 DP1_TX1- DisplayPort 1 Lane 1- / HDMI Lane 1- Output AC-Coupled on Carrier Board DP
C38 DP1_TX1+ DisplayPort 1 Lane 1+ / HDMI Lane 1+ Output AC-Coupled on Carrier Board DP
D36 DP1_TX2- DisplayPort 1 Lane 2- / HDMI Lane 0- Output AC-Coupled on Carrier Board DP
D37 DP1_TX2+ DisplayPort 1 Lane 2+ / HDMI Lane 0+ Output AC-Coupled on Carrier Board DP
E35 DP1_TX3- DisplayPort 1 Lane 3- / HDMI Clk Lane- Output AC-Coupled on Carrier Board DP
E36 DP1_TX3+ DisplayPort 1 Lane 3+ / HDMI Clk Lane+ Output AC-Coupled on Carrier Board DP
G34 DSI0_CLK- Display, DSI 0 Clock- Output MIPI D-PHY DPHY
G33 DSI0_CLK+ Display, DSI 0 Clock+ Output MIPI D-PHY DPHY
F35 DSI0_D0- Display, DSI 0 Data 0- Output MIPI D-PHY DPHY
F34 DSI0_D0+ Display, DSI 0 Data 0+ Output MIPI D-PHY DPHY
H33 DSI0_D1- Display, DSI 0 Data 1- Output MIPI D-PHY DPHY
H32 DSI0_D1+ Display, DSI 0 Data 1+ Output MIPI D-PHY DPHY
C35 DSI1_D0- Display, DSI 1 Data 2- Output MIPI D-PHY DPHY
C34 DSI1_D0+ Display, DSI 1 Data 2+ Output MIPI D-PHY DPHY
E33 DSI1_D1- Display, DSI 1 Data 3- Output MIPI D-PHY DPHY
E32 DSI1_D1+ Display, DSI 1 Data 3+ Output MIPI D-PHY DPHY
G31 DSI2_CLK- Display DSI 2 Clock- Output MIPI D-PHY DPHY
G30 DSI2_CLK+ Display DSI 2 Clock+ Output MIPI D-PHY DPHY
F32 DSI2_D0- Display, DSI 2 Data 0- Output MIPI D-PHY DPHY
F31 DSI2_D0+ Display, DSI 2 Data 0+ Output MIPI D-PHY DPHY
H30 DSI2_D1- Display, DSI 2 Data 1- Output MIPI D-PHY DPHY
H29 DSI2_D1+ Display, DSI 2 Data 1+ Output MIPI D-PHY DPHY
C32 DSI3_D0- Display, DSI 3 Data 2- Output MIPI D-PHY DPHY
C31 DSI3_D0+ Display, DSI 3 Data 2+ Output MIPI D-PHY DPHY
E30 DSI3_D1- Display, DSI 3 Data 3- Output MIPI D-PHY DPHY

Pin Type
Code
E29 DSI3_D1+ Display, DSI 3 Data 3+ Output MIPI D-PHY DPHY
B19 GPIO11/AP_WAKE_BT LCD Enable Output CMOS – 1.8V ST
B33 HDMI_CEC HDMI CEC Bidir Open Drain, 1.8V DD
B28 LCD_BKLT_EN Display Backlight Enable Output CMOS – 1.8V ST
A25 LCD_TE Display Tearing Effect Input CMOS – 1.8V ST
B26 LCD_VDD_EN Display Reset Output CMOS – 1.8V ST
B27 LCD0_BKLT_PWM Display Backlight PWM Output CMOS – 1.8V ST
Camera
F9 CAM0_MCLK Camera 0 Reference Clock Output CMOS – 1.8V ST
F8 CAM1_MCLK Camera 1 Reference Clock Output CMOS – 1.8V ST
G27 CSI0_CLK- Camera, CSI 0 Clock- Input MIPI D-PHY DPHY
G28 CSI0_CLK+ Camera, CSI 0 Clock+ Input MIPI D-PHY DPHY
F28 CSI0_D0- Camera, CSI 0 Data 0- Input MIPI D-PHY DPHY
F29 CSI0_D0+ Camera, CSI 0 Data 0+ Input MIPI D-PHY DPHY
H26 CSI0_D1- Camera, CSI 0 Data 1- Input MIPI D-PHY DPHY
H27 CSI0_D1+ Camera, CSI 0 Data 1+ Input MIPI D-PHY DPHY
D27 CSI1_CLK- Camera, CSI 1 Clock- Input MIPI D-PHY DPHY
D28 CSI1_CLK+ Camera, CSI 1 Clock+ Input MIPI D-PHY DPHY
C28 CSI1_D0- Camera, CSI 1 Data 0- Input MIPI D-PHY DPHY
C29 CSI1_D0+ Camera, CSI 1 Data 0+ Input MIPI D-PHY DPHY
E26 CSI1_D1- Camera, CSI 1 Data 1- Input MIPI D-PHY DPHY
E27 CSI1_D1+ Camera, CSI 1 Data 1+ Input MIPI D-PHY DPHY
G25 CSI2_CLK+ Camera, CSI 2 Clock+ Input MIPI D-PHY DPHY
F25 CSI2_D0- Camera, CSI 2 Data 0- Input MIPI D-PHY DPHY
F26 CSI2_D0+ Camera, CSI 2 Data 0+ Input MIPI D-PHY DPHY
G22 CSI4_CLK+ Camera CSI 4 Clock+ Input MIPI D-PHY DPHY
F22 CSI4_D0- Camera, CSI 4 Clock- Input MIPI D-PHY DPHY
F23 CSI4_D0+ Camera, CSI 4 Clock+ Input MIPI D-PHY DPHY
G8 GPIO0/CAM0_PWR# Camera 1 Powerdown Output CMOS – 1.8V ST

Pin Type
Code
F7 GPIO1/CAM1_PWR# Camera 1 Powerdown Output CMOS – 1.8V ST
H8 GPIO2/CAM0_RST# Camera Reset Output CMOS – 1.8V ST
H7 GPIO3/CAM1_RST# Camera Autofocus Enable Output CMOS – 1.8V ST
G7 GPIO4/CAM_STROBE Camera 1 Strobe Output CMOS – 1.8V ST
D7 GPIO5/CAM_FLASH_EN Camera Flash Enable Output CMOS – 1.8V ST
C6 I2C_CAM_CLK Camera I2C Clock Bidir Open Drain – 1.8V DD
D6 I2C_CAM_DAT Camera I2C Data Bidir Open Drain – 1.8V DD
Audio
F1 AUDIO_MCLK Audio Codec Master Clock Output CMOS – 1.8V ST
F2 GPIO19/AUD_RST Audio Codec Reset Output CMOS – 1.8V ST
H3 GPIO20/AUD_INT Audio Codec Interrupt Input CMOS – 1.8V ST
G2 I2S0_CLK Digital Audio Port 1 Clock Bidir CMOS – 1.8V CZ
H1 I2S0_LRCLK I2S Audio Port 0 Field Select Bidir CMOS – 1.8V CZ
G1 I2S0_SDIN Digital Audio Port 1 Data In Input CMOS – 1.8V CZ
H2 I2S0_SDOUT I2S Audio Port 0 Data Out Bidir CMOS – 1.8V CZ
C15 I2S1_CLK I2S Audio Port 1 Clock Bidir CMOS – 1.8V CZ
D13 I2S1_LRCLK I2S Audio Port 1 Field Select Bidir CMOS – 1.8V CZ
C14 I2S1_SDIN I2S Audio Port 1 Data In Input CMOS – 1.8V CZ
D14 I2S1_SDOUT I2S Audio Port 1 Data Out Bidir CMOS – 1.8V CZ
G5 I2S2_CLK Digital Audio Port 3 Clock Bidir CMOS – 1.8V ST
H5 I2S2_LRCLK I2S Audio Port 2 Field Select Bidir CMOS – 1.8V ST
G6 I2S2_SDIN Digital Audio Port 3 Data In Input CMOS – 1.8V ST
H6 I2S2_SDOUT I2S Audio Port 2 Data Out Bidir CMOS – 1.8V ST
E6 I2S3_CLK I2S Audio Port 3 Clock Bidir CMOS – 1.8V ST
F5 I2S3_LRCLK I2S Audio Port 3 Field Select Bidir CMOS – 1.8V ST
E5 I2S3_SDIN I2S Audio Port 3 Data In Input CMOS – 1.8V ST
F6 I2S3_SDOUT I2S Audio Port 3 Data Out Bidir CMOS – 1.8V ST
G13 SPI1_CLK SPI 1 Clock Bidir CMOS – 1.8V LV-CZ
E14 SPI1_CS0# SPI 1 Chip Select 0 Bidir CMOS – 1.8V LV-CZ
E13 SPI1_CS1# SPI 1 Chip Select 1 Bidir CMOS – 1.8V LV-CZ
F14 SPI1_MISO SPI 1 MISO Bidir CMOS – 1.8V LV-CZ
F13 SPI1_MOSI SPI 1 MOSI Bidir CMOS – 1.8V LV-CZ
WiFi/BT
B20 GPIO10/WIFI_WAKE_AP WiFi 2 Wake AP (Jetson TX1) Input CMOS – 1.8V ST
B21 GPIO12/BT_EN BT 2 Enable Output CMOS – 1.8V ST
B22 GPIO13/BT_WAKE_AP BT 2 Wake AP (Jetson TX1) Input CMOS – 1.8V ST
E50 PEX1_RST# PCIe 1 Reset Output Open Drain 3.3V, Pull-up on Jetson TX1 DD
A15 UART2_CTS# UART 2 Clear to Send Input CMOS – 1.8V ST
A16 UART2_RTS# UART 2 Request to Send Output CMOS – 1.8V ST
B15 UART2_RX UART 2 Receive Input CMOS – 1.8V ST
B16 UART2_TX UART 2 Transmit Output CMOS – 1.8V ST
B43 USB2_D- USB 2.0, Port 2 Data+ Bidir USB PHY USB
B42 USB2_D+ USB 2.0, Port 2 Data+ Bidir USB PHY USB
LAN
E47 GBE_LINK_ACT# GbE RJ45 connector Link ACT LED0 Output CMOS – 3.3V tolerant LAN_3V3
F50 GBE_LINK100# GbE RJ45 connector Link 100 LED1 Output CMOS – 3.3V Tolerant LAN_3V3
F46 GBE_LINK1000# GbE RJ45 connector Link 1000 LED2 Output CMOS – 3.3V Tolerant LAN_3V3

Pin Type
Code
E49 GBE_MDI0- GbE Transformer Data 0- Bidir MDI MDI
E48 GBE_MDI0+ GbE Transformer Data 0+ Bidir MDI MDI
F48 GBE_MDI1- GbE Transformer Data 1- Bidir MDI MDI
F47 GBE_MDI1+ GbE Transformer Data 1+ Bidir MDI MDI
G49 GBE_MDI2- GbE Transformer Data 2- Bidir MDI MDI
G48 GBE_MDI2+ GbE Transformer Data 2+ Bidir MDI MDI
H48 GBE_MDI3- GbE Transformer Data 3- Bidir MDI MDI
H47 GBE_MDI3+ GbE Transformer Data 3+ Bidir MDI MDI
Modem
A8 GPIO14/AP_WAKE_MODEM AP (Jetson TX1) Wake Modem Output CMOS – 1.8V CZ
A9 GPIO15/AP2MDM_READY AP (Jetson TX1) to Modem Ready Input CMOS – 1.8V ST
A10 GPIO16/MODEM_WAKE_AP Modem Wake AP Input CMOS – 1.8V ST
B9 GPIO17/MDM2AP_READY Modem to AP (Jetson TX1) Ready Input CMOS – 1.8V CZ
B10 GPIO18/MODEM_COLDBOOT Modem Coldboot Input CMOS – 1.8V CZ
SDIO
B30 SDIO_CLK SDIO Clock Output CMOS – 1.8V CZ
B29 SDIO_CMD SDIO Command Bidir CMOS – 1.8V CZ
B32 SDIO_D0 SDIO Data 0 Bidir CMOS – 1.8V CZ
A32 SDIO_D1 SDIO Data 1 Bidir CMOS – 1.8V CZ
A29 SDIO_RST# SDIO Reset Output CMOS – 1.8V ST
SD Card
F17 SDCARD_CD# SD Card Card Detect Input CMOS – 1.8V ST
G18 SDCARD_CLK SD Card Clock Output CMOS – 3.3/1.8V CZ
G19 SDCARD_CMD SD Card Command Bidir CMOS – 3.3/1.8V CZ
H18 SDCARD_D0 SD Card Data 0 Bidir CMOS – 3.3V/1.8V CZ
H17 SDCARD_D1 SD Card Data 1 Bidir CMOS – 3.3V/1.8V CZ
F19 SDCARD_D2 SD Card Data 2 Bidir CMOS – 3.3/1.8V CZ
F18 SDCARD_D3 SD Card Data 3 Bidir CMOS – 3.3/1.8V CZ
H16 SDCARD_PWR_EN SD Card power switch Enable Output CMOS – 1.8V ST
F20 SDCARD_WP SD Card Write Protect Input CMOS – 1.8V ST
USB 2.0
B40 USB0_D- Micro USB Data- Bidir USB PHY USB
B39 USB0_D+ Micro USB Data+ Bidir USB PHY USB
A17 USB0_EN_OC# Micro USB VBUS Enable 0 Bidir Open Drain – 3.3V DD
A18 USB1_EN_OC# USB 3.0 Type A, USB Enable 1 Bidir Open Drain – 3.3V DD
A36 USB0_OTG_ID USB0 ID / VBUS EN Input Analog USB
B37 USB0_VBUS_DET USB0 VBUS Input USB VBUS, 5V USB
A39 USB1_D- USB 2.0, Port 1 Data+ Bidir USB PHY USB
PCIe/USB 3.0/SATA
A44 PEX0_REFCLK+ PCIe Reference Clock 0+ Output PCIe PHY
A45 PEX0_REFCLK- PCIe Reference Clock 0- Output PCIe PHY
B45 PEX1_REFCLK+ PCIe Reference Clock 1+ Output PCIe PHY
B46 PEX1_REFCLK- PCIe Reference Clock 1- Output PCIe PHY
C40 PEX2_TX+ PCIe Lane 2 Transmit+ Output PCIe PHY, AC-Coupled on Carrier Board
C41 PEX2_TX- PCIe Lane 2 Transmit - Output PCIe PHY, AC-Coupled on Carrier Board

Pin Type
Code
C47 PEX1_CLKREQ# PCIE 1 Clock Request Bidir Open Drain 3.3V, Pull-up on Jetson TX1
C48 PEX0_CLKREQ# PCIE 0 Clock Request Bidir Open Drain 3.3V, Pull-up on Jetson TX1
C49 PEX0_RST# PCIe Reset 0 Output Open Drain 3.3V, Pull-up on Jetson TX1
D39 PEX_RFU_TX+ PCIe Lane RFU Transmit+ Output PCIe PHY, AC-Coupled on Carrier Board
D40 PEX_RFU_TX- PCIe Lane RFU Transmit- Output PCIe PHY, AC-Coupled on Carrier Board
D48 PEX_WAKE* PCIe Wake Input Open Drain 3.3V, Pull-up on Jetson TX1
E41 PEX1_TX+ PCIe Lane 1 Transmit+ Output PCIe PHY, AC-Coupled on Carrier Board
E42 PEX1_TX- PCIe Lane 1 Transmit - Output PCIe PHY, AC-Coupled on Carrier Board
E44 PEX0_TX+ PCIe Lane 0 Transmit+ Output PCIe PHY, AC-Coupled on Carrier Board
E45 PEX0_TX- PCIe Lane 0 Transmit- Output PCIe PHY, AC-Coupled on Carrier Board
F40 PEX2_RX+ PCIe Lane 2 Receive+ Input PCIe PHY, AC-Coupled on Carrier Board
F41 PEX2_RX- PCIe Lane 2 Receive- Input PCIe PHY, AC-Coupled on Carrier Board
G39 PEX_RFU_RX+ PCIe Lane RFU Receive+ Input PCIe PHY, AC-Coupled on Carrier Board
G40 PEX_RFU_RX- PCIe Lane RFU Receive+ Input PCIe PHY, AC-Coupled on Carrier Board
H41 PEX1_RX+ PCIe Lane 1 Receive+ Input PCIe PHY, AC-Coupled on Carrier Board
H42 PEX1_RX- PCIe Lane 1 Receive- Input PCIe PHY, AC-Coupled on Carrier Board
H44 PEX0_RX+ PCIe Lane 0 Receive+ Input PCIe PHY, AC-Coupled on Carrier Board
H45 PEX0_RX- PCIe Lane 0 Receive+ Input PCIe PHY, AC-Coupled on Carrier Board
D42 USB_SS1_TX+ USB 3.0 #1 or PCIe Lane 3 Transmit+ Output USB SS PHY, AC-Coupled on Carrier Board
D43 USB_SS1_TX- USB 3.0 #1 or PCIe Lane 3 Transmit- Output USB SS PHY, AC-Coupled on Carrier Board
G42 USB_SS1_RX+ USB 3.0 #1 or PCIe Lane 3 Receive+ Input USB SS PHY, AC-Coupled (off Jetson TX1)
G43 USB_SS1_RX- USB 3.0 #1 or PCIe Lane 3 Receive- Input USB SS PHY, AC-Coupled (off Jetson TX1)
D45 SATA_TX+ SATA Transmit+ Output SATA PHY, AC-Coupled on Carrier Board
D46 SATA_TX- SATA Transmit- Output SATA PHY, AC-Coupled on Carrier Board
G45 SATA_RX+ SATA Receive+ Input SATA PHY, AC-Coupled on Carrier Board
G46 SATA_RX- SATA Receive- Input SATA PHY, AC-Coupled on Carrier Board
C43 USB_SS0_TX+ USB 3.0 #0 Transmit+ (PCIe Lane 5) Output USB SS PHY, AC-Coupled on Carrier Board
C44 USB_SS0_TX- USB 3.0 #0 Transmit- (PCIe Lane 5) Output USB SS PHY, AC-Coupled on Carrier Board
F43 USB_SS0_RX+ USB 3.0 #0 Receive + (PCIe Lane 5) Input USB SS PHY, AC-Coupled (off Jetson TX1)
F44 USB_SS0_RX- USB 3.0 #0 Receive - (PCIe Lane 5) Input USB SS PHY, AC-Coupled (off Jetson TX1)
Touch/SPI
B25 GPIO6/TOUCH_INT Touch Interrupt Input CMOS – 1.8V ST
B23 GPIO7/TOUCH_RST Touch Reset Output CMOS – 1.8V ST
E3 SPI0_CLK SPI 0 Clock Bidir CMOS – 1.8V LV-CZ
F3 SPI0_CS0# SPI 0 Chip Select 0 Bidir CMOS – 1.8V LV-CZ
E4 SPI0_MISO SPI 0 MISO Bidir CMOS – 1.8V LV-CZ
F4 SPI0_MOSI SPI 0 MOSI Bidir CMOS – 1.8V LV-CZ
H14 SPI2_CLK SPI 2 Clock Bidir CMOS – 1.8V CZ
G16 SPI2_CS0# SPI 2 Chip Select 0 Bidir CMOS – 1.8V CZ
F16 SPI2_CS1# SPI 2 Chip Select 1 Bidir CMOS – 1.8V CZ
H15 SPI2_MISO SPI 2 MISO Bidir CMOS – 1.8V CZ
G15 SPI2_MOSI SPI 2 MOSI Bidir CMOS – 1.8V CZ
B24 TOUCH_CLK Touch Clock Output CMOS – 1.8V ST
Serial Port
E10 UART1_CTS# UART 1 Receive Input CMOS – 1.8V ST
E9 UART1_RTS# UART 1 Transmit Output CMOS – 1.8V ST
D10 UART1_RX UART 1 Receive Input CMOS – 1.8V ST

Pin Type
Code
D9 UART1_TX UART 1 Transmit Output CMOS – 1.8V ST
I2C
E15 I2C_GP0_CLK General I2C Bus #0 Clock Bidir Open Drain – 1.8V DD
D15 I2C_GP0_DAT General I2C Bus #1 Data Bidir Open Drain – 1.8V DD
A21 I2C_GP1_CLK General I2C Bus #1 Clock Bidir Open Drain – 3.3V DD
A20 I2C_GP1_DAT General I2C Bus #1 Data Bidir Open Drain – 3.3V DD
A6 I2C_PM_CLK PM I2C Bus Clock Bidir Open Drain – 1.8V DD
B6 I2C_PM_DAT PM I2C Bus Data Bidir Open Drain – 1.8V DD
Fan
C16 FAN_PWM Fan PWM Output CMOS – 1.8V ST
B17 FAN_TACH Fan Tach Input CMOS – 1.8V CZ
Sensor
H13 GPIO8/ALS_PROX_INT Proximity sensor Interrupt Input CMOS – 1.8V ST
G14 GPIO9/MOTION_INT ICM20628 Gyro/Accel Input CMOS – 1.8V ST
System
C7 BATLOW# GPIO – Low Battery Input CMOS – 1.8V ST
A48 CARRIER_PWR_ON Carrier Power On Output CMOS – 1.8V −
B7 CARRIER_STBY# SOC Power Request Output CMOS – 1.8V ST
A49 CHARGER_PRSNT# PMIC AC OK Input Open Drain, 1.8V PMIC
A7 CHARGING# Charger Interrupt Input CMOS – 1.8V ST
E1 FORCE_RECOV# Force Recovery strap pin Input CMOS – 1.8V ST
B50 POWER_BTN# Power on Input Open Drain, 1.8V ST
A47 RESET_IN# System Reset Input Input Open Drain, 1.8V JT_RST
A46 RESET_OUT# System Reset Output from PMIC Output CMOS – 1.8V PMIC
E2 SLEEP* Sleep input Input Open Drain, 1.8V ST
B8 VIN_PWR_BAD# Input Power Bad Input CMOS – VDD_IN −
C7 BATLOW# GPIO – Low Battery Input CMOS – 1.8V ST
GPIO
A23 GPIO_EXP0_INT GPIO expander 0 Interrupt Input CMOS – 1.8V CZ
A22 GPIO_EXP1_INT GPIO Expander 1 Interrupt Input CMOS – 1.8V ST
Debug
B13 JTAG_GP0 JTAG Test Reset Input CMOS – 1.8V JT_RST
A14 JTAG_RTCLK JTAG Return Clock Output CMOS – 1.8V JT_RST
B11 JTAG_TCLK JTAG Test Clock Input CMOS – 1.8V JT_RST
B12 JTAG_TDI JTAG Test Data In Input CMOS – 1.8V JT_RST
A13 JTAG_TDO JTAG Test Data Out Output CMOS – 1.8V ST
A12 JTAG_TMS JTAG Test Mode Select Input CMOS – 1.8V JT_RST
H11 UART0_CTS# UART 0 Clear to Send Input CMOS – 1.8V ST
G11 UART0_RTS# UART 1 Return to Send − CMOS – 1.8V ST
G12 UART0_RX UART 1 Receive Input CMOS – 1.8V ST
H12 UART0_TX UART 0 Transmit Output CMOS – 1.8V ST

Table 29 Power Pin List

VDD_IN Pins
Main VDD Input (5.5-19.6V) A1, A2, B1, B2, C1, C2
VDD_RTC Pins
PMIC Real Time Clock power A50
Table 30 Ground Pin List

GND Pins
Ground A3, A4, A28, A37, A40, A43, B3, B4, B14, B31, B38, B41, B44, C3, C4, C21, C24, C27, C30, C33, C36, C39, C42, C45, D20, D23,
D26, D29, D32, D35, D38, D41, D44, E19, E22, E25, E28, E31, E34, E37, E40, E43, E46, F10, F15, F21, F24, F27, F30, F33, F36,
F39, F42, F45, F49, G3, G17, G20, G23, G26, G29, G32, G35, G38, G41, G44, G47, G50, H19, H22, H25, H28, H31, H34, H37, H40,
H43, H46, H49, B47
Table 31 Reserved Pin List

Reserved Pins
Reserved A5, A11, A19, A24, A26, A27, A41, A42, B5, B18, B48, B49, C5, C8, C9, C10, C11, C12, C13, C17, C18, C19, C20, C46, C50, D1,
D2, D3, D4, D5, D8, D11, D12, D16, D17, D18, D19, D30, D31, D33, D34, D47, D49, D50, E7, E8, E11, E12, E16, E17, E18, F11,
F12, G4, G9, G10, H4, H9, H10, H50

5.0 Electrical Specification
Absolute Maximum Ratings

The absolute maximum ratings describe stress conditions. These parameters do not set minimum and maximum operating
conditions that will be tolerated over extended periods of time. If the device is exposed to these parameters for extended
periods of time, no guarantee is made and device reliability may be affected. It is not recommended to operate the Jetson TX1
module under these conditions, recommended operating conditions are provided in the following section.
WARNING: Exceeding the listed conditions may damage and/or affect long-term reliability of the part.
The Jetson TX1 module should never be subjected to conditions exceeding absolute maximum ratings.
Table 32 Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes
VDD_IN -0.5 30 V
VDDMAX
VDD_RTC -0.3 6.0 V
IDDMAX VDD_IN Imax 3 A
Voltage applied to any Pin of type DP_AUX -0.5 1.98 V
Voltage applied to any Pin of type ST V
Voltage applied to any Pin of type DP V
Voltage applied to any Pin of type DPHY V
Voltage applied to any Pin of type DD V
Voltage applied to any Pin of type CZ V
VM_PIN Voltage applied to any Pin of type LV_CZ V
Voltage applied to any Pin of type USB V
Voltage applied to any Pin of type LAN3V3 V
Voltage applied to any Pin of type MDI V
Voltage applied to any Pin of type PCIe V
Voltage applied to any Pin of type PMIC V
Voltage applied to any Pin of type JT_RST V
Electrostatic Discharge Voltage
V
Human Body Model
VESD
Electrostatis Discharge Voltage
V
Charge Device Model
TTTP Temperature Thermal transfer Plate 0 80 °C
TSTG Storage Temperature -25 +125 °C
Maximum allowable constant (static) pressure
PCONT psi
during operation
Maximum strain during system assembly or
eMAX uɛ
operation

Recommended Operating Conditions

The parameters listed in following table are specific to a temperature range and operating voltage. Operating the Jetson TX1
module beyond these parameters is not recommended. Exceeding these conditions for extended periods may adversely affect
device reliability.
Table 33 Recommended Operating Conditions
Symbol Parameter Min Max Unit Notes

VDD_IN 5.5 19.6 V
VDD_RTC 2.5 3.5 V
Voltage applied to any Pin of type DP_AUX
V
Voltage applied to any Pin of type ST

V
Voltage applied to any Pin of type DP

V
Voltage applied to any Pin of type DPHY

V
Voltage applied to any Pin of type DD

VV
Voltage applied to any Pin of type CZ

V
VDDDC
Voltage applied to any Pin of type LV_CZ
V
Voltage applied to any Pin of type USB

V
Voltage applied to any Pin of type LAN3V3

V
Voltage applied to any Pin of type MDI

V
Voltage applied to any Pin of type PCIe

V
Voltage applied to any Pin of type PMIC

V
Voltage applied to any Pin of type JT_RST

V
Ambient temperature operating temperature

Toperating °C
range

Digital Logic Characteristics

Voltages less than the minimum stated value can be interpreted as an undefined state or logic level low which may result in
unreliable operation. Voltages exceeding the maximum value can damage and/or adversely affect device reliability.
Table 34. Digital I/O Characteristics
Pad Type Symbol Parameter Min Max Unit Notes
ST VIL Input Low Voltage -0.5 0.25 x VDD

VIH Input High Voltage 0.75 x VDD 0.5 + VDD
V
VOL Output Low Voltage (IOL = 1mA) 0.15 x VDD
VOH Output High Voltage (IOH - -1mA) 0.85 x VDD
DD VIL Input Low Voltage -0.5 0.25 x VDD

VIH Input High Voltage 0.75 x VDD 3.63
V
LV_CZ VIL Input Low Voltage -0.5 0.25 x VDD

V
CZ VIL Input Low Voltage -0.5 0.25 x VDD

V

6.0 Package and Thermal Specification
Thermal Characteristics
Jetson TX1 was designed to be modular from both a functionality standpoint as well as a thermal standpoint. While it
integrates several individual components the primary Jetson TX1 thermal interface is via a single Thermal Transfer Plate
(TTP) that covers the top side. The TTP simplifies thermal design and integration with the system-level thermal solution. See
the Jetson TX1 Thermal Design Guide for complete details on the thermal evaluation and design process using Jetson TX1.
Package Drawing and Dimensions
Figure 8 Jetson TX1 Package Outline with Dimensions
SSSSAMTEC REF-186137-01
NOTES
1. All dimensions are in millimeters unless otherwise specified.
2. Tolerances are: .X ± .25, .XX ± .13, Angles ± 1°
3. Calculated Mass: 45 Grams
4. Thermal transfer Plate Finish: Clear Chemfilm per MIL-C-5541-E Class 3

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DATA SHEET [PRELIMINARY]

NVIDIA Jetson TX1 System-on-Module

NVIDIA Tegra Processors: TD580D, TD570D, CD580M, CD570M

 Advanced 3D graphics, video and image processing.

 Intelligent Video Analytics (IVA)

Downloaded from Arrow.com.

> Description Jetson TX1 System-on-Module

OpenGL ES Shader Performance (up to) GFLOPS (fp16) 1024

ARM® Cortex® -A57 MPCore (Quad-Core) Processor with

HD Video & JPEG

H.265: Main10 2160p 60fps | 1080p 240fps

WEBM VP9 2160p 60fps | 1080p 240fps

H.265 (I and P frames) 2160p 30fps | 1080p 120fps

WEBM VP8 2160p 30fps | 1080p 120fps

JPEG (Decode & Encode) 600 MP/sec

Display Controller Subsystem

eMMC and USB (recovery mode)

Downloaded from Arrow.com.

> Description Jetson TX1 System-on-Module

eMMC 5.1 Flash Storage

Bus Width 8-bit

Maximum Bus Frequency 200 MHz (HS400)

Radio type IEEE 802.11 ac 2x2

Maximum transfer rate 800 Mbps

Version level 4.0

Maximum transfer rate 24Mbps

10/100/1000 BASE-T Ethernet

Storage Temperature Range -40C – 125C

Maximum Total Module Power 6.5 – 15 W**

Downloaded from Arrow.com.

Downloaded from Arrow.com.

Downloaded from Arrow.com.

4.0 Pin Definitions 30

Downloaded from Arrow.com.

1.0 Module Overview

 NVIDIA Tegra X1 SoC

Component Manufacturer Part Number

WiFi 802.11ac Client/BT Broadcom Corp. BCM4354

Ethernet Controller 10/100/1000M Realtek Semiconductor Corp. RTL8153

PMIC Maxim Integrated MAX77620

400 pin Board-to-board connector Samtec SEAF-50-05-S-08-02-A-K

Figure 1 Jetson TX1 Block Diagram – General Application

Antenna Conn. #1 Antenna Conn. #2

Downloaded from Arrow.com.

Refer to the Tegra X1 Embedded Datasheet for details and specifications.

Figure 2 Tegra X1 SoC Block Diagram

CPU 0 CPU 1 CPU 2 CPU 3

AMBA PERIPHERIAL BUS (APB)

AHB Security Engine

MULTI-MASTER, AMBA HIGHSPEED BUS (AHB)

Serial Camera Sensors

USB 2.0 PHYs (x4)

USB3 / SATA x1 USB3 / PCIe x5 SD/SDIO/eMMC

Downloaded from Arrow.com.

Refer to the manufacturer’s documentation for details and specifications.

 10/100/1000M Ethernet controller

Refer to the manufacturer’s documentation for details and specifications.