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A New Design for Array Multiplier with Trade off in Power and Area

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IJCSI International Journal of Computer Science Issues, Vol. 8, Issue 3, No. 2, May 2011
ISSN (Online): 1694-0814
www.IJCSI.org 533

A New Design for Array Multiplier with Trade off in Power

and Area.
Nirlakalla Ravi1, Anchula Satish2, Dr.Talari Jayachandra Prasad3 and Dr.Thota Subba Rao4
1
Research Scholar(SVU), Department of Physics,
2, 3
Department of ECE,
1, 2, 3
RGMCET (Autonomous), JNT University-Anantapur, Nandyal, AP-518501, India.

4
Department of Physics, S.K.University,
Anantapur, AP-515003, India.

Abstract
In this paper a low power and low area array multiplier with carry A basic multiplier can be divided into three parts i)
save adder is proposed. The proposed adder eliminates the final partial product generation ii) partial product addition and
addition stage of the multiplier than the conventional parallel iii) final addition. In this paper we present a low power
array multiplier. The conventional and proposed multiplier both design methodology for parallel array multiplier using
are synthesized with 16-T full adder. Among Transmission Gate, Carry Save Adder (CSA). The rest of this paper is
Transmission Function Adder, 14-T, 16-T full adder shows organized as follows. Section-II presents the total power
energy efficiency. In the proposed 4x4 multiplier to add carry bits consumption in CMOS circuits with mathematical
with out using Ripple Carry Adder (RCA) in the final stage, the expression. Section-III explains the basic structure of an
carries given to the input of the next left column input. Due to array multiplier with mathematical expression. The
this the proposed multiplier shows 56 less transistor count, then methodology of the proposed multiplier with conventional
cause trade off in power and area. The proposed multiplier has array multiplier is presented in Section-IV. Results of total
shown 13.91% less power, 34.09% more speed and 59.91% less power, worse case delay and EDP with different
energy consumption for TSMC 0.18nm technology at a supply technologies is discussed in Section-V. Section-VI is the
voltage 2.0V than the conventional multiplier. conclusion of the work.
Keywords: Array Multiplier, CSA, Full Adder, Power, Delay,
Area and Energy Delay Product. 2. Power Consumption in CMOS VLSI
Circuits
1. Introduction There are three main components of power
consumption in digital CMOS VLSI circuits.
Multiplication is an essential arithmetic operation for
common Digital Signal Processing (DSP) applications, 2.1 Switching Power: consumed in charging and
such as filtering and fast Fourier transform (FFT). To discharging of the circuit capacitances during transistor
achieve high execution speed, parallel array multipliers are switching.
widely used. But these multipliers consume more power.
Power consumption has become a critical concern in 2.2 Short-Circuit Power: consumed due to short-circuit
today’s VLSI system design. Hence the designers are current flowing from power supply to ground during
needed to concentrate power efficient multipliers for the transistor switching. This power more dominates in Deep
design of low-power DSP systems. Sub Micron (DSM) technology.
In recent years, several power reduction techniques
have been proposed for low-power digital design, 2.3 Static Power: consumed due to static and leakage
including the reduction of supply voltage, multi threshold currents flowing while the circuit is in a stable state. The
logic and clock speed, the use of signed magnitude first two components are referred to as dynamic power,
arithmetic and differential data encoding, the since power is consumed dynamically while the circuit is
parallelization or pipelining of operations, and the tuning changing states. Dynamic power accounts for the majority
of input bit-patterns to reduce switching activity [1]. of the total power consumption in digital CMOS VLSI
circuits at micron technology [2], [3].
IJCSI International Journal of Computer Science Issues, Vol. 8, Issue 3, No. 2, May 2011
ISSN (Online): 1694-0814
www.IJCSI.org 534

P   iVDDVswing Cload fPi  VDD I isc  VDD I l In the given example, we have 4-bit multiplier
i and 4-bit multiplicand. By using the above equation (2) we
-------- (1) can generate 4-rows of partial products as shown in the
Where “Figure (1)”.The hardware required for the generation of
VDD – power supply voltage; these partial products is AND gates. Using any adder like
Vswing - voltage swing of the output which is ideally equal Carry Save Adder (CSA), Carry Propagate Adder (CPA)
to VDD; we can add the partial products. In this method we are
Cload – load capacitance at node i; following Carry Save Addition to add the products.
f – system clock frequency;
X3 X2 X1 X0
Pi – switching activity at node I;
Y3 Y2 Y1 Y0
Iisc - short-circuit current at node;
Il – leakage current.
X0Y3 X0Y2 X0Y1 X 0Y 0
As designing a low power CMOS 1-bit full adder, the
X1Y3 X1Y2 X1Y1 X1Y0
emphasis will be on these areas
X2Y3 X2Y2 X2Y1 X2Y0
i) to reduce the total number of transistors and the
X3Y3 X3Y2 X3Y1 X3Y0
total number of parasitic capacitances in internal nodes to
reduce the load capacitance.
P7 -P6 P5 P4 P3 P2 P1 P0
ii) to lower the switching activity to save the dynamic
power consumption.
Fig.1. Multiplier Architecture.
iii) to remove some direct paths from power supply to
ground to save the short-circuit power dissipation.
iv) to balance each path in the full adder to avoid the 4. Methodology
appearance of glitches since glitches not only cause a
unnecessary power dissipation hut may even lead to a fault In the Carry Save Addition method, the first row
circuit operation due to spurious transitions, especially in a will be either Half-Adders or Full-Adders. If the first row
low voltage operation system. of the partial products is implemented with Full-Adders,
v) in order to build a low-voltage full adder, all the Cin will be considered ‘0’. Then the carries of each Full-
nodes in the circuit must possess full voltage swing. Adder can be diagonally forwarded to the next row of the
vi) to build the low-voltage full adder design because adder. The resulting multiplier is said to be Carry Save
the power supply voltage is the crucial factor in reducing Multiplier, because the carry bits are not immediately
power dissipation. added, but rather are saved for the next stage. In the design
In Nanometer scale leakage power dominates the if the full adders have two input data the third input is
dynamic power and static power due to hot electrons. So considered as zero. In the final stage, carries and sums are
the concentration is on to trade off power in parallel merged in a fast carry-propagate (e.g. ripple carry or carry-
multipliers. look ahead) adder stage [5]. This is the conventional array
multiplier with CSA as shown in “Figure (2)”.
3.  Parallel Multiplier
In the proposed method, we implement all the
Consider the multiplication of two unsigned n-bit partial product rows of the multiplier as same as that of the
numbers, where X = xn-1, xn-2, … x0 is the multiplicand and conventional adder (explained above).The final adder
Y = yn-1,yn-2, ……,y0 is the multiplier. The product of these which is used to add carries and sums of the multiplier is
two bits can be written as [4] removed in this method. Then the carries of the multiplier
n 1 n 1 at the final stage is carefully added to the inputs of the
P X Y 2
(i  j )
----------- (2) multiplier as shown in the “Figure (3)”. The carry of the
i j
i 1 j 1 fourth column of the multiplier is given to the input of the
n 1 fifth column instead of zero. Then the carry of the fifth
X  X 2
i column is forwarded to the input of the sixth column so on.
i ----- Multiplicand In this multiplier the carry of the seventh column of the
i 1
adder is not neglected, it is considered as Most Significant
n 1

Y 2
Bit (MSB) of the multiplier. Due to elimination of four full
Y 
j
j
------ Multiplier adders in the final stage power and area can be trade off in
j 1 the proposed design than that of the conventional array
multiplier.
IJCSI International Journal of Computer Science Issues, Vol. 8, Issue 3, No. 2, May 2011
ISSN (Online): 1694-0814
www.IJCSI.org 535

Y3 0 Y2 0 Y1 0 Y0 0

F X0 F X0 F X0 F X0
0

F F F F
0 X1Y3 X1Y2 X1Y1 X1Y0

F X3Y3 F X2Y2 F X2Y1 F X2Y0

0

aF
3b2 X3Y3 F X3Y2 a3F X3Y1 F X3Y0
0

F F F F 0

P7 P6 P5 P4 P3 P2 P1 P0
Fig. 2. Conventional Array Multiplier with CSA.

Y0 0 Y0 0 Y0 0 Y0 0

F X0 F X0 F X0 F X0

F F F F
X1Y3 X1Y2 X1Y1 X1Y0

F F F F
X2Y3 X2Y2 X 2Y 1 X2Y0

F F F F
X3Y3 X3Y2 X3Y1 X3Y0

P7 P6 P5 P4 P3 P2 P1 P0
Fig .3. Proposed Array Multiplier with CSA.

5. Results and Discussions

IJCSI International Journal of Computer Science Issues, Vol. 8, Issue 3, No. 2, May 2011
ISSN (Online): 1694-0814
www.IJCSI.org 536

To show the proposed design very good

TotalPower
performance, the design is synthesized with 16-Transistor 0 2 4 6 8 10
10
0.0004
Full Adder design. Among the Transmission Gate CMOS,
Transmission Function Full Adder (TFA), 14-T adders this Conventional
8
shows good efficiency in terms of power and delay [6]. 0.0003
The results of the 16-T full adder are as shown in the Proposed

TotalPower (Watts)
“Table. (1)”. 6

0.0002

4
Table.1. Power, Delay and Energy Delay Product of the 16-T Adder.

Technology 16-T 16-T Full- EDP (JS) 0.0001

2
at (250C) Full-Total Prop-Delay
Power
0.18um 8.88E-06 5.08E-10 2.29161E-24 0.0000
0.18um 0.18um 90nm 90nm 65nm
0
65nm
90nm 1.36E-05 5.07E-10 3.49587E-24
Technology
65nm 6.15E-06 5.06E-10 1.57462E-24

Power, Propagation delays and Energy consumptions Fig. 4. Total Power Comparison.
are calculated for the conventional array and the proposed
multiplier with different technologies using H-Spice to
PropDelay
study the performance of the both multipliers shown in 0 2 4 6 8 10
10
“Table (2)”.
Conventional
8
5.1 Total Power:  The total power of these two
1.20E-009
multipliers is calculated at a simulation temperature of Proposed
PropDelay (Sec)

6
250C as shown in “Figure 4”. The proposed multiplier
has shown the power improvement than the 4
conventional for 180nm - 13.91 %, 90nm – 13.71% 6.00E-010

and 65nm – 18.59%. In the DSM technology the 2

proposed multiplier show good performance due to
less transistor count to avoid more leakage current. 0.00E+000 0
0.18um 0.18um 90nm 90nm 65nm 65nm
Technology
5.2 Propagation Delay: In the propagation delays of the
two multipliers, the proposed has shown more
efficient than the convention shown in “Figure 5”. The Fig. 5. Delay Graph.
propagation delay is calculated for all inputs and
outputs to find the worst case delay. 0 2 4 6 8
EDP
10
10
Conventional
5.3 Energy Delay Product:  The proposed multiplier
6.00E-022
shows more efficiency in Energy Delay Product is as 8

shown in “Figure 6”. It has shown for 180nm –

6
59.91%, 90nm – 9.35% and 65nm – 29.21%
EDP (J-S)

4.00E-022

improvement in the energy.

Proposed 4

5.4 Transistor count: The proposed multiplier has 56 2.00E-022

2
less transistors than that of the conventional
multiplier. These less count can trade off power
0.00E+000 0
consumption and area. 0.18um 0.18um 90nm 90nm 65nm 65nm
Technology

Fig. 6. EDP Graph.

 IJCSI International Journal of Computer Science Issues, Vol. 8, Issue 3, No. 2, May 2011
ISSN (Online): 1694-0814
www.IJCSI.org 537

Table. 2. Power, Delay and Energy Delay Product of the Conventional and Proposed Multiplier.

Technology Array Total Power Total Prop-Delay Prop- Energy EDP No.of Transistors
Multiplier type (Watts) Power (Sec) Delay Delay Percentage
Percentage Percentage Product (%)
(%) (%) (EDP) JS
Conventional 2.4628E-04 1.6490E-09 6.6968E-22 376
0.18um 13.91 34.09 59.91
Proposed 2.1200E-04 1.0867E-09 2.6841E-22 (Conventioal)
Conventional 3.8089E-04 8.3947E-10 2.5002E-22
90nm 13.71 1.12 9.35
Proposed 3.2864E-04 8.3000E-10 2.2664E-22 320
Conventional 2.0514E-04 1.1040E-09 2.8451E-22 (Proposed)
65nm 18.59 0.52 29.21
Proposed 1.6699E-04 1.0982E-09 2.0139E-22

6. Conclusion
N.Ravi holds B.Sc degree in electronics at Osmania Degree
College-Kurnool, S.K. University, Anantapur, Andhra Pradesh-
In this paper we have proposed a new design for India in 1998. He obtained Masters Degree in Physics (Solid State
low power, high performance and low area based array Physics) at S.K.University, Anantapur, AP- India in 2001. He is
multiplier with out RCA. It shows the same functionality pursuing Ph.D in VLSI Design from Sri Venkateswara University,
than the conventional adder. For higher bit multiplication it Tirupati, AP. He is presently working at Rajeev Gandhi memorial
College of Engg & Technology, Nandyal, Andhra Pradesh-India as
shows better power and area saving. For example, in the
proposed 4x4 multiplier it saves 56 MOS transistors. For
TSMC 0.18um it saves 13.91% of total power, 34.09% of An Assistant professor & Head in the department of Physics. His
more speed and 59.91% less energy consumption. To area of interest includes VLSI, Solid State Physics and
study the performance of the multiplier, it is synthesized Nanotechnology.
with different technologies. Dr.T.Jayachandra Prasad is a Principal and Professor of ECE at
Rajeev Gandhi Memorial College of Engg & Technology, Nandyal,
Andhra Padesh-India

References Dr.T.Subba Rao is a Professor in the department of Physics, Sri

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