List of Programs (As per University Syllabus)

KCS 352 Computer Organizations and Architecture Lab

1. Implementing HALF ADDER, FULL ADDER using basic logic gates

2. Implementing Binary -to -Gray, Gray -to -Binary code conversions.
3. Implementing 3-8 line DECODER.
4. Implementing 4x1 and 8x1MULTIPLEXERS.
5. Verify the excitation tables of various FLIP-FLOPS.
6. Design of an 8-bit Input/ Output system with four 8-bit Internal Registers.
7. Design of an 8-bit ARITHMETIC LOGIC UNIT.
8. Design the data path of a computer from its register transfer language description.
9. Design the control unit of a computer using either hardwiring or microprogramming
based on its register transfer language description.
10. Implement a simple instruction set computer with a control unit and a data path.
 PROGRAM: 1

1.1 OBJECTIVE: 1.2 THEORY 1.3 ALGORITHM 1.4 OUTPUT 1.5 VIVA
QUESTIONS

1.1 OBJECTIVE:

Implementing HALF ADDER, FULL ADDER using basic logic gates

1.2 THEORY

Half Adder:
Half Adder is combinational logic circuit that generates the sum of two binary numbers
(each having 1 bit length). The logic circuit has two inputs and two outputs i.e. Sum &
Carry abbreviated as SHA & CHA respectively.

First of all, we shall construct Truth Table of Half Adder

Now we write Boolean function from above Truth Table as

SHA =x′y + xy′
CHA = xy

1.3 ALGORITHM

Now we implement above Boolean expression by basic logic gates i.e.

Full Adder:
Full Adder is combination logic circuit that performs the sum of 3 input binary numbers,
(each having 1 bit length). Two of the binary input variables are x and y represent the two
significant bits to be added the third input z, represents the carry from previous lower
significant position. Outputs of Full Adder are Sum and Carry represented as
SFA and CFA respectively.

First of all, we shall construct Truth Table of Full Adder i.e.

Now we write Boolean expression for Sum and Carry of Full Adder.

Simplifying by using Boolean Postulates & theorems/k-map, we get

Simplifying by using Boolean Postulates & theorems/k-map, we get

Output:
Now we implement simplified Boolean expressions of SFA & CFA i.e.
 We shall check this logic circuit by the Truth Table of Full Adder

Viva Questions

1. Explain the basic logic gates in detail.

2. Describe the concept of combinational gates.

PROGRAM: 2

2.1 OBJECTIVE 2.2 THEORY 2.3 ALGORITHM 2.4 OUTPUT 2.5 VIVA
QUESTIONS

2.1 OBJECTIVE:

Implementing Binary -to -Gray, Gray -to -Binary code conversions

2.2 THEORY

The logical circuit which converts binary code to equivalent gray code is known as binary to
gray code converter. The gray code is a non-weighted code. The successive gray code
differs in one bit position only that means it is a unit distance code. It is also referred as
cyclic code. It is not suitable for arithmetic operations. It is the most popular of the unit
distance codes. It is also a reflective code. An n-bit Gray code can be obtained by reflecting
an n-1 bit code about an axis after 2n-1 rows, and putting the MSB of 0 above the axis and
the MSB of 1 below the axis.

2.3 PROCEDURE/ALGORITHM

Circuit implementation: Binary to gray code converter:

Truth Table

Gray to Binary Code Converter

2.4 OUTPUT
Viva Questions

1. Describe the binary to gray code convertor in detail.

2. Explain the process of gray to binary convertor.

PROGRAM: 3

3.1 OBJECTIVE 3.2 THEORY 3.3ALGORITH 3.4 OUTPUT 3.5VIVA

M QUESTIONS

3.1 OBJECTIVE:

Implementing 3-8 line DECODER using logic gates.

3.2 THEORY

DECODER: A decoder is a device which does the reverse operation of an encoder,

undoing the encoding so that the original information can be retrieved. The same method
used to encode is usually just reversed in order to decode. It is a combinational circuit
that converts binary information from n input lines to a maximum of 2n unique output lines.
In digital electronics, a decoder can take the form of a multiple- input, multiple-output logic
circuit that converts coded inputs into coded outputs, where the input and output codes are
different. e.g. n-to-2n , binary-coded decimal decoders. Enable inputs must be on for the
decoder to function, otherwise its outputs assume a single "disabled" output code word. In
case of decoding all combinations of three bits eight (23=8) decoding gates are required. This
type of decoder is called 3-8 decoder because 3 inputs and 8 outputs. For any input
combination decoder outputs are 1.

3.3 PROCEDURE/ALGORITHM

1) Connect the circuit as shown in figure.

2) Apply Vcc & ground signal to every IC.
3) Observe the input & output according to the truth table.
3.4 OUTPUT

3.5 Viva Questions

1. Describe the concept of 3-8 line Decoder.

2. Explain the logic gates in respect to 3-8 line decoders.

 PROGRAM: 4

4.1 OBJECTIVE 4.2 THEORY 4.3ALGORITH 4.4 OUTPUT 4.5VIVA

M QUESTIONS

4.1 OBJECTIVE:

Implementing 4x1 and 8x1 MULTIPLEXERS using logic gates.

4.2 4X 1 Multiplexer:
Theory
The Multiplexers or data selector is a logic circuit that selects one out of several inputs to a
single output. The input selected is controlled by a set of select lines. For selecting one output
line from n-input lines, a set of m-select lines is required. The relationship between the
number of input lines and the select lines is given by
2 m = n.

4.3 ALGORITHM
1. Connections are made as shown in the logic diagram using the pin details of the
gates.
2. Connect Vcc and GND to respective pins of each IC.
3. Connect the data, select and enable inputs to the toggle switches and outputs to the
LED‟s
4. Switch on the Trainer
5. Verify the truth table of the Multiplexer.

4.4 Output
8X 1 Multiplexer:
Theory
Take two 4:1 mux and connect their output to a 2:1 mux inputs. The result is a 8:1 mux. Now
you will be having 8 input lines, 1 output line and 3 control lines.

Algorithm
Connections are made as shown in the logic diagram using the pin details of the gates.
Output

Viva Questions

1. Explain the concept of 4x1 multiplexer using logic gates.

2. Explain the concept of 8x1 multiplexer using logic gates.

PROGRAM: 5

5.1 OBJECTIVE 5.2 THEORY 5.3ALGORITH 5.4 OUTPUT 5.5VIVA

M QUESTIONS
5.1 OBJECTIVE:

Verify the excitation of various Flip Flops

5.2 THEORY

RS FLIP-FLOP: There are two inputs to the flip-flop defined as R and S. When I/Ps R = 0 and
S = 0 then O/P remains unchanged. When I/Ps R = 0 and S = 1 the flip-flop is switches to the
stable state where O/P is 1 i.e. SET. The I/P condition
is R = 1 and S = 0 the flip-flop is switched to the stable state where O/P is 0 i.e. RESET. The I/P
condition is R = 1 and S = 1 the flip-flop is switched to the stable state where O/P is forbidden.
• JK FLIP-FLOP: For purpose of counting, the JK flip-flop is the ideal element to use. The
variable J and K are called control I/Ps because they determine what the flip- flop does when a
positive edge arrives. When J and K are both 0s, both AND gates are disabled and Q retains its
last value.
• D FLIP –FLOP: This kind of flip flop prevents the value of D from reaching the Q output until
clock pulses occur. When the clock is low, both AND gates are disabled D can change value
without affecting the value of Q. On the other hand, when the clock is high, both AND gates are
enabled. In this case, Q is forced to equal the value of D. When the clock again goes low, Q
retains or stores the last value of D. a D flip flop is a bistable circuit whose D input is transferred
to the output after a clock pulse is received.
• T FLIP-FLOP: The T or "toggle" flip-flop changes its output on each clock edge, giving an
output which is half the frequency of the signal to the T input. It is useful for constructing binary
counters, frequency dividers, and general binary addition devices. It can be made from a J-K flip-
flop by tying both of its inputs high.

5.3PROCEDURE/ALGORITHM

CIRCUIT DIAGRAM
PROCEDURE:
1. Connect the circuit as shown in fi gure.
2. Apply Vc c & ground signal to every IC.
3. Observe the input & output according to the truth table.

5.4 Output

5.5 Viva Questions

 1. Explain the various types of flip flops.
2. Define the concept of J K Flip flop using logic gates.

PROGRAM: 6

6.1 OBJECTIVE 6.2 THEORY 6.3ALGORITH 6.4 OUTPUT 6.5VIVA

M QUESTIONS

6.1 OBJECTIVE

Design of an 8-bit Input/ Output system with four 8-bit Internal Registers

6.2 THEORY

Registers are simply a group of flip flops that can be used to store a binary number. A shift
register is nothing but a register which can accept binary number and shift it. The data can be
entered in the shift register either in serial or in parallel. The output can be taken either in serial
or in parallel. Since there are two ways to shift data in to a register and two ways to shift data out
of the register four types of registers can be constructed. A register capable of shifting its binary
information either to the left or to the right is called a shift register. The logical configuration of
a shift register consists of a chain of flip flops connected in cascade with the output of one flip
flop connected to the input of the next flip flop. All the flip flops receive a common clock pulse
which causes the shift from one stage to the next.
The Q output of a D flip flop is connected to the D input of the flip flop to the left. Each clock
pulse shifts the contents of the register one bit position to the right. The serial input determines,
what goes into the right most flip flop during the shift. The serial output is taken from the output
of the left most flip flop prior to the application of a pulse. Although this register shifts its
contents to its left, if we turn the page upside down we find that the register shifts its contents to
the right. Thus a unidirectional shift register can function either as a shift right or a shift left
register.
The binary information (data) in a register can be moved within or into or out of the register
upon application of clock pulses. This type of bit movement or shifting is essential for certain
arithmetic and logic operations used in microprocessors. This gives rise to group of registers 33
Called shift registers. They are very important in applications involving the storage and transfer
of data in a digital system.
PIN DIAGRAM

6.3 PROCEDURE/ALGORITHM

1. Test all the ICs manually/ using IC tester.

2. Connect VCC and the ground.
3. Connect the appropriate pins to the input and output LEDs and switches.
4. Verify the truth table with respect to the clock.

6.4 OUTPUT

FUNCTION TABLE FOR IC 7474:

6.5 Viva Questions

1. Explain the types of registers.

2. Define the configuration of internal registers.
 PROGRAM: 7

7.1 OBJECTIVE 7.2 THEORY 7.3ALGORITH 7.4 OUTPUT 7.5VIVA

M QUESTIONS

7.1 OBJECTIVE

Design of an 8-bit ARITHMETIC LOGIC UNIT.

7.2 THEORY

Because ALUs can be built in so many ways with wide specifications and since the objective of
the class project is to learn the basic of VLSI design, the specifications of the ALU were relaxed.
The main objective of the project is to have a working ALU that performs different arithmetic
and logic functions for all possible combinations of the inputs. The speed of ALU was not an
issue and we wanted it to run at low power.

7.3 PROCEDURE/ALGORITHM

8 Bit ALU Circuit The 8-bit ALU was formed by combining three 4-bit ALU’s with 5
multiplexers as shown in Figure 2. The design of the 8-bit ALU is based on the use of a carry
select line. The four lowest bits of the input are fed into one of the 4 bit ALU’s. The carry out
line from this ALU is used to select the outputs from one of the two remaining ALUs. If carry
out is asserted then the ALU with carry in tied true is selected. If carry out is not asserted then
the ALU with carry in tied false is selected. The outputs of the selectable ALUs are multiplexed
together forming the upper and lower 4 bits, and carry out for the 8 Bit ALU

7.4 OUTPUT

Once verification was complete parasitic were extracted. To create a test for finding
the maximum operating frequency a pseudo-random input stream was applied to each
input of the ALU and observed the current during the input transition. Seeing that this
is a CMOS design the current drawn by the ALU will approach zero between states if
 operating correctly. If the switching of the transistors takes longer than the period of the
input then the ALU may give an erroneous output. The Mat lab code to create the
pseudo-random inputs is shown in Figure 4. A random input stream similar to the one
shown in Figure 5 was applied to each input of the ALU.

7.5 Viva Questions

1. Explain the functions of ALU.

2. How do ALU perform the computation task?
 PROGRAM: 8

8.1 OBJECTIVE 8.2 THEORY 8.3ALGORITH 8.4 OUTPUT 8.5VIVA

M QUESTIONS

8.1OBJECTIVE

Design the data path of a computer from its register transfer language description.

8.2 THEORY

A digital system composed of many registers, and paths must be provided to transfer information
from one register to another. The number of wires connecting all of the registers will be
excessive if separate lines are used between each register and all other registers in the system. A
bus structure, on the other hand, is more efficient for transferring information between registers
in a multi-register configuration system. A bus consists of a set of common lines, one for each bit
of register, through which binary information is transferred one at a time. Control signals
determine which register is selected by the bus during a particular register transfer.

8.3 ALGORITHM

The following block diagram shows a Bus system for four registers. It is constructed with the
help of four 4 * 1 Multiplexers each having four data inputs (0 through 3) and two selection
inputs (S1 and S2).

We have used labels to make it more convenient for you to understand the input-output
configuration of a Bus system for four registers. For instance, output 1 of register A is connected
to input 0 of MUX1.
The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers.
The selection lines choose the four bits of one register and transfer them into the four-line
common bus.

When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four
multiplexers are selected and applied to the outputs that forms the bus. This, in turn, causes the
bus lines to receive the content of register A since the outputs of this register are connected to the
0 data inputs of the multiplexers.

8.4 OUTPUT
8.5 Viva Questions
1. Explain the concept of register transfer.
2. How do registers perform the computation task?

PROGRAM: 9

9.1 OBJECTIVE 9.2 THEORY 9.3ALGORITH 9.4 OUTPUT 9.5VIVA

M QUESTIONS

9.1OBJECTIVE

Design the control unit of a computer using either hardwiring or microprogramming based on its
register transfer language description.

9.2 THEORY

Control Unit is the part of the computer’s central processing unit (CPU), which directs the
operation of the processor. It was included as part of the Von Neumann Architecture by John von
Neumann. It is the responsibility of the Control Unit to tell the computer’s memory,
arithmetic/logic unit and input and output devices how to respond to the instructions that have
been sent to the processor. It fetches internal instructions of the programs from the main memory
to the processor instruction register, and based on this register contents, the control unit generates
a control signal that supervises the execution of these instructions.

9.3 ALGORITHM

In the Hardwired control unit, the control signals that are important for instruction execution
control are generated by specially designed hardware logical circuits, in which we cannot modify
the signal generation method without physical change of the circuit structure. The operation code
of an instruction contains the basic data for control signal generation. In the instruction decoder,
the operation code is decoded. The instruction decoder constitutes a set of many decoders that
decode different fields of the instruction opcode.
9.4 OUTPUT

The control hardware can be viewed as a state machine that changes from one state
to another in every clock cycle, depending on the contents of the instruction register,
the condition codes and the external inputs. The outputs of the state machine are
the control signals.

9.5 Viva Questions

1. Explain Hardwired Control Unit
2. Explain micro programmed control unit.
PROGRAM: 10
 10.1 10.2 THEORY 10.3ALGORITH 10.4 OUTPUT 10.5VIVA
OBJECTIVE M QUESTIONS

10.1OBJECTIVE

Implement a simple instruction set computer with a control unit and a data path.

10.2 THEORY

In Figure 10.1, the typical organization of a modern von Neumann processor is illustrated. Note
that the CPU, memory subsystem, and I/O subsystem are connected by address, data, and control
buses. The fact that these are parallel buses is denoted by the slash through each line that
signifies a bus.

Figure 10.1. Schematic diagram of a modern von Neumann processor, where the CPU is
denoted by a shaded box.

It is worthwhile to further discuss the following components in Figure 10.1:

 Processor (CPU) is the active part of the computer, which does all the work of data
manipulation and decision making.
 Datapath is the hardware that performs all the required operations, for example, ALU,
registers, and internal buses.
 Control is the hardware that tells the datapath what to do, in terms of switching, operation
selection, data movement between ALU components, etc.

The processor represented by the shaded block in Figure 10.1 is organized as shown in Figure
10.2. Observe that the ALU performs I/O on data stored in the register file, while the Control
Unit sends (receives) control signals (resp. data) in conjunction with the register file.
 Figure 10.2. Schematic diagram of the processor

In MIPS, the ISA determines many aspects of the processor implementation. For example,
implementation strategies and goals affect clock rate and CPI. These implementation constraints
cause parameters of the components in Figure 10.3 to be modified throughout the design process.

Figure 10.3. Schematic diagram of MIPS architecture from an implementation perspective,

adapted from [Maf01].

Such implementation concerns are reflected in the use of logic elements and clocking strategies.
For example, with combinational elements such as adders, multiplexers, or shifters, outputs
depend only on current inputs. However, sequential elements such as memory and registers
contain state information, and their output thus depends on their inputs (data values and clock) as
well as on the stored state. The clock determines the order of events within a gate, and defines
when signals can be converted to data to be read or written to processor components (e.g.,
registers or memory). For purposes of review, the following diagram of clocking is presented:
Here, a signal that is held at logic high value is said to be asserted. In Section 1, we discussed
how edge-triggered clocking can support a precise state transition on the active clock pulse edge
(either the rising or falling edge, depending on what the designer selects). We also reviewed the
SR Latch based on nor logic, and showed how this could be converted to a clocked SR latch.
From this, a clocked D Latch and the D flip-flop were derived. In particular, the D flip-flop has a
falling-edge trigger, and its output is initially deasserted (i.e., the logic low value is present).

10.3 ALGORITHM

The datapath is the "brain" of a processor, since it implements the fetch-decode-execute cycle.
The general discipline for datapath design is to (1) determine the instruction classes and formats
in the ISA, (2) design datapath components and interconnections for each instruction class or
format, and (3) compose the datapath segments designed in Step 2) to yield a composite
datapath.

Simple datapath components include memory (stores the current instruction), PC or program

counter (stores the address of current instruction), and ALU (executes current instruction). The
interconnection of these simple components to form a basic datapath is illustrated in Figure. Note
that the register file is written to by the output of the ALU. The register file shown in Figure is
clocked by the RegWrite signal.
 Figure 10.5. Schematic high-level diagram of MIPS datapath from an implementation
perspective, adapted from [Maf01].

Implementation of the datapath for I- and J-format instructions requires two more components -
a data memory and a sign extender. The data memory stores ALU results and operands,
including instructions, and has two enabling inputs (MemWrite and MemRead) that cannot both
be active (have a logical high value) at the same time. The data memory accepts an address and
either accepts data (WriteData port if MemWrite is enabled) or outputs data (ReadData port if
MemRead is enabled), at the indicated address. The sign extender adds 16 leading digits to a 16-
bit word with most significant bit b, to product a 32-bit word. In particular, the additional 16
digits have the same value as b, thus implementing sign extension in twos complement
representation.

Schematic diagram of Data Memory and Sign Extender, adapted from [Maf01].
10.4 OUTPUT

A simple instruction set computer with a control unit and a data path is implemented.

10.5 Viva Questions

1. Explain the design of control unit.
2. Describe instruction set of computer system.