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    Flip Flops: Name - Marada Shamita Experiment No. - 9 Roll No. - 2101116 Date - 10

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    MOHIT MISHRA
    1) The document describes an experiment to verify the truth tables and timing diagrams of RS, JK, T, and D flip-flops using NAND and NOR gates. 2) A flip-flop is an electronic circuit that has two stable states and can store binary data. The stored data can be changed by applying varying inputs. 3) The experiment involves building circuits for each type of flip-flop, observing their behavior, and verifying that they operate according to their specifications. Simulations of the circuits are also presented.

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    Flip Flops: Name - Marada Shamita Experiment No. - 9 Roll No. - 2101116 Date - 10

    Uploaded by

    MOHIT MISHRA
    54 views9 pages
    1) The document describes an experiment to verify the truth tables and timing diagrams of RS, JK, T, and D flip-flops using NAND and NOR gates. 2) A flip-flop is an electronic circuit that has two stable states and can store binary data. The stored data can be changed by applying varying inputs. 3) The experiment involves building circuits for each type of flip-flop, observing their behavior, and verifying that they operate according to their specifications. Simulations of the circuits are also presented.

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    FLIP FLOPS

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    1) The document describes an experiment to verify the truth tables and timing diagrams of RS, JK, T, and D flip-flops using NAND and NOR gates. 2) A flip-flop is an electronic circuit that has two stable states and can store binary data. The stored data can be changed by applying varying inputs. 3) The experiment involves building circuits for each type of flip-flop, observing their behavior, and verifying that they operate according to their specifications. Simulations of the circuits are also presented.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    54 views9 pages

    Flip Flops: Name - Marada Shamita Experiment No. - 9 Roll No. - 2101116 Date - 10

    Uploaded by

    MOHIT MISHRA
    1) The document describes an experiment to verify the truth tables and timing diagrams of RS, JK, T, and D flip-flops using NAND and NOR gates. 2) A flip-flop is an electronic circuit that has two stable states and can store binary data. The stored data can be changed by applying varying inputs. 3) The experiment involves building circuits for each type of flip-flop, observing their behavior, and verifying that they operate according to their specifications. Simulations of the circuits are also presented.

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    You are on page 1of 9

    Name – Marada Shamita

    Experiment No. – 9
    Roll no. – 2101116
    Date – 10th March 2022

    Flip Flops

    AIM:
    To verify the truth table and timing diagram of RS, JK, T
    and D flip-flops by using NAND & NOR gates ICs and
    analyse the circuit of RS, JK, T and D flip-flops with the
    help of LEDs display.
    THEORY:
    A flip flop is an electronic circuit with two stable states
    that can be used to store binary data. The stored data can
    be changed by applying varying inputs. Flip-flops and
    latches are fundamental building blocks of digital
    electronics systems used in computers, communications,
    and many other types of systems.

    RS FLIP FLOP
    The basic NAND gate RS flip flop circuit is used to store the
    data and thus provides feedback from both of its outputs
    again back to its inputs. The RS flip flop actually has three
    inputs, SET, RESET and clock pulse.
    CIRCUIT DIAGRAM:

    TRUTH TABLE:

    INPUTS OUTPUT STATE

    CLK S R Q

    X 0 0 No change previous

    1 0 1 0 Reset

    1 1 0 1 Set

    1 1 1 - Forbidden
    SIMULATION:

    OBSERVATION:
    When clock is in don’t care condition, and set and reset is
    low, RS flip flop stores the memory, this way this flip flop
    is used.
    CONCLUSION:
    Hence, RS flip flop is verified and simulated.

    D FLIP FLOP
    A D flip flop has a single data input. This type of flip flop is
    obtained from the SR flip flop by connecting the R input
    through an inverter, and the S input is connected directly
    to data input. The modified clocked SR flip-flop is known
    as D-flip-flop and is shown below. From the truth table of
    SR flip-flop we see that the output of the SR flip-flop is in
    unpredictable state when the inputs are same and high. In
    many practical applications, these input conditions are not
    required. These input conditions can be avoided by
    making them complement of each other.
    CIRCUIT DIAGRAM:

    TRUTH TABLE:
    INPUT OUTPUT
    D RESET CLOCK Q Q’
    0 0 0 0 1
    0 0 1 0 1
    0 1 0 0 1
    0 1 1 0 1
    1 0 0 0 1
    1 0 1 1 0
    1 1 0 0 1
    1 1 1 0 1

    SIMULATION:

    OBSERVATION:
    In D flip flop there is only one input, which is
    complimented at set or reset. The outputs store memory
    as well as give as set or reset according to the clock and
    inputs respectively.
    CONCLUSION:
    Hence the D flip flop is verified and siumulated.

    J-K FLIP FLOP


    In a RS flip-flop the input R=S=1 leads to an
    indeterminate output. The RS flip-flop circuit may be re-
    joined if both inputs are 1 than also the outputs are
    complement of each other as shown in characteristics
    table below.
    CIRCUIT DIAGRAM:

    TRUTH TABLE:
    TRIGGER INPUTS OUTPUT Inference
    Present state Next State
    CLK J K Q Q’ Q Q’
    x x x - - Latched
    1 0 0 0 1 0 1 No
    1 1 0 1 0 Change

    1 0 1 0 1 0 1 Reset
    1 1 0 0 1
    1 1 0 0 1 1 0 Set
    1 1 0 1 0
    1 1 1 0 1 1 0 Toggles
    1 1 0 0 1
    SIMULATION:
    OBSERVATION:
    J K flip flop is modified to eliminate the invalid case in SR
    flip flop. It stores the memory in a case and compliments
    in other.
    CONCLUSION:
    Hence the JK flip flop is verified and simulated.

    T FLIP FLOP
    T flip-flop is known as toggle flip-flop. The T flip-flop is
    modification of the J-K flip-flop. Both the JK inputs of the
    JK flip – flop are held at logic 1 and the clock signal
    continuous to change as shown in table below.
    CIRCUIT DIAGRAM :

    TRUTH TABLE :
    T CLOCK Q Q’
    0 1 Q Q’
    1 1 Q’ Q
    X 0 Q Q’

    SIMULATION :
    OBSERVATION :
    T flip flop is single combination of J & K in JK flip flop, the
    output is as per the clock and its either the previous state
    or its compliment.

    CONCLUSION :
    Hence the T- flip flop is verified and simulated.

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