Name: SALAZAR, GERAND T .

Rating: ________________
Schedule: SAT 7:30-10:30AM Instructor: ENGR. EDWIN PURISIMA

Experiment No. 1
FLIP-FLOPS

I. OBJECTIVES:

1. To show the use of NAND gates in constructing a basic latch, a

clocked RS flip-flop, a debounceless switch.
2. To demonstrate how the JK flip-flops can be connected to produce
an RS flip-flop, a clocked RS flip-flop, and a T-type flip-flop.
3. To show the operation of D-type flip-flop.

II. MATERIALS NEEDED:

1 - logic trainer or equivalent

1 - 7400 quad two-input NAND gate DIP IC
8 - LED indicators
1 - 2KΩ resistor at 0.5 W
1 - 7476 dual JK master-slave flip-flop DIP IC
1 - 7474 dual D type flip-flop DIP IC
1 - 7475 quad D type flip-flop DIP IC
Several hook-up wires

III. PROCEDURES:

NAND gate RS Flip-Flop:

1. Construct the circuit shown in Figure 1-a. Use logic switches for inputs S
and R.
2. Set the input switches according to the input conditions in the truth table
and record the output Q and Q' states.

S R Q Q’
0 0 1 1
0 1 1 0
1 0 0 1
1 1 0/1 1/0

3. Modify the circuit shown in Figure 1-b to produce a clocked RS flip flop.
4. Set the switches S and R according to this truth table, then move the clocked
switch up and then down.

CLK S R Q Q’
1 0 0 0 1
1 0 1 0 1
1 1 0 1 0
1 1 1 1 1
5. Observe the output Q and Q' and record their states in the truth table.
6. Construct the circuit shown in Figure 13-c (S1 is directly connected to the
ground.)
7. Set S1 according to the truth table and record the condition of LED1 and
LED2 in the proper place.

SWITCH Q Q’
DOWN 0 1
UP 1 0

Fill-in Questions:

1. With RS flip-flop, having both inputs at 1 is INVALID.

2. With a clocked RS flip-flop, a clocked pulse is needed AT SAME time

together with either the S or the R input to cause the proper action.
3. The clocked RS flip-flop is a synchronous operation TRUE
4. A NAND gate bounceless switch has two outputs and when the switch is
actuated, one 3-output goes from low to HIGH and other output goes from
high to LOW.

Universal JK Flip-Flop:

1. Connect the circuit as shown in Figure 1-d; initially set the logic
switches thus, S1, S5=1; S2, S3, S4=0.
2. Move S5 (Clr) down and up. The flip-flop should now b off (Q=0,
Q'=1).

RS Flip-Flop Operation:

3. Move S1 (Ps) down and up. The flip-flop should now be on. Record the
states of the outputs; Q = _1__ Q' = _0__.
4. Move S5 (Clr) down and up. The flip-flop should be off. Record the states
of the inputs; Q = _0__ Q' = __1_.

Clocked RS Flip-Flop Operation:

5. Move S2 (J) up. Move S3 (Clk) up and down. (Notice that the flip flop
does not turn until S3 is brought down). Move S2 J down. Record the
states of the outputs; Q = _1__, Q' = _0__.
6. Move S4 up. Move S3 (Clk) up and down. (Again, notice that the flip flop
does not turn off until S3 is brought down). Move S4 (K) down. Record
the states of the outputs; Q = _0__, Q' = __1_.

T-Type Flip-Flop Operation:

7. Move S2 (J) and S4 (K) up. Move S3 clocked up and down. The flip flop
changes state when S3 went up. S3 went down. (Underline the record
answer). Record the states of the outputs; Q=_1__, Q'=_0__.
8. Move S3 (Clk) up and down. The flip-flop changes state when: S3 went
up, S3 went down (underline the correct answer). Record the states
of the outputs; Q = _0__, Q' = _1__.
9. Move S5 (Clr) down. Move S2 (J). Move S3 (Clk) up and down. Did the
flip-flop turn on? _NO__. Move S2 (J) down and S5 (Clr) up. 10. Move S1
(Ps) down. Move S4 (K) up. Move S3 (Clk) up and down. Did the flip-flop
turn off? _NO__

72
T-Type Flip-Flop with Outputs Connected to the Input:

11.Connect the circuit as shown in Figure 1-c. The outputs are cross
connected to the inputs Q to K, Q' to J, to form T-type flip-flop. The Ps pin
2 and Clr pin 3 inputs may not need to be wired since unconnected TTL
inputs float high or go to a logic 1.
12. Move S1 (Clk) up and down. Did the flip-flop changed states? _YES__
13.Repeat step 12 several times to understand better the operation of T-type
flip-flop.

Fill-in questions:

1. An RS flip-flop can be made from a JK flip-flop using only inputs _J__ and
_K__.
2. When inputs J=1, K=0, Ps=1, Clr=1, and the Clk is falling, a JK flip flop
will turn _ON__.
3. When inputs J=0, K=1, Ps=1, Clr=1, and the Clk is falling, a JK flip flop
will turn _OFF__.
4. When inputs J=1, K=1, Ps=1, Clr=1, and the Clk is falling, the JK flip-flop
acts like a _RS__ flip-flop.
5. When inputs J=1, K=0, Ps=1, Clk=0, and the Clk is falling, the output
Q=_0__ and Q'=_1__.
6. When inputs J=0, K=1, Ps=0, Clk=1, and the Clk is falling, the output
Q=_1__ and Q'=_0__.

D-Type Flip-Flip:

1. Connect the figure shown in Figure 1-f. Initially set the logic switches S1,
S2=0 and S3, S4=1.
2. Move S4 Clr down and up. The flip-flop should now be reset (Q=0,
Q'=1)TRUE.
3. Move S1 (D) up. Move S2 (Clk) up and down. The flip-flop changes states
when: S2 went up, S2 went down (underline the correct answer. Record
the states of outputs; Q=__1_, Q'=_0__.
4. Move S1 (D) down. Move S2 (D) up and down. The flip-flop changes states
when: S2 went up, S2 went down (underline the correct answer). Record
the states of the outputs Q=__0_, Q'=_1__.
5. Move S3 (Ps) down and up. Record the states of the outputs; Q=_1__,
Q'=_0__.
6. Move S4 (Clr) down and up. Record the state of the outputs; Q=_0__,
Q'=_1__.
7. Construct the circuit shown in Figure 1-g to produce a T-type flip flop. Pins
1 and 4 may not need to be connected since they will float high.
8. Move S1 (Clk) up and down several times. Notice that each time S1 goes
up the output changes states.
9. Construct the circuit shown in Figure 1-h. Select the logic switches; S1=1,
S2=0, S3=1, S4=1 and S5=0. There are four D-type flip-flops
in this package. The first one input is marked D0 and its outputs are
marked Q0 and Q'0. The other three flip-flops are identified in a similar
manner.
10. Move S5 (Clk) up and down. With a logic probe or LED indicator, test the
output s and place 0s and 1s on the figure at the respective output pins.

Fill-in Questions:

1. When D input=1, and a clock pulse appears, the outputs will be Q=_1__
and Q'=_0__.
2. When D input=0, and a clock pulse appears, the outputs will be Q=_0__
and Q'=_1__
3. A T-type flip-flop can be made from a D-type flip-flop by connecting the
_Q’__ output to the __D___ input.
4. The D-type flip-flop can function like an RS flip-flop if only inputs _D__ and
_CLK__ are used.
5. The operation of the D-type flip-flop is that the output follows the data at
the _previous state/input__ when a clock pulse appears.
IV. DIAGRAM:
V. CONCLUSION:

I conclude, that a flip-flop has two steady voltage output terminals

and two output terminals. states. When everything is working properly, if one
of the output terminals is at a high voltage, the other is at a low value. The
output terminal has a low voltage condition. The output voltages of the two
terminals can be switched back and forth (exchanged) in a flash by applying
a single input pulse to an appropriate input terminal. The new "flipped" state
of the output terminals is thus stable, meaning it continues long after the
input pulse has been removed. In addition, there are different types of flip-
flop RS, JK, T-type, and D-type of flip-flop.

VI. OBSERVATION:

The most extensively used flip-flop design, is the J-K flip-flop, is

regarded as the universal flip-flop circuit. It operates in the same way as an
S-R flip-flop with set and reset inputs. When both inputs S and R are identical
to logic 1, the S-R Latch has no restricted or invalid input states. A JK flip-flop
has four possible input combinations because to its added clocked input
circuitry: "logic 1", "logic 0", "no change", and "toggle". When both inputs are
low, no change occurs, but if both are high, the output will toggle from one
state to the other. It can carry out the functions of a set/reset flip-flop and
has the advantage of having no unclear states.

In the T-type flip-flop, when the clock signal is low, the input has no
effect on the output state. For the inputs to be active, the clock must be set
to a high value. Thus, a T flip-flop is a controlled Bi-stable latch in which the
clock signal serves as the control signal.

In the D-type flip-flop, the single input "D" is referred to as the "Data"
input. When the data input is set to 1, the flip flop is set; when it is set to 0,
the flip flop changes and resets. When the clock input is set to true, just the
condition of the D input is replicated to the output Q. And if the condition of D
input is set to logic “0” the output is complementary Q.