ST93CS46 ST93CS47: 1K (64 X 16) Serial Microwire Eeprom
ST93CS46 ST93CS47: 1K (64 X 16) Serial Microwire Eeprom
ST93CS46 ST93CS47: 1K (64 X 16) Serial Microwire Eeprom
ST93CS47
DESCRIPTION
The ST93CS46 and ST93CS47 are 1K bit Electri-
cally Erasable Programmable Memory (EEPROM)
fabricated with SGS-THOMSON’s High Endurance
Single Polysilicon CMOS technology. The memory
is accessed through a serial input D and output Q. VCC
The 1K bit memory is organized as 64 x 16 bit
words.The memory is accessed by a set of instruc-
tions which include Read, Write, Page Write, Write D
All and instructions used to set the memory protec-
tion. A Read instruction loads the address of the C Q
first word to be read into an internal address
pointer. ST93CS46
S ST93CS47
ST93CS46 ST93CS46
ST93CS47 ST93CS47
S 1 8 VCC S 1 8 VCC
C 2 7 PRE C 2 7 PRE
D 3 6 W D 3 6 W
Q 4 5 VSS Q 4 5 VSS
AI00885B AI00886C
2/16
ST93CS46, ST93CS47
AI00825
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Table 4. DC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V for ST93CS46 and
VCC = 2.5V to 5.5V for ST93CS47)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA
0V ≤ VOUT ≤ VCC,
ILO Output Leakage Current ±2.5 µA
Q in Hi-Z
ICC Supply Current (TTL Inputs) S = VIH, f = 1 MHz 3 mA
Supply Current (CMOS Inputs) S = VIH, f = 1 MHz 2 mA
ICC1 Supply Current (Standby) S = VSS, C = VSS 50 µA
Input Low Voltage (ST93CS46,47) 4.5V ≤ VCC ≤ 5.5V –0.1 0.8 V
VIL
Input Low Voltage (ST93CS46) 3V ≤ VCC ≤ 5.5V –0.1 0.2 VCC V
Input Low Voltage (ST93CS47) 2.5V ≤ VCC ≤ 5.5V –0.1 0.2 VCC V
Input High Voltage (ST93CS46,47) 4.5V ≤ VCC ≤ 5.5V 2 VCC + 1 V
VIH
Input High Voltage (ST93CS46) 3V ≤ VCC ≤ 5.5V 0.8 VCC VCC + 1 V
Input High Voltage (ST93CS47) 2.5V ≤ VCC ≤ 5.5V 0.8 VCC VCC + 1 V
IOL = 2.1mA 0.4 V
VOL Output Low Voltage
IOL = 10 µA 0.2 V
IOH = –400µA 2.4 V
VOH Output High Voltage
IOH = –10µA VCC – 0.2 V
3/16
ST93CS46, ST93CS47
Table 5. DC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V for ST93CS46 and
VCC = 2.5V to 5.5V for ST93CS47)
Symbol Alt Parameter Test Condition Min Max Unit
tPRVCH tPRES Protect Enable Valid to Clock High 50 ns
tWVCH tPES Write Enable Valid to Clock High 50 ns
tSHCH tCSS Chip Select High to Clock High 50 ns
tDVCH tDIS Input Valid to Clock High 100 ns
tCHDX tDIH Clock High to Input Transition 100 ns
tCHQL tPD0 Clock High to Output Low 500 ns
tCHQV tPD1 Clock High to Output Valid 500 ns
tCLPRX tPREH Clock Low to Protect Enable Transition 0 ns
tSLWX tPEH Chip Select Low to Write Enable Transition 250 ns
tCLSL tCSH Clock Low to Chip Select Transition 0 ns
tSLSH tCS Chip Select Low to Chip Select High Note 1 250 ns
tSHQV tSV Chip Select High to Output Valid 500 ns
tSLQZ tDF Chip Select Low to Output Hi-Z 300 ns
tCHCL tSKH Clock High to Clock Low Note 2 250 ns
tCLCH tSKL Clock Low to Clock High Note 2 250 ns
tW tWP Erase/Write Cycle time 10 ms
fC fSK Clock Frequency 0 1 MHz
Notes: 1. Chip Select must be brought low for a minimum of 250 ns (tSLSH) between consecutive instruction cycles.
2. The Clock frequency specification calls for a minimum clock period of 1 µs, therefore the sum of the timings tCHCL + tCLCH
must be greater or equal to 1 µs. For example, if tCHCL is 250 ns, then tCLCH must be at least 750 ns.
PRE
tPRVCH
tWVCH tCHCL
tSHCH tCLCH
tDVCH tCHDX
OP CODE INPUT
START
AI00887
4/16
ST93CS46, ST93CS47
tCLSL
D An A0
tCHQL tSLQZ
Hi-Z
Q Q15/Q7 Q0
AI00820C
PRE
tCLPRX
tSLWX
tCLSL
tSLSH
tDVCH tCHDX
D An A0/D0
tSHQV tSLQZ
Hi-Z
Q BUSY READY
tW
AI00888B
5/16
ST93CS46, ST93CS47
POWER-ON DATA PROTECTION edge of the clock C. The op-codes of the instruc-
tions are made up of the 2 following bits. Some
In order to prevent data corruption and inadvertent
instructions use only these first two bits, others use
write operations during power up, a Power On also the first two bits of the address field to define
Reset (POR) circuit resets all internal programming the op-code. The address field is six bits long
circuitry and sets the device in the Write Disable
(A5-A0).
mode. When VCC reaches its functional value, the
device is properlyreset (in the Write Disable mode) The ST93CS46/47 is fabricated in CMOS technol-
and is ready to decode and execute an incoming ogy and is therefore able to run from zero Hz (static
instruction. A stable VCC must be applied before input signals) up to the maximum ratings (specified
any logic signal. in Table 5).
Read
The Read instruction (READ) outputs serial data
INSTRUCTIONS on the Data Output (Q). When a READ instruction
The ST93CS46/47 has eleven instructions, as is received, the instruction and address are de-
shown in Table 6. Each instruction is preceded by coded and the data from the memory is transferred
the rising edge of the signal applied on the Chip into an output shiftregister. A dummy ’0’ bit is output
Select (S) input (assuming that the Clock C is low), first followed by the 16 bit word with the MSB first.
followed by a ’1’ read on D input during the rising
Write is executed if
the address is not
WRITE Write Data to Memory ’1’ ’0’ 01 A5-A0 D15-D0
inside the Protected
area
Write is executed if
all the addresses
PAWRITE Page Write to Memory ’1’ ’0’ 11 A5-A0 D15-D0
are not inside the
Protected area
Data Output =
Protect Register
PRREAD Protect Register Read X ’1’ 10 XXXXXX Q8-Q0
content + Protect
Flag bit
Data above
PRWRITE Protect Register Write ’1’ ’1’ 01 A5-A0 specified address
A5-A0 are protected
6/16
ST93CS46, ST93CS47
Output data changes are triggered by the Low to After the LSB of the last data word, Chip Select (S)
High transition of the Clock (C). The ST93CS46/47 must be brought Low before the next rising edge of
will automatically increment the address and will the Clock (C). The falling edge of Chip Select (S)
clock out the next word as long as the Chip Select initiates the internal, self-timed write cycle. The
input (S) is held High. In this case the dummy ’0’ bit Page Write operation will not be performed if any
is NOT output between words and a continuous of the 4 words is addressing the protected area. If
stream of data can be read. the ST93CS46/47 is still performing the program-
Write Enable and Write Disable ming cycle, the Busy signal (Q = 0) will be returned
if the Chip Select input (S) is driven high, and the
The Write Enable instruction (WEN) authorizes the ST93CS46/47 will ignore any data on the bus.
following Write instructions to be executed, the When the write cycle is completed, the Ready
Write Disable instruction (WDS) disables the exe- signal (Q = 1) will indicate (if S is driven high) that
cution of the following Erase/Write instructions. the ST93CS46/47is ready to receive a new instruc-
When power is first applied, the ST93CS46/47 tion.
enters the Disable mode. When the Write Enable
instruction (WEN) is executed, Write instructions Write All
remain enabled until a Write Disable instruction The Write All instruction (WRALL) is valid only after
(WDS) is executed or if the Power-on reset circuit the Protect Register has been cleared by executing
becomes active due to a reduced VCC. To protect a PRCLEAR (Protect Register Clear) instruction.
the memory contents from accidental corruption, it The Write All instruction simultaneously writes the
is advisable to issue the WDS instruction after whole memory with the same data word included
every write cycle. in the instruction. The Write Enable signal (W) must
The READ instruction is not affected by the WEN be held High before and during the Write instruc-
or WDS instructions. tion. Input address and data are read on the Low
to High transition of the clock. If the ST93CS46/47
Write is still performing the programming cycle, the Busy
The Write instruction (WRITE) is followed by the signal (Q = 0) will be returned if the Chip Select
address and the word to be written. The Write input (S) is driven high, and the ST93CS46/47 will
Enable signal (W) must be held high during the ignore any data on the bus. When the write cycle
WRITE instruction. Data input D is sampled on the is completed, the Ready signal (Q = 1) will indicate
Low to High transition of the clock. After the last (if S is driven high) that the ST93CS46/47 is ready
data bit has been sampled, Chip Select (S) must to receive a new instruction.
be brought Low before the next rising edge of the
clock (C), in order to start the self-timed program-
ming cycle, providing that the address is NOT in the MEMORY WRITE PROTECTION AND PROTECT
protected area. If the ST93CS46/47 is still per- REGISTER
forming the programming cycle, the Busy signal (Q The ST93CS46/47 offers a Protect Register con-
= 0) will be returned if the Chip Select input (S) is taining the bottom address of the memory area
driven high, and the ST93CS46/47 will ignore any which has to be protected against write instruc-
data on the bus. When the write cycle is completed, tions. In addition to this Protect Register, two flag
the Ready signal (Q = 1) will indicate (if S is driven bits are used to indicate the Protect Register status:
high) that the ST93CS46/47 is ready to receive a the Protect Flag enabling/disabling the protection
new instruction. of theProtect Register and the OTP bit which, when
Page Write set, disables access to the Protect Register and
thus prevents any further modifications of this Pro-
A Page Write instruction (PAWRITE) contains the tect Register value. The content of the Protect
first address to be written followed by up to 4 data Register is defined when using the PRWRITE in-
words. The Write Enable signal (W) must be held struction, it may be read when using the PRREAD
High duringthe Write instruction. Input address and instruction. A specific instruction PREN (Protect
data are read on the Low to High transition of the Register Enable) allows the user to execute the
clock. After the receipt of each data word, bits protect instructions PRCLEAR, PRWRITE and
A1-A0 of the internal address register are incre- PRDS; this PREN instruction being used together
mented, the high order bits A5-A2 remaining un- with the signals applied on the input pins PRE
changed. Users must take care by software to (Protect Register Enable pin) and W (Write En-
ensure that the last word address has the same able).
four upper order address bits as the initial address
transmitted to avoid address roll-over.
7/16
ST93CS46, ST93CS47
READ PRE
D 1 1 0 An A0
Q Qn Q0
WRITE PRE
CHECK
STATUS
D 1 0 1 An A0 Dn D0
W S
S D 1 0 0 0 0 Xn X0
D 1 0 0 1 1 Xn X0 OP
CODE
OP
CODE
AI00889D
8/16
ST93CS46, ST93CS47
PAGE PRE
WRITE
CHECK
STATUS
D 1 1 1 An A0 Dn D0
WRITE PRE
ALL
CHECK
STATUS
D 1 0 0 0 1 Xn X0 Dn D0
AI00890C
9/16
ST93CS46, ST93CS47
MEMORY WRITE PROTECTION (cont’d) tions equal to and above the specified address, are
protected from writing. The Protect Flag bit is set to
Accessing the Protect Register is done by execut- ’0’, it can be read with Protect Register Read
ing the following sequence: instruction. Both the Protect Enable (PRE) and
– WEN: execute the Write Enable instruction, Write Enable (W) input pins must be driven High
during the instruction execution.
– PREN: execute the PREN instruction,
– PRWRITE, PRCLEAR or PRDS: the protection Note: A PREN instruction must immediately pre-
then may be defined, in terms of size of the cede the PRWRITE instruction, but it is not neces-
protected area (PRWRITE, PRCLEAR) and sary to execute first a PRCLEAR.
may be set permanently (PRDS instruction). Protect Register Disable
Protect Register Read The Protect Register Disable instruction sets the
The Protect Register Read instruction (PRREAD) One Time Programmable bit (OTP bit). The Protect
outputs on the Data Output Q the content of the Register Disable instruction (PRDS) is a ONE TIME
Protect Register, followed by the Protect Flag bit. ONLY instruction which latches the Protect Regis-
The Protect Register Enable pin (PRE) must be ter content, this content is therefore unalterable in
driven High before and during the instruction. As in the future. Both the Protect Enable (PRE) and Write
the Read instruction a dummy ’0’ bit is output first. Enable (W) input pins must be driven High during
Since it is not possible to distinguish if the Protect the instruction execution. The OTP bit cannot be
Register is cleared (all 1’s) or if it is written with all directly read, it can be checked by reading the
1’s, user must check the Protect Flag status (and content of the Protect Register (PRREAD instruc-
not the Protect Register content) to ascertain the tion), then by writing this same value into the Pro-
setting of the memory protection. tect Register (PRWRITE instruction): when the
OTP bit is set, the Ready/Busy status cannot ap-
Protect Register Enable pear on the Data output (Q); when the OTP bit is
The Protect Register Enable instruction (PREN) is not set, the Busy status appear on the Data output
used to authorize the use of further PRCLEAR, (Q).
PRWRITE and PRDS instructions. The PREN
insruction does not modify the Protect Flag bit A PREN instruction must immediately precede the
value. PRDS instruction.
Note: A Write Enable (WEN) instruction must be READY/BUSY Status
executed before the Protect Enable instruction. When the ST93CS46/47 is performing the write
Both the Protect Enable (PRE) and Write Enable cycle, the Busy signal (Q = 0) is returned if S is
(W) input pins must be held High during the instruc- driven high, and the ST93CS46/47 will ignore any
tion execution. data on the bus. When the write cycle is completed,
Protect Register Clear the Ready signal (Q = 1) will indicate, if S is driven
The Protect Register Clear instruction (PRCLEAR) high, that the ST93CS46/47 is ready to receive a
clears the address stored in the Protect Register to new instruction. Once the ST93CS46/47 is Ready,
all 1’s, and thus enables the execution of WRITE the Data Output Q is set to ’1’ until a new Start bit
and WRALL instructions. The Protect Register is decoded or the Chip Select is brought Low.
Clear execution clears the Protect Flag to ’1’. Both
the Protect Enable (PRE) and Write Enable (W) COMMON I/O OPERATION
input pins must be driven High during the instruc-
tion execution. The Data Output (Q) and Data Input (D) signals can
Note: A PREN instruction must immediately pre- be connected together, through a current limiting
cede the PRCLEAR instruction. resistor, to form a common, one wire data bus.
Some precautions must be taken when operating
Protect Register Write the memory with this connection, mostly to prevent
The Protect Register Write instruction (PRWRITE) a short circuit between the last entered address bit
is used to write into the Protect Register the ad- (A0) and the first data bit output by Q. The reader
dress of the first word to be protected. After the should refer to the SGS-THOMSON application
PRWRITE instruction execution, all memory loca- note ”MICROWIRE EEPROM Common I/O Opera-
tion”.
10/16
ST93CS46, ST93CS47
Protect PRE
Register
READ
D 1 1 0 Xn X0
Q An A0 F
Protect PRE
Register
WRITE
CHECK
STATUS
D 1 0 1 An A0
Protect PRE
Register
ENABLE
D 1 0 0 1 1 Xn X0
OP
CODE AI00891D
11/16
ST93CS46, ST93CS47
Protect PRE
Register
CLEAR
CHECK
STATUS
D 1 11 111
Protect PRE
Register
DISABLE
CHECK
STATUS
D 1 00 000
AI00892C
12/16
ST93CS46, ST93CS47
Devices are shipped from the factory with the memory content set at all ”1’s” (FFFFh).
For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect
of this device, please contact the SGS-THOMSON Sales Office nearest to you.
13/16
ST93CS46, ST93CS47
mm inches
Symb
Typ Min Max Typ Min Max
A 4.80 0.189
A1 0.70 – 0.028 –
A2 3.10 3.60 0.122 0.142
B 0.38 0.58 0.015 0.023
B1 1.15 1.65 0.045 0.065
C 0.38 0.52 0.015 0.020
D 9.20 9.90 0.362 0.390
E 7.62 – – 0.300 – –
E1 6.30 7.10 0.248 0.280
e1 2.54 – – 0.100 – –
eA 8.40 – 0.331 –
eB 9.20 0.362
L 3.00 3.80 0.118 0.150
N 8 8
CP 0.10 0.004
PSDIP8
A2 A
A1 L
B e1 C
B1 eA
D eB
E1 E
1
PSDIP-a
14/16
ST93CS46, ST93CS47
mm inches
Symb
Typ Min Max Typ Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
N 8 8
CP 0.10 0.004
SO8
h x 45°
A
C
B
e CP
E H
1
A1 α L
SO-a
15/16
ST93CS46, ST93CS47
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
16/16
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