electronics

Article
Fully Integrated Low-Ripple Switched-Capacitor
DC–DC Converter with Parallel
Low-Dropout Regulator
Jeong-Yun Lee, Gwang-Sub Kim, Kwang-Il Oh and Donghyun Baek *
Microwave Embedded Circuit and System Laboratory, School of Electrical Engineering, Chung-Ang University,
Seoul 06974, Korea; lostria1985@gmail.com (J.-Y.L.); gsubkim@naver.com (G.-S.K.);
dhrhkddlf6763@hanmail.net (K.-I.O.)
* Correspondence: dhbaek@cau.ac.kr; Tel.: +82-02-820-5828




Received: 20 November 2018; Accepted: 11 January 2019; Published: 16 January 2019


Abstract: In this paper, we propose a fully integrated switched-capacitor DC–DC converter with low
ripple and fast transient response for portable low-power electronic devices. The proposed converter
reduces the output ripple by filtering the control ripple via combining a low-dropout regulator
with a main switched-capacitor DC–DC converter with a four-bit digital capacitance modulation
control. In addition, the four-phase interleaved technique applied to the main converter reduces
the switching ripple. The proposed converter provides an output voltage ranging from 1.2 to 1.5 V
from a 3.3 V supply. Its peak efficiency reaches 73% with ripple voltages below 55 mV over the
entire output power range. The transient response time for a load current variation from 100 µA to
50 mA is measured to be 800 ns. Importantly, the converter chip, which is fabricated using 0.13 µm
complementary metal–oxide–semiconductor (CMOS) technology, has a size of 2.04 mm2 . We believe
that our approach can contribute to advancements in power sources for applications such as wearable
electronics and the Internet of Things.

Keywords: DC–DC converter; switched capacitor; power management integrated circuit;

CMOS technology

1. Introduction
Rapid advances in the Internet of Things and wearable electronic devices have led to an increasing
demand for various types of sensors [1]. For portability, such devices/applications are usually powered
by small batteries, which limit the operating time of sensor-based devices. Therefore, in order to
increase the battery efficiency to provide longer operating times, power management units such
as power management integrated circuits (ICs) are used to control power consumption [2,3]. The
power management IC can be mounted on the same printed circuit board as the sensor IC, as shown
in Figure 1a. Meanwhile, certain off-chip passive components such as inductors and capacitors
are additionally required for external support of the power management IC because they cannot
be integrated into the chip. In this regard, although multichip configurations are convenient for
a sensor module design, the cost and size of the resulting modules increase. Thus, integration of
the power management unit and passive components into a single sensor chip (Figure 1b) is being
actively pursued to reduce the module size and to increase market competitiveness [4–9]. The power
management unit normally comprises a high-efficiency switching DC–DC converter and a linear
low-dropout regulator. The switching DC–DC converter adjusts the battery voltage that drops over
time to a fixed supply voltage, and its output drives the low dropout regulator to provide a voltage
with low ripple and low noise to supply-sensitive analog components on the sensors [10,11].

Electronics 2019, 8, 98; doi:10.3390/electronics8010098 www.mdpi.com/journal/electronics

Electronics 2019, 8, 98 2 of 16
Electronics 2019, 8, x FOR PEER REVIEW 2 of 15
Electronics 2019, 8, x FOR PEER REVIEW 2 of 15

management
management
Power
Power

(a) (b)
(a) (b)
Figure 1.
Figure 1. Types
Types of sensor modules:
of sensor modules: (a)
(a) Sensor
Sensor module
module with
with multichip
multichip architecture
architecture and
and (b) fully
(b) fully
Figure 1. Types of sensor modules: (a) Sensor module with multichip architecture and (b) fully
integrated
integrated sensor module (PMIC, power management IC; PMU, power management unit; and LDO,
integrated sensor
sensor module (PMIC, power
module (PMIC, power management
management IC;
IC; PMU,
PMU, power
power management
management unit;
unit; and
and LDO,
LDO,
linear low
linear low dropout regulator).
regulator).
linear low dropout
dropout regulator).

Figure 2 shows the two types types of currently

currently available switching switching DC–DC converters according to
Figure 2 shows the two types of of currently available
available switching DC–DC DC–DC converters according to
the passive components
components energy storage.
storage. The first inductor-based
the choice
choice of
of passive
passive components utilized utilized for for energy
energy storage. The first type type isis the
the inductor-based
inductor-based
converter, L push–pull as shown in Figure 2a.
converter, which employs inductor LS and a push–pull stage as shown in Figure 2a. The
which employs inductor S and a push–pull stage as shown in Figure 2a.
S The output
output
voltage is regulated by
regulated by
voltage is regulated
controlling
by controlling
controlling thethe switches
theswitches
switches(Φ (Φ andΦΦ
and
(Φ1 1and
1 Φ 2 ) with either a pulse–width modulator
) with either a pulse–width modulator
2) 2with either a pulse–width modulator or
or
a pulse–frequency
or a pulse–frequency modulator
modulator [12,13].
[12,13].The Thesecond
secondtype typeis the
the capacitor-based
capacitor-based converter,
a pulse–frequency modulator [12,13]. The second type isisthe capacitor-based converter, which
which
employs a flying
flying capacitor
capacitor C CFF and
and four
four switches
switches (Φ and Φ
(Φ11 and Φ22). The
The output
output voltage
voltage is regulated by
employs a flying capacitor CF and four switches (Φ1 and Φ2). The output voltage is regulated by
controlling the
controlling the switches with a pulse–width modulator, pulse–frequency modulator,
or digitalor digital
controlling theswitches
switches with
witha pulse–width
a pulse–width modulator,
modulator,pulse–frequency modulator,
pulse–frequency modulator, capacitor
or digital
capacitor modulator
modulator (DCpM) (DCpM)The
[14–17]. [14–17]. The converting
converting power power depends
depends on the on the capacity
storage storage capacity
of the of the
passive
capacitor modulator (DCpM) [14–17]. The converting power depends on the storage capacity of the
passive components
components as
as per the
passive components
per the
relation
as per PL = L·IPL/2=for
relation
the relation
P2L = L·I
L·I2the inductor-based
/2 for the inductor-based converter
converter C =P
2/2 for the inductor-based converter and PC =2C·V2/2 for
and Pand C·V /2 for the
C = C·V2/2 for
the capacitor-based
capacitor-based converter.
converter. Here, Here,
we we note
note that that inductor-based
inductor-based converters
converters can can deliver
deliver more more
power power
than
the capacitor-based converter. Here, we note that inductor-based converters can deliver more power
than capacitor-based
capacitor-based converters
converters via via increasing
increasing the the current
current at a at a battery
fixed fixed battery voltage,
voltage, V . V BAT. Moreover,
Moreover,
BAT VBAT. Moreover,high
than capacitor-based converters via increasing the current at a fixed battery voltage,
high power
power efficiency
efficiency can canachieved
be be achievedby by of
use usean ofoff-chip
an off-chip inductor
inductor withwith
highhigh inductance
inductance andand high
high Q
high power efficiency can be achieved by use of an off-chip inductor with high inductance and high
Q values
values while
while maintaining
maintaining a a low
low ripplevoltage.
ripple voltage.Thus,Thus,the thetraditional
traditionalinductor-based
inductor-based buck buck converter
Q values while maintaining a low ripple voltage. Thus, the traditional inductor-based buck converter
has been widely adopted for moderate- to to high-power applications.
applications.
has been widely adopted for moderate- to high-power high-power applications.

(a) (b)
(a) (b)
Figure 2. Configuration of the step-down switching DC–DC converters: (a) Inductor-based converter
Figure 2. Configuration
Figure of
of the
the step-down
step-down switching
Configuration converter. DC–DC converters:
switching DC–DC converters: (a)
(a) Inductor-based
Inductor-based converter
converter
and (b)2.capacitor-based
and (b) capacitor-based converter.
and (b) capacitor-based converter.
On the other hand, integrated inductors based on complementary metal–oxide–semiconductor
On the other hand, integrated inductors based on on complementary
complementary metal–oxide–semiconductor
metal–oxide–semiconductor
(CMOS) technology present many limitations. First, the feasible inductance LS on a chip is limited
(CMOS) technology present many limitations. First, First, the feasible inductance LSS on on a chip is limited
from a few to some tens of nanohenries due to the planar layout structure and fabrication cost. Thus,
from a few to some tens of nanohenries due to the planar layout structure and fabrication cost. Thus, Thus,
integrated inductor-based converters should increase the modulation frequency to maintain ripple
integrated inductor-based converters should increase the modulation frequency to maintain ripple
levels; however, this also increases the switching loss. Second, series resistance RS is very high, which
levels; however,
however,this
thisalso
alsoincreases thethe
increases switching loss.
switching Second,
loss. seriesseries
Second, resistance RS is very
resistance R ishigh,
verywhich
high,
leads to an increased inductor loss over the switching loss, regardless of the useS of expensive
leads to an increased inductor loss over the switching loss, regardless of the use of expensive
additional manufacturing processes involving thick metals or integrated magnetic materials. Finally,
additional manufacturing processes involving thick metals or integrated magnetic materials. Finally,
the integrated inductor exhibits power loss due to the large parasitic capacitance in relation to the
the integrated inductor exhibits power loss due to the large parasitic capacitance in relation to the
Electronics 2019, 8, 98 3 of 16

which leads to an increased inductor loss over the switching loss, regardless of the use of expensive
additional manufacturing
Electronics 2019, processes involving thick metals or integrated magnetic materials. Finally,
8, x FOR PEER REVIEW 3 of 15
the integrated inductor exhibits power loss due to the large parasitic capacitance in relation to the
substrate. In contrast, integrated capacitors afford either high parallel resistance RFF or high Q factor
the metal–insulator–metal
via the metal–insulator–metal (MIM) (MIM) structure.
structure. Therefore, when passive components are realized
technology, capacitors
with CMOS technology, capacitors afford
afford better
better energy
energy density
density per
per chip
chip area relative to inductors, as
explained in References [18–20]. Consequently, capacitor-based converters exhibit better power and
efficiencythan
cost efficiency than inductor-based
inductor-based converters
converters in low-power
in low-power applications,
applications, such assuch as sensors
sensors and Internetand
Internet
of Thingsofdevices.
Things devices.
Figure 33shows
Figure shows thethe block
block diagram
diagram of a commonly
of a commonly used switched-capacitor
used switched-capacitor (SC) DC–DC (SC)converter
DC–DC
converterone-boundary
utilizing utilizing one-boundary hysteresis
hysteresis feedback forfeedback for output
output voltage voltage
regulation andregulation
its outputand its voltage.
ripple output
ripple
The voltage.provides
controller The controller provides
switching controlswitching
signals tocontrol signals in
the converter to phase
the converter
with theininput
phase withCLK.
clock the
input
The clock CLK. The
one-boundary one-boundary
hysteresis hysteresis
configuration configuration
employs employs only
only one comparator forone comparator
the feedback for the
control to
feedback the
compare control
output to compare the output
voltage with voltagevoltage
the reference with the reference
V REF [21]. Involtage VREFstate,
the steady [21]. this
In the steady
feedback
state, this
causes feedback causes
a low-frequency a low-frequency
control control the
ripple. In addition, ripple. In addition,
SC DC–DC the SC
converter DC–DCthe
“dumps” converter
charge
“dumps”
from the charge
the input to the from
flyingthe input toand
capacitor thefrom
flying
thecapacitor
capacitorand from
to the the capacitor
output at discretetotime
the output
intervalsat
discrete time
according to theintervals accordingThis
clock frequency. to discrete
the clock frequency.
charge transferThis discrete
causes charge transfer
an unavoidable causes
switching an
ripple.
unavoidable
The switchingswitching ripple. lower
ripple is usually The switching ripple is
than the control usually
ripple lowerthe
because than the control
switching rippleisbecause
frequency higher
the switching
than the control frequency
frequency. is higher than the control frequency.

Figure 3.3.Block
Figure Blockdiagram of the
diagram of switched-capacitor (SC) DC–DC
the switched-capacitor converter
(SC) DC–DC using one-boundary
converter hysteresis
using one-boundary
feedback and its output ripple voltage.
hysteresis feedback and its output ripple voltage.

Fully integrated SC DC–DC converters require additional techniques to suppress the ripple due
Fully integrated SC DC–DC converters require additional techniques to suppress the ripple due
to the size limitations of the load and flying capacitors. Figure 4 shows three representative ripple
to the size limitations of the load and flying capacitors. Figure 4 shows three representative ripple
mitigation techniques applied to the SC DC–DC converters. The capacitance modulation technique
mitigation techniques applied to the SC DC–DC converters. The capacitance modulation technique
regulates the capacity of the flying capacitor, which transfers the charge to the load, to suppress
regulates the capacity of the flying capacitor, which transfers the charge to the load, to suppress the
the ripple. Flying capacitors are divided into several capacitors controlled by digital codes [15].
ripple. Flying capacitors are divided into several capacitors controlled by digital codes [15]. The
The capacitance modulation operates as a low-capacity flying capacitor in the light-load state and is
capacitance modulation operates as a low-capacity flying capacitor in the light-load state and is
controlled to operate as a high-capacity flying capacitor in the heavy-load state. Further, pulse–width
controlled to operate as a high-capacity flying capacitor in the heavy-load state. Further, pulse–width
modulation controls the time for which the flying capacitor is connected to the load. This method
modulation controls the time for which the flying capacitor is connected to the load. This method
reduces the ripple by regulating the amount of charge delivered to the load per clock cycle [22].
reduces the ripple by regulating the amount of charge delivered to the load per clock cycle [22].

Figure 4. Ripple mitigation techniques.

regulates the capacity of the flying capacitor, which transfers the charge to the load, to suppress the
ripple. Flying capacitors are divided into several capacitors controlled by digital codes [15]. The
capacitance modulation operates as a low-capacity flying capacitor in the light-load state and is
controlled to operate as a high-capacity flying capacitor in the heavy-load state. Further, pulse–width
modulation controls the time for which the flying capacitor is connected to the load. This method
Electronics 2019, 8, 98 4 of 16
reduces the ripple by regulating the amount of charge delivered to the load per clock cycle [22].

Figure 4.
Figure Ripplemitigation
4. Ripple mitigation techniques.
techniques.

The multiphase interleaving technique divides a converter into multiple units and drives each
unit in a different clock phase [19]. Because each converter operates in different phases, it appears
that the ripple waveform is operating at a frequency that is equal to the number of interleaved phases.
The ripple is reduced by the number of interleaved phases.
Against this backdrop, here, we propose a low-ripple fast-transient SC DC–DC converter operating
over the output current range, which integrates all the active and passive components on a single chip.
The converter employs a two-boundary hysteresis control with interleaving through a four-bit DCpM
to reduce the switching ripple and a parallel low-dropout regulator (LDR) to considerably mitigate
the ripple.

2. Principles of SC DC–DC Converters

2.1. Operation of the 2:1 Step-Down SC DC–DC Converter

The 2:1 step-down SC DC–DC converter operates in the two phases, as shown in Figure 5. The
output voltage is half the input voltage under ideal operation. Hence, maximum efficiency can only
be achieved if each phase operates at 50% duty cycle. During phase 1 (Φ1 ), the flying capacitor is
connected between the input node V BAT and output node V L , as shown in Figure 5b. In this phase, the
flying capacitor is charged up to the voltage difference between V BAT and V L . During phase 2 (Φ2 ), the
flying capacitor is connected to V L and the ground, as shown in Figure 5c. The charge acquired by the
flying capacitor during phase 1 is supplied to the output node. The repeated charging and discharging
during these phases produce output voltage ripple ∆V L , as illustrated in Figure 5d.
be achieved if each phase operates at 50% duty cycle. During phase 1 (Φ1), the flying capacitor is
connected between the input node VBAT and output node VL, as shown in Figure 5b. In this phase, the
flying capacitor is charged up to the voltage difference between VBAT and VL. During phase 2 (Φ2), the
flying capacitor is connected to VL and the ground, as shown in Figure 5c. The charge acquired by the
flying capacitor
Electronics 2019, 8, 98 during phase 1 is supplied to the output node. The repeated charging5 of and
16
discharging during these phases produce output voltage ripple ΔVL, as illustrated in Figure 5d.

(a) (b)

(c) (d)
Figure 5.
Figure 5. Operation
Operation of
of aa step-down
step-down SC
SC DC–DC
DC–DC converter.
converter. (a) Block diagram
(a) Block diagram of
of aa 2:1
2:1 step-down
step-down SCSC
DC–DC converter;
DC–DC converter; (b) operation during
(b) operation during phase
phase 1;
1; (c)
(c) operation
operation during
during phase
phase 2;
2; and
and (d)
(d) the
the output
output
voltage ripple.
voltage ripple.

Figure 6 shows a simplified model of the 2:1 step-down SC DC–DC converter. The parallel resistor
RP represents the shunt loss due to parasitic capacitances in the switches and flying capacitors. We
note here that RP is independent of the output current. The output impedance RO is connected in
series with the load resistor RL . RO changes the load voltage, and its power loss, called series loss, is
the sum of the switch conductance loss and the intrinsic SC loss. The switch conductance loss is caused
by the resistance in the on state of the switch. Increasing the size of the switch reduces the conductance
loss but increases the shunt loss via the parasitic capacitance of the switch [23]. The intrinsic SC loss is
caused by voltage ripple ∆V F due to the charge and discharge of the capacitor, as shown in Figure 5d.
The intrinsic SC loss of a 2:1 step-down SC DC–DC converter can be expressed as [24,25]

∆VF IL 2
PCF = IL · = (1)
2 4 · CF · fSW

where f SW denotes the switching frequency related to the two-phase operation. A fully-integrated
SC DC–DC converter provides a relatively large load current with a small flying capacitance due to
chip size limitations. Therefore, the intrinsic SC loss is larger than the switch conductance loss. In
this paper, assuming an ideal switch, only the intrinsic SC loss is expressed as the series loss. Upon
applying Equation (1) to this simplified model, the load current can be approximated as

(VBAT /2 − VL )
IL ≈ = 4 · CF · fSW · (VBAT /2 − VL ) (2)
RO

The SC DC–DC converters regulate the output voltage via changing the value of Ro, which is
adjusted through either frequency or pulse–width modulation of the switching clock.
 (VBAT / 2 − VL )
IL ≈ = 4 ⋅ CF ⋅ fSW ⋅ (VBAT / 2 − VL ) (2)
RO
The SC DC–DC converters regulate the output voltage via changing the value of Ro, which is
Electronics 2019, 8, 98 6 of 16
adjusted through either frequency or pulse–width modulation of the switching clock.

Simplified model of a 2:1 step-down switched-capacitor (SC) DC–DC converter.

Figure 6. Simplified converter.

2.2. Multiphase Interleaved

2.2. Multiphase Interleaved SCSC DC–DC
DC–DC Converter
Converter for
for Low
Low Switching
Switching Ripple
Ripple
As
As the
the SCSC DC–DC
DC–DC converter
converter performs
performs repeated
repeated charging
charging and
and discharging,
discharging, the the output
output voltage
voltage
exhibits
exhibits an inherent switching ripple. Multiphase interleaving aims to mitigate thisvia
an inherent switching ripple. Multiphase interleaving aims to mitigate this ripple dividing
ripple via
the converter into multiple units and driving each unit with different clock phases.
dividing the converter into multiple units and driving each unit with different clock phases. Figure 7 Figure 7 illustrates
aillustrates
four-phase a interleaved
four-phase converter, with
interleaved each unit
converter, utilizing
with each a quarter
unit of thea total
utilizing capacitance
quarter of the totaland
operating at a 45 ◦ phase shift relative to the clocks of the neighboring nodes. The flying capacitances
capacitance and operating at a 45° phase shift relative to the clocks of the neighboring nodes. The
of all units
flying are equal,
capacitances of and hence,
all units arethe output
equal, andcharge
hence,perthe cycle
outputis charge
also identical.
per cycle The output
is also current
identical. of
The
each
output unit is the of
current same
eachasunit
thatisofthe
thesame
converter
as thatwithout interleaving.
of the converter Thus,
without the charge Thus,
interleaving. flowingthethrough
charge
each
flowing through each unit of the flying capacitor in multiphase interleaving is the same as that of
unit of the flying capacitor in multiphase interleaving is the same as that in the case in the
the
Electronics
original 2019, 8,
converter.x FOR PEER REVIEW 6 of 15
case of the original converter.

Figure 7.
Figure Block diagram
7. Block diagram of
of ss four-phase
four-phase interleaved
interleaved SC
SC DC–DC
DC–DC converter.
converter.

Figure 8 shows the operation of a four-phase interleaved SC DC–DC converter including the
Figure 8 shows the operation of a four-phase interleaved SC DC–DC converter including the
output voltage ripple with and without phase interleaving. In Figure 8a, each SC DC–DC converter
output voltage ripple with and without phase interleaving. In Figure 8a, each SC DC–DC converter
without phase interleaving operates at the same clock phase (Φ and Φ2 ), producing output ripple ∆V L .
without phase interleaving operates at the same clock phase1 (Φ1 and Φ2), producing output ripple
In Figure 8b, each converter of the interleaving configuration operates with 45◦ phase-shifted clocks
ΔVL. In Figure 8b, each converter of the interleaving configuration operates with 45° phase-shifted
(ΦA_1 , ΦB_1 , ΦC_1 , and ΦD_1 ). Therefore, the effective switching frequency f ripple in the converter
clocks (ΦA_1, ΦB_1, ΦC_1, and ΦD_1). Therefore, the effective switching frequency fripple in the converter
increases by a factor of four relative to the case with no interleaving, thereby reducing the output
increases by a factor of four relative to the case with no interleaving, thereby reducing the output
ripple to 25% of the original ∆V L . Multiphase interleaving reduces the voltage ripple by increasing the
ripple to 25% of the original ΔV L. Multiphase interleaving reduces the voltage ripple by increasing

the effective switching frequency but maintains switching losses. To mitigate the output voltage
ripple, a load capacitor is generally used. Multiphase interleaving also decreases this load capacitor
value by a factor of four due to the increased ripple frequency.
 Figure 8 shows the operation of a four-phase interleaved SC DC–DC converter including the
output voltage ripple with and without phase interleaving. In Figure 8a, each SC DC–DC converter
without phase interleaving operates at the same clock phase (Φ1 and Φ2), producing output ripple
ΔVL. In Figure 8b, each converter of the interleaving configuration operates with 45° phase-shifted
clocks (Φ2019,
Electronics A_1, 8,
Φ98B_1, ΦC_1, and ΦD_1). Therefore, the effective switching frequency fripple in the converter
7 of 16
increases by a factor of four relative to the case with no interleaving, thereby reducing the output
ripple to 25% of the original ΔVL. Multiphase interleaving reduces the voltage ripple by increasing
effective switching frequency but maintains switching losses. To mitigate the output voltage ripple, a
the effective switching frequency but maintains switching losses. To mitigate the output voltage
load capacitor is generally used. Multiphase interleaving also decreases this load capacitor value by a
ripple, a load capacitor is generally used. Multiphase interleaving also decreases this load capacitor
factor of four due to the increased ripple frequency.
value by a factor of four due to the increased ripple frequency.

(a) (b)
Figure 8.
Figure 8. Operation
Operationof of
an an
interleaved switched-capacitor
interleaved (SC) (SC)
switched-capacitor DC–DC converter:
DC–DC (a) Without
converter: interleaving
(a) Without
and (b) uponand
interleaving applying interleaving.
(b) upon applying interleaving.

2.3. Output Voltage Regulation

The
The output
output voltage
voltage of the SC DC–DC converter can be modulated by the three methods depicted
in
in Figure
Figure9.9.First, frequency
First, modulation
frequency enables
modulation the adjustment
enables of the operating
the adjustment frequencyfrequency
of the operating of switching
of
according to the load impedance, with the duty cycle usually set to 50%. This method
switching according to the load impedance, with the duty cycle usually set to 50%. This method changes the
output
changesimpedance
the outputofimpedance
the converter by varying
of the theby
converter charge transferred
varying from
the charge the flying capacitor
transferred to the
from the flying
load. However, it requires an additional voltage-controlled oscillator for frequency modulation. Second,
time modulation enables the adjustment of the pulse width of the switching signal, which allows for
control of the output current for the flying capacitors to charge or discharge. This method modulates
the output current by varying the connection time to the output node. However, efficiency is low due
to switching losses under light loads, given the low output current of the converter; nevertheless, the
switching loss is maintained constant under this condition. Third, capacitance modulation of the charge
transfer can be achieved by dividing the SC DC–DC converter into multiple converter cells in parallel
and utilizing some cells to provide the required current to the load, thereby establishing “digital”
operation. In this method, only the flying capacitors and switches of the converter cells involved in the
output current circuit operate, thus improving the efficiency with respect to switching loss. However,
the main limitation of this method is the required division of the SC DC–DC converter into cells for
accurate output current control. This division increases the complexity of both the chip layout and the
state machine to select the appropriate number of cells, thus imposing a tradeoff between efficiency
and complexity.
load, thereby establishing “digital” operation. In this method, only the flying capacitors and switches
of the converter cells involved in the output current circuit operate, thus improving the efficiency
with respect to switching loss. However, the main limitation of this method is the required division
of the SC DC–DC converter into cells for accurate output current control. This division increases the
complexity of8,both
Electronics 2019, 98 the chip layout and the state machine to select the appropriate number of cells,
8 of 16
thus imposing a tradeoff between efficiency and complexity.

light load heavy load light load heavy load light load heavy load

Φ1 Φ1 Φ1

Φ2 Φ2 Φ2

CF CF CF
F↓ F↑ D↓ D↑ C↓ C↑

frequency control duty control capacitance control

(a) (b) (c)
Figure
Figure 9.
9. Methods
Methods for
for output
output voltage
voltage regulation:
regulation: (a)
(a) Pulse–frequency
Pulse–frequency modulation;
modulation; (b)
(b) pulse–width
pulse–width
modulation; and (c) capacitance modulation.
modulation; and (c) capacitance modulation.

2.4. DCpM
2.4. DCpMControl
Control
The DCpM
The DCpM approach
approachallows
allowscontrol
controlof of
thetheamount
amountof flying capacitance
of flying associated
capacitance with the
associated charge
with the
transfertransfer
charge in the converter, therebythereby
in the converter, enabling load current
enabling regulation
load current given that
regulation giventhethat
amount of charge
the amount of
transferred in one clock cycle is proportional to this capacitance. With this
charge transferred in one clock cycle is proportional to this capacitance. With this method, the total method, the total switch
size involved
switch in the output
size involved currentcurrent
in the output of the SC of DC–DC converter
the SC DC–DC can be adjusted
converter according
can be adjusted to the size
according to
of the flying capacitance. Thus, the shunt loss originating from parasitic capacitances
the size of the flying capacitance. Thus, the shunt loss originating from parasitic capacitances of the of the flying
capacitors
flying and switches
capacitors and the
and switches andconduction
the conduction loss due
loss to
duethetoswitch resistance
the switch are reduced
resistance are reduced whenwhenthe
loadload
the current is low,
current thereby
is low, maintaining
thereby maintaining highhighefficiency under
efficiency lightlight
under load.load.
In the
In the implementation
implementation of of the
the SCSC DC–DC
DC–DC converter
converter with
with DCpM
DCpM control,
control, the
the flying
flying capacitor
capacitor is is
divided into
divided into aa binary-weight
binary-weight bank.
bank. Figure
Figure 10 10 shows
shows thethe structure
structure of of the
the SC
SC DC–DC
DC–DC converter
converter withwith aa
four-bit DCpM
four-bit DCpM control.
control. The
Theflying
flyingcapacitance
capacitanceisisdivided
dividedintointofour
fourdifferent
differentbanks
banksof ofsize
sizex1,x1,x2,
x2,x4,
x4,
and
and x8. These
These four converter cells form a single matrix, and the charge transfer operation
converter cells form a single matrix, and the charge transfer operation is enabled is enabled by
control
by controlcode C[3:0].
code Figure
C[3:0]. 11 shows
Figure 11 showsa model of theofproposed
a model the proposedSC DC–DCSC DC–DCconverter based on
converter a four-bit
based on a
DCpM. The 2:1 transformer represents the required voltage step-down
four-bit DCpM. The 2:1 transformer represents the required voltage step-down process. The output process. The output impedance
RO and the Rshunt
impedance O andimpedance RP are binary-weighted
the shunt impedance according toaccording
RP are binary-weighted the DCpM to control
the DCpM signal. The
control
outputThe
signal. impedance is determined
output impedance as 1/(4·CF ·f SW
is determined as),1/(4·C
where f SW
F·fSW and CFfSW
), where denote
and C the switching
F denote frequency
the switching
and the unit
frequency andflying capacitance,
the unit respectively.respectively.
flying capacitance, The load current
The loadIL ofcurrent
the converter
IL of thecan be expressed
converter can be as
expressed as
X 3
IL = 4 · (0.5 · VBAT − VL ) · fSW · 3 C[n] · 2nn · CF (3)

I L = 4 ⋅ ( 0.5 ⋅ VBAT − VL ) ⋅ fSW ⋅ n=C
n =0
0 [ ]
n ⋅ 2 ⋅ CF (3)

where V I and V L represent the input and output voltages, respectively, and DCpM code C[n] determines
the output current.
Electronics 2019, 8, x FOR PEER REVIEW 8 of 15
Electronics 2019, 8, x FOR PEER REVIEW 8 of 15
where VI and VL represent the input and output voltages, respectively, and DCpM code C[n]
Electronics 2019, 8, 98 9 of 16
determines
where VI and the output current.
VL represent the input and output voltages, respectively, and DCpM code C[n]
determines the output current.

Figure 10. Binary-weighted switched-capacitor (SC) DC–DC converter cells for DCpM.
Figure
Figure 10. Binary-weighted switched-capacitor
10. Binary-weighted switched-capacitor (SC)
(SC) DC–DC
DC–DC converter
converter cells
cells for
for DCpM.
DCpM.

C[3] RO/23
VBAT VBAT/2 C[3] RO/23
VBAT VBAT/2
C[2] RO/22
C[2] RO/22
C[1] RO/21 CL RL
C[1] RO/21 CL RL
C[0] RO/20
C[0] RO/20

Figure 11.
Figure Model of
11. Model of the
the proposed
proposed switched-capacitor
switched-capacitor (SC)
(SC) DC–DC
DC–DC converter
converter using
using aa four-bit
four-bit DCpM.
DCpM.
Figure 11. Model of the proposed switched-capacitor (SC) DC–DC converter using a four-bit DCpM.
3. Proposed Low-Ripple SC DC–DC Converter
3. Proposed Low-Ripple SC DC–DC Converter
Figure 12
3. Proposed shows the block
Low-Ripple diagram
SC DC–DC of the proposed SC DC–DC converter, which is composed of a
Converter
Figure 12 shows the block diagram of the proposed SC DC–DC converter, which is composed of
main converter, an auxiliary LDR, and a DCpM controller. The main converter provides most of the
a main converter,
Figure 12 shows an the
auxiliary LDR, andofathe
block diagram DCpM controller.
proposed The main
SC DC–DC converter
converter, whichprovides most of
is composed
current to the load, whereas the LDR assists the main converter to provide an accurate output current.
the current
a main to the load,
converter, whereasLDR,
an auxiliary the LDR
and aassists
DCpMthe main converter
controller. The main to provide
converter anprovides
accuratemost
output
of
The LDR is powered by a small four-phase interleaved SC converter to improve efficiency. To reduce
current. The LDR is powered by a small four-phase interleaved SC converter to
the current to the load, whereas the LDR assists the main converter to provide an accurate outputimprove efficiency.
the switching ripple, four interleaved phases (0◦ , 45◦ , 90◦ , and 135◦ ) are adopted for the SC DC–DC
To reduce
current. theLDR
The switching ripple,by
is powered four interleaved
a small phases
four-phase (0°, 45°, 90°,
interleaved SC and 135°) are
converter adopted efficiency.
to improve for the SC
converter cells. The current of the main converter is controlled by the DCpM, which compares the
DC–DC
To reduceconverter cells.ripple,
the switching The current of the main
four interleaved converter
phases (0°, 45°, is controlled
90°, and 135°) by
are the DCpM,
adopted which
for the SC
output voltage with two reference voltages using two clocked comparators. If output voltage V O >
compares the output
DC–DC converter voltage
cells. Thewith two of
current reference
the mainvoltages usingistwo
converter clocked comparators.
controlled by the DCpM, If output
which
V REF + ∆V or <V REF − ∆V, the binary code decreases or increases, respectively. If V L lies between
voltage
compares VOthe
> Voutput
REF + ΔV or <VREF
voltage − ΔV,
with twothe binary code
reference decreases
voltages using twoor increases, respectively. If
clocked comparators. If output
VL lies
V REF + ∆V and V REF − ∆V, the binary code remains unchanged.
between
voltage VVOREF
>V + REF
ΔV+andΔV V
orREF<V−REF
ΔV,− the
ΔV,binary code code
the binary remains unchanged.
decreases or increases, respectively. If VL lies
between VREF + ΔV and VREF − ΔV, the binary code remains unchanged.
Electronics 2019, 8, 98 10 of 16
Electronics 2019, 8, x FOR PEER REVIEW 9 of 15

-1,0,1
decoder

Figure
Figure 12.
12. Block
Blockdiagram
diagramof
ofthe
theproposed
proposedswitched-capacitor
switched-capacitor (SC)
(SC) DC–DC
DC–DC converter.
converter.

Figure 13a
Figure 13a shows
shows one
one ofof the four-phase
four-phase interleaved
interleaved SC SC DC–DC
DC–DC converter
converter matrices
matrices used
used in
in the
the
main converter,
main converter,which whichis is
composed
composed of four converter
of four cells. cells.
converter Each cell
Each employs a 2:1 step-down
cell employs topology
a 2:1 step-down
and operates
topology in a bi-phase
and operates mode (Φmode
in a bi-phase 1 and (ΦΦ21) and
withΦ50% duty
2) with 50% cycle.
duty The magnitudes
cycle. The magnitudesof the of
flying
the
capacitors
flying CF andCswitches
capacitors are four-bit
F and switches binary-weighted.
are four-bit Binary code
binary-weighted. BinaryC[3:0]
codeof C[3:0]
the DCpMof thecontroller
DCpM
either enables
controller eitheror enables
disablesorthedisables
operationtheofoperation
each converter
of eachcell to adjustcell
converter thetooutput
adjustcurrent. As shown
the output current.in
Figure
As shown13b,inthe auxiliary
Figure LDR
13b, the powered
auxiliary LDR bypowered
the smallby four-phase SC converter
the small four-phase SCemploys
converter a employs
p–channel a
metal–oxide–semiconductor
p–channel metal–oxide–semiconductor(PMOS) pass transistor
(PMOS) pass and a two-stage
transistor operational
and a two-stage amplifier. amplifier.
operational Figure 14
shows the
Figure block diagram
14 shows the blockofdiagram
the proposed
of theLDR-assisted SC DC–DC converter
proposed LDR-assisted SC DC–DC with a low output
converter with ripple.
a low
The proposed
output ripple. converter
The proposedexhibits only a switching
converter exhibits only ripple, and the main
a switching converter
ripple, and theismaincontrolled by the
converter is
DCpM viaby
controlled two-boundary
the DCpM viahysteresis
two-boundary feedback, whichfeedback,
hysteresis also produces
whichaalso low-frequency control ripple.
produces a low-frequency
Nevertheless,
control ripple.the two-boundary
Nevertheless, the controller
two-boundary can limit the control
controller ripple
can limit controlVripple
between
the ∆V and VVREF
REF − between REF −+
∆V.and
∆V Therefore,
VREF + ∆V. theTherefore,
LDR with the a low
LDR output
withcurrent capability
a low output can compensate
current capability can forcompensate
the output current
for the
fluctuation
output due to
current the feedback
fluctuation duecontrol
to theripple by providing
feedback an opposite-phase
control ripple by providing accurate current to the
an opposite-phase
load. This
accurate approach
current ensures
to the load. that
Thisthe DCpM ensures
approach control bits
thatperforming
the DCpM coarse controltuning are fixed atcoarse
bits performing every
outputare
tuning current
fixedrange,
at everyand hence,
output the output
current range,voltage
and hence, ripple
theofoutput
the proposed converter
voltage ripple of thepresents
proposed no
control ripple
converter due to
presents nohysteresis feedback
control ripple due to but only switching
hysteresis feedback ripple.
but only switching ripple.
Figure 15a
Figure 15a shows
shows aa simplified
simplified model
model of of the
the proposed
proposed SC SC DC–DC
DC–DC converter,
converter, where
where thethe 2:1
2:1
transformer
transformer represents
represents thethe 2:1
2:1 voltage
voltage step-down
step-down process.
process. TheThe main
main converter
converter is is described
described using
using aa
binary-weighed unit-resistance RO
binary-weighed unit-resistance O,, which equals
equals 1/(4·C FLY·f
1/(4·CFLY ·fSW
SW),), where
where fSW SWandand C CFLY
FLY represent
represent the
the
switching
switching frequency and unit flying capacitance, respectively. Current IIMAIN
respectively. Current MAIN ofofthe
the main
main SCSC DC–DC
DC–DC
converter
converter cancan bebe expressed as
3
I MAIN = 4 ⋅ ki ⋅ ( 0.5 ⋅ VBAT − VL ) ⋅ fSW ⋅ X
C [ n ] ⋅ 2n ⋅nCF
3
(4)
IMAIN = 4 · ki · (0.5 · VBAT − VL ) · fSW n·=0 C[n] · 2 · CF (4)
n=0
where VI, VO, and ki denote the input voltage, output voltage, and number of interleaved phases,
respectively. The auxiliary LDR is modeled as a fixed resistance RSUB for each SC DC–DC converter
cell and a variable resistance RLDR for the LDR. Consequently, output current ILDR of the auxiliary LDR
can be expressed as
Electronics 2019, 8, 98 11 of 16

where V I , V O , and ki denote the input voltage, output voltage, and number of interleaved phases,
respectively. The auxiliary LDR is modeled as a fixed resistance RSUB for each SC DC–DC converter
cell and a variable resistance RLDR for the LDR. Consequently, output current ILDR of the auxiliary
Electronics 2019, 8,
Electronics 8, xx FOR
FOR PEER
PEER REVIEW
REVIEW 10 of
of 15
15
LDR can2019, be expressed as 10

ILDRI LDR
LDR i ⋅ ( 0.5
= 4=· 4ki⋅ ·k(i 0.5 · V⋅VBAT − VL
BAT
BAT L ) ⋅)f·SWfSW
− VL −−VVDODO
DO SW ⋅ 2 ⋅· C
2 F· CF
F
(5)
(5)

where VDO
where DO represents
DO representsthe
thedropout
dropout voltage
voltage of
of the
the pass
pass transistor
transistor in the
the LDR.
LDR. Hence,
Hence, the auxiliary LDR
can finely adjust the output current. From From Figure
Figure 15b,
15b, we
we note
note that the main converter provides a
discrete coarse
coarse current
currentthat
thatisisdetermined
determinedbybythe DCpM
the DCpM code, whereas
code, whereasthethe
auxiliary converter
auxiliary “fills”
converter the
“fills”
the discrete steps using the linear LDR. Thus, the proposed SC DC–DC converter can
discrete steps using the linear LDR. Thus, the proposed SC DC–DC converter can provide any output provide any
current current
output in its operating range without
in its operating requiringrequiring
range without a complex pulse–width
a complex modulated
pulse–width or pulse–frequency
modulated or pulse–
frequency modulated
modulated controller. controller.

(a) (b)

Figure 13. Schematic

Schematic of
of (a) the main switched-capacitor
switched-capacitor (SC)
(SC) DC–DC
DC–DC converter
converter and
and (b) the auxiliary
SC DC–DC converter.
SC DC–DC converter.

Figure 14.
Figure Block
14. Block diagram
diagram of the
of the proposed
proposed LDR-assisted
LDR-assisted SC DC–DC
SC DC–DC converter
converter and itsand its output
output ripple
ripple voltage.
voltage.
Electronics 2019, 8, 98 12 of 16
Electronics 2019, 8, x FOR PEER REVIEW 11 of 15

auxiliary converter
RSUB RLDR

C[3] RO/23
VBAT VBAT/2 VL

C[2] RO/22

C[1] RO/21 CL RL

C[0] RO/20

main converter

(a) (b)
Figure15.
Figure 15.(a)
(a)The
Thesimplified
simplifiedmodel
modelofof
thethe proposed
proposed switched-capacitor
switched-capacitor (SC)(SC) DC–DC
DC–DC converter
converter and and
(b)
(b) output current versus dropout voltage of the LDR pass transistor.
output current versus dropout voltage of the LDR pass transistor.

4.4.Results
Resultsand
andDiscussion
Discussion
The
Theproposed
proposedSC SCDC–DC
DC–DCconverter
converterwas wasimplemented
implementedusing usingaa0.130.13µmμmCMOSCMOSprocessprocess(Dongbu
(Dongbu
HiTek,
HiTek,Seoul,
Seoul,Korea),
Korea),which whichprovides
providestriple-well
triple-wellCMOSCMOSdevices
devicesand andMIMMIMcapacitors
capacitorswith witheight
eightmetal
metal
layers
layersand and one
onepoly layer.
poly Figure
layer. 16 shows
Figure the microphotograph
16 shows the microphotograph of the fabricated SC DC–DCSC
of the fabricated converter.
DC–DC
The core chip hascore
an area 2 . Several pads2 are allocated to the input and output ports to reduce
converter. The chipofhas 2.04anmm area of 2.04 mm . Several pads are allocated to the input and output
interconnection
ports to reduceloss during measurement.
interconnection loss during The area of the capacitors
measurement. The areaisofthe themajor contributor
capacitors is theto the
major
size of the main
contributor SC size
to the DC–DC of theconverter,
main SCconverter cells, and converter
DC–DC converter, load capacitor.
cells, Stacked
and loadcapacitors
capacitor.utilizing
Stacked
the MIM and
capacitors metal–oxide–semiconductor
utilizing (MOS) capacitors are(MOS)
the MIM and metal–oxide–semiconductor used to increase the
capacitors are capacitance
used to increase per
unit 2 2
the area, which are
capacitance per1unitfF/µm area, and 2.5 fF/µm
which for the and
are 1 fF/μm 2 MIM2.5 and MOS for
fF/μm 2 capacitors,
the MIM respectively. Figure 17
and MOS capacitors,
shows the measured
respectively. Figure output
17 shows voltage and current.
the measured Thevoltage
output proposed andconverter
current. hasThean output voltage
proposed converter range
has
of
an1.2 to 1.5 voltage
output V from arange 3.3 V of supply.
1.2 to The1.5 V output
from voltage
a 3.3 V waveforms
supply. Thewere measured
output voltagewith the use ofwere
waveforms an
MSO7104B
measured with oscilloscope
the use of (Keysight
an MSO7104B Technologies, Santa(Keysight
oscilloscope Rosa, CA,Technologies,
USA). The output Santavoltage
Rosa, CA, andUSA).
LDR
control
The outputsignalvoltage
are shown and LDR for the LDR in
control the on
signal areandshownoff states
for theinLDRFigure 17a.onThe
in the andoutput voltage
off states and
in Figure
current
17a. The were set to
output 1.2 V and 100
voltage respectively.
µA, were
current set to 1.2WhenV andthe 100LDRμA,was deactivated,
respectively. When a highthe ripple
LDR wasof
approximately
deactivated, a 380 highmV was of
ripple obtained. This is because
approximately 380 mVthe wasDCpM control
obtained. Thiscode does not
is because the converge to one
DCpM control
value
code atdoeslight
notloads,
converge and theto onevariation
value at in light
the control
loads, code generates
and the variation a large
in thecontrol
controlripple. However,a
code generates
the ripple
large drops
control below
ripple. 10 mV upon
However, activation
the ripple dropsof the LDR,
below 10 mV which
uponfine-tunes
activationthe output
of the LDR,current
which and
fine-
limits
tunesthe theDCpM
outputcontrol
current code
andtolimits
one value in the main
the DCpM controlSC code
DC–DC converter.
to one value in Thus,
the the
main control ripple
SC DC–DC
disappears due tothe
converter. Thus, thecontrol
bounded rippleDCpM controldue
disappears code, andbounded
to the only theDCpM switching ripple
control code,appears
and onlyin the
the
output
switchingvoltage waveform.
ripple appearsFigure in the17b showsvoltage
output the loadwaveform.
transient performance
Figure 17bwhen shows thethecurrent
loadsuddenly
transient
changes
performancefrom 120when µAthe to 50 mA. The
current output changes
suddenly current and fromoutput
120 μA voltage
to 50aremA. restored to theircurrent
The output regulated
and
values
outputinvoltage
less thanare800 ns. to their regulated values in less than 800 ns.
restored
Figure
Figure18a 18ashows
showsthe themeasured
measuredefficiency
efficiency according
according to to
thethe
output
output current
currentat the input
at the inputvoltage of
voltage
3.3 V. The efficiency depends on the output voltage, with the output voltage
of 3.3 V. The efficiency depends on the output voltage, with the output voltage of 1.5 V corresponding of 1.5 V corresponding
to
tothe
thehighest
highestefficiency
efficiencyand andlowest
lowestoutput
outputcurrent.
current.ThisThisisisbecause
becausethe thevoltage
voltageratio
ratioof ofthetheinput
inputtoto
output
outputisisthe theclosest
closesttotothe thetransformer
transformerratio ratioofofthe
the2:12:1step-down
step-downtopology
topologyininthis thiscase.
case.TheThepeak
peak
efficiency
efficiencyisis73,73,70,
70,andand65% 65% atat
output
output voltages
voltages of of
1.5,1.5,
1.35, andand
1.35, 1.2 1.2
V, respectively.
V, respectively. Figure 18b shows
Figure the
18b shows
measured
the measured output voltage
output rippleripple
voltage according to the output
according current.current.
to the output The maximum
The maximumripple values
rippleremain
values
below
remain 26,below
36, and26,55 36,mVand at 55
output
mV at voltages
outputofvoltages
1.5, 1.35,ofand
1.5,1.2 V, respectively.
1.35, Figure 19 shows
and 1.2 V, respectively. Figurethe19
loss
showscontributions and their ratio
the loss contributions andaccording
their ratio toaccording
the outputtocurrent.
the outputAt the very low
current. output
At the verycurrent, the
low output
DCpM
current, loss
theand
DCpMthe LDR quiescent
loss and the LDR lossquiescent
decrease thelosspower
decreaseefficiency,
the power but efficiency,
as the current but increases, the
as the current
switching loss and conduction loss dominates. Figure 19a shows an efficiency
increases, the switching loss and conduction loss dominates. Figure 19a shows an efficiency reduction reduction of 2.3% due to
the LDR loss
of 2.3% due atto the
the output
LDR loss current
at theofoutput
5 mA but only of
current a 0.23%
5 mA reduction
but only aat0.23%
the output current
reduction of 53
at the mA.
output
current of 53 mA.
Electronics 2019,
Electronics2019, 8,8,98x FOR PEER REVIEW
2019,8, 13 of 16
Electronics x FOR PEER REVIEW 1212ofof1515
Electronics 2019, 8, x FOR PEER REVIEW 12 of 15

Figure16.
Figure 16.Microphotograph
Microphotographof
ofthe
theproposed
proposedswitched-capacitor
switched-capacitor(SC)
(SC) converter.
Figure
Figure 16.
16. Microphotograph
Microphotograph of
of the
the proposed
proposed switched-capacitor
switched-capacitor (SC) converter.
converter.

VV =1.2 1.2 V
VLL L=
= 1.2 V
V

800 ns
800
800 ns
0.5VV
0.5
ns 0.5 V
1 1µsµs
1 µs

IILIL==0.1
0.1mA
mA IILIL==50
50mA
mA
L = 0.1 mA L = 50 mA

(a)
(a) (b)
(b)
(a) (b)
Figure17.
Figure 17.Measured
17. Measuredoutput
outputvoltage
voltageand
andcurrent
currentwaveforms:
waveforms:(a)
(a)the
theripple
ripplevoltage
voltageatataaalow
lowoutput
output
Figure
Figure 17. Measured
Measured output
output voltage
voltage and
and current
current waveforms:
waveforms: (a)
(a) the
the ripple
ripple voltage
voltage at low
at a low output
output
current
current with
current with
with andand without the low dropout regulator (LDR) in operation and (b) the load transient
current with and without
and without the
without the low
the low dropout
low dropout regulator
dropout regulator (LDR)
regulator (LDR) in
(LDR) in operation
in operation and
operation and (b)
and (b) the
(b) the load
the load transient
load transient
transient
responsestotoa asudden
responses suddencurrent
currentvariation.
variation.
responses to a sudden current variation.

75
75 60
60
75 60
(mV)
(mV)
ripple(mV)

70
70 50
50
70 50
65
ripple

65
(%)
(%)

voltageripple

65 40
40
efficiency(%)

40
60
60
efficiency

60 30
efficiency

30
voltage

30
outputvoltage

55
55
55
20
20 VVL=1.50V
50
50 VV =1.50V,Ideal
=1.50V,
VLL=1.50V,
L
Idealefficiency=90.9%
efficiency=90.9%
Ideal efficiency=90.9% 20 VLL=1.50V
=1.50V
50 VVL=1.35V
VV =1.35V,Ideal
=1.35V, Idealefficiency=81.8%
efficiency=81.8% VLL=1.35V
output

VLL=1.35V, Ideal efficiency=81.8% 10

10 =1.35V
output

L
45
45 10 V=1.20V
=1.20V
45 VV =1.20V,
=1.20V, Ideal
Ideal efficiency=72.7%
efficiency=72.7% V
V =1.20V
L L
VLL=1.20V,
L
Ideal efficiency=72.7% L
40
40 0 0
400 0 10
10 20
20 30
30 40
40 50
50 000 10
10 20
20 30
30 40
40 50
50
0 10 20 30 40 50 0 10 20 30 40 50
output current(mA)
output (mA) output current(mA)
(mA)
output current
current (mA) output
output current
current (mA)
(a)
(a) (b)
(b)
(a) (b)
Figure18.
Figure 18.(a)
(a)Measured
Measuredefficiency
efficiencyand
and (b)voltage
voltage rippleaccording
accordingtotooutput
outputcurrent.
current.
Figure
Figure 18.
18. (a)
(a) Measured
Measured efficiency
efficiency and (b)
(b) voltage ripple
ripple according to output current.
Electronics 2019, 8, 98 14 of 16
Electronics 2019, 8, x FOR PEER REVIEW 13 of 15

100 100
DCpM loss
LDR loss
80 Switching loss 80
Conduction loss

ratio of loss (%)

60 60
loss (%)

40 40
DCpM loss
LDR loss
20 20 Switching loss
Conduction loss
0 0
0 10 20 30 40 50 0 10 20 30 40 50
output current (mA) output current (mA)
(a) (b)
Figure 19. Loss
Figure 19. Loss contributions
contributions from
from DCpM,
DCpM, LDR,
LDR, switching,
switching, and
and conduction
conduction losses versus output
losses versus output
current
current for VLL ==1.2
for V 1.2V:
V:(a)
(a)the
theloss
losscontributions
contributionsand
and(b)
(b)the
theratio
ratioof
ofloss
losscontribution.
contribution.

Table 1 compares the performance of the proposed SC DC–DC converter with similar low-ripple
converters. As
As the
the ripple
ripple depends
depends on
on the
the output
output current,
current, load
load capacitance,
capacitance,and
andswitching
switchingfrequency,
frequency,
figure of
we used the following figure of merit
merit for
for aa fair
fair ripple
ripple comparison
comparison [26,27]:
[26,27]:

FoM ripple L

(
FoM ripple==II L/ CCL·⋅ ffSW ·⋅V
L SW Vripple ripple

) (6)
(6)
As can be observed from the table, our approach affords the highest figure of merit.
As can be observed from the table, our approach affords the highest figure of merit.

Table 1. Comparison of results of previously reported studies and current study.

Table 1. Comparison of results of previously reported studies and current study.
Characteristic [15] [22] [26] [28] This Work
Characteristic [15] [22] [26] [28] This Work
Technology (nm) 45 130 130 130 130
Technology (nm) 45 130 130 130 130
Input voltage (V) 1.8 1.8 1–1.2 1.2 3.3
Input voltage (V) 1.8 1.8 1–1.2 1.2 3.3
OutputOutput voltage
voltage (V) (V) 0.8–10.8–1 0.3–0.55
0.3–0.55 1.8–2.1
1.8–2.1 0.2–1.1
0.2–1.1 1.2–1.5
1.2–1.5
Maximum
Maximum load load current
current (mA) (mA)10 10 5555 2.61
2.61 2.53
2.53 5353
Power density (mW/mm 2) 50 24.5 0.67 7.56 31.2
Power density (mW/mm ) 2 50 24.5 0.67 7.56 31.2
Flying capacitance
Flying (pF) (pF) 534 534
capacitance -- 400
400 840840 21762176
Load capacitance (pF) 700 5000 400 764 1000
Load capacitance (pF) 700 5000 400 764 1000
30
Ripple (mV) <50 <50 <10 8–55
Ripple (mV) <50 <50 <10 @IL30 = 30 µA 8–55
Peak efficiency (%) 69 70 82 @IL = 30
80.6μA 73
Switching frequency
Peak (MHz)
efficiency (%) 30 69 10070 20
82 80.65 7340
Figure of merit, Equation
Switching frequency (6)
(MHz) 9.5 30 2.2
100 14
20 53.25 4024.1
Active area (mm2 ) 0.16 0.97 2.25 0.291 2.04
Figure of merit, Equation (6) 9.5 2.2 14 3.25 24.1
Active area (mm2) 0.16 0.97 2.25 0.291 2.04
5. Conclusions
5. Conclusions
We proposed a fully-integrated SC DC–DC converter with low ripple and high efficiency. The
proposed convertera fully-integrated
We proposed employs a four-bit DCpM control
SC DC–DC converter and includes
with an auxiliary
low ripple and highLDR in parallel.
efficiency. The
The DCpM efficiently optimizes the gate switching losses according to the
proposed converter employs a four-bit DCpM control and includes an auxiliary LDR in parallel. output current, and
Thea
two-boundary
DCpM hysteresis
efficiently method
optimizes supports
the gate the ripple
switching lossescontrol. In the
according toproposed
the output structure,
current,the
andfeedback
a two-
ripple is removed by means of an auxiliary LDR connected in parallel. Moreover, four-phase
boundary hysteresis method supports the ripple control. In the proposed structure, the feedback interleaving
is employed
ripple to reduce
is removed bythe switching
means of anripple in theLDR
auxiliary mainconnected
converter. The proposedMoreover,
in parallel. SC DC–DCfour-phase
converter
affords an output voltage range of 1.2–1.5 V from a 3.3 V supply and achieves a
interleaving is employed to reduce the switching ripple in the main converter. The proposed SC peak efficiency ofDC–
73%
and ripple below 55 mV over the entire output current range. We believe that our
DC converter affords an output voltage range of 1.2–1.5 V from a 3.3 V supply and achieves a peak approach will find
utility in power
efficiency of 73%sources for sensor-based
and ripple below 55 mVdevices of entire
over the the future.
output current range. We believe that our
approach will find utility in power sources for sensor-based devices of the future.
Author Contributions: J.-Y.L., G.-S.K., and K.-I.O. carried out the experiments and computer simulation and
wrote the paper under the supervision of D.B.
Electronics 2019, 8, 98 15 of 16

Funding: This research received no external funding.

Acknowledgments: This work was supported by the Institute for Information and Communications Technology
Promotion (IITP) grant funded by the Korea government (MSIT) (No. 2018-0-01663, Development of
Communication-Sensing Converged B5G Millimeter Wave System) and by the Chung-Ang University Graduate
Research Scholarship in 2018.
Conflicts of Interest: The authors declare no conflict of interest.

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