LP5907-Q1 Automotive 250-Ma, Ultra-Low-Noise, Low-I LDO

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LP5907-Q1
SNVSA34E – SEPTEMBER 2014 – REVISED DECEMBER 2019
LP5907-Q1 Automotive 250-mA, Ultra-Low-Noise, Low-IQ LDO

1 Features 3 Description
1• AEC-Q100 qualified for automotive applications: The LP5907-Q1 is a low-noise LDO that can supply
250 mA of output current. Designed to meet the
– Temperature grade 1: –40°C to 125°C, TA requirements of RF and analog circuits, the LP5907-
• Input voltage range: 2.2 V to 5.5 V Q1 provides low noise, high PSRR, low quiescent
• Output voltage range: 1.2 V to 4.5 V current, and low line or load transient response
figures. Using new innovative design techniques, the
• Stable with 1-µF ceramic input and output
LP5907-Q1 offers class-leading noise performance
capacitors without a noise bypass capacitor and the ability for
• No noise bypass capacitor required remote output capacitor placement.
• Remote output capacitor placement The device is designed to work with a 1-µF input and
• Thermal-overload and short-circuit protection a 1-µF output ceramic capacitor (no separate noise
• Output current: 250 mA bypass capacitor is required).
• Low output voltage noise: < 6.5 µVRMS This device is available with fixed output voltages
• PSRR: 82 dB at 1 kHz from 1.2 V to 4.5 V in 25-mV steps. Contact Texas
Instruments Sales for specific voltage option needs.
• Output voltage tolerance: ±2%
• Virtually zero IQ (disabled): < 1 µA Device Information(1)
• Very low IQ (enabled): 12 µA PART NUMBER PACKAGE BODY SIZE (NOM)
• Start-up time: 80 µs SOT-23 (5) 2.90 mm × 1.60 mm
LP5907-Q1
• Low dropout: 120 mV (typical) X2SON (4) 1.00 mm x 1.00 mm
• –40°C to 125°C junction temperature range for (1) For all available packages, see the orderable addendum at
operation the end of the data sheet.
2 Applications
• ADAS cameras and radar
• Automotive infotainment
• Telematics systems
• Navigation systems
Simplified Schematic
INPUT IN OUT OUTPUT
1 PF 1 PF
LP5907-Q1
ENABLE EN
GND
GND
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP5907-Q1
SNVSA34E – SEPTEMBER 2014 – REVISED DECEMBER 2019 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................. 13
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 14
3 Description ............................................................. 1 8 Application and Implementation ........................ 15
4 Revision History..................................................... 2 8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 15
5 Pin Configuration and Functions ......................... 4
6 Specifications......................................................... 5 9 Power Supply Recommendations...................... 18
6.1 Absolute Maximum Ratings ...................................... 5 10 Layout................................................................... 19
6.2 ESD Ratings.............................................................. 5 10.1 Layout Guidelines ................................................. 19
6.3 Recommended Operating Conditions....................... 5 10.2 Layout Examples................................................... 19
6.4 Thermal Information .................................................. 5 11 Device and Documentation Support ................. 20
6.5 Electrical Characteristics........................................... 6 11.1 Receiving Notification of Documentation Updates 20
6.6 Output and Input Capacitors ..................................... 7 11.2 Community Resources.......................................... 20
6.7 Typical Characteristics .............................................. 8 11.3 Trademarks ........................................................... 20
7 Detailed Description ............................................ 12 11.4 Electrostatic Discharge Caution ............................ 20
7.1 Overview ................................................................. 12 11.5 Glossary ................................................................ 20
7.2 Functional Block Diagram ....................................... 12 12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (December 2018) to Revision E Page
• Changed device status from advance information to production data for DQN (X2SON) package....................................... 1
• Changed DQN values and added RθJC(top) parameter to Thermal Information table .............................................................. 5
• Added X2SON rows to ΔVOUT parameter in Electrical Characteristics table.......................................................................... 6
Changes from Revision C (May 2018) to Revision D Page
• Added DQN (X2SON) package to document as Preview ..................................................................................................... 1

• Added Layout Example for the DQN Package figure........................................................................................................... 19
Changes from Revision B (September 2016) to Revision C Page
• Added ESD classification level sub-bullets to Features section ............................................................................................ 1

• Changed DBV values in Thermal Information table .............................................................................................................. 5
• Deleted footnote 1 from Thermal Information table ............................................................................................................... 5
• Added Overshoot on start-up with EN row to Electrical Characteristics table ...................................................................... 7
• Changed Device Comparison table: changed table title, added new rows and new data, moved to new sub-section ...... 13
Changes from Revision A (June 2016) to Revision B Page
• Changed wording of title ........................................................................................................................................................ 1

• Changed "Low Output Voltage Noise: < 10 µVRMS" to "Low Output Voltage Noise: < 6.5 µVRMS"......................................... 1
• Changed items listed in Applications ..................................................................................................................................... 1
• Changed wording of first sentence of Description ................................................................................................................. 1
2 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: LP5907-Q1

LP5907-Q1
www.ti.com SNVSA34E – SEPTEMBER 2014 – REVISED DECEMBER 2019
Changes from Original (September 2014) to Revision A Page
• Added Features bullets re: automotive .................................................................................................................................. 1

• Added top navigator icon for TI Designs ................................................................................................................................ 1
• Changed " linear regulator" to "LDO" ..................................................................................................................................... 1
• Changed storage temperature from Handling Ratings to Abs Max table; replaced Handling Ratings with ESD
Ratings per new format ......................................................................................................................................................... 5
Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback 3

LP5907-Q1
5 Pin Configuration and Functions
DBV Package DQN Package

5-Pin SOT-23 4-Pin X2SON
Top View Bottom View
OUT GND
IN 1 5 OUT 1 2
GND 2
5
EN 3 4 N/C
4 3
IN EN
Pin Functions
PIN
I/O DESCRIPTION
NAME SOT23-5 X2SON-4
Enable input. A low voltage (< VIL) on this pin turns the regulator off and
discharges the output pin to GND through an internal 230-Ω pulldown resistor. A
EN 3 3 I
high voltage (> VIH) on this pin enables the regulator output. This pin has an
internal 1-MΩ pulldown resistor to hold the regulator off by default.
GND 2 2 – Common ground
IN 1 4 I Input voltage supply. Connect a 1-µF capacitor at this input.
N/C 4 — – No internal electrical connection.
Regulated output voltage. Connect a minimum 1-µF low-ESR capacitor to this
pin. Connect this output to the load circuit. An internal 230-Ω (typical) pulldown
OUT 5 1 O
resistor prevents a charge remaining on VOUT when the regulator is in the
shutdown mode (VEN low).

LP5907-Q1
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN MAX UNIT
VIN Input voltage –0.3 6 V
(3)
VOUT Output voltage –0.3 See V
VEN Enable input voltage –0.3 6 V
Continuous power dissipation (4) Internally limited W
TJMAX Junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the GND pin.
(3) Abs Max VOUT is the VIN + 0.3 V or 6 V, whichever is less.
(4) Internal thermal shutdown circuitry protects the device from permanent damage.
6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per AEC
All pins ±2000
Q100-002 (1)
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per AEC Corner pins (1,3,4,5) ±1000
Q100-011 Other pin (2) ±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN MAX UNIT
VIN Input supply voltage 2.2 5.5 V
VEN Enable input voltage 0 5.5 V
IOUT Output current 0 250 mA
TJ-MAX-OP Operating junction temperature (3) –40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the GND pin.
(3) TJ-MAX-OP = [TA(MAX) + (PD(MAX) × RθJA )].
6.4 Thermal Information

LP5907-Q1
THERMAL METRIC (1) DBV (SOT-23) DQN (X2SON-4) UNIT
5 PINS 4-PINS
RθJA Junction-to-ambient thermal resistance 186.9 197.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 112.3 139.4 °C/W
RθJB Junction-to-board thermal resistance 52.3 130.2 °C/W
ψJT Junction-to-top characterization parameter 27.5 6.4 °C/W
ψJB Junction-to-board characterization parameter 51.8 130.2 °C/W
RθJC(top) Junction-to-case (bottom) thermal resistance — 139.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

LP5907-Q1
6.5 Electrical Characteristics

VIN = VOUT(NOM) + 1 V, VEN = 1.2 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF (unless otherwise noted) (1) (2) (3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GENERAL
VIN Input voltage TA = 25°C 2.2 5.5 V
VIN = (VOUT(NOM) + 1 V) to VOUT ≥ 1.8 V –2 2
5.5 V,
IOUT = 1 mA to 250 mA VOUT < 1.8 V –3 3
SOT-23 package
Output voltage tolerance %VOUT
VIN = (VOUT(NOM) + 1 V) to VOUT > 2.5 V –2 2
ΔVOUT 5.5 V,
IOUT = 1 mA to 250 mA VOUT ≤ 2.5 V –3 3
X2SON package
VIN = (VOUT(NOM) + 1 V) to 5.5 V,
Line regulation 0.02 %/V
IOUT = 1 mA
Load regulation IOUT = 1 mA to 250 mA 0.001 %/mA
ILOAD Output load current 0 250 mA
VEN = 1.2 V, IOUT = 0 mA 12 25
IQ Quiescent current (4) VEN = 1.2 V, IOUT = 250 mA 250 425 µA
VEN = 0.3 V (Disabled) 0.2 1
IG Ground current (5) VEN = 1.2 V, IOUT = 0 mA 14 µA
IOUT = 100 mA 50
VDO Dropout voltage (6) mV
IOUT = 250 mA 250
ISC Short-circuit current limit TA = 25°C (7) 250 500 mA
f = 100 Hz, IOUT = 20 mA 90
f = 1 kHz, IOUT = 20 mA 82
PSRR Power-supply rejection ratio (8) dB
f = 10 kHz, IOUT = 20 mA 65
f = 100 kHz, IOUT = 20 mA 60
IOUT = 1 mA 10
eN Output noise voltage (8) BW = 10 Hz to 100 kHz µVRMS
IOUT = 250 mA 6.5
Output automatic discharge
RAD VEN < VIL (output disabled) 230 Ω
pulldown resistance
Thermal shutdown TJ rising 160
TSD °C
Thermal hysteresis TJ falling from shutdown 15
LOGIC INPUT THRESHOLDS
VIN = 2.2 V to 5.5 V,
VIL Low input threshold 0.4 V
VEN falling until the output is disabled
VIN = 2.2 V to 5.5 V,
VIH High input threshold 1.2 V
VEN rising until the output is enabled
VEN = 5.5 V and VIN = 5.5 V 5.5
IEN Input current at EN pin (9) µA
VEN = 0 V and VIN = 5.5 V 0.001
(1) All voltages are with respect to the device GND terminal, unless otherwise stated.
(2) Minimum and maximum limits are ensured through test, design, or statistical correlation over the junction temperature (TJ) range of
–40°C to 125°C, unless otherwise stated. Typical values represent the most likely parametric norm at TA = 25°C, and are provided for
reference purposes only.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX). See Application and
Implementation.
(4) Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT.
(5) Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device.
(6) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its
nominal value.
(7) Short-circuit current (ISC) for the LP5907-Q1 is equivalent to current limit. To minimize thermal effects during testing, ISC is measured
with VOUT pulled to 100 mV below its nominal voltage.
(8) This specification is verified by design.
(9) There is a 1-MΩ resistor between EN and ground on the device.

LP5907-Q1
Electrical Characteristics (continued)

VIN = VOUT(NOM) + 1 V, VEN = 1.2 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF (unless otherwise noted)(1)(2)(3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TRANSIENT CHARACTERISTICS
VIN = (VOUT(NOM) + 1 V) to
–1
(8)
(VOUT(NOM) + 1.6 V) in 30 µs
Line transient
VIN = (VOUT(NOM) + 1.6 V) to
1 mV
(VOUT(NOM) + 1.6 V) in 30 µs
IOUT = 1 mA to 250 mA in 10 µs –40
Load transient (8)
ΔVOUT IOUT = 250 mA to 1 mA in 10 µs 40
(8)
Overshoot on start-up Stated as a percentage of VOUT(NOM) 5%
Stated as a percentage of VOUT(NOM), VIN =
VOUT + 1 V to 5.5 V, 0.7 µF < COUT < 10 µF, 0
Overshoot on start-up with EN (8) 1%
mA < IOUT < 250 mA, EN rising until the output
is enabled
From VEN > VIH to VOUT = 95% of VOUT(NOM),
tON Turnon time 80 150 µs
TA = 25°C
6.6 Output and Input Capacitors

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN (1) TYP MAX UNIT
(2)
CIN Input capacitance 0.7 1
Capacitance for stability µF
COUT Output capacitance (2) 0.7 1 10
ESR Output/input capacitance (2) 5 500 mΩ
(1) The minimum capacitance should be greater than 0.5 μF over the full range of operating conditions. The capacitor tolerance should be
30% or better over the full temperature range. The full range of operating conditions for the capacitor in the application should be
considered during device selection to ensure this minimum capacitance specification is met. X7R capacitors are recommended however
capacitor types X5R, Y5V and Z5U may be used with consideration of the application and conditions.
(2) This specification is verified by design.

LP5907-Q1
6.7 Typical Characteristics

VIN = 3.7 V, VOUT = 2.8 V, IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF, TA = 25°C (unless otherwise noted)
16 1
14
0.9
12
10
0.8
IQ( A)
VEN (V)
8
6 0.7
2 0.6
VIH Rising
0 VIL Falling
0.5
2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8
2 2.5 3 3.5 4 4.5 5 5.5 6
VIN(V) VIN (V)
SVA-30180569 D001
Figure 1. Quiescent Current vs Input Voltage Figure 2. VEN Thresholds vs VIN

1.4 5
4.5
1.2
4
1 3.5
3
VOUT (V)
VOUT (V)
0.8
2.5
0.6
2
0.4 1.5
1
0.2 RLOAD = 1.2 k: RLOAD = 4.5 k:
0.5
RLOAD = 4.8 : RLOAD = 18 :
0 0
0 0.5 1 1.5 2 2.5 0 1 2 3 4 5 6
VIN (V) D002
VIN (V) D003
VOUT = 1.2 V, VEN = VIN VOUT = 4.5 V, VEN = VIN
Figure 3. VOUT vs VIN Figure 4. VOUT vs VIN

350 2.900
VIN= 3.6V
300 2.875
GROUND CURRENT ( A)
250 2.850
2.825
VOUT(V)
200
2.800
150
2.775
100
2.750
VIN = 3.0V -40°C
50 VIN = 3.8V 2.725 90°C
VIN = 4.2V 25°C
VIN = 5.5V
0 2.700
0 50 100 150 200 250 300 0 50 100 150 200 250
IOUT(mA) LOAD (mA)
SVA-30180571 SVA-30180567
Figure 5. Ground Current vs Output Current Figure 6. Load Regulation

LP5907-Q1
Typical Characteristics (continued)

2.900
2V/DIV
2.875 Load = 10 mA
2.850 VOUT
2.825 2V/DIV
VOUT(V)
2.800
2.775 VIN = VEN
2.750
-40°C
2.725 90°C IIN 1A/DIV
25°C
2.700
2 ms/DIV
3.0 3.5 4.0 4.5 5.0 5.5
VIN(V) SVA-30180568 SVA-30180509
Figure 7. Line Regulation Figure 8. Inrush Current
VOUT 10 mV/ VOUT 10 mV/

(AC Coupled) DIV (AC Coupled) DIV
VIN 1V/DIV VIN 1V/DIV
10 s/DIV 10 s/DIV
SVA-30180510 SVA-30180511
VIN = 3.2 V ↔ 4.2 V, load = 1 mA VIN = 3.2 V ↔ 4.2 V, load = 250 mA
Figure 9. Line Transient Figure 10. Line Transient
VOUT 100 mV/DIV VOUT 100 mV/DIV
LOAD 200 mA/DIV

LOAD 200 mA/DIV
100 s/DIV
100 s/DIV
SVA-30180512 SVA-30180513
Load = 0 mA ↔ 250 mA, –40°C Load = 0 mA ↔ 250 mA, 90°C
Figure 11. Load Transient Figure 12. Load Transient

LP5907-Q1

1V/DIV
VOUT 100 mV/DIV
VOUT
LOAD 200 mA/DIV 1V/DIV
EN
100 s/DIV 20 s/DIV

SVA-30180514 SVA-30180515
Load = 0 mA ↔ 250 mA, 25°C 0 mA
Figure 13. Load Transient Figure 14. Start-Up
1V/DIV
VOUT
1V/DIV
EN
20 s/DIV
SVA-30180516
250 mA
Figure 15. Start-Up Figure 16. Noise Density Test

140 0
250 mA
120 200 mA
DROPOUT VOLTAGE (mV)
-20 150 mA
100 100 mA
50 mA
-40 20 mA
80
PSRR (dB)
60 -60
40
-80
Dropout Voltage
20
-100
0
0 50 100 150 200 250 -120
LOAD CURRENT (mA) 0.1 1 10 100
SVA-30180573 FREQUENCY (kHz) D004
Figure 17. Dropout Voltage vs Load Current

Figure 18. PSRR Loads Averaged 100 Hz To 100 KHz

LP5907-Q1

0
-20
-40
PSRR (dB)
-60
-80 250 mA
200 mA
150 mA
-100 100 mA
50 mA
20 mA
-120
0.01 0.1 1 10 100 1000 10000
FREQUENCY (kHz) D005
Figure 19. PSRR Loads Averaged 10 Hz To 10 MHz

LP5907-Q1
7 Detailed Description
7.1 Overview
Designed to meet the needs of sensitive RF and analog circuits, the LP5907-Q1 provides low noise, high PSRR,
low quiescent current, as well as low line and load transient response figures. Using new innovative design
techniques, the LP5907-Q1 offers class leading noise performance without the need for a separate noise filter
capacitor.
The LP5907-Q1 is designed to perform with a single 1-µF input capacitor and a single 1-µF ceramic output
capacitor. With a reasonable PCB layout, the single 1-µF ceramic output capacitor can be placed up to 10 cm
away from the LP5907-Q1 package.
7.2 Functional Block Diagram
IN OUT
EN POR
EN
+
RF
CF
+
VBG
RAD
1.20V
EN
EN + EN
1M
VIH GND

LP5907-Q1
7.3 Feature Description

7.3.1 LP5907-Q1 Voltage Options
Table 1 lists the available voltage options for the LP5907-Q1 SOT-23 package.
Table 1. Voltage Options

SOT-23 PACKAGE ORDER NUMBER VOLTAGE OPTION (V)
LP5907QMFX-1.2Q1 1.2
— 1.3
— 1.5
LP5907QMFX-1.8Q1 1.8
LP5907QMFX-2.5Q1 2.5
LP5907QMFX-2.8Q1 2.8
2.85
2.9
LP5907QMFX-3.0Q1 3.0
LP5907QMFX-3.3Q1 3.3
LP5907QMFX-3.8Q1 3.8
LP5907QMFX-4.5Q1 4.5
7.3.2 Enable (EN)

The LP5907-Q1 EN pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be higher than
the VIH threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage
must be lower than the VIL threshold to ensure that the device is fully disabled and the automatic output
discharge is activated.
7.3.3 Low Output Noise

Any internal noise at the LP5907-Q1 reference voltage is reduced by a first order low-pass RC filter before it is
passed to the output buffer stage. The low-pass RC filter has a –3 dB cut-off frequency of approximately 0.1 Hz.
7.3.4 Output Automatic Discharge

The LP5907-Q1 output employs an internal 230-Ω (typical) pulldown resistance to discharge the output when the
EN pin is low, and the device is disabled.
7.3.5 Remote Output Capacitor Placement

The LP5907-Q1 requires at least a 1-µF capacitor at the OUT pin, but there are no strict requirements about the
location of the capacitor in regards the OUT pin. In practical designs, the output capacitor may be located up to
10 cm away from the LDO.
7.3.6 Thermal Overload Protection (TSD)

Thermal shutdown disables the output when the junction temperature rises to approximately 160°C which allows
the device to cool. When the junction temperature cools to approximately 145°C, the output circuitry enables.
Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may
cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a
result of overheating.
The thermal shutdown circuitry of the LP5907-Q1 has been designed to protect against temporary thermal
overload conditions. The thermal shutdown circuitry was not intended to replace proper heat-sinking.
Continuously running the LP5907-Q1 device into thermal shutdown may degrade device reliability.

LP5907-Q1
7.4 Device Functional Modes

7.4.1 Enable (EN)
The LP5907-Q1 Enable (EN) pin is internally held low by a 1-MΩ resistor to GND. The EN pin voltage must be
higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions.
When the EN pin is pulled low, and the output is disabled, the output automatic discharge circuitry is activated.
Any charge on the OUT pin is discharged to GND through the internal 230-Ω (typical) pull-down resistance.
7.4.2 Minimum Operating Input Voltage (VIN)

The LP5907-Q1 does not include any dedicated undervoltage lockout circuitry. The LP5907-Q1 internal circuitry
is not fully functional until VIN is at least 2.2 V. The output voltage is not regulated until VIN has reached at least
the greater of 2.2 V or (VOUT + VDO).

LP5907-Q1
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information

Figure 20 shows the typical application circuit for the LP5907-Q1. Input and output capacitances may need to be
increased above the 1 µF minimum for some applications.
8.2 Typical Application
INPUT IN OUT OUTPUT
1 PF 1 PF
LP5907-Q1
ENABLE EN
GND
GND
Figure 20. LP5907-Q1 Typical Application
8.2.1 Design Requirements
DESIGN PARAMETER EXAMPLE VALUE

Input voltage range 2.2 to 5.5 V
Output voltage 1.8 V
Output current 200 mA
Output capacitor range 0.7 to 10 µF
Input/output capacitor ESR range 5 to 500 mΩ
8.2.2 Detailed Design Procedure

To begin the design process, determine the following:
• Available input voltage range
• Output voltage needed
• Output current needed
• Input and Output capacitors
8.2.2.1 Power Dissipation and Device Operation

The permissible power dissipation for any package is a measure of the capability of the device to pass heat from
the power source, the junctions of the device, to the ultimate heat sink, the ambient environment. Thus, the
power dissipation is dependent on the ambient temperature and the thermal resistance across the various
interfaces between the die junction and ambient air.

LP5907-Q1
The maximum allowable power dissipation for the device in a given package can be calculated using Equation 1:
PD-MAX = ((TJ-MAX – TA) / RθJA) (1)
The actual power being dissipated in the device can be represented by Equation 2:
PD = (VIN - VOUT) × IOUT (2)
Equation 1 and Equation 2 establish the relationship between the maximum power dissipation allowed due to
thermal consideration, the voltage drop across the device, and the continuous current capability of the device.
These two equations should be used to determine the optimum operating conditions for the device in the
application.
In applications where lower power dissipation (PD) and/or excellent package thermal resistance (RθJA) is present,
the maximum ambient temperature (TA-MAX) may be increased.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum
ambient temperature (TA-MAX) may have to be derated. TA-MAX is dependent on the maximum operating junction
temperature (TJ-MAX-OP = 125°C), the maximum allowable power dissipation in the device package in the
application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA),
as given by Equation 3:
TA-MAX = (TJ-MAX-OP – (RθJA × PD-MAX)) (3)
Alternately, if TA-MAX can not be derated, the PD value must be reduced. This can be accomplished by reducing
VIN in the VIN – VOUT term as long as the minimum VIN is met, or by reducing the IOUT term, or by some
combination of the two.
8.2.2.2 External Capacitors

Like most LDOs, the LP5907-Q1 requires external capacitors for regulator stability. The device is specifically
designed for portable applications requiring minimum board space and smallest components. These capacitors
must be correctly selected for good performance.
8.2.2.3 Input Capacitor

An input capacitor is required for stability. The input capacitor should be at least equal to, or greater than, the
output capacitor for good load transient performance. At least a 1-µF capacitor has to be connected between the
LP5907-Q1 input pin and ground for stable operation over full load current range. Basically, it is acceptable to
have more output capacitance than input, as long as the input is at least 1 µF.
The input capacitor must be located a distance of not more than 1 cm from the IN pin and returned to a clean
analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
Important: To ensure stable operation it is essential that good PCB practices are employed to minimize ground
impedance and keep input inductance low. If these conditions cannot be met, or if long leads are to be used to
connect the battery or other power source to the LP5907-Q1, TI recommends increasing the input capacitor to at
least 10 µF. Also, tantalum capacitors can suffer catastrophic failures due to surge current when connected to a
low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the
input, it must be verified by the manufacturer to have a surge current rating sufficient for the application. The
initial tolerance, applied voltage de-rating, and temperature coefficient must all be considered when selecting the
input capacitor to ensure the actual capacitance is never less than 0.7 µF over the entire operating range.
8.2.2.4 Output Capacitor

The LP5907-Q1 is designed specifically to work with a very small ceramic output capacitor, typically 1 µF. A
ceramic capacitor (dielectric types X5R or X7R) in the 1-µF to 10-µF range, and with equivalent series resistance
(ESR) between 5 mΩ to 500 mΩ, is suitable in the LP5907-Q1 application circuit. For this device connect the
output capacitor between the OUT pin and a good connection back to the GND pin.
It may also be possible to use tantalum or film capacitors at the device output, VOUT, but these are not as
attractive for reasons of size and cost (see Capacitor Characteristics).
The output capacitor must meet the requirement for the minimum value of capacitance and have an ESR value
that is within the range 5 mΩ to 500 mΩ for stability. Like the input capacitor, the initial tolerance, applied voltage
de-rating, and temperature coefficient must all be considered when selecting the input capacitor to ensure the
actual capacitance is never less than 0.7 µF over the entire operating range.

LP5907-Q1
8.2.2.5 Capacitor Characteristics

The LP5907-Q1 is designed to work with ceramic capacitors on the input and output to take advantage of the
benefits they offer. For capacitance values in the range of 1 µF to 10 µF, ceramic capacitors are the smallest,
least expensive, and have the lowest ESR values, thus making them best for eliminating high frequency noise.
The ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability for the LP5907-Q1.
A better choice for temperature coefficient in a ceramic capacitor is X7R. This type of capacitor is the most stable
and holds the capacitance within ±15% over the temperature range. Tantalum capacitors are less desirable than
ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance
and voltage ratings in the 1 µF to 10 µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. The ESR of a typical tantalum increases about 2:1 as the temperature goes
from 25°C down to –40°C, so some guard band must be allowed.
8.2.2.6 Remote Capacitor Operation

The LP5907-Q1 requires at least a 1-µF capacitor at the OUT pin, but there are no strict requirements about the
location of the capacitor in regards to the pin. In practical designs the output capacitor may be located up to 10
cm away from the LDO. This means that there is no need to have a special capacitor close to the output pin if
there is already respective capacitors in the system (like a capacitor at the input of supplied part). The remote
capacitor feature helps user to minimize the number of capacitors in the system.
As a good design practice, keep the wiring parasitic inductance at a minimum, which means to use as wide as
possible traces from the LDO output to the capacitors, keeping the LDO output trace layer as close as possible
to ground layer and avoiding vias on the path. If there is a need to use vias, implement as many as possible vias
between the connection layers. The recommendation is to keep parasitic wiring inductance less than 35 nH. For
the applications with fast load transients, it is recommended to use an input capacitor equal to or larger to the
sum of the capacitance at the output node for the best load transient performance.
8.2.2.7 No-Load Stability

The LP5907-Q1 remains stable, and in regulation, with no external load.
8.2.2.8 Enable Control

The LP5907-Q1 may be switched ON or OFF by a logic input at the EN pin. A voltage on this pin greater than
VIH turns the device on, while a voltage less than VIL turns the device off.
When the EN pin is low, the regulator output is off and the device typically consumes less than 1 µA.
Additionally, an output pulldown circuit is activated which ensures that any charge stored on COUT is discharged
to ground.
If the application does not require the use of the shutdown feature, the EN pin can be tied directly to the IN pin to
keep the regulator output permanently on.
An internal 1-MΩ pulldown resistor ties the EN input to ground, ensuring that the device remains off if the EN pin
is left open circuit. To ensure proper operation, the signal source used to drive the EN pin must be able to swing
above and below the specified turnon or turnoff voltage thresholds listed in the Electrical Characteristics under
VIL and VIH.

LP5907-Q1
8.2.3 Application Curves
1V/DIV
VOUT 100 mV/DIV
VOUT
1V/DIV LOAD 200 mA/DIV
EN
20 s/DIV 100 s/DIV

SVA-30180515 SVA-30180514
Figure 21. Start-Up Figure 22. Load Transient Response
9 Power Supply Recommendations

This device is designed to operate from an input supply voltage range of 2.2 V to 5.5 V. The input supply must
be well regulated and free of spurious noise. To ensure that the LP5907-Q1 output voltage is well regulated and
dynamic performance is optimum, the input supply must be at least VOUT + 1 V. A minimum capacitor value of
1 µF is required to be within 1 cm of the IN pin.

LP5907-Q1
10 Layout
10.1 Layout Guidelines

The dynamic performance of the LP5907-Q1 is dependant on the layout of the PCB. PCB layout practices that
are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5907-Q1.
Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5907-Q1, and as
close as is practical to the package. The ground connections for CIN and COUT must be back to the LP5907-Q1
ground pin using as wide and short copper traces as are practical.
Avoid connections using long trace lengths, narrow trace widths, and/or connections through vias. These add
parasitic inductances and resistance that results in inferior performance especially during transient conditions
10.2 Layout Examples

VIN VOUT
CIN 1 IN OUT 5 COUT
GND GND
2 GND
Enable
3 EN N/C 4
Figure 23. LP5907MF-x.x (SOT-23) Typical Layout
OUT IN
1 4
COUT
CIN
EN
2 3
GND PLANE
Represents via used for application

specific connections
Figure 24. Layout Example for the DQN Package

LP5907-Q1
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 7-Oct-2021
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
LP590712QDQNRQ1 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D1
LP590722QDQNRQ1 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 FV
LP590733QDQNRQ1 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 DA
LP590738QDQNRQ1 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 DB
LP590745QDQNRQ1 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 DC
LP5907QMFX-1.2Q1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 RAFQ
LP5907QMFX-1.8Q1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 RAGQ
LP5907QMFX-2.5Q1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 RAJQ
LP5907QMFX-2.8Q1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 RAKQ
LP5907QMFX-3.0Q1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 RALQ
LP5907QMFX-3.3Q1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 RAHQ
LP5907QMFX-3.8Q1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 RAMQ
Addendum-Page 1
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
LP5907QMFX-4.5Q1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 125 RAIQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LP5907-Q1 :
• Catalog : LP5907
Addendum-Page 2
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP590712QDQNRQ1 X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2
LP5907QMFX-1.2Q1 SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP5907QMFX-1.8Q1 SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP5907QMFX-2.5Q1 SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP5907QMFX-2.8Q1 SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP5907QMFX-3.0Q1 SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
Pack Materials-Page 1
Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP5907QMFX-3.3Q1 SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP5907QMFX-3.8Q1 SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP5907QMFX-4.5Q1 SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP590712QDQNRQ1 X2SON DQN 4 3000 213.0 191.0 35.0
LP5907QMFX-1.2Q1 SOT-23 DBV 5 3000 208.0 191.0 35.0
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP5907QMFX-1.8Q1 SOT-23 DBV 5 3000 208.0 191.0 35.0
LP5907QMFX-2.5Q1 SOT-23 DBV 5 3000 208.0 191.0 35.0
LP5907QMFX-2.8Q1 SOT-23 DBV 5 3000 208.0 191.0 35.0
LP5907QMFX-3.0Q1 SOT-23 DBV 5 3000 208.0 191.0 35.0
LP5907QMFX-3.3Q1 SOT-23 DBV 5 3000 208.0 191.0 35.0
LP5907QMFX-3.8Q1 SOT-23 DBV 5 3000 208.0 191.0 35.0
LP5907QMFX-4.5Q1 SOT-23 DBV 5 3000 208.0 191.0 35.0
PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA
1 5
2X 0.95
3.05
2.75
1.9 1.9
2
4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00
0.25
GAGE PLANE 0.22
TYP
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3 4
(R0.05) TYP (2.6)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
EXPOSED METAL EXPOSED METAL
0.07 MAX 0.07 MIN

ARROUND ARROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/F 06/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
2 (1.9)
2X(0.95)
3 4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DQN0004A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
B 1.05 A
0.95
1.05
PIN 1 0.95
INDEX AREA
C
0.4 MAX
SEATING PLANE
0.08
NOTE 6
0.48+0.12
-0.1
0.05
(0.05) TYP 0.00
2 NOTE 6
3
EXPOSED
5 THERMAL PAD
2X 0.65
(0.07) TYP
NOTE 5
1 4
PIN 1 ID 4X 0.28
0.15
(OPTIONAL) (0.11)
NOTE 4 0.3 0.1 C A B
0.2
0.05 C
3X 0.30
0.15
4215302/E 12/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
5. Shape of exposed side leads may differ.
6. Number and location of exposed tie bars may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
(0.86)
SYMM
4X (0.36) 4X SEE DETAIL

(0.03)
4
4X (0.21) 1
SYMM 5 (0.65)
4X (0.18)
( 0.48)
(0.22) TYP
EXPOSED METAL
CLEARANCE
LAND PATTERN EXAMPLE

SCALE: 40X
0.05 MIN
ALL AROUND
SOLDER MASK
EXPOSED METAL OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAIL

4215302/E 12/2016
NOTES: (continued)
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
(0.9)
SYMM
4X (0.4)
4X (0.03)
4
4X (0.21) 1
5
SYMM
(0.65)
SOLDER MASK
EDGE 4X (0.22)
2
3
( 0.45)
4X (0.235)
SOLDER PASTE EXAMPLE

BASED ON 0.075 - 0.1mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE: 60X
4215302/E 12/2016
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated

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INPUT IN OUT OUTPUT

Changes from Revision D (December 2018) to Revision E Page

Changes from Revision C (May 2018) to Revision D Page

• Added DQN (X2SON) package to document as Preview ..................................................................................................... 1

Changes from Revision B (September 2016) to Revision C Page

• Added ESD classification level sub-bullets to Features section ............................................................................................ 1

Changes from Revision A (June 2016) to Revision B Page

• Changed wording of title ........................................................................................................................................................ 1

2 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated

Product Folder Links: LP5907-Q1

Changes from Original (September 2014) to Revision A Page

• Added Features bullets re: automotive .................................................................................................................................. 1

Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback 3

5 Pin Configuration and Functions

DBV Package DQN Package

4 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated

Product Folder Links: LP5907-Q1

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback 5

6.5 Electrical Characteristics

6 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated

Product Folder Links: LP5907-Q1

Electrical Characteristics (continued)

6.6 Output and Input Capacitors

Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback 7

6.7 Typical Characteristics

Figure 1. Quiescent Current vs Input Voltage Figure 2. VEN Thresholds vs VIN

Figure 3. VOUT vs VIN Figure 4. VOUT vs VIN

Figure 5. Ground Current vs Output Current Figure 6. Load Regulation

8 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated

Product Folder Links: LP5907-Q1

Typical Characteristics (continued)

2.775 VIN = VEN

Figure 7. Line Regulation Figure 8. Inrush Current

VOUT 10 mV/ VOUT 10 mV/

VIN 1V/DIV VIN 1V/DIV

Figure 9. Line Transient Figure 10. Line Transient

VOUT 100 mV/DIV VOUT 100 mV/DIV

LOAD 200 mA/DIV

Figure 11. Load Transient Figure 12. Load Transient

Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback 9

Typical Characteristics (continued)

LOAD 200 mA/DIV 1V/DIV

100 s/DIV 20 s/DIV

Figure 13. Load Transient Figure 14. Start-Up

Figure 15. Start-Up Figure 16. Noise Density Test

Figure 17. Dropout Voltage vs Load Current

10 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated

Product Folder Links: LP5907-Q1

Typical Characteristics (continued)

Figure 19. PSRR Loads Averaged 10 Hz To 10 MHz

Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback 11

7.2 Functional Block Diagram

12 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated