Z490-I Gaming Rev1.03

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Rev 1.

02X Allen_cheng
2019.11

Z490-I
128-bit Dual-Channel Memory x 4 Slots

Intel Processor
Channel A DDR4 2133/2400/ 2666/ 2933/ 3200

IMVP8 SVID COMETLAKE - S Channel B DDR4 2133/2400/ 2666/ 2933/ 3200


(10+2 or 8/6/4+2)

LGA-1200 Pin Socket


DDI B Display Port
PCIE_x16 slot PCIEx16

DDI C 2.0a
HDMI

DMI

FDI

Intel_I225V PCIE x1(L5) SIO


LPC BUS

INTEL 24MHz
NCT6798D

port1,2
FRONT
USB3.2 Type C
U32G2x2 PI3EQX1002B
U32G2_C1
COMET Lake

PCH port3
Back
USB3.2 Type A
U32G2x1
(LAN_U32G2_3)
PI3EQX1004B Back
PCH M.2_1(Card) port4
PCIE x4(L9-12) USB3.2 Type C
(SATA Mode+PCIE mode) U32G2x1 ASM1543
U32G2_C4

Integrated port5
PCH M.2_2(Card) Clock Back
PCIE x4 (L17-L20)
(SATA Mode+PCIE mode) U32G2x1
USB3.2 Type A
PI3EQX1004B
port6 (U32G2_56)
CNVi signal
U32G2x1
Intel CNVi 38.4MHz

GPIO
Front Back
U32G1_7 U32G1_9
U32G1 x4
U32G1_8 U32G1_10

Port11
Front
USB_E1
USB2.0 x1 GL852 USB2.0 x4
USB_E2

Audio
Realtek ALC1220 Codec Realtek
Port12 BACK
BIOS
USB2.0 x1 USB2.0 x1 USB2_12
Flash BACK

SPI FLASH SPI Port13 BACK


32M USB2.0 x1 USB2_13

L13~16
SATA3 SATA1 Port2 <Variant Name>
SATA 6Gb/s
SATA4 SATA2 USB2.0 x1 AURA Title : BLOCK DIAGRAM
ASUSTek COMPUTER INC.
Engineer: Allen_Cheng
Size Project Name Rev
C Z490-I Gaming R1.01

Date: Thursday, December 12, 2019 Sheet 1 of 119


Intel Processor
ICG : Integrated Clock Gen.
Coffee Lake S

LGA-1151 Pin Socket

CLOCK Gen
INTEL
Canon Lake PCH-H
SIO 24MHz 100MHz
NCT6798D
CLKOUT_PCI0 PCH CLKOUT_DMI
24MHz
24MHz CLKOUT_NSCC
EC-KB3728 CLKOUT_PCI1 Integrated
Clock 100MHz
CLKOUT_BCLK

CLKOUT_48 100MHz
CLKOUT_ITPXDP ITP

38.4MHz CLKOUT_PCIE0 N/A 100MHz


CNVI MAC_CLK

CLKOUT_PCIE1 DIMM.2_1(CPU) 100MHz


24MHz
XTAL PCH_CLK
CLKOUT_PCIE2 I219V 100MHz

32.768KHz
XTAL RTC_CLK CLKOUT_PCIE3 PCIEX16_1 100MHz

CLKOUT_PCIE4 PCIEX16_2 100MHz

CLKOUT_PCIE5 PCIEX16_3 100MHz

CLKOUT_PCIE15 CLKOUT_PCIE6 AQC111 100MHz

CLKOUT_PCIE14 CLKOUT_PCIE7 M.2_1(PCH) 100MHz

CLKOUT_PCIE13 CLKOUT_PCIE8 M.2_1(PCH) 100MHz

CLKOUT_PCIE12 CLKOUT_PCIE9 ASM1042 100MHz

100MHz DIMM.2_2(CPU) CLKOUT_PCIE11 CLKOUT_PCIE10 PCIEX1_1 100MHz

<Variant Name>

Title : Clock Distribution


ASUSTek COMPUTER INC.
Engineer: Aaron_Su
Size Project Name Rev
A3 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 2 of 119


RESET_SWITCH

teknisi indonesia
PCI_Express x 16_1 <19>O_PCIRST#_PCIEX16_1 XDP
PWRGD
SYS_RESET#
<19>O_PCIRST#_PCIEX16_2 DBR#
PCI_Express x 16_2
PWRGD H_CPURST#
RESET#
<19>O_PCIRST#_PCIEX16_3
PCH
PCI_Express x 1_1,2
& x16_3 LYNX POINT OBSDATA
PWRGD

SIO
AZ_RST# AUDIO
POWER_SWITCH NCT6779D HDA_RST# RESET#
ALC898
PROCESSOR
<5>O_PWRBTN#IN PCIRST1# HASWELL
PS_IN#
PCIRST2#
SYS_RESET#
PCIRST3# SYS_RESET# DBR#
*9
<18>S_PLTRST# *8 <18>H_CPURST#
LRESET# PLTRST# PLTRST_PROC# RESET#
*5
O_KB_RST# <13>S_DRAMPWRGD
KBRST# RCIN# DRAMPWROK SM_DRAMPWROK
<4>O_RSMRST# <1>RTCRST#
RSMRST# RSMRST# RTCRST#
CFG
<6>O_PWRBTN# <1>SRTCRST#
PS_OUT# PWRBTN# SRTCRST#
POWER SUPPLY
<10>12V,5V,3V SLP_S5#
Main PWR
<3>+5VSB, +3VSB <4.1> / <8>S_SLPS4# BATTERY
VSB SUSC# SLP_S4# *4
<9>O_PSON#
<2>AC Power PSON# PSON# *1 <4.2> / <9>S_SLPS3# *7
Switch On <11>B_ATX_PWROK SUSB# SLP_S3# *5 <14>H_CPUPWRGD
PWROK ATXPGD *2 PROCPUPWRGD PWRGOOD
<7>S_SLP_A#
SLP_A# *3
PWROK <15>VRM_SVID
<7.1>S_SLP_LAN# <3.1>S_DPWROK SVID
SLP_LAN# DPWROK <16>VCORE
VCORE
SYS_PWROK
*1
PSON# is inverted by SLP_S3#,
but gated and delayed by PCH_PWROK MEPWROK
PWRBTN#

*2 Non-AMT AMT
PWROK will assert when +3V arrives
at +2.1V then delay 300ms~500ms
and gated by ATXPGD
<12>O_PWROK
*3
If support AMT, SLP_A# ME_POWER
could already be high
before sequence begins. +1.05ME
If not support AMT, SLP_A# Vcore Controller
will come with SLP_S3 +3V_DUAL_LAN/EPW
<7.2>S_MEPWROK
SVID
*4
SLP_S4# controls +1.5VDual and VCORE
+VTTDDR
*6 S_SLPS3#
*5 <17>VRMPWRGD VR_ON
Come with 1.5VDUAL PGOOD +12V
*6 +3V
Come with +3V,+12V and gated ISL95818
by SLP_S3#
*7
CPUPWRGD= After PWROK
*8 <Variant Name>
PLTRST# = PCH PWROK AND PCH
SYS_PWROK Title : Signal & Reset map
*9 CHIP SOCKET or SLOT
PLTRST_PROC#=PLTRST#, ASUSTek COMPUTER INC.
Engineer: Aaron_Su
voltage=1V, directly connect
Size Project Name Rev
to CPU
A3 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 3 of 119


+12V_CPU ASP1405I VCORE 0.5V~1.55V (100A)
+12V_CPU Twin10 PHASE - Loop1 S0/S1
TDA21462
Switch ON/OFF
P_+VCCIO_PG_10 SVID Switching Linear

Control signal Power Rail

ASP1405I VCCGT 0.5V~1.55V (49A)


2PHASE - Loop2 S0/S1
TDA21462

P_+VCCIO_PG_10 SVID

+12V RT3601EAGQW+RT9611CGQW VCCSA 1.05V (11A)


S0/S1
NTMFS4C10*2+NTMFS4C06*2

P_+VCCIO_PG_10

VCCIO_0 0.95V (5.5A)


RT6541 S0/S1

VCCIO_12
RT6541 S0/S1

+5V

RT8125DGQW 1 phase VDDQ 1.2V (12.87A) S0/S1/S3


PEA16BA*3
VTTDDR 0.6V (0.6A) S0/S1
RT9088AGQW
P_+VPPDDR_PG_5

S_SLPS3#
S_SLPS4#
DDR_VTT_CNTL

+5V +5V_DUAL_USBKB
UP7501
+5VDUAL_AUX 5V (18.92A) VPPDDR 2.5V(2.24A) S0/S1/S3
NTMFS4C10NBT1G+AP2301GN RT7276
+5VSB_ATX
+5VSB_ATX

MPQ8633BGLE-Z +1.05V_A 1.05V(16A)

+5VSB_ATX +3VSB_ATX 3.38V(2.29A)


UZ2085G

O_DEEPS5

RT7276GQW +VCCST
O_DEEPS5

+3V UP7501 +3VDUAL_AUX

NTMFS4C10NBT1G+AP2301GN
RT7276GQW +VCCSTG

+3.3V

+12V

<Variant Name>

Title
<Title>

Size Document Number X99 Deluxe Rev


A2 <Doc> <RevCode>

Date: Thursday, December 12, 2019 Sheet 5 of 121


141023 加入enable線路- Gamnig only

0.1UF/16V
PM ADDRESS OFFSET SETTING
+VCCST +3VSB VCORE REMOTE SENSE
P_VRMVCC_20 VCORE:

8.2KOhm

8.2KOhm
PR1002

PR1003

1KOhm
N/A Vboot = 0V
VID = 0.5V ~ 1.55V +VCORE
20191101 /X /X
ICCMAX = 79A

1
P_VRM_ADDR_PROT_6 ICC_Transient = 69A PJP1034

2
ICC_SlewRate = 601A/us PR1011 100Ohm

140OHM

140OHM

1
PU1000 Loadline = 2.1mOhm 1 2 1 2

PR1005

PR1006

PR1009
2
PM_ADDR : 40h PC1002 P_VCORE_VCC_SE_10 P_VCORE_VSEN_10
I2C_ADDR : 20h
16 28 /X PR1013 0Ohm
GAME#/SV_ADDR/VDDIO PWM1 P_VRM_PWMA_5 7 PWR_FB_SHORTPIN
DGND1 PR1045 0Ohm P_VRM_SV_ADDR_10 1 2

2
36 P_+VCORE_VCC_10

1
1 2 17 29
12,35 H_VIDALERT# SV_ALERT#/SVT PWM2 P_VRM_PWMB_5 7

1
PR1010 49.9Ohm H_VIDALERT#_R PC1007
1 2 18 30 3300PF/25V

1
12,35 H_VIDCLK SV_CLK PWM3 P_VRM_PWMC_5 7

1
PR1001 PC1001 PR1004 10Ohm P_VRM_CLK_10 PR1012 0Ohm

2
845Ohm 0.01UF/16V 1 2 19 31 1 2
12,35 H_VIDDATA SV_DIO PWM4 P_VRM_PWMD_5 7 36 P_+VCORE_VSS_10
1% P_VRM_DAT_10
PJP1035

2
22 32 PR1014 100Ohm

2
ADDR_PROT PWM5
P_VRM_ADDR_PROT_6 1 2 1 2
23 33 P_VCORE_VSS_SE_10 P_VCORE_VRTN_10
SM_ALERT# PWM6
PR1007 0Ohm /X
PWR_FB_SHORTPIN

10PF/50V

10PF/50V
1 2 24 34
72,80 O2_SMB1_DATA SM_DIO PWM7/PWM2_L2 P_VCCGT_PWMB_5 10
DGND1 PR1018 0Ohm PU1000_SMB1_DATA
1 2 25 35 DGND1 GND
72,80 O2_SMB1_CLK SM_CLK PWM8/PWM1_L2 P_VCCGT_PWMA_5 10
PU1000_SMB1_CLK
+VCCST 20 54
VRHOT_ICRIT# ISEN1

PR9743

1
P_VCORE_PROCHOT_4 P_ISEN1_7

1
PC1003

PC1004

1
DGND1 9 55
TSEN1 IRTN1
PC1005 PC1006 P_VRM_TSEN_10 P_IRTN1_7

2
PT1000 PT1001

2
33PF/50V 27 52

140OHM
TSEN2/VAUXSEN ISEN2

2
/X /X 33PF/50V P_VCCGT_TSEN_10 P_ISEN2_7 VCCGT REMOTE SENSE
/X P_VRMVCC_20 5 53
VSEN IRTN2
P_VCORE_VSEN_10 P_IRTN2_7
6 50 +VCCGT
VRTN ISEN3

1
2015.03.19 Remove PR9742 P_VCORE_VRTN_10 P_ISEN3_7

1
PJP1300
DGND1 PR1024 37 51 PR1311 100Ohm
VSEN_L2 IRTN3
4.7KOhm P_VCCGT_VSEN_10 P_IRTN3_7 1 2 1 2
+12V_CPU 36 48 P_VCCGT_VCC_SE_10 P_VCCGT_VSEN_10
/X VRTN_L2 ISEN4
P_VCCGT_VRTN_10 P_ISEN4_7 PWR_FB_SHORTPIN PR1312 0Ohm

2
26 49 1 2
PIN_ALERT# IRTN4 36 P_+VCCGT_VCC_10
PR1124 0Ohm P_VCORE_PIN_10 P_IRTN4_7 /X

1
1 2 21 46 PC1314
VRMPWRGD_5 23,54 6.8KOhm EN ISEN5
VRM_PGD_5 VRMPWRGD_5 P_VRM_EN1_5 3300PF/25V
PR1015 12 47 PR1313 0Ohm
VR_SHDN#/EN_L2/PWROK/CAT_FLT IRTN5

2
PR1020 0Ohm P_VCCGT_EN_5 1 2

2
36 P_+VCCGT_VSS_10
1 2 11 1
12 P_+VCCSA_PG_5 VRDY1 ISEN6 PJP1301
2 VRM_PGD_5 PR1314 100Ohm
PR1091 4 56 1 2 1 2
VRDY2 IRTN6
6.2KOhm P_VCCGT_VSS_SE_10 P_VCCGT_VRTN_10
14 44 DGND1 PWR_FB_SHORTPIN
VINSEN ISEN2_L2/ISEN7
P_VINSEN_10 P_VCCGT_ISEN2_7
1

8 45 /X
I_IN IRTN2_L2/IRTN7
P_VCCGT_IRTN2_7 GND
38 42
1

VCC ISEN1_L2/ISEN8
1

PR1016 PC1008 P_VCCGT_ISEN1_7


1KOhm 1000PF/50V 10
CFILT IRTN1_L2/IRTN8
43
20191218

1
PC1009 PC1010 P_CFILT_S P_VCCGT_IRTN1_7
2

1UF/16V 0.1UF/25V 57 2
2

GND1 RCSP
mbs_c0603 mbs_c0603 P_VRM_RCSP_7

2
P_VRMVCC_20 58 3 P_ISEN_REF_7
GND2 RCSM

1
PC1011 P_VRM_RCSM_7
20190628 LL=1.1 mOhm 1UF/16V 59 40
GND3 RCSP_L2
Loop1 LOADLINE (VCCIN ) DGND1 mbs_c0603 P_VCCGT_RCSP_7

2
60 39
GND4 RCSM_L2 P_VCORE_IOUT1_7 7
PR1017 PC1123 P_VCCGT_RCSM_7 P_ISEN1_7 2 1
1 2 DGND1 61 PR1092 10KOhm
GND5
P_VRM_RCSP_7 1 2 2 1 1 2
P_VCORE_IOUT6_7 7
6.04KOhm 10NF/25V 7 15 P_IRTN1_7 2 1
P_ISEN_REF_7 IMON RBOOT/SV_ADDR
20150421 8.2K->0歐姆 100PF/50V PC1171 PR1104 2.49KOhm PR1093 10KOhm
PJP1000 13 41
NC MODE 20180306 /X /X P_VCORE_IOUT2_7 7
1 2 P_ISEN2_7 2 1
20191023
PR1094 10KOhm
1

SHORT_PIN Ground=Doubler 2 1 1 2
Float=Normal P_VCORE_IOUT7_7 7
PC1012 /X ASP1405I-42T P_IRTN2_7 2 1
VCC=Quad
DGND1 100PF/50V PC1172 PR1105 2.49KOhm PR1095 10KOhm
68PF/50V GND DGND1 VCORE&VCCGT Tsense 20190821 VAX enable
2

/X P_VCORE_IOUT3_7 7
P_ISEN3_7 2 1
+5V PR1096 10KOhm
20150521 ASP1405I-42T P_VCORE_TOUT_7 7,10
2 1 1 2
P_VCORE_IOUT8_7 7
+5V +5V +5V P_IRTN3_7 2 1

2
100PF/50V PC1173 PR1106 2.49KOhm PR1097 10KOhm

1
PR1019 layout check PR1021 PR1315 /X P_VCORE_IOUT4_7 7
1 2 6.49KOhm 5.36KOhm P_ISEN4_7 2 1
1

P_VRM_RCSM_7 PR1034 PR1035 SV_ADDR : 00h PR1098 10KOhm


5.1KOhm 100KOhm 10Ohm GND 2 1 1 2

2
P_VCORE_IOUT9_7 7

1
mbs_r0603 mbs_r0603 P_VRMVCC_20 P_IRTN4_7 2 1
PU1062
P_VRM_TSEN_10 P_VCCGT_TSEN_10 100PF/50V PC1174 PR1107 2.49KOhm PR1099 10KOhm
2

VCORE ; DCLL = 1.1m ohm 13


DCLL=Rtotal/1.3295/8/R_ISEN GND3 /X

1
DCLL=11.59k/1.3295/8/1000 = 1.089m 12 PC1014 PC1301

1
AVPBW=1/(2*3.14*11.59k*68p)=200K GND2
11 P_VRMVCC_20 PR1008 PR1025 100PF/50V PR1304 0.01UF/25V
GND1
10 1 8.2KOhm 10KOhm 1KOhm
VCNTL POK

2
Loop2 LOADLINE (VCCGT ) P_VRMVCC_VCNTL_10 9
EN FB
2 VRM_PGD_5 N/A
P_VRMVCC_EN_10 8 3

2
VIN3 VOUT1

1
7 4
VIN2 VOUT2
6 5 P_VRM_SV_ADDR_10
1

VIN1 VOUT3

1
PR1040 PC1018

1
PR1301 31.6KOHM 33PF/50V PC1019 PC1000 DGND1 DGND1
UP0132PDDA
1 2 mbs_r0603 2 /X 10UF/6.3V 0.01UF/16V

2
2

P_VCCGT_RCSP_7 mbs_c0603 /X
2

2
1

13.7KOhm PR1042 PC1023 20160512改APL5930QBI_TRG


20160616改UP0132PDDA
PC1021 PC1022 49.9KOhm 1UF/16V P_VRMVCC_FB_10
10UF/6.3V 10UF/6.3V mbs_c0603 VCNTL POR 2.7V GND
1

P_VCCGT_IOUT1_7 10
2

mbs_c0603 mbs_c0603 mbs_r0603 VIN POR 0.8V PR9744 P_VCCGT_ISEN1_7 2 1


EN_H=1.4V(min)
1

EN_L=0.8V(max) 10KOhm DGND1 PR1027 10KOhm


IR3535:
1

mbs_r0603 2 1 1 2
Start:3.3V~4.1V P_VRMVCC_20
PC1300 GND GND GND GND P_VCCGT_IRTN1_7
2

Stop:3V~3.8V
27PF/50V 20190815 100PF/50V PC1177 PR1110 2.49KOhm
2

不會走SVID offset功能移除對地電阻
20191030 /X
N/A GND
P_VCCGT_IOUT2_7 10
P_VCCGT_ISEN2_7 2 1

1
PR1023 PR1030 10KOhm
H_PROCHOT# SEQUENCE 2 1 1 2
1KOhm
PR1303 Active Low P_VCCGT_IRTN2_7
1 2 /X 100PF/50V PC1033 PR1031 2.49KOhm

2
P_VCCGT_RCSM_7 /X
18.2KOhm PR1041 0Ohm
2 1 P_VRM_EN1_5
H_PROCHOT# 12,35 20191206 PR1028或PR1029上件,PR1024需/X

1
20191015 P_VCORE_PROCHOT_4 PC1178
/X PR1028 0Ohm PC1013 0.1UF/25V
/X PR1170 0Ohm 1 2 1UF/16V mbs_c0603

2
1 2 P_VCORE_PIN_10 VRM_PGD_5 mbs_c0603
H_THERMTRIP# 35,44
P_VCCGT_EN_5
VCCGT ; DCLL = 3.1m ohm VCORE ; DCLL = 1.1m ohm PR1029 0Ohm
Rtotal=13.7k*2+(47k//10k)=35.65k DCLL=Rtotal/1.3295/8/R_ISEN /X/POWER
DCLL=Rtotal*DCR/8/R_ISEN DCLL=11.59k/1.3295/8/1000 = 1.089m 1 2 DGND1
3.12m ohm=35.65k*0.7m/8/1000 AVPBW=1/(2*3.14*11.59k*68p)=200K 20190730 P_VCORE_PROCHOT_4
DGND1
P_VRM_EN_5 23,72

0Ohm PR1022
2 1
P_+VCCIO_PG_5 12,13

<Variant Name>

Title : VCCIN (IR1405)


ASUSTeK Computer Inc.
Engineer: Cisco Wang
Size Project Name Rev
Custom Maximus XII Extreme R1.01

Date: Thursday, December 19, 2019 Sheet 6 of 157


PC1201 PC1231
PR1201 PR1216
1 2 1 2
P_VCORE_PHASE1_20 P_VCORE_BST1_R_20 1 2 P_VCORE_BST1_20 P_VCORE_PHASE6_20 P_VCORE_BST6_R_20 1 2 P_VCORE_BST6_20
2.2Ohm 2.2Ohm 20191216
0.22UF/25V 0.22UF/25V
mbs_r0603 20191216 mbs_r0603
mbs_c0603 mbs_c0603

PR1202 PR1217
1 2 P_VCORE_PHASE1_20 1 2 P_VCORE_PHASE6_20
+5V +5V
P_VCORE_SW1_VCC_20 P_VCORE_SW6_VCC_20 +12V_CPU
1Ohm 1Ohm

32

32
+5V PUQ1011A +5V PUQ1061A
GND GND
PC1202 2 1
1UF/6.3V 3
VCC
33 PC1232 2 1
1UF/6.3V 3 33 20191216

PHASE
BOOT VCC

PHASE
BOOT
P_VCORE_BST1_20 PJP1011 PWR_FB_SHORTPIN 20191216 P_VCORE_BST6_20 PJP1061 PWR_FB_SHORTPIN
4 1 2 1 4 1 2 1
VDRV VOS VDRV VOS
P_VCORE_VOS1_5 +VCORE P_VCORE_VOS6_5 +VCORE
PL1011 PL1061
34 10 2 1 34 10 2 1
6,7 P_VRM_PWMA_5 6,7 P_VRM_PWMA_5

270UF/16V

270UF/16V

270UF/16V

270UF/16V

270UF/16V

270UF/16V
PWM SW PWM SW
1

1
P_VRM_PWMA_5 P_VCORE_PHASE1_S P_VRM_PWMA_5 P_VCORE_PHASE6_S P_VRM_L+12V_S
35 35

PCE1002

PCE1003

PCE1004

PCE1005

PCE1006

PCE1007
PC1203 0.15UH PUQ1011B PC1233 0.15UH PUQ1061B
+5V EN +5V EN
1UF/6.3V 09016-00361400
5 25 1UF/6.3V 09016-00361400
5 25 20180417

11031V0017F001

11031V0017F001

11031V0017F001

11031V0017F001

11031V0017F001

11031V0017F001
PGND1 VIN1 PGND1 VIN1
2

1
40 48 P_VRM_L+12V_S 40 48 P_VRM_L+12V_S
PGND2 VIN2 PGND2 VIN2
38 36 7 49 38 36 7 49 + + + + + +
6 P_VCORE_IOUT1_7 IOUT TOUT/FLT P_VCORE_TOUT_7 6,7,10 PGND3 VIN3 6 P_VCORE_IOUT6_7 IOUT TOUT/FLT P_VCORE_TOUT_7 6,7,10 PGND3 VIN3
42 50 42 50
PGND4 VIN4 PGND4 VIN4
GND 39 37 43 51 GND 39 37 43 51 DCR=0.27m
P_ISEN_REF_7 REFIN OCSET PGND5 VIN5 P_ISEN_REF_7 REFIN OCSET PGND5 VIN5

2
Isat=25A at100度

1
44 30 PC1204 PC1205 PC1206 44 30 PC1234 PC1235 PC1236
PGND6 VIN6 PGND6 VIN6 5*5
TDA21472 45 31 0.22UF/16V 10UF/16V 10UF/16V TDA21472 45 31 0.22UF/16V 10UF/16V 10UF/16V
PGND7 NC PGND7 NC

2
46 mbs_c0402 mbs_c0805 mbs_c0805 46 mbs_c0402 mbs_c0805 mbs_c0805
PGND8 PGND8

2
PR1215 47 2 PR1231 47 2
PGND9 LGND PGND9 LGND
33KOhm 52 33KOhm 52
PGND10 PGND10
53 53
PGND11 PGND11

PGND14
PGND15

PGND14
PGND15
GATEL1
GATEL2

GATEL1
GATEL2
54 54 Leakage Current=1080uA Leakage Current=320uA
PGND12 PGND12

1
55 GND 55 GND Ripple Current=3800mA Ripple Current=2820mA
PGND13 PGND13 ESR=15m ESR=25m

GND TDA21472 GND GND TDA21472 GND GND

56
57
6
41

56
57
6
41
Iirpple = 4.7041A (Vcore=1.55V, Io=118A)
we use 3.8A*2PCS+2.82A*2PCS = 13.24A
GND GND

GND GND +VCORE

1
+ PCE1011 + PCE1012 + PCE1013 + PCE1016
820UF/3V 820UF/3V 820UF/3V 820UF/3V

2
PC1207
PR1204
1 2 Leakage Current=882uA 20190816空間EE要求
P_VCORE_PHASE2_20 P_VCORE_BST2_R_20 1 2 P_VCORE_BST2_20 Ripple Current=5600mA
GND 20191018 ACDC需求
PC1237 ESR=7m
2.2Ohm 20191216 PR1219 5PCS
0.22UF/25V
1 2
mbs_r0603
mbs_c0603 P_VCORE_PHASE7_20 P_VCORE_BST7_R_20 1 2 P_VCORE_BST7_20
2.2Ohm +VCORE +VCORE
0.22UF/25V
PR1205 mbs_r0603 20191216
1 2 P_VCORE_PHASE2_20 mbs_c0603
+5V
P_VCORE_SW2_VCC_20
1Ohm PR1220
32

1
+5V PUQ1021A 1 2 P_VCORE_PHASE7_20
GND +5V

1
PC1208 2 1
1UF/6.3V 3
VCC
33 20191216 P_VCORE_SW7_VCC_20 PC1079 PC1080 PC1081 PC1082 PC1083 PC1078 PC1059 PC1084 + PCE1014 + PCE1015 + PCE1019 + PCE1018 + PCE1000 + PCE1001 + PCE1008 + PCE1009
PHASE

BOOT
P_VCORE_BST2_20 PJP1021 PWR_FB_SHORTPIN 1Ohm 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 220UF/6.3V 220UF/6.3V 220UF/6.3V 220UF/6.3V 220UF/6.3V 220UF/6.3V 220UF/6.3V 220UF/6.3V

32
4 1 2 1 +5V PUQ1071A N/A N/A
VDRV VOS GND

2
P_VCORE_VOS2_5 +VCORE PC1238 2 1
1UF/6.3V 3 33
VCC

PHASE
BOOT
PL1021 P_VCORE_BST7_20 PJP1071 PWR_FB_SHORTPIN 20191216
34 10 2 1 4 1 2 1
6,7 P_VRM_PWMB_5 PWM SW VDRV VOS
1

P_VRM_PWMB_5 P_VCORE_PHASE2_S P_VCORE_VOS7_5 +VCORE


PC1209
+5V
35
EN
0.15UH PUQ1021B PL1071 20190718 Remove : PC1053~PC1055&PC1079~1082
1UF/6.3V 5 25 34 10 2 1 20190718 Add PCBE1000 & PCBE1001 20190816空間EE要求
09016-00361400 PGND1 VIN1 6,7 P_VRM_PWMB_5 PWM SW
2

40 48

1
P_VRM_L+12V_S P_VRM_PWMB_5 P_VCORE_PHASE7_S
PGND2 VIN2
38
IOUT TOUT/FLT
36 7
PGND3 VIN3
49 PC1239
+5V
35
EN
0.15UH PUQ1071B GND GND 20191218採購建議換料
6 P_VCORE_IOUT2_7 P_VCORE_TOUT_7 6,7,10
42 50 1UF/6.3V 5 25
PGND4 VIN4 09016-00361400 PGND1 VIN1

2
GND 39 37 43 51 40 48 P_VRM_L+12V_S
P_ISEN_REF_7 REFIN OCSET PGND5 VIN5 PGND2 VIN2

1
44 30 PC1210 PC1211 PC1212 38 36 7 49
PGND6 VIN6 6 P_VCORE_IOUT7_7 IOUT TOUT/FLT P_VCORE_TOUT_7 6,7,10 PGND3 VIN3
TDA21472 45 31 0.22UF/16V 10UF/16V 10UF/16V 42 50
PGND7 NC PGND4 VIN4
2

46 mbs_c0402 mbs_c0805 mbs_c0805 GND 39 37 43 51


PGND8 P_ISEN_REF_7 REFIN OCSET PGND5 VIN5

1
PR1221 47 2 44 30 PC1240 PC1241 PC1242 20160413 remove VGD (MP1470) circuit
PGND9 LGND PGND6 VIN6
33KOhm 52 TDA21472 45 31 0.22UF/16V 10UF/16V 10UF/16V
PGND10 PGND7 NC

2
53 46 mbs_c0402 mbs_c0805 mbs_c0805
PGND11 PGND8

2
PGND14
PGND15
GATEL1
GATEL2
54 PR1230 47 2
PGND12 PGND9 LGND
1

55 GND 33KOhm 52
PGND13 PGND10
53
PGND11

PGND14
PGND15
GATEL1
GATEL2
GND TDA21472 GND 54
56
57
6
41
PGND12

1
55 GND
PGND13

GND GND TDA21472 GND

56
57
6
41
GND
GND

20160413 remove 5m ohm Resistor


GND 20180227 PC1068 PC1069刪除

PC1213
PR1207
PC1243
1 2 PR1222
P_VCORE_PHASE3_20 P_VCORE_BST3_R_20 1 2 P_VCORE_BST3_20 1 2
2.2Ohm 20191216 P_VCORE_PHASE8_20 P_VCORE_BST8_R_20 1 2 P_VCORE_BST8_20
0.22UF/25V
mbs_r0603 2.2Ohm
mbs_c0603 0.22UF/25V
mbs_r0603 20191216
mbs_c0603
PR1208
1 2 P_VCORE_PHASE3_20 PR1223
+5V
P_VCORE_SW3_VCC_20 1 2 P_VCORE_PHASE8_20
+5V
1Ohm P_VCORE_SW8_VCC_20
32

+5V PUQ1031A 1Ohm


GND

32
PC1214 2 1
1UF/6.3V 3
VCC
33 20191216 +5V
GND
PUQ1081A
PHASE

BOOT
P_VCORE_BST3_20 PJP1031 PWR_FB_SHORTPIN PC1244 2 1
1UF/6.3V 3 33
VCC

PHASE
BOOT
4
VDRV VOS
1 2 1 P_VCORE_BST8_20 PJP1081 PWR_FB_SHORTPIN 20191216
P_VCORE_VOS3_5 +VCORE 4 1 2 1
VDRV VOS
PL1031 P_VCORE_VOS8_5 +VCORE
34 10 2 1 PL1081
6,7 P_VRM_PWMC_5 PWM SW
1

P_VRM_PWMC_5 P_VCORE_PHASE3_S 34 10 2 1
6,7 P_VRM_PWMC_5 PWM SW

1
PC1215 35 0.15UH PUQ1031B P_VRM_PWMC_5 P_VCORE_PHASE8_S
+5V EN
1UF/6.3V 5 25 PC1245 35 0.15UH PUQ1081B
09016-00361400 PGND1 VIN1 +5V EN
2

40 48 P_VRM_L+12V_S 1UF/6.3V 5 25
PGND2 VIN2 09016-00361400 PGND1 VIN1

2
38 36 7 49 40 48 P_VRM_L+12V_S
6 P_VCORE_IOUT3_7 IOUT TOUT/FLT P_VCORE_TOUT_7 6,7,10 PGND3 VIN3 PGND2 VIN2
42 50 38 36 7 49
PGND4 VIN4 6 P_VCORE_IOUT8_7 IOUT TOUT/FLT P_VCORE_TOUT_7 6,7,10 PGND3 VIN3
GND 39 37 43 51 42 50
P_ISEN_REF_7 REFIN OCSET PGND5 VIN5 PGND4 VIN4
1

44 30 PC1216 PC1217 PC1218 GND 39 37 43 51


PGND6 VIN6 P_ISEN_REF_7 REFIN OCSET PGND5 VIN5

1
TDA21472 45 31 0.22UF/16V 10UF/16V 10UF/16V 44 30 PC1246 PC1247 PC1248
PGND7 NC PGND6 VIN6
2

46 mbs_c0402 mbs_c0805 mbs_c0805 TDA21472 45 31 0.22UF/16V 10UF/16V 10UF/16V


PGND8 PGND7 NC
2

2
PR1224 47 2 46 mbs_c0402 mbs_c0805 mbs_c0805
PGND9 LGND PGND8

2
33KOhm 52 PR1229 47 2
PGND10 PGND9 LGND
53 33KOhm 52
PGND11 PGND10
PGND14
PGND15
GATEL1
GATEL2

54 53
PGND12 PGND11
1

PGND14
PGND15
GATEL1
GATEL2
55 GND 54
PGND13 PGND12

1
55 GND
PGND13
GND TDA21472 GND
56
57
6
41

GND TDA21472 GND

56
57
6
41
GND
GND

GND
GND

PC1219
PR1210
1 2
P_VCORE_PHASE4_20 P_VCORE_BST4_R_20 1 2 P_VCORE_BST4_20
2.2Ohm 20191216
0.22UF/25V
mbs_r0603
mbs_c0603

PC1249
PR1211 PR1225
1 2 P_VCORE_PHASE4_20 1 2
+5V
P_VCORE_SW4_VCC_20 P_VCORE_PHASE9_20 P_VCORE_BST9_R_20 1 2 P_VCORE_BST9_20
1Ohm 2.2Ohm 20191216
0.22UF/25V
32

+5V
GND
PUQ1041A 20191216 mbs_r0603
PC1220 2 1
1UF/6.3V 3 33 mbs_c0603
VCC
PHASE

BOOT
P_VCORE_BST4_20 PJP1041 PWR_FB_SHORTPIN
4 1 2 1 PR1226
VDRV VOS
P_VCORE_VOS4_5 +VCORE 1 2 P_VCORE_PHASE9_20
+5V
PL1041 P_VCORE_SW9_VCC_20
34 10 2 1 1Ohm
6,7 P_VRM_PWMD_5 PWM SW

32
1

P_VRM_PWMD_5 P_VCORE_PHASE4_S +5V PUQ1091A


GND
PC1221
+5V
35
EN
0.15UH PUQ1041B PC1250 2 1
1UF/6.3V 3
VCC
33 20191216

PHASE
BOOT
1UF/6.3V 5 25 P_VCORE_BST9_20 PJP1091 PWR_FB_SHORTPIN
09016-00361400 PGND1 VIN1
2

40 48 P_VRM_L+12V_S 4 1 2 1
PGND2 VIN2 VDRV VOS
38 36 7 49 P_VCORE_VOS9_5 +VCORE
6 P_VCORE_IOUT4_7 IOUT TOUT/FLT P_VCORE_TOUT_7 6,7,10 PGND3 VIN3
42 50 PL1091
PGND4 VIN4
GND 39 37 43 51 34 10 2 1
P_ISEN_REF_7 REFIN OCSET PGND5 VIN5 6,7 P_VRM_PWMD_5 PWM SW
1

44 30
1

PC1222 PC1223 PC1224 P_VRM_PWMD_5 P_VCORE_PHASE9_S


PGND6 VIN6
TDA21472 45 31 0.22UF/16V 10UF/16V 10UF/16V PC1251 35 0.15UH PUQ1091B
PGND7 NC +5V EN
2

46 mbs_c0402 mbs_c0805 mbs_c0805 1UF/6.3V 5 25


PGND8 09016-00361400 PGND1 VIN1
2
2

PR1227 47 2 40 48 P_VRM_L+12V_S
PGND9 LGND PGND2 VIN2
33KOhm 52 38 36 7 49
PGND10 6 P_VCORE_IOUT9_7 IOUT TOUT/FLT P_VCORE_TOUT_7 6,7,10 PGND3 VIN3
53 42 50
PGND11 PGND4 VIN4
PGND14
PGND15
GATEL1
GATEL2

54 GND 39 37 43 51
PGND12 P_ISEN_REF_7 REFIN OCSET PGND5 VIN5
1

1
55 GND 44 30 PC1252 PC1253 PC1254
PGND13 PGND6 VIN6
TDA21472 45 31 0.22UF/16V 10UF/16V 10UF/16V
PGND7 NC
2

GND TDA21472 GND 46 mbs_c0402 mbs_c0805 mbs_c0805


56
57
6
41

PGND8

2
PR1228 47 2
PGND9 LGND
33KOhm 52
PGND10
GND 53
PGND11

PGND14
PGND15
GATEL1
GATEL2
54
PGND12
1

55 GND
PGND13

GND GND TDA21472 GND

56
57
6
41
GND

GND

www.teknisi-indonesia.com

<Variant Name>

Title : VCCIN (IR3555)


ASUSTeK Computer Inc.
Engineer: Cisco Wang
Size Project Name Rev
Custom Maximus XII Extreme R1.01

Date: Thursday, December 19, 2019 Sheet 7 of 157


<Variant Name>

Title : VCORE DRIVER2

ASUSTek COMPUTER INC. Engineer: Mandy


Size Project Name Rev
R1.00
A1 COMET LAKE
Date: Thursday, December 12, 2019 Sheet 8 of 121
<Variant Name>

Title : empty
ASUSTeK Computer Inc.
Engineer:
Size Project Name Rev
A Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 9 of 152


PC1302
PR1305
1 2
PC1308
P_VCCGT_PHASE1_20 P_VCCGT_BST1_R_20 1 2 P_VCCGT_BST1_20 PR1308
2.2Ohm 1 2
0.22UF/25V
mbs_r0603 20191216 P_VCCGT_PHASE2_20 P_VCCGT_BST2_R_20 1 2 P_VCCGT_BST2_20
mbs_c0603 2.2Ohm
0.22UF/25V
mbs_r0603 20191216
PR1306 mbs_c0603
1 2 P_VCCGT_PHASE1_20
+5V
P_VCCGT_SW1_VCC_20 PR1309
1Ohm 1 2 P_VCCGT_PHASE2_20
+5V

32
+5V PUQ1311A P_VCCGT_SW2_VCC_20
GND
PC1303 2 1
1UF/6.3V 3 33 1Ohm

PHASE
VCC BOOT

32
P_VCCGT_BST1_20 PJP1311 PWR_FB_SHORTPIN 20191216 +5V
GND
PUQ1321A
4 1 2 1 PC1309 2 1
1UF/6.3V 3 33

PHASE
VDRV VOS VCC BOOT
P_VCCGT_VOS1_5 +VCCGT P_VCCGT_BST2_20 PJP1321 PWR_FB_SHORTPIN 20191216
PL1311 +12V_CPU 4 1 2 1
VDRV VOS
34 10 2 1 P_VCCGT_VOS2_5 +VCCGT
6 P_VCCGT_PWMA_5 PWM SW
1

P_VCCGT_PWMA_5 P_VCCGT_PHASE1_S PL1321


PC1304 35 0.15UH PUQ1311B 34 10 2 1
+5V EN 6 P_VCCGT_PWMB_5 PWM SW

1
1UF/6.3V 5 25 P_VCCGT_PWMB_5 P_VCCGT_PHASE2_S
09016-00361400 PGND1 VIN1
2

40 48 P_VRM_L+12V_S PC1310 35 0.15UH PUQ1321B


PGND2 VIN2 +5V EN
38 36 7 49 1UF/6.3V 5 25
IOUT TOUT/FLT P_VCORE_TOUT_7 6,7,10 PGND3 VIN3 09016-00361400 PGND1 VIN1

2
6 P_VCCGT_IOUT1_7 42 50 40 48 P_VRM_L+12V_S
PGND4 VIN4 PGND2 VIN2
GND 39 37 43 51 38 36 7 49
P_ISEN_REF_7 REFIN OCSET PGND5 VIN5 6 P_VCCGT_IOUT2_7 IOUT TOUT/FLT P_VCORE_TOUT_7 6,7,10 PGND3 VIN3

1
44 30 PC1305 PC1306 PC1307 42 50
PGND6 VIN6 PGND4 VIN4
TDA21472 20190821 45
PGND7 NC
31 0.22UF/16V 10UF/16V 10UF/16V GND
P_ISEN_REF_7
39
REFIN OCSET
37 43
PGND5 VIN5
51

1
46 mbs_c0402 mbs_c0805 mbs_c0805 44 30 PC1311 PC1312 PC1313
PGND8 PGND6 VIN6

2
47 2 TDA21472 45 31 0.22UF/16V 10UF/16V 10UF/16V
PGND9 LGND PGND7 NC
20191121換MOS對應Tti-state 52
PGND10 20190821 46
PGND8
mbs_c0402 mbs_c0805 mbs_c0805

2
53 47 2
PGND11 PGND9 LGND

PGND14
PGND15
GATEL1
GATEL2
54
PGND12 20191121換MOS對應Tti-state 52
PGND10
+5V 55 GND 53
PGND13 PGND11

PGND14
PGND15
GATEL1
GATEL2
54
PGND12
TDA21472 GND +5V 55 GND

56
57
6
41
PGND13
2

TDA21472 GND

56
57
6
41
PR1300 GND

2
8.2KOHM
PR1307 GND
/X 8.2KOHM
1

GND
/X

1
P_VCCGT_PWMA_5 GND
2

P_VCCGT_PWMB_5
PR1302

2
4.22KOHM
PR1310
/X 4.22KOHM
1

/X

1
GND

GND

+VCCGT

1
+ PCE1300 + PCE1301 + PCE1302 + PCE1303 + PCE1304 + PCE1305 + PCE1306 + PCE1307
220UF/6.3V 220UF/6.3V 220UF/6.3V 220UF/6.3V 220UF/6.3V 220UF/6.3V 220UF/6.3V 220UF/6.3V

2
20190816空間EE要求
GND
20191218採購建議換料

2015.03.25 Remove PC7004, PC7005, PC7007, PC7008, PC7011, PCB7033 for layout routing

+VCCGT

1
PC1325 PC1326 PC1327 PC1328 PC1329 PC1330
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603

2
/X /X /X

<Variant Name>

Socket Bottm 9PCS Title : VCCGT


GND

ASUSTeK Computer Inc.


Engineer:
Size Project Name Rev
Custom Maximus XII Extreme R1.01

Date: Thursday, December 19, 2019 Sheet 10 of 157


<Variant Name>

Title : empty
ASUSTeK Computer Inc.
Engineer:
Size Project Name Rev
A Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 11 of 152


1212
/X 20191029 EE需新增3933
PJP1501 PWR_FB_SHORTPIN PR1504 100Ohm
1 2
P_VCCSA_RGND_L_10 2
PR1503 1 P_VCCSA_RGND_10 PR1513
1 2
13,36 VSS_SA_PCIE_IO_SENSE_10 80 P_VCCSA_3933_OV_10
2 1

1
GND 0Ohm PC1507 0Ohm
1000PF/50V
1028 PR1507 0Ohm

2
36 P_+VCCSA_VCC_10
2 1
1129 LL=4mohm
+VCCSA PR1502 100Ohm P_VCCSA_FB_R1_10
1 2 PR1509 1KOhm PR1508 10KOhm PR1512
P_VCCSA_VSEN_H_10 2 1 P_VCCSA_VSEN_10
1127 1 2 1 2 1 2
PJP1500 PWR_FB_SHORTPIN /X
34.8kOhm
1030
PC1508 220PF/50V PC1525 68PF/50V
2 1 2 1
1028 P_VCCSA_FB_10
PR1510 P_VCCSA_VREF_20
1 2 P_VCCSA_COMP_10
H_PROCHOT# P_VCCSA_VRHOT#_10
1218

1
+5V
/X 0Ohm PR1511 PR1516 PR1517
1212

1
1 2 PR1520 30KOHM 143KOhm +5VDUAL_AUX +5VDUAL_AUX
54.9KOhm

1
1
PC1524 0Ohm PR1518

P_VCCSA_RGND_10
P_VCCSA_VSEN_10

2
1

1
P_VCCSA_SET1_10
P_VCCSA_SET2_10
P_VCCSA_SET3_10
PR1532 SGND 1000PF/50V 47KOhm PR1519

2
/X
2.2OHM /X 47KOhm

1
PR1528
2
mbs_r0805 P_VCCSA_SET3_H_10 P_VCCSA_SET2_H_10 P_VCCSA_SET2_H2_10 PR1514 PR1525
1028 SGND 1030

1
0.1UF/16V
3

3
+VCCST 5% PR1521
1218 100KOhm 100KOhm

1
D

2
P_VCCSA_TSEN_SET_H_10 475Ohm PR1523

PC1519
PR1526

PR1527

2
SGND PR1522 PQ1503

21KOhm
68Ohm

2
PR1530

2
4.7Ohm PR1524 P_VCCSA_SET1_H_10 H2N7002 11

2
1
PC1520 PU1501 mbs_r0603 PR1529 N/A G
1101 820Ohm

2
2
S

33
32
31
30
29
28
27
26
25
24
23
22
2

3
4.7UF/6.3V 33Ohm PQ1509B
140OHM

140OHM

2
2

1
2

6
PQ1509A 2N7002KDW

140OHM

GND5
GND4
GND3
GND2
GND1
SET1
SET2
SET3
VSEN
FB
COMP
RGND

1
PR1531 P_VCCSA_VREF_R_20 P_VCCSA_SET3_10 P_VCCSA_SET2_10 2N7002KDW 5

2
O2_CPU_ID_10 35,72

1
1KOhm SGND P_VCCSA_TSEN_SET_10 2

4
2
/X SGND 1 21 PC1526 PTR1500 P_VCCSA_SET1_10

1
VCC ISENN

1
1

2
P_VCCSA_VCC_20 2 20 P_VCCSA_ISENN_10 0.47UF/16V PR1533
1028

1
EN ISENP
1

2
P_VCCSA_EN_10 3 19 P_VCCSA_ISENP_10 100KOhm PR1536 PR1537 PR1534 PR1538 PR1539
VR_HOT# PSYS
1 2 P_VCCSA_VRHOT#_10 4 18 P_VCCSA_PSYS_10 120KOhm 14.3KOhm 33Ohm 24kOhm 27.4kOHM 130KOhm GND GND
VDIO IMON
H_VIDDATA 1
PR1535 2
10Ohm P_SVID_VCCSA_DATA 5 17 P_VCCSA_IMON_10 SGND

2
ALERT# VREF

1
H_VIDALERT# 1
PR1540 0Ohm2 /X P_SVID_VCCSA_ALERT# 6 16 P_VCCSA_VREF_20

2
VCLK TSEN

1
H_VIDCLK PR1541 49.9Ohm P_SVID_VCCSA_CLK 7 15 P_VCCSA_TSEN_10
VR_READY# DRVEN
3

3
PC1512 P_+VCCSA_PG_5 P_VCCSA_OD#_10 P_VCCSA_SET1_L_10 P_VCCSA_SET3_L_10 P_VCCSA_SET2_L_10
1212

1
D
1

PC1511 PC1517 P_VCCSA_TSEN_SET_L_10 PR1542 PR1543 PR1544

PHASE
UGATE

LGATE
2

BOOT

PVCC

PWM
+12V_CPU PQ1504
15KOhm 270Ohm 68Ohm

1
VIN
+5V 11
33PF/50V 47PF/50V 22PF/50V PR1545 H2N7002
1

P_+VCCSA_PG_5 6
2

/X /X RT3601EAGQW 169OHM G P_CPU_ID_VCCSA_10

8
9
10
11
12
13
14

2
S
2

2
2
PR1548

2
PQ1501
PR1547 2.2OHM
1212 PZD502CMA 1213 mbs_r0805
SGND SGND SGND
SGND SGND 0Ohm
mbs_r0603 P_VCCSA_PWM_10
1028 +12V_CPU
SGND SGND SGND

2
1
3 S
2D

H_VIDALERT# 2 3 P_SVID_VCCSA_ALERT# P_VCCSA_PVCC_20

NTMFS4C10NBT1G

NTMFS4C10NBT1G
1
PC1523 P_VCCSA_VIN_20
2.2UF/6.3V PC1510 P_VRM_L+12V_S
2 0.22UF/25V
G
1 1

2
mbs_c0603
SGND

PQ1505

PQ1506
5

5
D D

1
SGND 5% PC1515 PC1516 PC1501
P_CPU_ID_VCCSA_10 PR1551 1Ohm 10UF/16V 10UF/16V 1UF/16V
4 4 mbs_c0805 mbs_c0805 mbs_c0603

2
P_VCCSA_UGATE_20 P_VCCSA_UGATE_M_20 G S G S
mbs_r0603
Leakage Current=1080uA

1
2
3

1
2
3
Ripple Current=3800mA

1
PU1500 GND PC1522
ESR=15m
11 470PF/16V GND
1028 GND4
10 mbs_c0603
GND GND
+VCCSA
GND3
1.05V (11A)

2
9 PR1501 1Ohm mbs_r0603 PC1502 0.1UF/16V mbs_c0603 MLCC/+/-5%
GND2
+12V_CPU P_VCCSA_PWM_10
1
2
PWM BOOT
8
7 P_VCCSA_BOOT_20 5% P_VCCSA_BOOT_R_20
2 1
PL1502
RKL (22A)
GND1 UGATE
3 6 P_VCCSA_UGATE_20 1 2
NC PHASE
P_VCCSA_OD#_10 4 5 P_VCCSA_PHASE_20
VCC LGATE

NTMFS4C06NBT1G

NTMFS4C06NBT1G
P_VCCSA_DR_VCC_20 P_VCCSA_LGATE_20 1UH
RT9624FGQW
GND

1
PL1501

1
PR1500 1 2 + PCE1502 + PCE1503

PWR_FB_SHORTPIN

PWR_FB_SHORTPIN
PJP1503

PJP1505
1 2 PC1506 PC1503 PC1504

PWR_FB_SHORTPIN

PWR_FB_SHORTPIN
PJP1506

PJP1502
20191105 560UF/6.3V 560UF/6.3V

PQ1502

PQ1507
4700PF/50V 1UH 11031V0004F601 11031V0004F601 22UF/6.3V 22UF/6.3V

5
D D

2
2.2OHM mbs_c0603 mbs_c0603 mbs_c0603
1

mbs_r0805
PC1500 4 4 P_VCCSA_SNB

1
1UF/16V P_VCCSA_LGATE_20 G S G S /X /X

1
2

mbs_c0603 PR1505 /X /X

1
PC1509 PC1514 1Ohm

1
2
3

1
2
3
2200PF/50V 2200PF/50V mbs_r1206
GND /X /X 5% GND

2
2

2
1028

2
PR1555 PR1558
PC1518 1031
H_PROCHOT# 6,35 GND GND GND GND GND
1 2 1 2 2 1

H_VIDCLK 6,35
2.74KOhm 2.74KOhm
0.1UF/16V
H_VIDDATA 6,35

H_VIDALERT# 6,35 PTR1501


PR1556

PC1521 P_VCCSA_ISENP_10 1 2 2 1
2 1
1KOhm 10KOHM

0.01UF/16V
PR1557
PJP1504 1 2
1 2
1218 LL=4mohm 3KOHM
SHORT_PIN
/X
GND SGND P_VCCSA_ISENN_10

1212

P_VCCSA_TSEN_SET_10
20191030

2
PR1515 2 +3VSB PR1552 +3VSB
10KOhm PR1550 51KOhm
1 2 84.5KOhm
6,13 P_+VCCIO_PG_5
P_VCCSA_EN_10

1
1

1
1

PR1553 PR1554
100KOhm 100KOhm

3 3
3

3
2

2
D D

PQ1510 PQ1511
H2N7002 11 H2N7002 11
P_VCCSA_VBOOT1_5 13,35,80 P_VCCSA_VBOOT2_5 13,35,80
N/A G N/A G
S S
2 2
1.2V VBOOT 1.05V VBOOT
2

2
GND GND

<Variant Name>
請確認是否Default high push pull Title : VCCSA
ASUSTek COMPUTER INC.
Engineer: Mandy_cao
Size Project Name Rev
A2 coffeelake demo R1.00

Date: Thursday, December 19, 2019 Sheet 12 of 121


+12V

PL1600
+3V 1 2
VCCIO_0 P_+12V_REGIN_S
35Ohm/100Mhz

1
PC1602 PC1603 PC1613
+5V 10UF/16V 10UF/16V 10UF/16V + PCE1607 + PCE1603
0701 mbs_c0805 mbs_c0805 mbs_c0805 100UF/16V 100UF/16V

2
1

2
PR1636 20190814
10KOhm 重複pull high移除PR1634、PR1674
+VCCIO_0_VCC_10

1
PR1630 PC1628

2
0Ohm 5% 1UF/6.3V GND
/X 20190808空間需求 20190829 layout需求

2
P_+VCCIO_0_EN_5 17,23,72
CPU_VCCIO_PWR_GATEB_10 1 2

5
mbs_c0603
D
20190820 PQ1600
PU1600 PEA16BA

0.1UF/16V PC1616
1
PC1615 GND 9 6 4
VCC UGATE
1UF/6.3V VCCIO_0_UG_20 PR1638 0Ohm G S
/X 2 5 1 2
PGOOD BOOT

2
P_+VCCIO_PG_5 VCCIO_0_BT_20 5% VCCIO_0_BT_R_20
mbs_r0603

1
2
3
1
+VCCIO_0

1
3 7 PR1631
EN PHASE
P_+VCCIO_0_EN_5 8 VCCIO_0_VSW_20 8.2KOhm PL1610
LGATE
20191008 OCP調整 1 VCCIO_0_LG_20 mbs_r0603 0.33UH 2019.07.16 By Emma
MODE

2
VCCIO_0_G0_MODE_10 4 Irat=25A

2
LPM#
PR1635 CPU_VCCIO_PWR_GATEB_10 1 2
GND OCP = 19A +1.8V_A +3VSB +3VSB +1.8V_A
1 2 14 12
CS RGND
VCCIO_0_CS_10 13 VCCIO_0_RGND_10
FB
62KOhm 15 VCCIO_0_FB_10
GND1
16 10

5
GND2 G0 D D

1
17 11 VCCIO_0_G0_MODE_10 PQ1601 PQ1617 PC1617

1
GND3 G1

1
VCCIO_0_G1_10 PEA16BA PEA16BA 1000PF/50V PC1608 PC1612 PC1631 PC1632 + PCE1602 PR1680 PR1686
RT6541AGQW 4 4 mbs_c0603 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 560UF/6.3V 8.2KOhm 100KOhm

2
G S G S mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603 11031V0004F601 /X

1
2

2
20191213 GND GND PR1679

2
1
VCCIO_0_SNB_S
20190422 PR1676 33KOhm

1
2
3

1
2
3
CPU_VCCIO_PWR_GATEB_10 30
+3V +3V 8.2KOhm

1
+3V PR1639 3

3
D

1
PC1633 1Ohm 5%

2
1
2200PF/50V PC1635 mbs_r1206 PQ1616
/X 2200PF/50V 11 H2N7002

2
2
/X G
1

1
S

2
PR1668 PR1623 PR1627 PR1678 3 2
GND

2
1
100KOhm 100KOhm 100KOhm PR1664 +VCCIO_0 10KOhm C
PR1600 1 B PMBS3904
1KOhm 1 2
51 CPU_C10_GATE_N_10
2 1 PQ1615
2

2
CPU_ID_10 E
GND GND

2
VCCIO_0_G1_10 VCCIO_0_G0_MODE_10 2
0Ohm
3 20190814 /X
C10 GATE LEVEL SHIFTER
3

1
D
由CPU_ID控電壓移除PR1624、PR1626、PR1628 +VCCIO_0

2
PJP1601 PR1629
MODE跟G0共用pull high +VCCIO_0_REF_3933_10 80
PQ1619 PR1643 PR1642 PR1640 PWR_FB_SHORTPIN 100Ohm
11 H2N7002 0Ohm 0Ohm 100Ohm /X mbs_r0603 GND GND
CPU_ID_N_10 G

2
S
2 /X /X 2 1 VCCIO_0_VO_10 1 2
2

1
3
3

1
D
PR1659
PQ1604 PQ1606A 1KOhm

6
PR1601
11 H2N7002 2N7002KDW
12,13,35,72 CPU_ID_10
G 2 1 2 /X

2
S 46,72 GPP_F_22
2 GPIO1_VCCIO_0_G_10
2

1
2
GND 20190820
0Ohm

1
PC1601 PR1603 GND
VCCIO_0_SENSE_10 36
+3V +3VSB /X 2200PF/50V 20KOhm VCCIO_0_FB_R_10
/X

2
GND /X

1
VSS_SA_PCIE_IO_SENSE_10 12,36
PQ1606B

3
PR1602
GND GND GND 2N7002KDW
1

1
+3VSB PR1662 PR1661 2 1 5 /X
46,72 GPP_F_23
8.2KOhm 8.2KOhm GPIO2_VCCIO_0_G_10

4
2
0Ohm

1
/X PC1604 PR1604 PJP1602
2

2
/X 2200PF/50V 20KOhm PR1641 PWR_FB_SHORTPIN
P_+VCCIO_1_2_EN_5 23
/X GND 100Ohm /X
1

2
PR1658 /X

1
8.2KOhm 2 1 1 2 +3V
3
2019.07.18 By Emma
3

12,13,35,72 CPU_ID_10 D
GND GND
2

PQ1607 GND
11 H2N7002

1
G PR1665
2
S 20191108 add GPIO to change +VCCIO_0 voltage for RKL-S 1KOhm
2

VCCIO_1_2

2
6

PQ1605A
2 2N7002KDW P_+12V_REGIN_S
0705
1

1
GND PC1619 PC1621 PC1614
P_+VCCIO_PG_5 6,12
+3V +5V 10UF/16V 10UF/16V 10UF/16V + PCE1606 + PCE1608 P_+VCCIO_PG_5
mbs_c0805 mbs_c0805 mbs_c0805 100UF/16V 100UF/16V

2
+VCCIO_1_2_VCC_10 +3VSB_ATX

1
PC1618
1UF/6.3V GND
1

PR1650 20190829 layout需求


3

2
PQ1605B 100KOhm
5 2N7002KDW 20190808空間需求

1
D
P_+VCCIO_0_EN_5 PQ1602 PR1666
4

PU1601 PEA16BA 100KOhm

0.1UF/16V PC1630
GND 9 6 4
VCC UGATE
VCCIO_1_2_UG_20 PR1654 0Ohm G S

2
2 5 1 2

3
mbs_c0603
PGOOD BOOT
VCCIO_1_2_PG_5 VCCIO_1_2_BT_20 5% VCCIO_1_2_BT_R_20
mbs_r0603 PQ1611B

1
2
3
1
+VCCIO_1_2

1
3 7 PR1632 5 2N7002KDW
20190814 LPM共用CPU_VCCIO_PWR_GATEB_10 EN PHASE
P_+VCCIO_1_2_EN_5 8 VCCIO_1_2_VSW_20 8.2KOhm PL1620

4
LGATE
1 VCCIO_1_2_LG_20 mbs_r0603 0.33UH
MODE

2
VCCIO_1_2_G1_MODE_10 4 Irat=25A
20191008 OCP調整

2
LPM#
PR1652 CPU_VCCIO_PWR_GATEB_10 1 2
1 2 14 12 3
GND OCP = 19A

6
CS RGND D
VCCIO_1_2_CS_10 13 PQ1611A
FB
62KOhm 15 VCCIO_1_2_FB_10 PQ1610 2 2N7002KDW
GND1
16 10 11 H2N7002 VCCIO_1_2_PG_5

1
5

5
GND2 G0 D D

1
17 11 VCCIO_1_2_G0_10 PQ1603 PQ1618 PC1623 CPU_ID_N_10 G
GND3 G1 S

1
VCCIO_1_2_G1_MODE_10 PEA16BA PEA16BA 1000PF/50V PC1624 PC1625 PC1626 PC1627 + PCE1604 2

2
RT6541AGQW 4 4 mbs_c0603 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 560UF/6.3V

2
G S G S mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603 11031V0004F601

2
GND GND GND
VCCIO_1_2_SNB_S

1
2
3

1
2
3
+3V

1
1
20190820 PC1634 PR1655
PR1670 0Ohm 2200PF/50V 1Ohm 5%

1
/X PC1636 mbs_r1206 GND GND
80 +VCCIO_1_2_REF_3933_10

2
1 2 2200PF/50V

2
N/A /X
1

2
PR1669 +VCCIO_1_2
GND

1
100KOhm PR1677
1KOhm
GND
2

GND
VCCIO_1_2_G1_MODE_10 2

1
PR1681
20190814 PJP1603 +VCCIO_1_2 100Ohm
由CPU_ID控EN移除PR1645、PR1646、PR1649 PR1656 PWR_FB_SHORTPIN mbs_r0603
PR1647移除改直接接地 100Ohm /X

2
MODE跟G1共用pull high
2 1 VCCIO_1_2_VO_10 1 2

PR1657
0Ohm 5%
VCCIO_1_2_SENSE_10 36
VCCIO_1_2_FB_R_10 1 2
GND
1

PR1660
1KOhm
/X
2

GND

<Variant Name>

Title : VCCIO(RT6541)
ASUSTeK Computer Inc.
Engineer: Cisco Wang
Size Project Name Rev
A1 Maximus XII Extreme R1.01

Date: Monday, December 16, 2019 Sheet 13 of 152


<Variant Name>

Title : empty
ASUSTeK Computer Inc.
Engineer:
Size Project Name Rev
A2 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 14 of 152


<Variant Name>

Title : empty
ASUSTeK Computer Inc.
Engineer:
Size Project Name Rev
A Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 15 of 152


2019.07.18 By Emma
+VCCIO_0 +VCCSA +VDDQ
1

1
PCB1601 PCB1602 PCB1603 PCB1604 PCB1607 PCB1501 PCB1502 PCB1503 PCB1504 PCB1505
47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V

1
mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 PCB2000
2

2
47UF/4V
mbs_c0805

2
GND GND

+VCCIO_1_2
GND
1

1
PCB1621 PCB1622 PCB1623 PCB1624 PCB1626 PCB1627
47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V
mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805
2

2
GND

20190702

+VCORE www.teknisi-indonesia.com
1

1
PCB1003 PCB1004 PCB1005 PCB1008 PCB1009 PCB1010 PCB1011 PCB1014 PCB1015 PCB1016 PCB1017
PCB1001 PCB1002 47UF/4V 47UF/4V 47UF/4V PCB1006 PCB1007 47UF/4V 47UF/4V 47UF/4V 47UF/4V PCB1012 PCB1013 47UF/4V 47UF/4V 47UF/4V 47UF/4V PCB1018
100UF/4V 100UF/4V mbs_c0805 mbs_c0805 mbs_c0805 100UF/4V 100UF/4V mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 100UF/4V 100UF/4V mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 100UF/4V
2

2
GND

+VCORE
1

1
PCB1020 PCB1021 PCB1022 PCB1023 PCB1024 PCB1026 PCB1027 PCB1028 PCB1029 PCB1030 PCB1032 PCB1033 PCB1034 PCB1035 PCB1036
PCB1019 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V PCB1025 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V PCB1031 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V
100UF/4V mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 100UF/4V mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 100UF/4V mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805
2

2
GND

+VCORE
1

PCB1037 PCB1038 PCB1039 PCB1040 PCB1041 PCB1042


100UF/4V 100UF/4V 100UF/4V 100UF/4V 100UF/4V 100UF/4V
2

GND

+VCCGT
1

1
PCB1044 PCB1045 PCB1046 PCB1047 PCB1048 PCB1049 PCB1050 PCB1051 PCB1052 PCB1053 PCB1054 PCB1055 PCB1056 PCB1057 PCB1058
47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V 47UF/4V
mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805 mbs_c0805
2

GND

20190702 for GT, TOP*4, BOT*7

<Variant Name>

Title : VCORE MLCC&CAP


ASUSTeK Computer Inc.
Engineer: Miles Liu
Size Project Name Rev
Custom Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 16 of 152


+5VDUAL_AUX

Irms,cin=Io(D(1-D))^0.5
PL2001
1 2

11031V0004F601
PCE2001
P_VDDQ_REGIN_S
35Ohm/100Mhz

+12V

560UF/6.3V
1
5
D

1
PD2000 PQ2011 +
1 PEA16BA PC2001 PC2038
3 4 10UF/16V 10UF/16V

2
2 P_VDDQ_VCC_P_20 P_VDDQ_UGATE_M_20 G S

2
BAT54CW

1
2
3
PR2002
8.2KOhm +VDDQ
mbs_r0603

2
1.2V

1
PR2000 GND 空間需求
2.2Ohm PL2011
1 2
s_r0805_h24 5%

1
0.33UH
PC2002
PC2003 4700PF/50V

P_VDDQ_SNB
2
PR2003 mbs_c0603
2 1

1
P_VDDQ_BOOT_R_20
1009 OCP=24A

1
1Ohm mbs_r0603 + PCE2013 + PCE2011 + PCE2012

5
0.1UF/16V mbs_c0603 D D
5% PQ2012 PQ2014 470UF/4V 470UF/4V 470UF/4V PC2004

1
PEA16BA PEA16BA PR2006 10UF/6.3V

2
4 4 1Ohm mbs_c0603
P_VDDQ_BOOT_20 G S G S mbs_r1206
0308

2
5%

2
PU2011 PR2007

1
2
3

1
2
3
13 8.2KOhm
GND3
12 mbs_r0603 +3VSB_ATX
GND2
11 GND
GND1

1
10 1 GND GND
REFOUT BOOT

1
1 2 P_VDDQ_REFOUT_10 9 2 PC2214

1
OFS UGATE
P_VDDQ_OFS_10 8 3 P_VDDQ_UGATE_20 2200PF/50V GND PC2215 +5VSB_ATX PR2216
POK PHASE GND
PR2008 0Ohm P_+VDDQ_PG_5 7 4 P_VDDQ_PHASE_20 GND /X 680PF/50V 1KOhm
COMP LGATE/OCSET

2
/X 6 5 P_VDDQ_LGATE_20
FB VCC
1

GND PC2005 P_VDDQ_VCC_20

2
PR2009 PJP2001
1000PF/50V PC2006 APW8723AQBI-TRG GND GND

1
0.1UF/16V 1 2 1 2 PR2017 P_+VDDQ_PG_5
2

P_VDDQ_FB_10 P_VDDQ_FB_shortpin 3.24KOhm


3.24KOhm
PWR_FB_SHORTPIN
PQ2015A

6
PC2008 PR2012
/X
1

GND GND PR2010 PC2007 2N7002KDW


1 2 PC2000 1 2 2
P_+VDDQ_EN_5

P_VDDQ_FB_R_10 1 2 1UF/16V 1 2 P_VDDQ_FB_C_10 +VDDQ +VDDQ_power_off_gate_4

1
2

1104 解干擾 10KOhm 0.01UF/16V mbs_c0603


2200PF/50V 0Ohm 3
PC2009 PR2016 C
1 2 1 B PQ2017
1 2 GND +VDDQ_Close_4 PMBS3904 GND
E

1
PC2017
33PF/50V 2KOhm 2
1UF/6.3V
P_+VCCIO_0_EN_5 13,23,72

2
GND

GND GND

PQ2015B

3
2N7002KDW
PR222
5
1 2

4
72 O2_VDDQ_VREF
+VDDQ_VREF P_VDDQ_OFS_10

0Ohm

1229
GND

+VDDQ

1113 EE需求
2

PR2102
10KOhm
PR2104
/X
0Ohm
0308
1

N/A

VDDQ ===> VTT_DDR


72 P_+VTTDDR_REFIN_10
1 2 P_VTT_DDR_REFIN_10
combine RT9040
Io:0.75A
+3V_S0IX +5VDUAL_AUX
2

SIO 控制P_+VDDQ_EN_5 需使用OPEN DRAIN 訊號


1

PR2103 PC2111
10KOhm 0.1UF/16V PR2100
1

PR2101
/X P_+VDDQ_EN_5 18,66
2

8.2KOhm 10Ohm P_+VDDQ_EN_5


1

PU2101 5%
+VDDQ +VTTDDR 13 mbs_r0603 P_+VDDQ_EN_5
2

GND4
12 3

3
GND3 D
11
GND2
GND 1 10 PQ2016
REFIN VCNTL
2 9 P_VTT_DDR_CTRL_10 11 H2N7002
VIN PGOOD 23,26 P_Bleed_cut_5
3 8 G
VOUT GND1 S
1

4 7 2
0412

2
PGND EN
1

PC2104 PC2105 5 6 P_VTT_DDR_EN_10 PC2100


VSENSE REFOUT
10UF/6.3V 10UF/6.3V PC2101 PC2102 PC2103 P_VTT_DDR_REOUT_10 4.7UF/6.3V
2
P_VTT_DDR_VOSNS_10

mbs_c0603 mbs_c0603 22UF/6.3V 22UF/6.3V 22UF/6.3V UP8815PDDA mbs_c0603


2

mbs_c0603 mbs_c0603 mbs_c0603 mbs_dfn_10p_s118_p_2v_half PC2107


/X
0.1UF/16V GND
1

0724
2

GND
GND GND GND GND GND GND
PJP2100
PWR_FB_SHORTPIN GND
2

/X GND

P_+VTTDDR_EN_5 23
1

PC2112 +VDDQ
0.1UF/16V

10UF/6.3V

10UF/6.3V

10UF/6.3V

10UF/6.3V
0715
2

GND

PC2034

PC2035

PC2036

PC2037
1

1
0305 2

2
mbs_c0603

mbs_c0603

mbs_c0603

mbs_c0603
GND
<Variant Name>

Title : 1.2VDUAL

ASUSTek COMPUTER INC.


Engineer: RAY
Size Project Name Rev
A2 H370-PLUS R1.00

Date: Thursday, December 12, 2019 Sheet 17 of 102


+VPPDDR

+5VDUAL_AUX +5VDUAL_AUX

1
PC2201

P_+VPPDDR_PVCC_10
1UF/25V

1
2
mbs_c0603 PR2201

2
PR2200 47KOhm
1031 VIN UVLO=3.55V ~4.15V N/A
200KOhm
mbs_r0603 GND

2
PU2200

1
9 3 PR2202
VIN1 PVCC
10 5 1 2
VIN2 PGOOD P_+VDDQ_EN_5 17,66
VEN min=2V 8 P_+VPPDDR_PG_5 0Ohm /X
Iq=0.7mA 1
BOOT
7 P_+VPPDDR_Boot_10
+2.51V
EN SW2

1
P_+VPPDDR_EN_5 4 6 PC2202
SS SW1
+VPPDDR

P_+VPPDDR_SS_10
11 2 0.1UF/16V
GND3 FB

P_+VPPDDR_FB_10
12 mbs_c0603
GND4 0715

2
2
13 PL2200
GND5

1
PR2203 PC2203 PC2204 1 2
200KOhm 0.1UF/16V 0.047UF/16V P_+VPPDDR_SW_S
RT7276GQW
1

PC2206 /X 700KHz 2.2UH

2
PC2200 PC2205 0.1UF/16V FB=0.765V
1

10UF/16V 10UF/16V mbs_c0603 HG Rds=90m


2

LG Rds=60m

1
mbs_c0805 mbs_c0805 PC2207 PC2208 PC2209 PC2210

1
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
0725 PC2213 /X mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603

2
GND GND GND GND GND GND GND 2 1
P_+VPPDDR_SENSE_10 PJP2201
22PF/50V PWR_FB_SHORTPIN

2
/X
PR2206
PR2204
1 2 1 2
GND GND GND GND
49.9KOhm

1
66 P_+VPPDDR_EN_5 499Ohm
P_+VPPDDR_EN_5
PR2205
22KOhm PR2209 0Ohm
1 2

2
P_+VPPDDR_TEST_3933 80

GND

+5VSB_ATX

0308

P_+VDDQ_EN_5 66 P_+VPPDDR_PG_5 P_+VPPDDR_PG_5


2

PR2212
33KOhm
3
3

D
1

PQ2201
+VPPDDR 11 H2N7002
G
S
3 2
0720
2

PR2214 C
1 2 1 B PQ2200
PMBS3904
0412
E N/A
2

10KOhm PC2212
PR2215 1UF/10V 2

1% 6.2KOhm /X
2
1

1% 180108 dual
GND

GND GND GND

防止 PG彈跳

<Variant Name>

Title : +VPPDDR(TR8125D)
ASUSTek Computer Inc.
Engineer: Miles Liu
Size Project Name Rev
A3 BMWB180 1.01

Date: Thursday, December 12, 2019 Sheet 18 of 129


<Variant Name>

Title :
ASUSTek COMPUTER INC.
Engineer:
Size Project Name Rev
A3 R1.01

Date: Thursday, December 12, 2019 Sheet 4 of 119


180102

+1.05V_A_IN 66

O1JP11

1 2
20170209 update +1.05V_A_IN

PC3005 PWR_FB_SHORTPIN
/X
P_+1.05VAUX_PCH_BST_25 1 2

1UF/16V
+1.05V_A
+5VDUAL_AUX Iin =2.965A mbs_c0603 DCR=3.5mΩ, Isat=25A
1.05V/15A
PL3000 PU3000 MPQ8633BGLE-Z PL3010
OCP=19A

11031V0004F601

11031V0004F601
560UF/6.3V PCE3001

560UF/6.3V PCE3002
1 2 10 20 1 2

BST
VIN1 SW
21 P_+1.05VAUX_PCH_PH_S
VIN2
35Ohm/100Mhz 0.33UH

1
09016-00331200
8 PC3008 PC3013 PC3010 PC3011
EN

1
P_+1.05V_A_EN_10 9 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V

1
PGOOD

2
1

1
P_+1.05V_A_PG_10 19 7 + +
VCC FB
PC3022 PC3024 PC3012 PC3009 PC3014 P_+1.05VAUX_PCH_VCC_15 P_+1.05VAUX_PCH_FB_10
22UF/16V 22UF/16V 22UF/16V 22UF/16V 1UF/16V
2

2
4 6 GND GND GND GND PJP3000
mbs_c0603 MODE RGND
s_c1206_h71 s_c1206_h71 s_c1206_h71 s_c1206_h71 P_+1.05VAUX_PCH_RTN_10 PWR_FB_SHORTPIN

2
3 5 /X
CS TRK/REF

P_+1.05VAUX_PCH_MODE_10

P_+1.05VAUX_PCH_CS_10

PGND

AGND
PC3006
GND GND GND GND GND GND

1
2 1
PC3007 P_+1.05VAUX_PCH_SEN_10

11

2
0.1UF/16V

2
2200PF/50V
P_+1.05V_A_PG_10
/X

PR3000 PR3013 PR3005 PR3009 PR3014


VCC = 3.0V PR3018 1KOhm
1 2 1 2 1 2 1 2
53,66,72,73 O_RSMRST# VCCMPHY_SENSE 48
2 1 2 1 20191007 P_+1.05VAUX_PCH_VREF_10
0Ohm GND
0Ohm 3KOHM 499Ohm 0Ohm

2
/X PR3046 0Ohm

1
PR3010 PR3007 PR3011 Rtop 1 2
+1.05V_A_VREF_3933 80

1
0Ohm 6.65KOhm 2KOhm
PC3000 PC3001
10UF/16V Mode Current Limit 0.1UF/16V Rbt

2
PJP3003 PJP3001 PJP3002

2
1 2 1 2
VSSMPHY_SENSE 48
2 1

SHORT_PIN PWR_FB_SHORTPIN PWR_FB_SHORTPIN


GND AGND_P1V05AUX AGND_P1V05AUX AGND_P1V05AUX AGND_P1V05AUX /X GND /X

CAD NOTE: CAD NOTE:


Short pin should be placed close to 10uF/16V MLCC. Place in PCH cavity.
AGND Shape, and 30mil trace connect to short pin#1.

Layout note: DESIGN NOTE:


(1) VIN的1UF務必要放在同層PIN21 Vout = Vref × (1+(Rtop/Rbt))
,然後GND打2顆VIA. 1.05V = 0.6 × (1+(1.5k/2k))
20191018 (2) VCC的10UF務必要放在同層PIN19
,VCC出PIN腳後,走線寬度至少15MILS.
(3) AGND和GND之間SHORT PIN
D = 1.05/5 = 0.21
Iin_ripple = Io × sqrt{D × (1-D)}=4.9A
務必要靠近VCC的10UF GND. △I = (Vi-Vo) × D/(L × Freq)
(4) BST電容1UF要放在同層PIN1 =(5-1.05) × 0.21/(0.33μH × 1000kHz)=2.514A
+3VSB (5) 大顆的輸入電容務必要有1 顆 RLim(kΩ) = VLim/{Gcs × (ILim-△I/2)}
放在同層PIN10,該GND亦要靠近PIN11. VLim = 1.2V, Gcs = 10μA/A, ILim = 15.6A, RLim = 8.45kΩ
(6) 0.1UF要靠近PIN5
1

PR5000
+5VSB_ATX 8.2KOhm

teknisi indonesia
5%
+5VDUAL_AUX +3VSB +1.8V_A
走1.8V_PG左方元件/X
2
1

PR3004
33KOhm P_+1.05V_A_EN_10

3
2

D
1
2

PR3001 PQ3001
1

PR3033 PR3045 10KOhm 2 1 11


20,21,66 O_DEEPS5 H2N7002
10KOhm 4.3KOHM G
S
/X /X N/A 0Ohm PR3021 2 N/A
2

/X
2
1

3
C

P_+1.05V_A_EN_G_10
1 B PQ3000
PMBS3904
1.8V_A上這路
E N/A
2
20180323 single

PC3016 PR3044 +5VSB_ATX


1
1

0.1UF/16V 3.9KOHM PR3036 0Ohm


/X /X 1 2
GND O_DEEPS5 P_+1.05V_A_PG_10
2

GND /X
2

1
PR3037
10KOhm 3

3
D

GND GND +1.05V_A PQ3003

2
11
N/A H2N7002
G
S
3 2 N/A

2
PR3035 C
1 2 1 B PQ3002
PMBS3904
E N/A

1
PC3025
2KOhm 2 <Variant Name>
1UF/16V
N/A N/A
Title : +1.0_A/+VCCSFR_OC
2
GND GND GND
ASUSTek COMPUTER INC.
Engineer: Cisco Wang
Size Project Name Rev
2016/07/14 依照EE指示更新,參照201607131916mail
A2 Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 19 of 152


+5VSB_ATX ====>+3VSB_ATX Io:1.5A
+5VSB跟+5VDUAL_AUX合併
+5VSB_ATX PU4000
+3VSB_ATX
3 2

ADJ/GND
IN OUT

( +3.38V )

UZ2085G-AD-TN3-R

2
mbs_to252_share_lf3 PR4000

1.27KOhm

1
1

1
PC4007
PC4003 P_+3VSB_ATX_ADJ_20 22UF/6.3V
10UF/16V mbs_c0805

2
2
PR4002
mbs_c0805 2.15KOhm

1
+3VSB follow Z390-I 作法 GND

+3VSB_ATX --> +3VSB SEQUENCY


+3VSB_ATX 20160516 remove +3VSB

PQ4002
1 8
2 7
3 S 6
+5VSB_ATX 4 D 5 5
SLP_SUS_FET, O_DEEPS5
G
S0 S0 EMF44P02V

1
1 PC4010

1
空間需求移除+1.8V_A,SR959需上件 DS4,DS5
PR4010
200KOHM
0.22UF/10V

2
0 mbs_r0603

2
PR4014 10KOhm
0128 1 2
19,21,66 O_DEEPS5
P_+3VSB_SW_10

20190816合併到+1.05V_A

<Variant Name>

Title : +3VSB_ATX/+1.8V_A
ASUSTek Computer Inc.
Engineer: Miles Liu
Size Project Name Rev
A2 Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 20 of 152


+5V +5VDUAL_AUX
20190815空間限制移除一顆

PQ4559
NTMFS4C10NBT1G
+5V +5V_DUAL_USBKB 3

S
USBKB
+5V +5VSB_ATX 2 5

D
1

G
PD4500

4
2
1 2
PR4589
3KOhm SX34 /X/TEST

5VDUAL_AUX
mbs_r0603
PU4502

1
UP7501M8 PQ4502 P_5V_USB_N_SW_10
1 8 +12V
0521 NTMFS4C10NBT1G +5V +5VDUAL_AUX
23 P_PSU_PWROK
2
5VCC 5VCC_DRV
7 P_5V_USB_N_SW_10 3
0821 PQ4553

S
5VSB 5VSB_DRV
3 6 P_5V_USB_P_SW_10 2 5 NTMFS4C10NBT1G

D
GND S5#

2
4 5 SLP_S5_L_UVP 1 3 +3V +3VDUAL_AUX

S
MODE S3#
P_5V_MODE_10 PR4533 2 5 PQ4556

D
2KOhm 1 EMB20N03V

4
PQ4533 8
mbs_r0603 1

G
PEA16BA 2 7
GND

4
1
1

1
PC4532 PC4509 3 3 S 6

S
2
0.1UF/16V 1UF/16V 2 5 4 D 5 5

D
23,30,45,54,66,72 S_SLPS3#
mbs_c0603 mbs_c0603 PR4534 1 G
2

/X 2KOhm mbs_powerpak_5p_s118_colay

G
20170904 mbs_r0603

4
1
GND GND 23,30,45,66,72,115 S_SLPS4#_SIO
20190815空間限制 P_5V_USB_N_SW_10 P_5V_USB_N_SW_10

0419 P_5V_USB_N_SW_10
PR4503
0510
10KOhm
1 2
P_+5V_DUAL_USBKB_FLAG_10 +5V_DUAL_USBKB +3VDUAL_AUX
+5VSB_ATX 0821 精簡線路
0821 精簡線路
PQ4555
+3VSB_ATX
PU4503
0827 只有一個UP7501移除RC delay AP2301GN
5 1 +5VSB_ATX PQ4526 +5VDUAL_AUX
IN OUT
2 AP2301GN
1008

D
PR4579 GND
1 2 4 3 mbs_sot23 2 3

3
EN(EN#) FLAG
10KOhm P_+5V_DUAL_USBKB_EN_10

1
G517G1TO1U
0821 精簡線路

11
S

D
1

1
PC4526 PC4523 2 3 PCE4500

3
2

1
PC4525 0.1UF/25V 10UF/16V 20170925 PC4504 100UF/6.3V

2
1
PR4586 1UF/16V mbs_c0603 mbs_c0805 N/A PC4511 0.01UF/16V
1030

11
2

2
10KOhm mbs_c0603 /X 0.01UF/16V mbs_c0603
0821 精簡線路
2

2
mbs_c0603
set MODE pin (AUX & USB) 20180308 dual

2
1

20170904 PR4512
+5VSB_ATX 205Ohm
1 2
P_5V_USB_P_SW_10 P_3V_DUALAUX_PG_10
0313

2
GND
PR4525
+5VSB_ATX 100KOhm PR4528
mbs_r0603 0Ohm 5%
GND GND GND GND 1 2

1
P_5V_USB_P_SW_10 P_5V_AUX_P_SW_PGATE_10

1
PR4570 P_5V_MODE_10
8.2KOhm 20170901 add
/X
Default low +5V_DUAL_USBKB Enable

2
For BACKFEED_CUT_DSW# Active HIGH +5V_DUAL_USBKB disable 0510
20180308 dual 3
DS5/S5/S4/S3 DS5/S5/S4/S3

3
D

1 PQ4550
11 H2N7002
19,20,66 O_DEEPS5
G
S0 S
P_+5V_DUAL_USBKB_EN_10 P_+5V_DUAL_USBKB_EN_10 2
0

2
6

BACKFEED_CUT_DSW_N PQ4554A
3

Stuff BFC_DSW due to 2 2N7002KDW PQ4554B GND


in-rush concern 50 USBPWR_SW
5 2N7002KDW
1

P_5V_USB_P_SW_10
4
2

PR4585
100KOhm
1

PR4587
For BACKFEED_CUT#
1

100KOhm
/X
0510
S5/S4/S3 S5/S4/S3 GND
2

1 GND

DS5 S0 DS5
0
GND GND

BACKFEED_CUT_DSW#_S0IDLE
DS5/S5/S4/S3/S0ix DS5/S5/S4/S3/S0ix

S0
0

Title
<Title>

Size Document Number Rev


D <Doc> <RevCode>

Date: Thursday, December 12, 2019 Sheet 21 of 129


FOR SLP_S0_PLT_N_10
DS5/S5/S4/S3/S0 DS5/S5/S4/S3/S0

1
S0iX
0

改成AUDIO開頭

20171101
+3V +3V_S0IX

+5V +5V_S0IX

+12V_CPU +12V_S0IX

<Variant Name>

Title : S0IX POWER

ASUSTek COMPUTER INC.


Engineer: Morse_Peng
Size Project Name Rev
A2
Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 22 of 152


0423
+3VSB
1226 +3VATX->+5VATX
P_VRM_EN_5 6,72
P_+VTTDDR_EN_5 17
P_+VTTDDR_EN_5
+5VSB_ATX

1
PR5003
8.2KOhm
5%

1
PR5001

2
33KOhm

3
PQ5000B
5 2N7002KDW

6
P_VREN#_5 PQ5002A

4
2 2N7002KDW

1
GND 0911空間限制移除

6
PQ5000A GND
VRMPWRGD_5 6,54
2 2N7002KDW
21,30,45,54,66,72 S_SLPS3#

1
1 P_PSU_PWROK 21
PC5000
0.1UF/16V
/X
2

3 PR5006 3
GND

3
D
1KOhm C
PQ5005 1 2 1 B PQ5004

3
35 DDR_VTT_CNTL
GND 11 H2N7002 DDR_VTT_CNTL_L_10 PMBS3904 PQ5002B
26 P_VREN#_5 E
G N/A 5 2N7002KDW
S 2

1
2 PC5002 P_+VCORE_EN_G_10

4
0.1UF/16V
P_+VCCIO_0_EN_5 13,17,23,72
20191029 /X

2
+12V GND GND

6
PQ5006A
2 2N7002KDW GND GND

1
P_+VCCIO_1_2_EN_5 13,23
2

PR5009
13KOhm GND

3
mbs_r0603 PQ5006B
5 2N7002KDW
1

4
+3VSB

P_+VCCIO_0_EN_5 13,17,23,72
2

GND
1

PR5008 PR5010
13KOhm 33KOhm
mbs_r0603
6

PQ5007A
2
1

2 2N7002KDW
20160516 P_+VCORE_EN_G_10
1

P_+VCCIO_1_2_EN_5 13,23
3
C
1 B PQ5008 21,30,45,66,72,115 S_SLPS4#_SIO
PMBS3904
E
20180320 single
1

2
1

PR5014 PC5003 20160711 remove


2.37KOHM 0.1UF/16V VGD要比+5V早掉壓
GND +5VSB_ATX +VDDQ
2

1225
2

PQ5007B
5 2N7002KDW

1
GND GND 0311 PR5015 PR5016
4

8.2KOhm 51Ohm
P_+VCORE_EN_3V_10

5% 5%
+5V /NA s_r0805_h24

2
1215
P_Bleed_cut_10
3 3

3
D D
2

PR5018 阻值須修正 GND 1 PQ5009 PQ5010


20KOhm 11 H2N7002 11 H2N7002
3 G G
S3/S0 S3/S0 S S
C 2 2
0 S4/S5

2
1

1 B PQ5012
PMBS3904
E
GND
1

2
1

PR5020 PC5004 GND


4.7KOHM 0.1UF/16V P_Bleed_cut_5 17,26
2

20160516
2

0311

GND GND

+3V
1

PR5023
10KOhm
3
C
2

1 B PQ5015
PMBS3904
E
1

2
1

PR5026 PC5007
4.7KOHM 0.1UF/16V
0911空間限制移除
2

20160516
2

+5VSB_ATX

GND GND
2

PR5025
100KOhm
3

1
1

PQ5011B PR5027
1

5 2N7002KDW PC5008 0Ohm


0.1UF/10V /X
4

/X
2
6

PQ5011A
2 2N7002KDW
24,72 O2_PSON#
GND GND
1

GND

GND

<Variant Name>

Title : POWER SEQUENCE


ASUSTek COMPUTER INC.
Engineer: RAY
Size Project Name Rev
A2 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 23 of 152


All Gaming only
20150715

Default unstuff vcore OVP circuit

2019.07.18 為了蘇州TUF系列共用假北橋多開一個孔位
By Emma

O3_PSON# 76

O_PSON#_P

PR5118
0Ohm 5%
1 2
23,72 O2_PSON#

<Variant Name>

Title : PWM7-8
ASUSTeK Computer Inc.
Engineer: Miles Liu
Size Project Name Rev
Custom BMWB180 1.00

Date: Thursday, December 12, 2019 Sheet 24 of 129


20160602 update /Test
0210 update form Z170-A
2019.07.24
follow Z390 統一移除
By Emma

20160520 follow Strix Z270

2018.01.17

<Variant Name>

Title : +5VSB_AUD
ASUSTek COMPUTER INC.
Engineer: RAY
Size Project Name Rev
Custom Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 25 of 152


P_+VCCST_PVCC_10
+VCCST_REF_XDP

1
PR6041 PC6020
10KOhm 1UF/25V
+5VDUAL_AUX mbs_c0603

2
2 1
PU6000
RT7276GQW PR6014
9 3 GND 100KOhm +VCCST
VIN1 PVCC
10 5 1 2
VIN2 PGOOD
8 P_+VCCST_PG_5
BOOT
1

1
PC6016 PC6017 PC6018 1 7 P_+VCCST_Boot_10
EN SW2

1
22UF/6.3V 22UF/6.3V 22UF/6.3V 4 6 PC6021
SS SW1

P_+VCCST_SW_S
mbs_c0603 mbs_c0603 mbs_c0603 P_+VCCST_SS_10 11 2 0.1UF/16V
GND3 FB
2

1
PC6019 12 mbs_c0603
GND4

2
47NF/6.3V 13 PL6010
GND5
1 2 180227
170719

2
GND GND GND
2.2UH
170511
PR6039

2
GND GND 0Ohm 5% +VCCST_REF_XDP
PJP6001 /X
23 P_VREN#_5
PWR_FB_SHORTPIN 1 2
/X

1
PC6022 PC6023 PC6024
22UF/6.3V 22UF/6.3V 22UF/6.3V

1
FB=0.765V PR6016 PR6017 mbs_c0603 mbs_c0603 mbs_c0603 3

3
D

2
6.65KOhm 1KOhm
1 2 1 2 PQ6000
P_+VCCST_FB_10 11 H2N7002
17,23 P_Bleed_cut_5
G
S
2

2
1
PR6015 GND GND GND
20KOhm

2
GND
PR6018
0Ohm 5%
GND 1 2
+VCCST_REF_3933_10 80
P_Bleed_cut_10

20160523 10mV/step, Source是超壓; Sink是降壓 1

S4/S5 S4/S5
0 S3/S0
Rserved VCCPLL & VCCST Merge 0ohm

0708

VCCPLL合併到VCCST
VCCPLL_OC合併到VDDQ

0708

<Variant Name>

Title :
VCCST/VCCPLL/VCCPLL_OC
ASUSTeK Computer Inc.
Engineer: Cisco Wang
Size Project Name Rev
A2 Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 26 of 152


Title : CPTH (CNVi)

ASUSTek Computer Inc.


Engineer: Aaron_Su
Size Project Name
Maximus XI Extreme Rev
A4 R1.01

Date: Thursday, December 12, 2019 Sheet 27 of 152


Title : CPTH (CNVi)

ASUSTek Computer Inc.


Engineer: Aaron_Su
Size Project Name
Maximus XI Extreme Rev
Custom R1.01

Date: Thursday, December 12, 2019 Sheet 28 of 152


LGA1200D

F39 M15
64 H_DP_B_TXP0 DDI1_TXP[0] EDP_TXP[0]
F38 M14
64 H_DP_B_TXN0 DDI1_TXN[0] EDP_TXN[0]
G40 N15
DP 1.2 64 H_DP_B_TXP1 G39
DDI1_TXP[1] EDP_TXP[1]
N14
64 H_DP_B_TXN1 DDI1_TXN[1] EDP_TXN[1]
H38 L14
64 H_DP_B_TXP2 DDI1_TXP[2] EDP_TXP[2]
H39 L15
64 H_DP_B_TXN2 DDI1_TXN[2] EDP_TXN[2]
J39 L13
64 H_DP_B_TXP3 DDI1_TXP[3] EDP_TXP[3]
J40 K13
64 H_DP_B_TXN3 DDI1_TXN[3] EDP_TXN[3]

K39 K12
64 H_DP_B_AUXP DDI1_AUXP EDP_AUXP
K38 K11
64 H_DP_B_AUXN DDI1_AUXN EDP_AUXN

F35 L37 1 HT153


63 H_HDMI_C_TXP2 DDI2_TXP[0] DISP_UTILS
F36 TP_CPU_L37
63 H_HDMI_C_TXN2 DDI2_TXN[0]
E36 M9
63 H_HDMI_C_TXP1 DDI2_TXP[1] PROC_AUDIO_CLK H_HDA_SCLK 45
E37 N9
HDMI2.0a 63 H_HDMI_C_TXN1 D37
DDI2_TXN[1] PROC_AUDIO_SDI
M10 1 2
H_HDA_SDO_R 45
63 H_HDMI_C_TXP0 DDI2_TXP[2] PROC_AUDIO_SDO H_HDA_SDI 45
D38 H_HDA_SDI_R HR1 /1200 1% 20OHM
63 H_HDMI_C_TXN0 DDI2_TXN[2]
G36 B39 1 HT154
63 H_HDMI_C_TXPC DDI2_TXP[3] RSVD_TP_1
G37 RSVD_TP_1
63 H_HDMI_C_TXNC DDI2_TXN[3]

1
H36 EC13
63 H_DP_C_AUXP DDI2_AUXP
H35 10PF/50V
63 H_DP_C_AUXN DDI2_AUXN
/X/EMI

2
A37
20190728 for HDMI2.0a DDI3_TXP[0]
B37
DDI3_TXN[0]
C38
DDI3_TXP[1]
B38
DDI3_TXN[1]
D40
DDI3_TXP[2] GND
C40
DDI3_TXN[2]
E39
DDI3_TXP[3]
E40
DDI3_TXN[3]

B36
DDI3_AUXP
C36
DDI3_AUXN

SOCKET_1200P
12001-00280300

Title : LGA1200 (FDI/DISPLAY)


ASUSTek Computer Inc.
Engineer: Aaron_Su
Size Project Name Rev
A3 Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 32 of 152


Channel A
8 Layer routing

39 D4_DQ_A[0:63]

LGA1200A

AE39 AU24
DDR0_DQ[0] DDR0_CKP[0] D4_MA_CLK0 39
D4_DQ_A5 AE38 AV24
DDR0_DQ[1] DDR0_CKN[0] D4_MA_CLK#0 39
D4_DQ_A4 AH39 AY23
DDR0_DQ[2] DDR0_CKP[1] D4_MA_CLK1 39
D4_DQ_A7 AH38 AW23
DDR0_DQ[3] DDR0_CKN[1] D4_MA_CLK#1 39
D4_DQ_A3 AF40 AT19
DDR0_DQ[4] DDR0_CKP[2] D4_MA_CLK2 39
D4_DQ_A1 AE40 AU19
DDR0_DQ[5] DDR0_CKN[2] D4_MA_CLK#2 39
D4_DQ_A0 AH40 AY18 +VDDQ
DDR0_DQ[6] DDR0_CKP[3] D4_MA_CLK3 39
D4_DQ_A2 AG40 AW18
DDR0_DQ[7] DDR0_CKN[3] D4_MA_CLK#3 39
D4_DQ_A6 AK39
DDR0_DQ[8]
D4_DQ_A8 AK40 AY31
DDR0_DQ[9] DDR0_CKE[0] D4_CKE_A0 39
D4_DQ_A13 AN39 AW31
DDR0_DQ[10] DDR0_CKE[1] D4_CKE_A1 39
D4_DQ_A10 AM40 AV30
DDR0_DQ[11] DDR0_CKE[2] D4_CKE_A2 39

1
D4_DQ_A14 AL40 AV31
DDR0_DQ[12] DDR0_CKE[3] D4_CKE_A3 39
D4_DQ_A9 AK38 D4C49
DDR0_DQ[13]

2
D4_DQ_A12 AN40 AY15 0.1UF/16V
DDR0_DQ[14] DDR0_CS#[0] D4_CS_A#0 39

2
D4_DQ_A15 AN38 AY13 D4R130 /DDR4
DDR0_DQ[15] DDR0_CS#[1] D4_CS_A#1 39
D4_DQ_A11 AR39 AV15 2KOhm
DDR0_DQ[16]/DDR0_DQ[32] DDR0_CS#[2] D4_CS_A#2 39
D4_DQ_A21 AR40 AV13 /DDR4
DDR0_DQ[17]/DDR0_DQ[33] DDR0_CS#[3] D4_CS_A#3 39
D4_DQ_A20 AV39 1% GND
DDR0_DQ[18]/DDR0_DQ[34]

1
D4_DQ_A22 AU40 AY14 D4R136 2Ohm D4R129
DDR0_DQ[19]/DDR0_DQ[35] DDR0_ODT[0] D4_ODT_A0 39
D4_DQ_A17 AR38 AV14 1 2 1 2
DDR0_DQ[20]/DDR0_DQ[36] DDR0_ODT[1] D4_ODT_A1 39 D4_VREFCA_A0 41
D4_DQ_A19 AT40 AU14 H_D4_VREFCA_A0 /DDR4 H_D4_VREFCA_A0_R 0Ohm
DDR0_DQ[21]/DDR0_DQ[37] DDR0_ODT[2] D4_ODT_A2 39
D4_DQ_A16 AW38 AT14 /DDR4
DDR0_DQ[22]/DDR0_DQ[38] DDR0_ODT[3] D4_ODT_A3 39

2
D4_DQ_A18 AV38 D4R131
DDR0_DQ[23]/DDR0_DQ[39]
D4_DQ_A23 AV36 AY16
DDR0_DQ[24]/DDR0_DQ[40] DDR0_BA[0] D4_BAA0 39

1
D4_DQ_A28 AY36 AW17 D4C53 2KOhm
DDR0_DQ[25]/DDR0_DQ[41] DDR0_BA[1] D4_BAA1 39
D4_DQ_A24 AV33 0.022UF/16V /DDR4
DDR0_DQ[26]/DDR0_DQ[42]
2019.10.17 D4_DQ_A31 AY34 AV29 /DDR4 1%
DDR0_DQ[27]/DDR0_DQ[43] DDR0_BG[0] D4_BGA0 39

1
DQ follow Intel CRB SWAP D4_DQ_A30 AY35 AW29
DDR0_DQ[28]/DDR0_DQ[44] DDR0_BG[1] D4_BGA1 39

2
D4_DQ_A25 AW36
DDR0_DQ[29]/DDR0_DQ[45] D4_MAA[0:16] 39
D4_DQ_A29 AY33 AV16 D4R137
DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[16]
D4_DQ_A26 AW33 AW16 D4_MAA16 24.9Ohm
DDR0_DQ[31]/DDR0_DQ[47] DDR0_MA[14]
D4_DQ_A27 AW11 AU16 D4_MAA14 /DDR4
DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[15]
D4_DQ_A36 AV11 D4_MAA15 GND
DDR0_DQ[33]/DDR1_DQ[1]

1
D4_DQ_A37 AY7 AU18
DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]
D4_DQ_A34 AY8 AY25 D4_MAA0
DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[1]
D4_DQ_A38 AW9 AY24 D4_MAA1 GND
DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[2]
D4_DQ_A33 AW10 AW25 D4_MAA2
DDR0_DQ[37]/DDR1_DQ[5] DDR0_MA[3]
D4_DQ_A32 AV7 AV25 D4_MAA3
DDR0_DQ[38]/DDR1_DQ[6] DDR0_MA[4]
D4_DQ_A35 AW7 AY26 D4_MAA4
DDR0_DQ[39]/DDR1_DQ[7] DDR0_MA[5]
D4_DQ_A39 AW5 AV26 D4_MAA5
DDR0_DQ[40]/DDR1_DQ[8] DDR0_MA[6]
D4_DQ_A40 AY5 AY27 D4_MAA6
DDR0_DQ[41]/DDR1_DQ[9] DDR0_MA[7]
D4_DQ_A45 AW2 AW27 D4_MAA7
DDR0_DQ[42]/DDR1_DQ[10] DDR0_MA[8]
D4_DQ_A47 AW3 AY28 D4_MAA8
DDR0_DQ[43]/DDR1_DQ[11] DDR0_MA[9]
D4_DQ_A46 AY4 AU17 D4_MAA9
DDR0_DQ[44]/DDR1_DQ[12] DDR0_MA[10]
D4_DQ_A41 AV5 AV27 D4_MAA10
DDR0_DQ[45]/DDR1_DQ[13] DDR0_MA[11]
D4_DQ_A44 AV1 AV28 D4_MAA11
DDR0_DQ[46]/DDR1_DQ[14] DDR0_MA[12]
D4_DQ_A43 AV2 AW14 D4_MAA12
DDR0_DQ[47]/DDR1_DQ[15] DDR0_MA[13]
D4_DQ_A42 AT1 D4_MAA13
DDR0_DQ[48]/DDR1_DQ[32]
D4_DQ_A48 AN1 AY30
DDR0_DQ[49]/DDR1_DQ[33] DDR0_ACT# D4_A_ACT# 39
D4_DQ_A50 AT3 AV18
DDR0_DQ[50]/DDR1_DQ[34] DDR0_PAR D4_A_PAR 39
D4_DQ_A52 AP1 AY29
DDR0_DQ[51]/DDR1_DQ[35] DDR0_ALERT# D4_A_ALERT# 39
D4_DQ_A54 AT2
DDR0_DQ[52]/DDR1_DQ[36]
D4_DQ_A53 AN3 AF38
DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[0] D4_DQS_A#0 39
D4_DQ_A51 AR1 AL38 D4_DQS_A#0
DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSN[1] D4_DQS_A#1 39
D4_DQ_A49 AN2 AT38 D4_DQS_A#1
DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[2]/DDR0_DQSN[4] D4_DQS_A#2 39
D4_DQ_A55 AL2 AV35 D4_DQS_A#2
DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSN[3]/DDR0_DQSN[5] D4_DQS_A#3 39
D4_DQ_A56 AH1 AV9 D4_DQS_A#3
DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSN[4]/DDR1_DQSN[0] D4_DQS_A#4 39
D4_DQ_A58 AL3 AV4 D4_DQS_A#4
DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSN[5]/DDR1_DQSN[1] D4_DQS_A#5 39
D4_DQ_A60 AJ1 AR3 D4_DQS_A#5
DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQSN[6]/DDR1_DQSN[4] D4_DQS_A#6 39
D4_DQ_A62 AH3 AK3 D4_DQS_A#6
DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQSN[7]/DDR1_DQSN[5] D4_DQS_A#7 39
D4_DQ_A59 AL1 D4_DQS_A#7
DDR0_DQ[61]/DDR1_DQ[45]
D4_DQ_A61 AH2 AG38 High frequency termination,
DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQSP[0] D4_DQS_A0 39 can absorb any high
D4_DQ_A63 AK1 AM38 D4_DQS_A0
DDR0_DQ[63]/DDR1_DQ[47] DDR0_DQSP[1] D4_DQS_A1 39 frequency noise coming from
Follow M11A@20190813 D4_DQ_A57 AU38 D4_DQS_A1 CPU/board crosstalk.
DDR0_DQSP[2]/DDR0_DQSP[4] D4_DQS_A2 39
AL30 AV34 D4_DQS_A2
DDR0_ECC[0] DDR0_DQSP[3]/DDR0_DQSP[5] D4_DQS_A3 39
20190731:Remove for ONE DIMM AM30 AV8 D4_DQS_A3
DDR0_ECC[1] DDR0_DQSP[4]/DDR1_DQSP[0] D4_DQS_A4 39
AM31 AV3 D4_DQS_A4
DDR0_ECC[2] DDR0_DQSP[5]/DDR1_DQSP[1] D4_DQS_A5 39
AL32 AP3 D4_DQS_A5
DDR0_ECC[3] DDR0_DQSP[6]/DDR1_DQSP[4] D4_DQS_A6 39
AK32 AJ3 D4_DQS_A6
DDR0_ECC[4] DDR0_DQSP[7]/DDR1_DQSP[5] D4_DQS_A7 39
AJ32 D4_DQS_A7
DDR0_ECC[5]
AM32 AJ30
DDR0_ECC[6] DDR0_DQSP[8]
AK30 AJ31
DDR0_ECC[7] DDR0_DQSN[8]
20190808:Remove D4_DQS_A#8
D4R149 AC40
DDR_VREF_CA[0]
1 2 H_D4_VREFCA_A0 AC38
DDR_VREF_CA[1]
0Ohm H_D4_VREFCA_A1
/X/DDR4
SOCKET_1200P
12001-00280300

Title : LGA1200 (DDR4_A Control)


ASUSTek Computer Inc.
Engineer: Aaron_Su
Size Project Name Rev
A2 Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 33 of 152


LGA1200C

G12 A8
60 X_1X16_RXP0 PEG_RXP[0] PEG_TXP[0] X_1X16_TXP0 60
H12 B8
60 X_1X16_RXN0 PEG_RXN[0] PEG_TXN[0] X_1X16_TXN0 60

F11 B7
60 X_1X16_RXP1 PEG_RXP[1] PEG_TXP[1] X_1X16_TXP1 60
G11 C7
60 X_1X16_RXN1 PEG_RXN[1] PEG_TXN[1] X_1X16_TXN1 60

G10 A6
60 X_1X16_RXP2 PEG_RXP[2] PEG_TXP[2] X_1X16_TXP2 60
H10 A5
60 X_1X16_RXN2 PEG_RXN[2] PEG_TXN[2] X_1X16_TXN2 60

F9 B5
60 X_1X16_RXP3 PEG_RXP[3] PEG_TXP[3] X_1X16_TXP3 60
G9 B4
60 X_1X16_RXN3 PEG_RXN[3] PEG_TXN[3] X_1X16_TXN3 60

J9 C4
60 X_1X16_RXP4 PEG_RXP[4] PEG_TXP[4] X_1X16_TXP4 60
K9 C3
60 X_1X16_RXN4 PEG_RXN[4] PEG_TXN[4] X_1X16_TXN4 60

E7 D3
60 X_1X16_RXP5 PEG_RXP[5] PEG_TXP[5] X_1X16_TXP5 60
E6 D2
60 X_1X16_RXN5 PEG_RXN[5] PEG_TXN[5] X_1X16_TXN5 60

F6 E2
60 X_1X16_RXP6 PEG_RXP[6] PEG_TXP[6] X_1X16_TXP6 60
F5 E1
60 X_1X16_RXN6 PEG_RXN[6] PEG_TXN[6] X_1X16_TXN6 60

G7 F3
60 X_1X16_RXP7 PEG_RXP[7] PEG_TXP[7] X_1X16_TXP7 60
G6 F2
60 X_1X16_RXN7 PEG_RXN[7] PEG_TXN[7] X_1X16_TXN7 60

H5 G2
60 X_1X16_RXP8 PEG_RXP[8] PEG_TXP[8] X_1X16_TXP8 60
H6 G1
60 X_1X16_RXN8 PEG_RXN[8] PEG_TXN[8] X_1X16_TXN8 60

J6 H3
60 X_1X16_RXP9 PEG_RXP[9] PEG_TXP[9] X_1X16_TXP9 60
J7 H2
60 X_1X16_RXN9 PEG_RXN[9] PEG_TXN[9] X_1X16_TXN9 60

K5 J2
60 X_1X16_RXP10 PEG_RXP[10] PEG_TXP[10] X_1X16_TXP10 60
K6 J1
60 X_1X16_RXN10 PEG_RXN[10] PEG_TXN[10] X_1X16_TXN10 60

L6 K3
60 X_1X16_RXP11 PEG_RXP[11] PEG_TXP[11] X_1X16_TXP11 60
L7 K2
60 X_1X16_RXN11 PEG_RXN[11] PEG_TXN[11] X_1X16_TXN11 60

M5 L2
60 X_1X16_RXP12 PEG_RXP[12] PEG_TXP[12] X_1X16_TXP12 60
M6 L1
60 X_1X16_RXN12 PEG_RXN[12] PEG_TXN[12] X_1X16_TXN12 60

N6 M3
60 X_1X16_RXP13 PEG_RXP[13] PEG_TXP[13] X_1X16_TXP13 60
N7 M2
60 X_1X16_RXN13 PEG_RXN[13] PEG_TXN[13] X_1X16_TXN13 60

P5 N2
60 X_1X16_RXP14 PEG_RXP[14] PEG_TXP[14] X_1X16_TXP14 60
P6 N1
60 X_1X16_RXN14 PEG_RXN[14] PEG_TXN[14] X_1X16_TXN14 60

R6 P3
60 X_1X16_RXP15 PEG_RXP[15] PEG_TXP[15] X_1X16_TXP15 60
R7 P2
60 X_1X16_RXN15 PEG_RXN[15] PEG_TXN[15] X_1X16_TXN15 60

AD4 AF1
43 H_DMI_RXP0 DMI_RXP[0] DMI_TXP[0] H_DMI_TXP0 43
AD5 AF2
43 H_DMI_RXN0 DMI_RXN[0] DMI_TXN[0] H_DMI_TXN0 43

AD7 AE2
43 H_DMI_RXP1 DMI_RXP[1] DMI_TXP[1] H_DMI_TXP1 43
AD8 AE3
43 H_DMI_RXN1 DMI_RXN[1] DMI_TXN[1] H_DMI_TXN1 43

AC5 AD1
43 H_DMI_RXP2 DMI_RXP[2] DMI_TXP[2] H_DMI_TXP2 43
AC6 AD2
43 H_DMI_RXN2 DMI_RXN[2] DMI_TXN[2] H_DMI_TXN2 43

AB6 AC2
43 H_DMI_RXP3 DMI_RXP[3] DMI_TXP[3] H_DMI_TXP3 43
AB7 AC3
43 H_DMI_RXN3 DMI_RXN[3] DMI_TXN[3] H_DMI_TXN3 43

AA7 AB4
43 H_DMI_RXP4 DMI_RXP[4] DMI_TXP[4] H_DMI_TXP4 43
AA8 AB3
43 H_DMI_RXN4 DMI_RXN[4] DMI_TXN[4] H_DMI_TXN4 43

Y6 AA5
43 H_DMI_RXP5 DMI_RXP[5] DMI_TXP[5] H_DMI_TXP5 43
Y7 AA4
43 H_DMI_RXN5 DMI_RXN[5] DMI_TXN[5] H_DMI_TXN5 43

43 H_DMI_RXP6
W5
DMI_RXP[6] DMI_TXP[6]
Y4
H_DMI_TXP6 43
DMI4-7 is for RKL Use
W6 Y3
43 H_DMI_RXN6 DMI_RXN[6] DMI_TXN[6] H_DMI_TXN6 43

V4 W3
43 H_DMI_RXP7 DMI_RXP[7] DMI_TXP[7] H_DMI_TXP7 43
V5 W2
43 H_DMI_RXN7 DMI_RXN[7] DMI_TXN[7] H_DMI_TXN7 43

HT145 1 H15 A12 1 HT137


PEG60_RXP[0] PEG60_TXP[0]
HT146 1 PEG60_RXP0 J15 B12 PEG60_TXP0 1 HT138
PEG60_RXN[0] PEG60_TXN[0]
PEG60_RXN0 PEG60_TXN0
HT147 1 E15 B11 1 HT139
PEG60_RXP[1] PEG60_TXP[1]
HT148 1 PEG60_RXP1 F15 C11 PEG60_TXP1 1 HT140
PEG60_RXN[1] PEG60_TXN[1]
PEG60_RXN1 PEG60_TXN1
HT149 1 G14 C10 1 HT141
PEG60_RXP[2] PEG60_TXP[2]
HT150 1 PEG60_RXP2 H14 D10 PEG60_TXP2 1 HT142
PEG60_RXN[2] PEG60_TXN[2]
PEG60_RXN2 PEG60_TXN2
HT151 1 F13 B9 1 HT143
PEG60_RXP[3] PEG60_TXP[3]
HT152 1 PEG60_RXP3 G13 C9 PEG60_TXP3 1 HT144
PEG60_RXN[3] PEG60_TXN[3]
PEG60_RXN3 PEG60_TXN3

SOCKET_1200P
12001-00280000

PEG60 is for RKL Use

Title : LGA1200 (DMI/PEG)

ASUSTek Computer Inc.


Engineer: Aaron_Su
Size Project Name
Maximus XII Extreme Rev
A3 R1.01

Date: Thursday, December 12, 2019 Sheet 31 of 152


Channel B
8 Layer routing

40 D4_DQ_B[0:63]

LGA1200B

AD34 AT23
DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKP[0] D4_MB_CLK0 40
D4_DQ_B4 AD35 AU23
DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[0] D4_MB_CLK#0 40
D4_DQ_B5 AE36 AV22
DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[1] D4_MB_CLK1 40
D4_DQ_B1 AF36 AU22
DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKN[1] D4_MB_CLK#1 40
D4_DQ_B6 AG35 AT21
DDR1_DQ[4]/DDR0_DQ[20] DDR1_CKP[2] D4_MB_CLK2 40
D4_DQ_B3 AG34 AU21
DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKN[2] D4_MB_CLK#2 40
D4_DQ_B7 AD36 AU20
DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKP[3] D4_MB_CLK3 40
D4_DQ_B0 AG36 AV20 +VDDQ
DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKN[3] D4_MB_CLK#3 40
D4_DQ_B2 AJ36
DDR1_DQ[8]/DDR0_DQ[24]
D4_DQ_B13 AJ35 AT25
DDR1_DQ[9]/DDR0_DQ[25] DDR1_CKE[0] D4_CKE_B0 40
D4_DQ_B8 AL36 AR26
DDR1_DQ[10]/DDR0_DQ[26] DDR1_CKE[1] D4_CKE_B1 40
D4_DQ_B14 AM35 AT26
DDR1_DQ[11]/DDR0_DQ[27] DDR1_CKE[2] D4_CKE_B2 40

1
D4_DQ_B10 AK36 AP26
DDR1_DQ[12]/DDR0_DQ[28] DDR1_CKE[3] D4_CKE_B3 40

2
D4_DQ_B9 AJ34 D4C56
DDR1_DQ[13]/DDR0_DQ[29]
D4_DQ_B12 AM36 AN17 D4R141 0.1UF/16V
DDR1_DQ[14]/DDR0_DQ[30] DDR1_CS#[0] D4_CS_B#0 40

2
D4_DQ_B15 AM34 AN15 2KOhm /DDR4
DDR1_DQ[15]/DDR0_DQ[31] DDR1_CS#[1] D4_CS_B#1 40
D4_DQ_B11 AT36 AR16 /DDR4
DDR1_DQ[16]/DDR0_DQ[48] DDR1_CS#[2] D4_CS_B#2 40
D4_DQ_B17 AP36 AM15 1%
DDR1_DQ[17]/DDR0_DQ[49] DDR1_CS#[3] D4_CS_B#3 40

1
2019.10.17 D4_DQ_B20 AT34 D4R147 2Ohm GND D4R140
DDR1_DQ[18]/DDR0_DQ[50]
DQ follow Intel CRB SWAP D4_DQ_B22 AP33 AM17 1 2 1 2
DDR1_DQ[19]/DDR0_DQ[51] DDR1_ODT[0] D4_ODT_B0 40 D4_VREFCA_B0 41
D4_DQ_B19 AR36 AP14 H_D4_VREFCA_B0 H_D4_VREFCA_B0_R 0Ohm
DDR1_DQ[20]/DDR0_DQ[52] DDR1_ODT[1] D4_ODT_B1 40
D4_DQ_B16 AT35 AM16 /DDR4 /DDR4
DDR1_DQ[21]/DDR0_DQ[53] DDR1_ODT[2] D4_ODT_B2 40

2
D4_DQ_B21 AR33 AM14
DDR1_DQ[22]/DDR0_DQ[54] DDR1_ODT[3] D4_ODT_B3 40
D4_DQ_B23 AT33 D4R142
DDR1_DQ[23]/DDR0_DQ[55]

1
D4_DQ_B18 AP31 AP18 D4C55 2KOhm
DDR1_DQ[24]/DDR0_DQ[56] DDR1_BA[0] D4_BAB0 40
D4_DQ_B28 AT31 AN19 0.022UF/16V /DDR4
DDR1_DQ[25]/DDR0_DQ[57] DDR1_BA[1] D4_BAB1 40
D4_DQ_B29 AT29 /DDR4 1%
DDR1_DQ[26]/DDR0_DQ[58]

1
D4_DQ_B30 AP28 AM23
DDR1_DQ[27]/DDR0_DQ[59] DDR1_BG[0] D4_BGB0 40

2
D4_DQ_B27 AR31 AM22
DDR1_DQ[28]/DDR0_DQ[60] DDR1_BG[1] D4_BGB1 40
D4_DQ_B24 AT30 D4R148
DDR1_DQ[29]/DDR0_DQ[61] D4_MAB[0:16] 40
D4_DQ_B25 AR28 AM18 24.9Ohm GND
DDR1_DQ[30]/DDR0_DQ[62] DDR1_MA[16]
D4_DQ_B31 AT28 AP17 D4_MAB16 /DDR4
DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[14]
D4_DQ_B26 AT12 AP16 D4_MAB14
DDR1_DQ[32]/DDR1_DQ[16] DDR1_MA[15]

1
D4_DQ_B37 AR12 D4_MAB15
DDR1_DQ[33]/DDR1_DQ[17]
D4_DQ_B33 AT10 AP19
DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[0]
D4_DQ_B34 AR10 AP20 D4_MAB0 GND
DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[1]
D4_DQ_B39 AP12 AR20 D4_MAB1
DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[2]
D4_DQ_B36 AT11 AM20 D4_MAB2
DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[3]
D4_DQ_B32 AP10 AP21 D4_MAB3
DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[4]
D4_DQ_B38 AN10 AN21 D4_MAB4
DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[5]
D4_DQ_B35 AR8 AR22 D4_MAB5
DDR1_DQ[40]/DDR1_DQ[24] DDR1_MA[6]
D4_DQ_B40 AT8 AM21 D4_MAB6
DDR1_DQ[41]/DDR1_DQ[25] DDR1_MA[7]
D4_DQ_B45 AT5 AP22 D4_MAB7
DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[8]
D4_DQ_B42 AT6 AN23 D4_MAB8
DDR1_DQ[43]/DDR1_DQ[27] DDR1_MA[9]
D4_DQ_B46 AP8 AR18 D4_MAB9
DDR1_DQ[44]/DDR1_DQ[28] DDR1_MA[10]
D4_DQ_B44 AT7 AP23 D4_MAB10
DDR1_DQ[45]/DDR1_DQ[29] DDR1_MA[11]
D4_DQ_B41 AP5 AR24 D4_MAB11
DDR1_DQ[46]/DDR1_DQ[30] DDR1_MA[12]
D4_DQ_B47 AR5 AP15 D4_MAB12
DDR1_DQ[47]/DDR1_DQ[31] DDR1_MA[13]
D4_DQ_B43 AM8 D4_MAB13
DDR1_DQ[48]
D4_DQ_B52 AM7 AP25
DDR1_DQ[49] DDR1_ACT# D4_B_ACT# 40
D4_DQ_B53 AK6 AM19
DDR1_DQ[50] DDR1_PAR D4_B_PAR 40
D4_DQ_B54 AM5 AP24
DDR1_DQ[51] DDR1_ALERT# D4_B_ALERT# 40
D4_DQ_B48 AM6
DDR1_DQ[52]
D4_DQ_B49 AK7 AE34
DDR1_DQ[53] DDR1_DQSN[0]/DDR0_DQSN[2] D4_DQS_B#0 40
D4_DQ_B51 AK5 AK34
DDR1_DQ[54] DDR1_DQSN[1]/DDR0_DQSN[3] D4_DQS_B#1 40
D4_DQ_B55 AL5 AP35
DDR1_DQ[55] DDR1_DQSN[2]/DDR0_DQSN[6] D4_DQS_B#2 40
D4_DQ_B50 AF7 AP30
DDR1_DQ[56] DDR1_DQSN[3]/DDR0_DQSN[7] D4_DQS_B#3 40
D4_DQ_B58 AH8 AN12
DDR1_DQ[57] DDR1_DQSN[4]/DDR1_DQSN[2] D4_DQS_B#4 40
D4_DQ_B60 AG5 AP7
DDR1_DQ[58] DDR1_DQSN[5]/DDR1_DQSN[3] D4_DQS_B#5 40
D4_DQ_B62 AF6 AL8
DDR1_DQ[59] DDR1_DQSN[6] D4_DQS_B#6 40
D4_DQ_B59 AH6 AG8
DDR1_DQ[60] DDR1_DQSN[7] D4_DQS_B#7 40
D4_DQ_B57 AH7 High frequency termination,
DDR1_DQ[61] can absorb any high
D4_DQ_B56 AF5 AF34
DDR1_DQ[62] DDR1_DQSP[0]/DDR0_DQSP[2] D4_DQS_B0 40 frequency noise coming from
D4_DQ_B63 AH5 AL34 CPU/board crosstalk.
DDR1_DQ[63] DDR1_DQSP[1]/DDR0_DQSP[3] D4_DQS_B1 40
D4_DQ_B61 AP34
DDR1_DQSP[2]/DDR0_DQSP[6] D4_DQS_B2 40
AJ28 AP29
DDR1_ECC[0] DDR1_DQSP[3]/DDR0_DQSP[7] D4_DQS_B3 40
AK26 AN11
DDR1_ECC[1] DDR1_DQSP[4]/DDR1_DQSP[2] D4_DQS_B4 40
20190731:Remove for ONE DIMM AL26 AP6
DDR1_ECC[2] DDR1_DQSP[5]/DDR1_DQSP[3] D4_DQS_B5 40
AM28 AK8
DDR1_ECC[3] DDR1_DQSP[6] D4_DQS_B6 40
AK28 AF8
DDR1_ECC[4] DDR1_DQSP[7] D4_DQS_B7 40
AL28
DDR1_ECC[5]
AM27 AJ27
DDR1_ECC[6] DDR1_DQSP[8]
AM26 AJ26
DDR1_ECC[7] DDR1_DQSN[8]

20190803 for ONE DIMM D4R150 AC39


1 2 H_D4_VREFCA_B0 AB40
DDR_VREF_CA[2]
DDR_VREF_CA[3]
20190808:Remove D4_DQS_B#8
0Ohm H_D4_VREFCA_B1
/X/DDR4

SOCKET_1200P
12001-00280300

www.teknisi-indonesia.com

Title : LGA1200 (DDR4_B Control)


ASUSTek Computer Inc.
Engineer: Aaron_Su
Size Project Name Rev
A2 Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 34 of 152


+VCCST

PLACE NEAR CPU HR91 /X/1200


1 1KOhm 2
H_CFG0
HR92 /X/1200
Peter request

1
1 1KOhm 2

2
HC3 H_CFG1
0.1UF/16V HR210 HR4 HR209 HR93 /X/1200

2
/1200 100Ohm 45.3Ohm 56.2Ohm 1 1KOhm 2
/1200 /X/1200 /1200 H_CFG2
GND 1% LGA1200E HR95 /X/1200 +5V_S0IX +VCCST

1
1 1KOhm 2
U1 L35 H_CFG3
47,86 C_CPU0 BCLKP CFG[0]
T1 K36 H_CFG0 20190801 Remove XDP Hotplug HR94 is 1.5KOhm on Z390 CRB
47,86 C_CPU0# BCLKN CFG[1]
M35 H_CFG1 H_CFG10

1
CFG[2]
T4 N35 H_CFG2 HR96 /X/1200 HR3086
47 C_PCIBCLK PCI_BCLKP CFG[3]
T3 N37 H_CFG3 1 1KOhm 2 HR96 unstuff , No eDP support 8.2KOhm
47 C_PCIBCLK# PCI_BCLKN CFG[4]
H_CFG4 H_CFG4 /X/1200 3 3

3
D D
U8 P36 HR98 /X/1200

2
47 C_CPU_NSCCCLK CLK24P CFG[5]
U7 R36 H_CFG5_R 1 1KOhm 2 HQ1237 HQ1238
47 C_CPU_NSCCCLK# CLK24N CFG[6]
P37 H_CFG6_R H_CFG5_R 11 H2N7002 11 H2N7002
CFG[7] 72 O2_CFG10_TEST
HR208 /1200 220Ohm N34 H_CFG7 HR97 1 1KOhm 2 G /1200 G /X/1200
CFG[8] S S
A14 L36 H_CFG5 /1200 2 2

2
6,12 H_VIDALERT# VIDALERT# CFG[9]
2 1 CPU_VIDALERT# C14 H_CFG9 20190731 CF5 CF6 pull up +VCCIO
6,12 H_VIDCLK VIDSCK
B14 M37 HR99 /X/1200
6,12 H_VIDDATA VIDSOUT CFG[10]
P34 H_CFG10 1 1KOhm 2
CFG[11]
HR218 1 2 499Ohm A16 M38 H_CFG6_R
6,12 H_PROCHOT# PROCHOT# CFG[12]
/1200 H_PROCHOT#_R N36 HR4217 1 1KOhm 2
AC33
CFG[13]
P38 H_CFG6 /1200 HR191 /X/1200
Peter request H_CFG10

1
23 DDR_VTT_CNTL DDR_VTT_CNTL CFG[14]
1 1KOhm 2 HR4166
B13 P39 H_CFG7 H_CFG9 8.2KOhm
54 H_VCCST_PWRGD VCCST_PWRGD CFG[15]
H_VCCST_PWRGD_CPU J36 1 HT180 /1200
CFG[16]
D14 J37 H_CFG16 1 HT179 20190731 CF16~19 Test Pin

2
45 H_PWRGD PROCPWRGD CFG[17]
2

HR215 R34 H_CFG17 1 HT178


CFG[18]
2.8KOhm T7 R35 H_CFG18 1 HT177 3
GND

3
SYS_RESET# CFG[19] D
1% H_CPURST# H_CFG19 HR194 /X/1200
/X/1200 C15 L38 20190801 Remove XDP 1 1KOhm 2 HQ1231 GND
44 S_PM_SYNC_H PM_SYNC BPM#[0]
D13 L40 +VCCIO_0 H_CFG9 11 H2N7002
PM_DOWN BPM#[1] 72 O2_CFG9
1

H_PM_DOWN_R T32 1 HT155 HR193 /X/1200 G /1200


A15
BPM#[2]
R32 BPM_2 1 HT156 1 1KOhm 2 2
S Peter request

2
69 H_PECI PECI BPM#[3]
GND AF3 BPM_3
THERMTRIP#
H_THERMTRIP# N40 HR195 /X/1200
PROC_TDO
AC37 N39 H_TDO 1 1KOhm 2

1
66,72,76 H_SKTOCC# SKTOCC# PROC_TDI
HR215, HR216 Close to CPU HT14 1 D16 L39 H_CFG10 HR3065
CATERR# PROC_TMS
AT3 1 H_TP_CATERR# M40 8.2KOhm
PROC_TCK
H_TCK /1200
N38 GND

2
PROC_TRST#
K35
PROC_PREQ#
L34 H_PREQ#
PROC_PRDY#

AB39 GND
CPU_ID CPU_ID_10 13,72

HR3 +3VSB
SOCKET_1200P
12001-00280300 1 8.2KOhm 2

/1200 +VCCIO_0
ALL CFG 1 = NO TERMAINATION ON BOARD DEFAULT HIGH
ALL CFG 0 = PHYSICAL STRAP LOW ON BOARD

2
CoffeeLake Strap Table Rev 0.5 HR4239

2
All Have Internal Pull-Ups +VCCIO 100KOhm
CFG H = 1 L = 0 Description 1% HR3095
0 Normal STALL EAR /1200 8.2KOhm
1 Reserved ENG Feature : CFG Starps Customer Should Follow PDG&EDS /1200

1
2 Normal Lane Reverse PCIEX16 Lane Reversal GND

1
O2_CPU_ID_10 12,72
3 Reserved PCIE Config Table
4 disable enable eDP SEL[1] SEL[0] PCIE Config
5 PCIE Config PCIE Config SEL[0] 0 0 1 x8, 2 x4 PCIE
6 PCIE Config PCIE Config SEL[1] 0 1 Reserved H_CFG2
7 RESET# BIOS REQ PEG Training 1 0 2 x8 PCIE CFG no IPU issue
8-19 Reserved 1 1 1 x16 PCIE default
HR217
1 2
44 H_PM_DOWN_S
20OHM H_PM_DOWN_R H_TCK TERMINATION (HR127)
2

/1200 +VCCIO_0 +VCCST +VCCSTG +VCCIO_1_2 PLACE HR24 CLOSER TO CPU HR23 PLACE NEAR CPU WITHIN 1.1 INCH
HR506 1% +3VSB
1KOhm OD227
1

2
/X/1200 +VCCST H_TCK

2
HR3094 HR4231

1
1

110Ohm 110Ohm HR23


HR3093 HR11 10G212110014020 10G212110014020 51Ohm

1
GND VPORT0402220MV05 HR3091 110Ohm 110Ohm /X/1200 /X/1200 HR24 /X/XDP
2

1
/X/PANEL 8.2KOhm /X/1200 /1200 mbs_r0402 mbs_r0402 100Ohm 5%

2
1

1
/1200 mbs_r0402 mbs_r0402
1

/X/XDP

2
H_CPURST# GND
3 H_TDO
GND 20190801 Remove XDP follow Z390-I
3

HQ8
+VCCST +VCCSTG 11
G H2N7002
S
UNSTUFF HR201 FOR MERGED XDP 3 2 /1200
2

HR520 C
HR202, 1Kohm ver:Coffee Lake 1 2 1 B HQ9
42,55,66,81 S_PLTRST#
8.2KOhm PMBS3904
E /1200
2

/1200
HR203 HR201 HR202 HR4238 2
1KOhm 51Ohm 1KOhm 1KOhm
/1200 /X/1200 /X/1200 /1200 GND
1

GND

H_PROCHOT#
HR3092
H_PREQ# 1 2
44 H_CPURST_SB#
0Ohm
H_THERMTRIP# 6,44
H_THERMTRIP# /X/1200

PLACE HR203 CLOSE TO SPT-H


OD4
1

+VCCIO_0
VPORT0402220MV05
For CPU Raid support
2

/X/PANEL
+3VSB
2

GND QSWR15 QSWR16


1.5PF/50V 8.2KOhm 8.2KOhm
1

1 2 H_PWRGD SR110
1

HC9 8.2KOhm
/X/1200 N/A
2

SD6
GND

2 H_CFG6
44 SWITCH_CFG6
3
1 H_CFG5

BAT54CW

Title : LGA1200 (Control)

ASUSTek Computer Inc.


Engineer: Aaron_Su
Size Project Name Rev
A2 Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 35 of 152


+VDDQ Power Monitor
+VCCGT Power Monitor

+5V Power Monitor

+VCCSA Power Monitor

+VCORE Power Monitor


+1.05V_A Power Monitor

+VCCIO Power Monitor

A1 A0 Address

Gnd Gnd 1000000 ; 40


Gnd Vcc 1000001 ; 41
+5VSB_ATX Power Monitor
Gnd SDA 1000010 ; 42
Gnd SCL 1000011 ; 43
Vcc Gnd 1000100 ; 44 +5VSB

Vcc Vcc 1000101 ; 45


Vcc SDA 1000110 ; 46
Vcc SCL 1000111 ; 47
SDA Gnd 1001000 ; 48
SDA Vcc 1001001 ; 49
SDA SDA 1001010 ; 4A
SDA SCL 1001011 ; 4B
SCL Gnd 1001100 ; 4C +5V

SCL Vcc 1001101 ; 4D +3V

SCL SDA 1001110 ; 4E


+3VSB_ATX Power Monitor
SCL SCL 1001111 ; 4F

<Variant Name>

Title : Power monitor-1


ASUSTek COMPUTER INC.
Engineer: RAY
Size Project Name Rev
A2 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 29 of 152


+VCORE +VCORE
+VCCSA +VCORE +VCORE
+VDDQ LGA1200J
LGA1200K LGA1200I
F23 J34
VCCCORE_100 VCCCORE_150
B3 AR14 A17 C18 F25 K17
VCCSA_1 VDDQ_1 VCCCORE_1 VCCCORE_50 VCCCORE_101 VCCCORE_151
B6 AT24 A18 C19 F27 K19
VCCSA_2 VDDQ_2 VCCCORE_2 VCCCORE_51 VCCCORE_102 VCCCORE_152
D1 AU15 A23 C20 F29 K21
VCCSA_3 VDDQ_3 VCCCORE_3 VCCCORE_52 VCCCORE_103 VCCCORE_153
G3 AU25 A24 C21 F31 K23
VCCSA_4 VDDQ_4 VCCCORE_4 VCCCORE_53 VCCCORE_104 VCCCORE_154
H1 AV17 A25 C22 F33 K25
VCCSA_5 VDDQ_5 VCCCORE_5 VCCCORE_54 VCCCORE_105 VCCCORE_155
L11 AV19 A26 C23 G17 K27
VCCSA_6 VDDQ_6 VCCCORE_6 VCCCORE_55 VCCCORE_106 VCCCORE_156
L12 AV23 A27 C24 G18 K29
VCCSA_7 VDDQ_7 VCCCORE_7 VCCCORE_56 VCCCORE_107 VCCCORE_157
L3 AW13 A28 C25 G19 K31
VCCSA_8 VDDQ_8 VCCCORE_8 VCCCORE_57 VCCCORE_108 VCCCORE_158
M1 AW15 A29 C26 G20 K32
VCCSA_9 VDDQ_9 VCCCORE_9 VCCCORE_58 VCCCORE_109 VCCCORE_159
M11 AW24 A30 C27 G21 K33
VCCSA_10 VDDQ_10 VCCCORE_10 VCCCORE_59 VCCCORE_110 VCCCORE_160
M12 AW26 +VCCST A31 C28 G22 L17
VCCSA_11 VDDQ_11 VCCCORE_11 VCCCORE_60 VCCCORE_111 VCCCORE_161
N11 AW28 +VDDQ_EDGECAP2 A32 C29 G23 L18
VCCSA_12 VDDQ_12 VCCCORE_12 VCCCORE_61 VCCCORE_112 VCCCORE_162
N12 AW30 A33 C30 G24 L19
VCCSA_13 VDDQ_13 VCCCORE_13 VCCCORE_62 VCCCORE_113 VCCCORE_163
N13 AY17 +VDDQ_EDGECAP1 A34 C31 G25 L20
VCCSA_14 VDDQ_14 VCCCORE_14 VCCCORE_63 VCCCORE_114 VCCCORE_164
+VCCIO_1_2 +VCCST A35 C32 G26 L21
VCCCORE_15 VCCCORE_64 VCCCORE_115 VCCCORE_165
AM13 AJ12 C33 G27 L22
VDDQ_15_CAP2 VCCCORE_16 VCCCORE_65 VCCCORE_116 VCCCORE_166
AJ9 AM24 AJ13 C34 G28 L23
VCCIO2_1 VDDQ_16_CAP1 VCCCORE_17 VCCCORE_66 VCCCORE_117 VCCCORE_167
AK10 AJ14 C35 G29 L24
VCCIO2_2 VCCCORE_18 VCCCORE_67 VCCCORE_118 VCCCORE_168
AK11 U2 AJ15 D17 G30 L25
VCCIO2_3 VCCST_1 VCCCORE_19 VCCCORE_68 VCCCORE_119 VCCCORE_169
AL10 V1 AJ16 D19 G31 L26
VCCIO2_4 VCCST_2 VCCCORE_20 VCCCORE_69 VCCCORE_120 VCCCORE_170
+VCCIO_1_2 AL11 V2 AJ17 D21 G32 L27
VCCIO2_5 VCCST_3 VCCCORE_21 VCCCORE_70 VCCCORE_121 VCCCORE_171
AJ18 D23 G33 L28
VCCCORE_22 VCCCORE_71 VCCCORE_122 VCCCORE_172
AK25 R1 AJ19 D25 G34 L29
VCCIO1_1 VCCPLL VCCCORE_23 VCCCORE_72 VCCCORE_123 VCCCORE_173
AL12 +VCCPLL_20 AJ20 D27 H17 L30
VCCIO1_2 VCCCORE_24 VCCCORE_73 VCCCORE_124 VCCCORE_174
AL24 AU13 AJ21 D29 H19 L31
VCCIO1_3 VCCPLL_OC_1 VCCCORE_25 VCCCORE_74 VCCCORE_125 VCCCORE_175

1
+VCCIO_0 AM12 AU27 AJ22 D31 H21 L32
VCCIO1_4 VCCPLL_OC_2 VCCCORE_26 VCCCORE_75 VCCCORE_126 VCCCORE_176
+VCCPLL_OC_R_40 HC7036 AJ23 D33 H23 M17
VCCCORE_27 VCCCORE_76 VCCCORE_127 VCCCORE_177
AA3 R2 +VCCSTG 22UF/6.3V AJ24 D34 H25 M19
VCCIO0_1 VCCSTG_1 VCCCORE_28 VCCCORE_77 VCCCORE_128 VCCCORE_178

2
AB8 R3 AK13 D35 H27 M21
VCCIO0_2 VCCSTG_2 VCCCORE_29 VCCCORE_78 VCCCORE_129 VCCCORE_179
AC1 11G233222625320 AK14 E17 H29 M23
VCCIO0_3 VCCCORE_30 VCCCORE_79 VCCCORE_130 VCCCORE_180
AC7 R4 mbs_c0603 AK15 E18 H31 M25
VCCIO0_4 VCCSTG_3 VCCCORE_31 VCCCORE_80 VCCCORE_131 VCCCORE_181
AD6 T5 +VCCSTG GND AK16 E19 H33 M27
VCCIO0_5 VCCSTG_4 VCCCORE_32 VCCCORE_81 VCCCORE_132 VCCCORE_182
U5 T6 AK17 E20 J17 M29
VCCIO0_6 VCCSTG_5 VCCCORE_33 VCCCORE_82 VCCCORE_133 VCCCORE_183
V3 AK18 E21 J18 M31
VCCIO0_7 VCCCORE_34 VCCCORE_83 VCCCORE_134 VCCCORE_184
V7 +VDDQ AK19 E22 J19 M32
VCCIO0_8 VCCCORE_35 VCCCORE_84 VCCCORE_135 VCCCORE_185
W1 AK20 E23 J20 N17
VCCIO0_9 VCCCORE_36 VCCCORE_85 VCCCORE_136 VCCCORE_186
W7 AK21 E24 J21 N18
VCCIO0_10 VCCCORE_37 VCCCORE_86 VCCCORE_137 VCCCORE_187
W8 AK22 E25 J22 N19
VCCIO0_11 VCCCORE_38 VCCCORE_87 VCCCORE_138 VCCCORE_188
AK23 E26 J23 N20
VCCCORE_39 VCCCORE_88 VCCCORE_139 VCCCORE_189

1
HC53 HC54 HC7038 B17 E27 J24 N21
VCCCORE_40 VCCCORE_89 VCCCORE_140 VCCCORE_190
C6 22UF/6.3V 1UF/6.3V 10UF/6.3V B18 E28 J25 N22
12 P_+VCCSA_VCC_10 VCCSA_SENSE VCCCORE_41 VCCCORE_90 VCCCORE_141 VCCCORE_191
AE4 mbs_c0603 /X/1200 mbs_c0603 B23 E29 J26 N23
VCCIO1_SENSE/VCCIO2_SENSE VCCCORE_42 VCCCORE_91 VCCCORE_142 VCCCORE_192

2
13 VCCIO_1_2_SENSE_10 D5 B25 E30 J27 N24
/X/1200
13 VCCIO_0_SENSE_10 VCCIO0_SENSE VCCCORE_43 VCCCORE_92 VCCCORE_143 VCCCORE_193
B27 E31 J28 N25
VCCCORE_44 VCCCORE_93 VCCCORE_144 VCCCORE_194
D6 B29 E32 J29 N26
12,13 VSS_SA_PCIE_IO_SENSE_10 VSSSA_SENSE VCCCORE_45 VCCCORE_94 VCCCORE_145 VCCCORE_195
GND GND B31 E33 J30 N27
VCCCORE_46 VCCCORE_95 VCCCORE_146 VCCCORE_196
B33 E34 J31 N28
VCCCORE_47 VCCCORE_96 VCCCORE_147 VCCCORE_197
B35 F17 J32 N29
SOCKET_1200P VCCCORE_48 VCCCORE_97 VCCCORE_148 VCCCORE_198
C17 F19 J33 N30
VCCCORE_49 VCCCORE_98 VCCCORE_149 VCCCORE_199
12001-00280300 F21 N32
VCCCORE_99 VCCCORE_200

B16
VCCCORE_SENSE
C16
SOCKET_1200P VSS_SENSE
+VCCSTG +VDDQ_EDGECAP1 +VDDQ_EDGECAP2 +VCCST
12001-00280300

SOCKET_1200P
X5R X5R X5R X5R
1

1
HC51 HC52 HC7 HC8 12001-00280300
22UF/6.3V 1UF/6.3V HC12 HC13 22UF/6.3V 1UF/6.3V
mbs_c0603 /X/1200 22UF/6.3V 22UF/6.3V mbs_c0603 /1200
6 P_+VCORE_VSS_10
2

2
/X/1200 /1200 /1200 /1200
6 P_+VCORE_VCC_10
Place at Socket Edge Place at Socket Edge
GND GND GND GND

AS CLOSE AS POSSIBLE TO THE VIAS

LGA1200M

K16 AH33 +VCCGT


RSVD1 RSVD8
G16 AH32
RSVD2 RSVD9
LGA1200L
H8 D8
RSVD3 RSVD10
F8 AA32 AB37
RSVD11 VCCGT_1 VCCGT_SENSE P_+VCCGT_VCC_10 6
AU32 AA34 AB38
RSVD4 VCCGT_2 VSSGT_SENSE P_+VCCGT_VSS_10 6
AN25 D12 HR4226 1 2 0Ohm AA35
RSVD5 PROC_TRIGOUT CPU_2_PCH_TRIGGER 49 VCCGT_3
E12 CPU_2_PCH_TRIGGER_R /1200 AA36
PROC_TRIGIN PCH_2_CPU_TRIGGER 49 VCCGT_4
P33 AA37
RSVD_TP_2 VCCGT_5
R33 AL18 AA38
IST_TRIG RSVD12 VCCGT_6
HT123 1 TP_CPU_R33 J4 L33 AB32
RSVD_TP_3 RSVD13 VCCGT_7
L4 AB33
RSVD_TP_4 VCCGT_8
AB34
VCCGT_9
P8 M16 AB35
RSVD_PEG60_TP2 RSVD14 VCCGT_10
M8 M33 AB36
RSVD_PEG60_TP1 RSVD15 VCCGT_11
N4 AC32
RSVD16 VCCGT_12
G4 T33 AD32
RSVD6 RSVD17 VCCGT_13
E4 AE32
RSVD7 VCCGT_14
AF32
VCCGT_15
J11 AG32
VSS_377 VCCGT_16
J13 R40
VSS_378 VCCGT_17
T37
VCCGT_18
NP_NC1
NP_NC2
NP_NC3
NP_NC4
NP_NC5
NP_NC6
NP_NC7

B15 T38
RTCCLK VCCGT_19
CPU_RTCCLK T39
VCCGT_20
T40
VCCGT_21
U33
1
2
3
4
5
6
7

SOCKET_1200P VCCGT_22
U34
VCCGT_23
12001-00280300 U35
VCCGT_24
U36
VCCGT_25
U37
VCCGT_26
U38
VCCGT_27
U39
VCCGT_28
U40
VCCGT_29
GND V32
VCCGT_30
V33
VCCGT_31
V34
VCCGT_32
V36
VCCGT_33
V38
VCCGT_34
V40
VCCGT_35
W32
VCCGT_36
W34
VCCGT_37
W35
VCCGT_38
W36
VCCGT_39
W37
VCCGT_40
W38
VCCGT_41
+3VSB_ERP +VCCST Y32
VCCGT_42
Y33
VCCGT_43
Y34
VCCGT_44
2

Y36
VCCGT_45
HR3111 HR3110 Y38
VCCGT_46
0Ohm 0Ohm
/1200 /1200

SOCKET_1200P
1

U2
1 6 12001-00280300
VCCA VCCB
2 5
GND DIR
1 HR3112 2 3 4
45,87,97 PCH_SUSCLK A B
33Ohm CPU_RTCCLK
/1200 74AVC1T45GW
/1200

GND GND

Title : LGA1200 (POWER)

ASUSTek Computer Inc.


Engineer: Aaron_Su
Size Project Name Rev
A2 Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 36 of 152


LGA1200F LGA1200G LGA1200H

A13 AK31 AP11 AU8 F18 L9


VSS_247 VSS_312 VSS_117 VSS_182 VSS_1 VSS_66
A36 AK33 AP13 AU9 F20 M13
VSS_248 VSS_313 VSS_118 VSS_183 VSS_2 VSS_67
A38 AK35 AP2 AV10 F22 M18
VSS_249 VSS_314 VSS_119 VSS_184 VSS_3 VSS_68
A4 AK37 AP27 AV12 F24 M20
VSS_250 VSS_315 VSS_120 VSS_185 VSS_4 VSS_69
A7 AK4 AP32 AV21 F26 M22
VSS_251 VSS_316 VSS_121 VSS_186 VSS_5 VSS_70
AA33 AK9 AP37 AV32 F28 M24
VSS_252 VSS_317 VSS_122 VSS_187 VSS_6 VSS_71
AA6 AL13 AP38 AV37 F30 M26
VSS_253 VSS_318 VSS_123 VSS_188 VSS_7 VSS_72
AB5 AL14 AP39 AV6 F32 M28
VSS_254 VSS_319 VSS_124 VSS_189 VSS_8 VSS_73
AC34 AL15 AP4 AW12 F34 M30
VSS_255 VSS_320 VSS_125 VSS_190 VSS_9 VSS_74
AC35 AL16 AP40 AW32 F37 M34
VSS_256 VSS_321 VSS_126 VSS_191 VSS_10 VSS_75
AC36 AL17 AP9 AW34 F4 M36
VSS_257 VSS_322 VSS_127 VSS_192 VSS_11 VSS_76
AC4 AL19 AR11 AW35 F40 M39
VSS_258 VSS_323 VSS_128 VSS_193 VSS_12 VSS_77
AC8 AL20 AR13 AW37 F7 M4
VSS_259 VSS_324 VSS_129 VSS_194 VSS_13 VSS_78
AD3 AL21 AR15 AW4 G15 M7
VSS_260 VSS_325 VSS_130 VSS_195 VSS_14 VSS_79
AD33 AL22 AR17 AW6 G35 N10
VSS_261 VSS_326 VSS_131 VSS_196 VSS_15 VSS_80
AD37 AL23 AR19 AW8 G38 N16
VSS_262 VSS_327 VSS_132 VSS_197 VSS_16 VSS_81
AD38 AL25 AR2 AY12 G5 N3
VSS_263 VSS_328 VSS_133 VSS_198 VSS_17 VSS_82
AD39 AL27 AR21 AY3 G8 N33
VSS_264 VSS_329 VSS_134 VSS_199 VSS_18 VSS_83
AD40 AL29 AR23 AY32 H11 N5
VSS_265 VSS_330 VSS_135 VSS_200 VSS_19 VSS_84
AE1 AL31 AR25 AY6 H13 N8
VSS_266 VSS_331 VSS_136 VSS_201 VSS_20 VSS_85
AE33 AL33 AR27 B10 H16 P1
VSS_267 VSS_332 VSS_137 VSS_202 VSS_21 VSS_86
AE35 AL35 AR29 B24 H18 P32
VSS_268 VSS_333 VSS_138 VSS_203 VSS_22 VSS_87
AE37 AL37 AR30 B26 H20 P35
VSS_269 VSS_334 VSS_139 VSS_204 VSS_23 VSS_88
AE5 AL39 AR32 B28 H22 P4
VSS_270 VSS_335 VSS_140 VSS_205 VSS_24 VSS_89
AE6 AL4 AR34 B30 H24 P40
VSS_271 VSS_336 VSS_141 VSS_206 VSS_25 VSS_90
AE7 AL6 AR35 B32 H26 P7
VSS_272 VSS_337 VSS_142 VSS_207 VSS_26 VSS_91
AE8 AL7 AR37 B34 H28 R37
VSS_273 VSS_338 VSS_143 VSS_208 VSS_27 VSS_92
AF33 AL9 AR4 C12 H30 R38
VSS_274 VSS_339 VSS_144 VSS_209 VSS_28 VSS_93
AF35 AM1 AR6 C13 H32 R39
VSS_275 VSS_340 VSS_145 VSS_210 VSS_29 VSS_94
AF37 AM10 AR7 C2 H34 R5
VSS_276 VSS_341 VSS_146 VSS_211 VSS_30 VSS_95
AF39 AM11 AR9 C37 H37 R8
VSS_277 VSS_342 VSS_147 VSS_212 VSS_31 VSS_96
AF4 AM2 AT13 C39 H4 T2
VSS_278 VSS_343 VSS_148 VSS_213 VSS_32 VSS_97
AG1 AM25 AT15 C5 H40 T34
VSS_279 VSS_344 VSS_149 VSS_214 VSS_33 VSS_98
AG2 AM29 AT16 C8 H7 T35
VSS_280 VSS_345 VSS_150 VSS_215 VSS_34 VSS_99
AG3 AM3 AT17 D11 H9 T36
VSS_281 VSS_346 VSS_151 VSS_216 VSS_35 VSS_100
AG33 AM33 AT18 D15 J10 T8
VSS_282 VSS_347 VSS_152 VSS_217 VSS_36 VSS_101
AG37 AM37 AT20 D18 J12 U3
VSS_283 VSS_348 VSS_153 VSS_218 VSS_37 VSS_102
AG39 AM39 AT22 D20 J14 U32
VSS_284 VSS_349 VSS_154 VSS_219 VSS_38 VSS_103
AG4 AM4 AT27 D22 J16 U4
VSS_285 VSS_350 VSS_155 VSS_220 VSS_39 VSS_104
AG6 AM9 AT32 D24 J3 U6
VSS_286 VSS_351 VSS_156 VSS_221 VSS_40 VSS_105
AG7 AN13 AT37 D26 J35 V35
VSS_287 VSS_352 VSS_157 VSS_222 VSS_41 VSS_106
AH34 AN14 AT39 D28 J38 V37
VSS_288 VSS_353 VSS_158 VSS_223 VSS_42 VSS_107
AH35 AN16 AT4 D30 J5 V39
VSS_289 VSS_354 VSS_159 VSS_224 VSS_43 VSS_108
AH36 AN18 AT9 D32 J8 V6
VSS_290 VSS_355 VSS_160 VSS_225 VSS_44 VSS_109
AH37 AN20 AU1 D36 K1 V8
VSS_291 VSS_356 VSS_161 VSS_226 VSS_45 VSS_110
AH4 AN22 AU10 D39 K10 W33
VSS_292 VSS_357 VSS_162 VSS_227 VSS_46 VSS_111
AJ11 AN24 AU11 D4 K14 W4
VSS_293 VSS_358 VSS_163 VSS_228 VSS_47 VSS_112
AJ2 AN26 AU12 D7 K15 Y35
VSS_294 VSS_359 VSS_164 VSS_229 VSS_48 VSS_113
AJ25 AN27 AU2 D9 K18 Y37
VSS_295 VSS_360 VSS_165 VSS_230 VSS_49 VSS_114
AJ29 AN28 AU26 E10 K20 Y5
VSS_296 VSS_361 VSS_166 VSS_231 VSS_50 VSS_115
AJ33 AN29 AU28 E11 K22 Y8
VSS_297 VSS_362 VSS_167 VSS_232 VSS_51 VSS_116
AJ37 AN30 AU29 E13 K24
VSS_298 VSS_363 VSS_168 VSS_233 VSS_52
AJ38 AN31 AU3 E14 K26
VSS_299 VSS_364 VSS_169 VSS_234 VSS_53
AJ39 AN32 AU30 E16 K28
VSS_300 VSS_365 VSS_170 VSS_235 VSS_54
AJ4 AN33 AU31 E3 K30
VSS_301 VSS_366 VSS_171 VSS_236 VSS_55
AJ40 AN34 AU33 E35 K34
VSS_302 VSS_367 VSS_172 VSS_237 VSS_56
AJ5 AN35 AU34 E38 K37
VSS_303 VSS_368 VSS_173 VSS_238 VSS_57
AJ6 AN36 AU35 E5 K4
VSS_304 VSS_369 VSS_174 VSS_239 VSS_58
AJ7 AN37 AU36 E8 K40
VSS_305 VSS_370 VSS_175 VSS_240 VSS_59
AJ8 AN4 AU37 E9 K7
VSS_306 VSS_371 VSS_176 VSS_241 VSS_60
AK12 AN5 AU39 F1 K8
VSS_307 VSS_372 VSS_177 VSS_242 VSS_61
AK2 AN6 AU4 F10 L10
VSS_308 VSS_373 VSS_178 VSS_243 VSS_62
AK24 AN7 AU5 F12 L16
VSS_309 VSS_374 VSS_179 VSS_244 VSS_63
AK27 AN8 AU6 F14 L5
VSS_310 VSS_375 VSS_180 VSS_245 VSS_64
AK29 AN9 AU7 F16 L8
VSS_311 VSS_376 VSS_181 VSS_246 VSS_65

SOCKET_1200P SOCKET_1200P SOCKET_1200P


12001-00280300 12001-00280300 12001-00280300

GND GND GND GND GND GND

ILM2
ILM1

Change BOM (R1.02)


1. ILM + COVER P/N : 13020-00061900
2. BACKPLATE P/N : 13020-00062000 (替代料 13020-00061300)
各別加入 BOM 內, Location 皆為 ILM1 , ILM2 Title : LGA1200 (GND)

ASUSTek Computer Inc.


Engineer: Aaron Su
Size Project Name Rev
ILM2
A3 Maximus XII Extreme R1.01
ILM1
13020-05100100 13020-00064200 Date: Thursday, December 12, 2019 Sheet 37 of 152
P_+VCCSTG_PVCC_10

1
OR +VCCSTG_REF_10 PC6038
1UF/25V
PR6028 0Ohm +5VDUAL_AUX mbs_c0603
20190815不支援XDP移除

2
1 2 20191030改走0OHM PU6005
N/A +3VSB RT7276GQW PR6030
9 3 GND 100KOhm +VCCSTG
VIN1 PVCC
10 5 1 2
VIN2 PGOOD
8 P_+VCCSTG_PG_5
BOOT

1
PC6034 PC6035 PC6036 1 7 P_+VCCSTG_Boot_10
EN SW2
+3VSB_ATX

1
22UF/6.3V 22UF/6.3V 22UF/6.3V 4 6 PC6039
SS SW1

P_+VCCSTG_SW_S
mbs_c0603 mbs_c0603 mbs_c0603 P_+VCCSTG_SS_10 11 2 0.1UF/16V

1
GND3 FB

1
PR6027 PC6037 12 mbs_c0603
GND4

2
8.2KOhm 47NF/6.3V 13 PL6020
GND5
5% 1 2

2
/X GND GND GND

2
2.2UH

1
PR6026

2
8.2KOhm GND GND
5% PJP6002
/X PWR_FB_SHORTPIN

2
+VCCSTG_REF_10 /X

1
PC6040 PC6041 PC6042
22UF/6.3V 22UF/6.3V 22UF/6.3V

1
/X FB=0.765V PR6032 PR6033 mbs_c0603 mbs_c0603 mbs_c0603

2
PR6038 /X PQ6004B 6.65KOhm 1KOhm
8.2KOhm 5 2N7002KDW 1 2 1 2
1 2 5% P_+VCCSTG_FB_10

4
21,23,45,66,72,115 S_SLPS4#_SIO

1
PR6023 PR6031 GND GND GND

6
8.2KOhm 5% PQ6004A 20KOhm
1 2 2 2N7002KDW
21,23,45,54,66,72 S_SLPS3#
/X GND
1

2
PR6034
0Ohm 5%
GND 1 2
+VCCSTG_REF_3933_10 80
20190905
3
3

D
2
PR6025 20160523 10mV/step, Source是超壓; Sink是降壓
0Ohm 5% PQ6005 PR6024
/X 11 H2N7002 0Ohm
13 CPU_VCCIO_PWR_GATEB_10
1 2 G /X
S
2 /X
2

GND

<Variant Name>

Title :
VCCSTG,VCCSTG_OUT
ASUSTek Computer Inc.
Engineer: Cisco Wang
Size Project Name Rev
Custom Maximus XII Extreme R1.00

Date: Thursday, December 12, 2019 Sheet 30 of 152


33 D4_DQ_A[0:63]

33 D4_MAA[0:16] DIMM_A1A
234 280
A17 DQ63
82 135 D4_DQ_A63
A16_RAS_N DQ62
D4_MAA16 86 273 D4_DQ_A62
A15_CAS_N DQ61
D4_MAA15 228 128 D4_DQ_A61
A14_WE_N DQ60
D4_MAA14 232 282 D4_DQ_A60
A13 DQ59
D4_MAA13 65 137 D4_DQ_A59
A12 DQ58
D4_MAA12 210 275 D4_DQ_A58
A11 DQ57
D4_MAA11 225 130 D4_DQ_A57
A10 DQ56
D4_MAA10 66 269 D4_DQ_A56
A9 DQ55
D4_MAA9 68 124 D4_DQ_A55
A8 DQ54
D4_MAA8 211 262 D4_DQ_A54
A7 DQ53
D4_MAA7 69 117 D4_DQ_A53
D4_MAA6 213
A6 DQ52
271 D4_DQ_A52 20190728 Remove DIMMA2
A5 DQ51
D4_MAA5 214
A4 DQ50
126 D4_DQ_A51 Allen
D4_MAA4 71 264 D4_DQ_A50
A3 DQ49
D4_MAA3 216 119 D4_DQ_A49
A2 DQ48
D4_MAA2 72 258 D4_DQ_A48
A1 DQ47
D4_MAA1 79 113 D4_DQ_A47
A0 DQ46
D4_MAA0 251 D4_DQ_A46
DQ45
224 106 D4_DQ_A45
33 D4_BAA1 BA1 DQ44
81 260 D4_DQ_A44
33 D4_BAA0 BA0 DQ43
207 115 D4_DQ_A43
33 D4_BGA1 BG1 DQ42
63 253 D4_DQ_A42
33 D4_BGA0 BG0 DQ41
108 D4_DQ_A41
DQ40
218 247 D4_DQ_A40
33 D4_MA_CLK1 CK1P DQ39
219 102 D4_DQ_A39
33 D4_MA_CLK#1 CK1N DQ38
74 240 D4_DQ_A38
33 D4_MA_CLK0 CK0P DQ37
75 95 D4_DQ_A37
33 D4_MA_CLK#0 CK0N DQ36
249 D4_DQ_A36
DQ35
235 104 D4_DQ_A35
C2 DQ34
D4_CS_A#3 237 242 D4_DQ_A34
S3_N_C1 DQ33
D4_ODT_A3 93 97 D4_DQ_A33
S2_N_C0 DQ32
89 188 D4_DQ_A32
33 D4_CS_A#1 S1_N DQ31
84 43 D4_DQ_A31
33 D4_CS_A#0 S0_N DQ30
181 D4_DQ_A30
DQ29
203 36 D4_DQ_A29
33 D4_CKE_A1 CKE1 DQ28 33 D4_MA_CLK3
60 190 D4_DQ_A28 D4_MA_CLK3
33 D4_CKE_A0 CKE0 DQ27 33 D4_MA_CLK#3
45 D4_DQ_A27 D4_MA_CLK#3
DQ26 33 D4_MA_CLK2
91 183 D4_DQ_A26 D4_MA_CLK2
33 D4_ODT_A1 ODT1 DQ25 33 D4_MA_CLK#2
87 38 D4_DQ_A25 D4_MA_CLK#2
33 D4_ODT_A0 ODT0 DQ24
177 D4_DQ_A24
DQ23
32 D4_DQ_A23
DQ22
199 170 D4_DQ_A22
CB7 DQ21
D4_MA_CLK#3 54 25 D4_DQ_A21
CB6 DQ20 33 D4_CS_A#3
+VDDQ D4_MA_CLK3 192 179 D4_DQ_A20 D4_CS_A#3
CB5 DQ19 33 D4_CS_A#2
Follow X99 47 34 D4_DQ_A19 D4_CS_A#2
CB4 DQ18
201 172 D4_DQ_A18
CB3 DQ17 33 D4_CKE_A3
2

D4_MA_CLK#2 56 27 D4_DQ_A17 D4_CKE_A3


CB2 DQ16 33 D4_CKE_A2
D4R1 D4_MA_CLK2 194 166 D4_DQ_A16 D4_CKE_A2
CB1 DQ15
240Ohm D4_CKE_A3 49 21 D4_DQ_A15
CB0 DQ14 33 D4_ODT_A3
/X/DDR4 D4_CKE_A2 159 D4_DQ_A14 D4_ODT_A3
DQ13 33 D4_ODT_A2
1% 222 14 D4_DQ_A13 D4_ODT_A2
33 D4_A_PAR PAR DQ12
1

58 168 D4_DQ_A12
RESET_N DQ11
S_D4_RESET#_R 78 23 D4_DQ_A11
EVENT_N DQ10
CHA_DIMM0_TS_EVENT# 208 161 D4_DQ_A10
33 D4_A_ALERT# ALERT_N DQ9
62 16 D4_DQ_A9
33 D4_A_ACT# ACT_N DQ8
155 D4_DQ_A8
DQ7
10 D4_DQ_A7
Address A0 238
SA2
DQ6
DQ5
148 D4_DQ_A6 20190731:Add DIMM expander
140 3 D4_DQ_A5
SA1 DQ4
139 157 D4_DQ_A4
SA0 DQ3
12 D4_DQ_A3
DQ2
150 D4_DQ_A2
DQ1
GND 5 D4_DQ_A1
DQ0
285 D4_DQ_A0
40,52 S_SMBDATA_DDR SDA
S_SMBDATA_DDR 141
40,52 S_SMBCLK_DDR SCL
S_SMBCLK_DDR
144
RFU2
227
RFU1
D4_CS_A#2 205
RFU0
1

D4C5 D4C6 230 +VDDQ


SAVE_N_NC
330PF/50V 330PF/50V +VDDQ D4_ODT_A2
/X/DDR4 /X/DDR4 D4R103
2

1 2 0Ohm 197 51
DQS8P DQS17P
/X mbs_r0603 196 52
DQS8N DQS17N
278 132
33 D4_DQS_A7 DQS7P DQS16P
GND GND 277 133
33 D4_DQS_A#7 DQS7N DQS16N
267 121
33 D4_DQS_A6 DQS6P DQS15P
266 122
33 D4_DQS_A#6 DQS6N DQS15N
256 110
33 D4_DQS_A5 DQS5P DQS14P
255 111
33 D4_DQS_A#5 DQS5N DQS14N
245 99
33 D4_DQS_A4 DQS4P DQS13P
244 100
33 D4_DQS_A#4 DQS4N DQS13N
186 40
33 D4_DQS_A3 DQS3P DQS12P
185 41
33 D4_DQS_A#3 DQS3N DQS12N
175 29
33 D4_DQS_A2 DQS2P DQS11P
174 30
33 D4_DQS_A#2 DQS2N DQS11N
164 18
33 D4_DQS_A1 DQS1P DQS10P
163 19
33 D4_DQS_A#1 DQS1N DQS10N
153 7
33 D4_DQS_A0 DQS0P DQS9P
152 8
33 D4_DQS_A#0 DQS0N DQS9N

DDR4_DIMM_288P
12002-00096300

DIMM A1,B1 ==> 黑

40,45 S_D4_RESET#_R
S_D4_RESET#_R teknisi indonesia
1

D4C7
0.1UF/10V
/X/DDR4
2

Put One Caps Per DIMM Slot


GND

<Variant Name>

Title :
DDR4 Channel A
ASUS TeK Computer INC
Engineer: Aaron_Su
Size Project Name Rev
A2 Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 39 of 152


34 D4_DQ_B[0:63]

34 D4_MAB[0:16] DIMM_B1A
234 280
A17 DQ63
82 135 D4_DQ_B63
A16_RAS_N DQ62
D4_MAB16 86 273 D4_DQ_B62
A15_CAS_N DQ61
D4_MAB15 228 128 D4_DQ_B61
A14_WE_N DQ60
D4_MAB14 232 282 D4_DQ_B60
A13 DQ59
D4_MAB13 65 137 D4_DQ_B59
A12 DQ58
D4_MAB12 210 275 D4_DQ_B58
A11 DQ57
D4_MAB11 225 130 D4_DQ_B57
A10 DQ56
D4_MAB10 66 269 D4_DQ_B56
A9 DQ55
D4_MAB9 68 124 D4_DQ_B55
A8 DQ54
D4_MAB8 211 262 D4_DQ_B54
D4_MAB7 69
A7 DQ53
117 D4_DQ_B53 20190728 Remove DIMMB2
A6 DQ52
D4_MAB6 213
A5 DQ51
271 D4_DQ_B52 Allen
D4_MAB5 214 126 D4_DQ_B51
A4 DQ50
D4_MAB4 71 264 D4_DQ_B50
A3 DQ49
D4_MAB3 216 119 D4_DQ_B49
A2 DQ48
D4_MAB2 72 258 D4_DQ_B48
A1 DQ47
D4_MAB1 79 113 D4_DQ_B47
A0 DQ46
D4_MAB0 251 D4_DQ_B46
DQ45
224 106 D4_DQ_B45
34 D4_BAB1 BA1 DQ44
81 260 D4_DQ_B44
34 D4_BAB0 BA0 DQ43
207 115 D4_DQ_B43
34 D4_BGB1 BG1 DQ42
63 253 D4_DQ_B42
34 D4_BGB0 BG0 DQ41
108 D4_DQ_B41
DQ40
218 247 D4_DQ_B40
34 D4_MB_CLK1 CK1P DQ39
219 102 D4_DQ_B39
34 D4_MB_CLK#1 CK1N DQ38
74 240 D4_DQ_B38
34 D4_MB_CLK0 CK0P DQ37
75 95 D4_DQ_B37
34 D4_MB_CLK#0 CK0N DQ36
249 D4_DQ_B36
DQ35
235 104 D4_DQ_B35
C2 DQ34
D4_CS_B#3 237 242 D4_DQ_B34
S3_N_C1 DQ33
D4_ODT_B3 93 97 D4_DQ_B33
S2_N_C0 DQ32
89 188 D4_DQ_B32
34 D4_CS_B#1 S1_N DQ31
84 43 D4_DQ_B31
34 D4_CS_B#0 S0_N DQ30
181 D4_DQ_B30
DQ29
203 36 D4_DQ_B29
34 D4_CKE_B1 CKE1 DQ28
60 190 D4_DQ_B28
34 D4_CKE_B0 CKE0 DQ27
45 D4_DQ_B27
DQ26 34 D4_MB_CLK3
91 183 D4_DQ_B26 D4_MB_CLK3
34 D4_ODT_B1 ODT1 DQ25 34 D4_MB_CLK#3
87 38 D4_DQ_B25 D4_MB_CLK#3
34 D4_ODT_B0 ODT0 DQ24 34 D4_MB_CLK2
177 D4_DQ_B24 D4_MB_CLK2
DQ23 34 D4_MB_CLK#2
32 D4_DQ_B23 D4_MB_CLK#2
DQ22
199 170 D4_DQ_B22
CB7 DQ21
D4_MB_CLK#3 54 25 D4_DQ_B21
CB6 DQ20
+VDDQ D4_MB_CLK3 192 179 D4_DQ_B20
CB5 DQ19
47 34 D4_DQ_B19
CB4 DQ18 34 D4_CS_B#3
Follow X99 201 172 D4_DQ_B18 D4_CS_B#3
CB3 DQ17 34 D4_CS_B#2
2

D4_MB_CLK#2 56 27 D4_DQ_B17 D4_CS_B#2


CB2 DQ16
D4R3 D4_MB_CLK2 194 166 D4_DQ_B16
CB1 DQ15 34 D4_CKE_B3
240Ohm D4_CKE_B3 49 21 D4_DQ_B15 D4_CKE_B3
CB0 DQ14 34 D4_CKE_B2
/X/DDR4 D4_CKE_B2 159 D4_DQ_B14 D4_CKE_B2
DQ13
1% 222 14 D4_DQ_B13
34 D4_B_PAR PAR DQ12 34 D4_ODT_B3
1

58 168 D4_DQ_B12 D4_ODT_B3


RESET_N DQ11 34 D4_ODT_B2
S_D4_RESET#_R 78 23 D4_DQ_B11 D4_ODT_B2
EVENT_N DQ10
CHB_DIMM0_TS_EVENT# 208 161 D4_DQ_B10
34 D4_B_ALERT# ALERT_N DQ9
62 16 D4_DQ_B9
34 D4_B_ACT# ACT_N DQ8
155 D4_DQ_B8
DQ7
+VDDSPD 10 D4_DQ_B7
DQ6
238 148 D4_DQ_B6
Address A0
140
SA2
SA1
DQ5
DQ4
3 D4_DQ_B5 20190731:Add DIMM expander
139 157 D4_DQ_B4
SA0 DQ3
12 D4_DQ_B3
DQ2
150 D4_DQ_B2
DQ1
GND 5 D4_DQ_B1
DQ0
285 D4_DQ_B0
39,52 S_SMBDATA_DDR SDA
S_SMBDATA_DDR 141
39,52 S_SMBCLK_DDR SCL
S_SMBCLK_DDR
144
RFU2
227
RFU1
D4_CS_B#2 205
RFU0
1

D4C9 D4C10 230 +VDDQ


SAVE_N_NC
330PF/50V 330PF/50V +VDDQ Follow M11A D4_ODT_B2
/X/DDR4 /X/DDR4 D4R104
2

1 2 0Ohm 197 51
DQS8P DQS17P
/X mbs_r0603 196 52
DQS8N DQS17N
278 132
34 D4_DQS_B7 DQS7P DQS16P
GND GND 277 133
34 D4_DQS_B#7 DQS7N DQS16N
267 121
34 D4_DQS_B6 DQS6P DQS15P
266 122
34 D4_DQS_B#6 DQS6N DQS15N
256 110
34 D4_DQS_B5 DQS5P DQS14P
255 111
34 D4_DQS_B#5 DQS5N DQS14N
245 99
34 D4_DQS_B4 DQS4P DQS13P
244 100
34 D4_DQS_B#4 DQS4N DQS13N
186 40
34 D4_DQS_B3 DQS3P DQS12P
185 41
34 D4_DQS_B#3 DQS3N DQS12N
175 29
34 D4_DQS_B2 DQS2P DQS11P
174 30
34 D4_DQS_B#2 DQS2N DQS11N
164 18
34 D4_DQS_B1 DQS1P DQS10P
163 19
34 D4_DQS_B#1 DQS1N DQS10N
153 7
34 D4_DQS_B0 DQS0P DQS9P
152 8
34 D4_DQS_B#0 DQS0N DQS9N

DDR4_DIMM_288P
12002-00096300

DIMM A1,B1 ==> 黑

39,45 S_D4_RESET#_R
S_D4_RESET#_R
1

D4C11 X5R D4C12 X5R


0.1UF/10V 0.1UF/10V
/X/DDR4 /X/DDR4
2

Put One Caps Per DIMM Slot


GND GND

<Variant Name>

Title : DDR4 Channel B


ASUS TeK Computer INC
Engineer: Aaron_Su
Size Project Name Rev
A2 Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 40 of 152


+VPPDDR +VPPDDR
DIMM_A1B DIMM_B1B
142 1 142 1
VPP4 12V_1 VPP4 12V_1
143 145 143 145
VPP3 12V_0 VPP3 12V_0
288 288
VPP2 VPP2
286 286
VPP1 VPP1
287 +VDDSPD 287 +VDDSPD
VPP0 VPP0
+VTTDDR +VTTDDR

77 284 77 284
VTT1 VDDSPD VTT1 VDDSPD
221 221
VTT0 VTT0

1
+VDDQ +VDDQ
D4C13 D4C14
59 0.1UF/16V 59 0.1UF/16V
VDD25 VDD25

2
61 /DDR4 61 /DDR4
64
VDD24
64
VDD24 20190728 Remove DIMMB2
67
VDD23
GND 20190728 Remove DIMMA2 67
VDD23
GND Allen
VDD22 VDD22
70
VDD21 VREFCA
146 Allen 70
VDD21 VREFCA
146
73 D4_VREFCA_A0 73 D4_VREFCA_B0
VDD20 VDD20
76 76
VDD19 VDD19
80 80
VDD18 VDD18
83 83
VDD17 VDD17
85 85
VDD16 VDD16
88 88
VDD15 VDD15
90 90
VDD14 VDD14
92 92
VDD13 VDD13
204 204
VDD12 VDD12
206 289 206 289
VDD11 P_GND1 VDD11 P_GND1
209 290 209 290
VDD10 P_GND2 VDD10 P_GND2
212 291 212 291
VDD9 P_GND3 VDD9 P_GND3
215 215
VDD8 33 D4_VREFCA_A0 VDD8 34 D4_VREFCA_B0
217 217
VDD7 VDD7
220 220
VDD6 VDD6
223 X7R X7R 223 X7R X7R
VDD5 VDD5
1

1
226 D4C38 D4C39 226 D4C45 D4C46
VDD4 VDD4
229 /DDR4 /X/DDR4 229 /DDR4 /X/DDR4
VDD3 VDD3
231 0.1UF/16V 0.1UF/16V 231 0.1UF/16V 0.1UF/16V
VDD2 VDD2
2

2
233 233
VDD1 VDD1
236 236
VDD0 VDD0

GND GND
2 147 2 147
VSS93 VSS46 VSS93 VSS46
4 149 4 149
VSS92 VSS45 VSS92 VSS45
6 151 6 151
VSS91 VSS44 VSS91 VSS44
9 154 9 154
VSS90 VSS43 VSS90 VSS43
11 156 11 156
VSS89 VSS42 VSS89 VSS42
13 158 13 158
VSS88 VSS41 VSS88 VSS41
15 160 15 160
VSS87 VSS40 VSS87 VSS40
17 162 17 162
VSS86 VSS39 VSS86 VSS39
20 165 20 165
VSS85 VSS38 VSS85 VSS38
22 167 22 167
VSS84 VSS37 VSS84 VSS37
24 169 24 169
VSS83 VSS36 VSS83 VSS36
26 171 26 171
VSS82 VSS35 VSS82 VSS35
28 173 28 173
VSS81 VSS34 VSS81 VSS34
31 176 31 176
VSS80 VSS33 VSS80 VSS33
33 178 33 178
VSS79 VSS32 VSS79 VSS32
35 180 35 180
VSS78 VSS31 VSS78 VSS31
37 182 37 182
VSS77 VSS30 VSS77 VSS30
39 184 39 184
VSS76 VSS29 VSS76 VSS29
42 187 42 187
VSS75 VSS28 VSS75 VSS28
44 189 44 189
VSS74 VSS27 VSS74 VSS27
46 191 46 191
VSS73 VSS26 VSS73 VSS26
48 193 48 193
VSS72 VSS25 VSS72 VSS25
50 195 50 195
VSS71 VSS24 VSS71 VSS24
53 198 53 198
VSS70 VSS23 VSS70 VSS23
55 200 55 200
VSS69 VSS22 VSS69 VSS22
57 202 57 202
VSS68 VSS21 VSS68 VSS21
94 239 94 239
VSS67 VSS20 VSS67 VSS20
96 241 96 241
VSS66 VSS19 VSS66 VSS19
98 243 98 243
VSS65 VSS18 VSS65 VSS18
101 246 101 246
VSS64 VSS17 VSS64 VSS17
103 248 103 248
VSS63 VSS16 VSS63 VSS16
105 250 105 250
VSS62 VSS15 VSS62 VSS15
107 252 107 252
VSS61 VSS14 VSS61 VSS14
109 254 109 254
VSS60 VSS13 VSS60 VSS13
112 257 112 257
VSS59 VSS12 VSS59 VSS12
114 259 114 259
VSS58 VSS11 VSS58 VSS11
116 261 116 261
VSS57 VSS10 VSS57 VSS10
118 263 118 263
VSS56 VSS9 VSS56 VSS9
120 265 120 265
VSS55 VSS8 VSS55 VSS8
123 268 123 268
VSS54 VSS7 VSS54 VSS7
125 270 125 270
VSS53 VSS6 VSS53 VSS6
127 272 127 272
VSS52 VSS5 VSS52 VSS5
129 274 129 274
VSS51 VSS4 VSS51 VSS4
131 276 131 276
VSS50 VSS3 VSS50 VSS3
134 279 134 279
VSS49 VSS2 VSS49 VSS2
136 281 136 281
VSS48 VSS1 VSS48 VSS1
138 283 138 283
VSS47 VSS0 VSS47 VSS0

GND DIMM A1,B1 ==> 黑 GND GND DIMM A1,B1 ==> 黑 GND

DDR4_DIMM_288P DDR4_DIMM_288P
12002-00096300 12002-00096300

+3V
+VDDSPD
07013-00240000
D3F502
1 2
<Variant Name>

1.75A/6V
Title : DDR4 (Power)
Engineer: Aaron_Su
預留VDDSPD Fuse, DOA/FA改善Solution. ASUS TeK Computer INC
Size Project Name Rev

非ROG機種請自行改小顆Fuse. A3 Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 41 of 152


Remove SBK_LED

+3VSB

1
SR1
8.2KOhm
/CPTH

2
SU1A
IPU BE36 AV29
GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST# PCH_PLTRST# 42,72
PME# PCH_PLTRST#
ST1 1 R15
RSVD2
ST2 1 TP_PCH_R15 R13 Y47
RSVD1 GPP_K16/GSXCLK
TP_PCH_R13 Y46 20190808 remove GPP_K12 B_CIO_PLUG_EVENT_HD1
GPP_K12/GSXDOUT
Y48
GPP_K13/GSXSLOAD
W46
GPP_K14/GSXDIN C_DOC0 86
AL37 AA45
VSS GPP_K15/GSXSRESET# C_DOC1 86
ST4 1 PCH_AL37 AN35
TP1
TP_PCH_TP1
AU41 AL47
114 F_SPI_MOSI SPI0_MOSI GPP_E3/CPU_GP0
F_SPI_MOSI IPU BA45 AM45 20190808 remove GPP_E7 B_CIO_PLUG_EVENT_HD1
114 F_SPI_MISO SPI0_MISO GPP_E7/CPU_GP1
AY47 BF32
2017.11.29:Rename SPI netname 114 F_SPI_CS0# SPI0_CS0# GPP_B3/CPU_GP2 M.2_BT_RF_KILL# 87
AW47 BC33 M.2_BT_RF_KILL#
114 F_SPI_CLK SPI0_CLK GPP_B4/CPU_GP3
ST5 1 IPU AW48
SPI0_CS1#
TP_SPI_CS1# AE44 +BAT_3V
GPP_H18/SML4ALERT#
IPU AY48 AJ46
75 F_SPI_IO2 SPI0_IO2 GPP_H17/SML4DATA
IPU BA46 AE43
75 F_SPI_IO3 SPI0_IO3 GPP_H16/SML4CLK
ST6 1 AT40 AC47
SPI0_CS2# GPP_H15/SML3ALERT#
TP_SPI_CS2# BE19 AD48 GPP_H_15 20190801 remove GPP_H14 X_2X16_DET#

1
52 O_PLED_BLNK# GPP_D1/SPI1_CLK/SBK1/BK1 GPP_H14/SML3DATA
BF19 AF47 SR3
GPP_D0/SPI1_CS#/SBK0/BK0 GPP_H13/SML3CLK X_1X16_DET# 60
20191030 Remove GPP_D3 O2_SMI# BF18 AB47 IPD X_1X16_DET# 1MOhm
GPP_D3/SPI1_MOSI/SBK3/BK3 GPP_H12/SML2ALERT#
BE18 AD47 /CPTH
GPP_D2/SPI1_MISO/SBK2/BK2 GPP_H11/SML2DATA M.2_WIFI_RF_KILL# 87
BC17 AE48 M.2_WIFI_RF_KILL#

2
GPP_D22/SPI1_IO3 GPP_H10/SML2CLK
BD17 BB44
2019007 Remove RTD3 PCIEX16 GPP_D21/SPI1_IO2 INTRUDER#
S_INTRUDER#
FH82Z490 1 AT6
1 OF
02001-00860000 13

ESPI Flash sharing mode


FOLLOW CRB +3VSB 0:Master ATTACHED FLASH SHARING
1:SLAVE ATTACEHD FLASH SHARING
PCH HAS INTERNAL WEAK PD
2

CFL Rev1.0 : NO PU
RVP Stuff SR1868 SR4
For BUF 8.2KOhm
/CPTH
1%
1

20190808 Remove follow Z490G


F_SPI_MOSI
2

BOOT HALT ENABLED IF LOW SR5


CONSENT STRAP IS ENABLE IF LOW 4.7KOHM
PCH HAS INTERNAL WEAK PU PCH HAS INTERNAL WEAK PU /X/CPTH
For External Flash Protection
1

GND +3VSB

FOLLOW CRB

2
RVP Stuff SR1868 PCH_AL37 SR15
For BUF
4.7KOHM
/CPTH

1
SR18 1%

1
8.2KOhm Z390 CRB
/X/CPTH
20190808 Remove follow Z490G

2
GPP_H_15
JTAG ODT IS DISABLED IF LOW GND
PESONALITY STRAP IS ENABLE IF LOW
PCH HAS INTERNAL WEAK PU PCH HAS INTERNAL WEAK PU
For External Flash Protection
+3VSB JTAG ODT IS DISABLED IF LOW
Follow RVP1.0.
eSPI Flash Sharing Mode Reserved
This signal has a weak internal pull-down. External pull-up is required. Recommend 100K if pulled
0 = Master Attached Flash Sharing (MAFS) enabled (Default) up to 3.3V or 75K if pulled up to 1.8V.
1 = Slave Attached Flash Sharing (SAFS) enabled. This strap should sample HIGH. There should NOT be
Notes: any on-board device driving it to opposite direction
1. The internal pull-down is disabled after RSMRST# de-asserts. during strap sampling.
2. This signal is in the primary well.
+3VSB Warning: This strap must be configured to ‘0’
(SAFS is disabled) if the eSPI or LPC strap is configured to ‘0’ (eSPI is disabled)
If not CLK buffer ,SU2 &SR1642不上件
改上SR561
1

SR1642
8.2KOhm
/CPTH
SU2
2

1 A 5
72 O2_PLTRST# VCC

2 B S_PLTRST# 35,55,66,81
42,72 PCH_PLTRST#

3 4
GND
Y
SN74AUP1G08DRLR
/CPTH

GND Title : CPTH (PCI/SPI)


0Ohm 1 2 SR561
/X/CPTH
ASUSTek Computer Inc.
Engineer: Aaron_Su
Size Project Name Rev
A3 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 42 of 152


SU1C
CRB_GFX_SEL AR2 F44
CL_CLK PCIE15_RXN/SATA2_RXN T_SATA_RXN2 79
CRB: LOW AT5 E45
+3VSB
CLINK(No AMT) AU4
CL_DATA PCIE15_RXP/SATA2_RXP
B40
T_SATA_RXP2 79
CL_RST# PCIE15_TXN/SATA2_TXN T_SATA_TXN2 79
C40
0 NORMAL GFX PCIE15_TXP/SATA2_TXP T_SATA_TXP2 79
ST59 1 P48
1 CUSTOMER GFX ST61 1 GPP_K_8 V47
GPP_K8
L41 SATA6G_34
RSVD ST62 1 GPP_K_9 V48
GPP_K9 PCIE16_RXN/SATA3_RXN
M40
T_SATA_RXN3 79

1
GPP_K10 PCIE16_RXP/SATA3_RXP T_SATA_RXP3 79
SR184 20190801 Remove SWITCH_CFG6 ST630 1 GPP_K_10 W47 B41
GPP_K11 PCIE16_TXN/SATA3_TXN T_SATA_TXN3 79
CRB_PCB_STYLE CRB: HIGH 8.2KOhm GPP_K_11 C41
PCIE16_TXP/SATA3_TXP T_SATA_TXP3 79
/CPTH L47
35 SWITCH_CFG6 GPP_K0
L46 K43
0 SV ADVANCE MENU

2
81 L1_DEV_OFF# GPP_K1 PCIE17_RXN/SATA4_RXN PE_M2_2_RXN0/SA 97
U48 K44
81 O_X1_RST# GPP_K2 PCIE17_RXP/SATA4_RXP PE_M2_2_RXP0/SA 97
U47 A42
1 NORMAL MENU (DEFAULT) GPP_K3 PCIE17_TXN/SATA4_TXN PE_M2_2_TXN0/SA 97
CRB_EC_SCI# N48 B42
GPP_K4 PCIE17_TXP/SATA4_TXP PE_M2_2_TXP0/SA 97
N47
GPP_K5
CRB_SV_DET P47 P41
GPP_K6 PCIE18_RXN/SATA5_RXN PE_M2_2_RXN1 97
+3V_S0IX 20190731 Remove PCIEX16_2 RDT3 Allen R46 R40
GPP_K7 PCIE18_RXP/SATA5_RXP PE_M2_2_RXP1 97
C42
PCIE18_TXN/SATA5_TXN PE_M2_2_TXN1 97
AR42 D42
GPP_F10/SATA_SCLOCK PCIE18_TXP/SATA5_TXP PE_M2_2_TXP1 97
8.2KOhm 20190807 Remove PCIEX16_1 RDT3 Allen AR48
SR189 1 2 /X/CPTH Intel Q AU47
GPP_F11/SATA_SLOAD
M44 PCH_M.2_2
GPP_F13/SATA_SDATAOUT0 PCIE19_RXN PE_M2_2_RXN2 97
1 2 Intel Q CRB_GFX_SEL AU46 N42 +3V
GPP_F12/SATA_SDATAOUT1 PCIE19_RXP PE_M2_2_RXP2 97
SR191 /CPTH CRB_PCB_STYLE C44
PCIE19_TXN PE_M2_2_TXN2 97
8.2KOhm G36 D43
97 PE_M2_RXN3 PCIE9_RXN PCIE19_TXP PE_M2_2_TXP2 97
F36

1
97 PE_M2_RXP3 PCIE9_RXP
SR188 SR190 C34 R35 SR143
97 PE_M2_TXN3 PCIE9_TXN PCIE20_RXN PE_M2_2_RXN3 97
8.2KOhm 8.2KOhm D34 R37 8.2KOhm
97 PE_M2_TXP3 PCIE9_TXP PCIE20_RXP PE_M2_2_RXP3 97
/CPTH /X/CPTH K37 A44 /CPTH
97 PE_M2_RXN2 PCIE10_RXN PCIE20_TXN PE_M2_2_TXN3 97
J37 B44
2

2
97 PE_M2_RXP2 PCIE10_RXP PCIE20_TXP PE_M2_2_TXP3 97
C35
97 PE_M2_TXN2 PCIE10_TXN
B35 AK48
+3V_S0IX GND GND PCH_M.2_1 97 PE_M2_TXP2 G38
PCIE10_TXP GPP_E8/SATALED#
AH41
T_SATALED# 78
97 PE_M2_RXN1 PCIE11_RXN/SATA0A_RXN GPP_E0/SATAXPCIE0/SATAGP0
F39 AJ43
97 PE_M2_RXP1 PCIE11_RXP/SATA0A_RXP GPP_E1/SATAXPCIE1/SATAGP1
B36 AK47
97 PE_M2_TXN1 PCIE11_TXN/SATA0A_TXN GPP_E2/SATAXPCIE2/SATAGP2 Set 0 : SATA (default)
C36 AN47
97 PE_M2_TXP1 PCIE11_TXP/SATA0A_TXP GPP_F0/SATAXPCIE3/SATAGP3 Set 1 : PCIE
H42 AM46
1

97 PE_M2_RXN0/SA PCIE12_RXN/SATA1A_RXN GPP_F1/SATAXPCIE4/SATAGP4


SR185 J41 AM43
97 PE_M2_RXP0/SA PCIE12_RXP/SATA1A_RXP GPP_F2/SATAXPCIE5/SATAGP5
8.2KOhm D38 AM47
97 PE_M2_TXN0/SA PCIE12_TXN/SATA1A_TXN GPP_F3/SATAXPCIE6/SATAGP6
/X/CPTH E37 AM48 Server/Workstation only.
97 PE_M2_TXP0/SA PCIE12_TXP/SATA1A_TXP GPP_F4/SATAXPCIE7/SATAGP7
Intel
2

C45 AU48
79 T_SATA_RXN0 PCIE13_RXN/SATA0B_RXN GPP_F21/eDP_BKLTCTL
C46 AV46 20190731 Remove PCIEX16_2 RDT3 Allen
79 T_SATA_RXP0 PCIE13_RXP/SATA0B_RXP GPP_F20/eDP_BKLTEN
CRB_SV_DET B38 AV44
79 T_SATA_TXN0 PCIE13_TXN/SATA0B_TXN GPP_F19/eDP_VDDEN
C38 SR40
1

79 T_SATA_TXP0 PCIE13_TXP/SATA0B_TXP
SR186 AD3 /CPTH 1 619Ohm 2
THRMTRIP# H_THERMTRIP# 6,35
8.2KOhm D46 AF2 H_THERMTRIP#_R
/CPTH SATA6G_12 79 T_SATA_RXN1
C47
PCIE14_RXN/SATA1B_RXN PECI
AF3 SR44 1 /CPTH 2 30OHM
S_H_PECI 69
79 T_SATA_RXP1 PCIE14_RXP/SATA1B_RXP PM_SYNC S_PM_SYNC_H 35
C39 AG5
2

79 T_SATA_TXN1 PCIE14_TXN/SATA1B_TXN PLTRST_CPU# H_CPURST_SB# 35


D39 AE2
79 T_SATA_TXP1 PCIE14_TXP/SATA1B_TXP PM_DOWN H_PM_DOWN_S 35

2
1
GND 3 OF 13 SC6 SR41
FH82Z490
OD6 OD5 47PF/50V 1KOhm

1
02001-00860000 /X/CPTH /X/CPTH

2
Co-lay SR185 AND SR186 PADS

1
VPORT0402220MV05 VPORT0402220MV05

2
/X/PANEL /X/PANEL

GND
GND

Title CPTH
: (HOST/FAN/SATA)

ASUSTek Computer Inc.


Engineer: Aaron_Su
Size Project Name Rev
A2 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 44 of 152


+3VSB_HDA +3VSB

2
SU1D

1
SR104 BD11 BF36 SR1657
98 A_Z_BITCLK HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ ISH_GP6/SX_EXIT_HOLDOFF#
1KOhm BE10 AV32 SX_EXIT_HOLDOFF# 100KOhm
HDA_RST#/I2S1_SCLK GPP_A8/CLKRUN# CLK_REQ_SIO# 66
/X/CPTH IPD BE11 /S0IX
97 A_Z_SDIN0 HDA_SDI0/I2S0_RXD
SJP21 IPD BF10 BF41

2
HDA_SDI1/I2S1_RXD GPD11/LANPHYPC L1_LAN_DISABLE# 81

1
50 S_ME_UNLOCK
2 1 A_Z_SDOUT IPD BF12 BD42
98 A_Z_SDOUT HDA_SDO/I2S0_TXD GPD9/SLP_WLAN#
SHORTPIN IPD BG13 S_SLP_WLAN# S_SLPS0#

1
98 A_Z_SYNC HDA_SYNC/I2S0_SFRM
/X/SPTH SR105 BE12 BB46 +3VSB +3VSB_ATX
I2S1_TXD/SNDW2_DATA DRAM_RESET# ST781
8.2KOhm BD12 BE32 S_D4_RESET#
/X/CPTH
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT#
BF33 1
ST7811 MR request
GPP_B1/GSPI1_CS1#/TIME_SYNC1

2
BE29 CRB_GSPI1_CS#1 1

2
GPP_B0/GSPI0_CS1#
SR49 1 /CPTH 2 33Ohm IPD AM2 R47 CRB_GSPI0_CS#1 SR1827 SR60
32 H_HDA_SDO_R HDACPU_SDO GPP_K17/ADR_COMPLETE
H_HDA_SDO IPD AN3 AP29 1 ST112 /X/CPTH 1KOhm 1KOhm
32 H_HDA_SDI HDACPU_SDI GPP_B11/I2S_MCLK
GND 1 2 AM3 AU3 CRB_SSP_MCLK /CPTH /X/CPTH
32 H_HDA_SCLK HDACPU_SCLK SYS_PWROK PCH_SYSPWROK 54
SR50 /CPTH 33Ohm H_HDA_SCLK_R

1
/X/CPTH ST324 1 AV18 BB47
CNVi CLKREQ /X/CPTH ST325 1 M.2_BT_PCMCLK_R AW18
GPP_D8/I2S2_SCLK WAKE#
BE40 1 ST799 /X/CPTH
X_WAKE# 60,81,97
GPP_D7/I2S2_RXD GPD6/SLP_A#
SR1857 1 33Ohm 2 M.2_BT_PCMIN_R BA17 BF40 S_SLP_A# 1 ST800 /X/CPTH
87 S_M.2_WIFI_CLKREQ GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN#
SR1858 1 33Ohm 2 PCMOUT/CLKREQ_R BE16 BC28 S_SLP_LAN#
87 S_M.2_CRF_RST# GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0#
PCMFRM/CRF_RST#_R BF15 BF42 S_SLPS0# +3VSB_ERP
GPP_D20/DMIC_DATA0/SNDW4_DATA GPD4/SLP_S3# S_SLPS3# 21,23,30,54,66,72
BD16 BE42
CNVi RST# AV16
GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4#
BC42 1 ST7819
S_SLPS4#_PCH 66
GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5#
AW15 S_SLPS5# SR900
GPP_D17/DMIC_CLK1/SNDW3_CLK S_SLPS4#_SIO 21,23,30,66,72,115
BE45 2 0Ohm 1
GPD8/SUSCLK PCH_SUSCLK 36,87,97
AT4 1 BF44 PCH_SUSCLK /X/CPTH +3V
GPD0/BATLOW#

2
BE35 BATLOW#
GPP_A15/SUSACK#
BE47 BC37 SUSACK# SR64 SR38
52 S_RTCRST# RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK

2
BD46 SUSWARN# 8.2KOhm 8.2KOhm
52 S_SRTCRST# SRTCRST#
AT5 1 SR72 /CPTH /CPTH
AY42 BG44 1KOhm
52,54 O_PWROK PCH_PWROK GPD2/LAN_WAKE# L1_LAN_WAKE# 81

1
BA47 BG42 /X/CPTH BATLOW# for mobile
73 S_RSMRST# RSMRST# GPD1/ACPRESENT
S_RSMRST# BD39 TP_GPD_1 1 ST7820 20190806 TEST Pin Allen
SLP_SUS#

1
AW41 BE46 SLP_SUS#
53 S_DSWPWROK DSW_PWROK GPD3/PWRBTN# O_PWRBTN# 66
IPD BE25 AU2 BATLOW#
GPP_C2/SMBALERT# SYS_RESET# O_RSTCONO# 66,72
TLS_STRAP BE26 AW29 IPD H: No Reboot mode
52,60,114,115 S_SMBCLK_PCI GPP_C0/SMBCLK GPP_B14/SPKR S_SPKR 78
BF26 AE3 TP_GPD_1
52,60,115 S_SMBDATA_PCI GPP_C1/SMBDATA CPUPWRGD
IPD BF24 H_PWRGD_R AC Present
GPP_C5/SML0ALERT#

2
ESPI_LPC#_SEL BF25 AL3 1 ST1800 /X/CPTH 20190801 Remove ITP mode SC29

2
GPP_C3/SML0CLK ITP_PMODE
L1_SMBCLK BE24 AH4 ITP_PMODE 0.1UF/16V SR39 TOP SWAP
GPP_C4/SML0DATA PCH_JTAGX
L1_SMBDATA IPD BD33 AJ4 /X/CPTH 20KOHM

1
GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TMS
1 0Ohm 2 SR1663 PCH_HOT# BF27 AH3 /X/CPTH
66,72,73 O2_SMB2_CLK GPP_C6/SML1CLK PCH_JTAG_TDO
1 0Ohm 2 SR1664 PCH_SML1_CLK BE27 AH2
66,72,73 O2_SMB2_DATA GPP_C7/SML1DATA PCH_JTAG_TDI

1
PCH_SML1_DATA AJ3 20190812 Remove SR37
PCH_JTAG_TCK
S_JTAG_TCK GND
4 OF 13
GND
FH82Z490
02001-00860000
SJP6

H_PWRGD 35
H_PWRGD_R 2 1
SHORTPIN S_JTAG_TCK PCH_SUSCLK
LPT-H : PD
PLACE ALL SERIES /X/SPTH
RES CLOSE TO PCH

1
SR174 SR247
PLACE CLOSE TO PCH 51Ohm 8.2KOhm
/X/1151/XDP /X/CPTH
+VDDQ

2
2

for SLPS3
SR57 GND GND Fan Out
470Ohm

SJP3 1%
1

S_D4_RESET#_R 39,40
S_D4_RESET# 2 1
SHORTPIN
/X/SPTH
+VCCST
+3VSB SR13
1KOhm

+3VSB +3VSB_ATX S_JTAG_TCK 2 1


/X follow CRB reverse

2
SR1611 SR1651
8.2KOhm 8.2KOhm SR1772 SR1698
/X/CPTH /X/CPTH 8.2KOhm 8.2KOhm
/X/CPTH /X/CPTH

1
PLACE ALL SERIES RES CLOSE TO PCH SX_EXIT_HOLDOFF#

S_SLP_WLAN# L1_LAN_WAKE#

+3VSB +3VSB

LAN SMBUS SIO SMBUS +3VSB


2

SR166 SR167 +3VSB


499Ohm 499Ohm 20190812 Remove SR93 SR96

2
/CPTH /CPTH
1% 1% SR34 0 : LPC for EC
1

2
L1_SMBCLK 81 4.7KOhm 1 : eSPI for EC
L1_SMBCLK PCH_SML1_CLK /X/CPTH SR95
1% 4.7KOhm PCH HAS INTERNAL WEAK PD
L1_SMBDATA 81

1
L1_SMBDATA PCH_SML1_DATA /X/CPTH

1
1

SC31 SC32 SC27 SC28


/X/CPTH /X/CPTH /X/CPTH /X/CPTH ESPI_LPC#_SEL
10PF/50V 10PF/50V 10PF/50V 10PF/50V
2

TLS_STRAP PCH_HOT#

2
GND GND GND GND SR35 CRB PCH_HOT# to EC

2
20KOHM
/X/CPTH SR94 DCI ENABLE STRAP ENABLED IF SAMPLED HIGH
PCH HAS INTERNAL WEAK PD
1KOhm

1
/CPTH
1%

1
GND

GND
TLS Confidentiality

0 = Disable Intel ME Crypto Transport Layer


Security (TLS) cipher suite (no confidentiality).
1 = Enable Intel ME Crypto Transport Layer
Security (TLS) cipher suite (with confidentiality).
Must be pulled up to support IntelR AMT with
TLS and Intel SBA (Small Business Advantage)
with TLS.

CPTH (AUDIO/SMBUS/MISC)
Title :
ASUSTek Computer Inc.
Engineer: Aaron_Su
Size Project Name Rev
A2 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 45 of 152


+3V

SR80 2.2KOhm mbs_r0402


1 /CPTH 2 S_HDMI_C_CTRL_CLK SU1E
SR81 2.2KOhm mbs_r0402 AL13
GPP_I5/DDPB_CTRLCLK S_DP_B_CTRL_CLK 64
1 /CPTH 2 S_HDMI_C_CTRL_DATA AT6 AR8 S_DP_B_CTRL_CLK
64 S_DP_B_HPD
AN10
GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I6/DDPB_CTRLDATA
AN13 S_DP_B_CTRL_DATA
S_DP_B_CTRL_DATA 64 PS_ON# Control for CEC.
63 S_HDMI_C_HPD GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I7/DDPC_CTRLCLK
AP9 AL10 S_HDMI_C_CTRL_CLK 20190728 Allen Remove Port C
GPP_I2/DDPD_HPD2/DISP_MISC2 GPP_I8/DDPC_CTRLDATA
AL15 AL9 S_HDMI_C_CTRL_DATA
GPP_I3/DDPF_HPD3/DISP_MISC3 GPP_I9/DDPD_CTRLCLK
AR3
GPP_I10/DDPD_CTRLDATA

AT49 +3VSB
GPP_F22/DDPF_CTRLCLK GPP_F_22 13,72
SR84 2.2KOhm mbs_r0402 AN40 GPP_F_22
SR1828 GPP_F23/DDPF_CTRLDATA GPP_F_23 13,72
1 /CPTH 2 S_DP_B_CTRL_CLK AP41 GPP_F_23
GPP_F14/PS_ON#
SR85 2.2KOhm mbs_r0402 1 2 AN6 PS_ON_B
GPP_I4/EDP_HPD/DISP_MISC4 20190807 Remove PS_ON_B

2
1 /CPTH 2 S_DP_B_CTRL_DATA eDP_HPD 100KOhm eDP_HPD_R M45 1 ST97
GPP_K23/IMGCLKOUT1
/CPTH L48 TP_GPP_K23 1 ST795 SR802
GPP_K22/IMGCLKOUT0
T45 TP_GPP_K22 1 ST99 8.2KOhm
GPP_K21
T46 TP_GPP_K21 1 ST100
Reserved /X/CPTH
GPP_K20
GND Pull down to ground via 100k Ω resistor AJ47 TP_GPP_K20
GPP_H23/TIME_SYNC0

1
5 OF 13
FH82Z490
有on board TB請上件 02001-00860000
PS_ON_B

+3VSB +3V_S0IX

1
SR829 SR830
8.2KOhm 8.2KOhm
/CPTH /X/CPTH +3V_S0IX

2
F_LAD[0:3] 66,72
SU1F

1
D11 BB39 IPU SR827 SR826 SR825
119 S_U3D1RXDN1_R USB31_1_RXN GPP_A1/LAD0/ESPI_IO0
C11 AW37 F_LAD0 IPU 8.2KOhm 8.2KOhm 8.2KOhm
119 S_U3D1RXDP1_R USB31_1_RXP GPP_A2/LAD1/ESPI_IO1
SC591 2 1 0.22UF/10V F9 AV37 F_LAD1 IPU /CPTH /CPTH /CPTH
119 S_U3D1TXDN1_R USB31_1_TXN GPP_A3/LAD2/ESPI_IO2
SC592 2 1 0.22UF/10V S_U3D1TXDN1_C F7 BA38 F_LAD2 IPU
FRONT U31G2_C1

2
119 S_U3D1TXDP1_R USB31_1_TXP GPP_A4/LAD3/ESPI_IO3
void
S_U3D1TXDP1_C B9 F_LAD3
119 S_U3D1RXDN2_R USB31_2_RXN
void C9
119 S_U3D1RXDP2_R USB31_2_RXP
SC593 2 1 0.22UF/10V C3 BE38 H
119 S_U3D1TXDN2_R USB31_2_TXN GPP_A5/LFRAME#/ESPI_CS0# F_FRAME# 66,72
SC594 2 1 0.22UF/10V S_U3D1TXDN2_C D4 AW35 SERIRQ: An external Pull-up is required. On SIO side
119 S_U3D1TXDP2_R USB31_2_TXP GPP_A6/SERIRQ/ESPI_CS1# F_SERIRQ# 66,72
void
S_U3D1TXDP2_C BA36
GPP_A7/PIRQA#/ESPI_ALERT0# S_ESPI_ALERT# 66
void B10 BE39 ESPI_Alert0#
88 S_U3D1RXDN3_R USB31_3_RXN GPP_A0/RCIN#/ESPI_ALERT1# O_KB_RST# 66
C10 BF38
88 S_U3D1RXDP3_R USB31_3_RXP GPP_A14/SUS_STAT#/ESPI_RESET# S_ESPI_RST# 66
SC163 2 1 0.22UF/10V F11
Back U31G2_3 88 S_U3D1TXDN3_R
SC162 2 1 0.22UF/10V S_U3D1TXDN3_C G12
USB31_3_TXN
BB36 SR1694 1 2 15Ohm
88 S_U3D1TXDP3_R USB31_3_TXP GPP_A9/CLKOUT_LPC0/ESPI_CLK C_PCI_SIO 66
void
S_U3D1TXDP3_C BB34 C_PCI_SIO_R SR1836 1 2 15Ohm
GPP_A10/CLKOUT_LPC1 C_PCI_EC1 72
void K16 C_PCI_EC1_R
88 S_U3D1RXDN4_R USB31_4_RXN
J15 T48
88 S_U3D1RXDP4_R USB31_4_RXP GPP_K19/SMI#
SC146 2 1 0.22UF/10V B14 T47
Back U31G2_C4 88 S_U3D1TXDN4_R
SC145 2 1 0.22UF/10V S_U3D1TXDN4_C C14
USB31_4_TXN GPP_K18/NMI# 2X4_POWER_DETECT change to SIO
88 S_U3D1TXDP4_R void
USB31_4_TXP
S_U3D1TXDP4_C
void J13 AH40
88 S_U3D1RXDN5_R USB31_5_RXN GPP_E6/SATA_DEVSLP2
K13 AH35
88 S_U3D1RXDP5_R USB31_5_RXP GPP_E5/SATA_DEVSLP1
SC154 2 1 0.22UF/10V C15 AL48
88 S_U3D1TXDN5_R USB31_5_TXN GPP_E4/SATA_DEVSLP0
SC149 2 1 0.22UF/10V S_U3D1TXDN5_C B15 AP47 +3V_S0IX
88 S_U3D1TXDP5_R USB31_5_TXP GPP_F9/SATA_DEVSLP7
void
S_U3D1TXDP5_C AN37
Back U31G2_56 void G14
GPP_F8/SATA_DEVSLP6
AN46
88 S_U3D1RXDN6_R USB31_6_RXN GPP_F7/SATA_DEVSLP5
F14 AR47 +3V_S0IX
88 S_U3D1RXDP6_R USB31_6_RXP GPP_F6/SATA_DEVSLP4
SC148 2 1 0.22UF/10V C17 AP48

1
88 S_U3D1TXDN6_R USB31_6_TXN GPP_F5/SATA_DEVSLP3
SC147 2 1 0.22UF/10V S_U3D1TXDN6_C C16 SR240
88 S_U3D1TXDP6_R void
USB31_6_TXP
S_U3D1TXDP6_C 8.2KOhm
void 6 OF 13
/X/CPTH

1
FH82Z490
SR238

2
02001-00860000 8.2KOhm
20190812 Remove SC140 C_PCI_SIO /X/CPTH
M2/SE1_DEVSLP 97

1
M2/SE0_DEVSLP 97
SR241
8.2KOhm
/X/CPTH

1
SC142 GND SR239

2
10PF/50V 8.2KOhm
C_PCI_EC1 1 2 M2/SE0_DEVSLP M2/SE1_DEVSLP /X/CPTH
/X/CPTH

2
1

1
SC141 GND
1.5PF/50V SC409 SC410
O_KB_RST# 1 2 0.22UF/6.3V 0.22UF/6.3V

2
/X/CPTH /X/CPTH /X/CPTH GND

GND GND

For SB ESD Protection

Title : CPTH (DISPLAY/USB3)

ASUSTek Computer Inc.


Engineer: Aaron_Su
Size Project Name Rev
A2 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 46 of 152


+3VSB +3VSB

2
SR916 SR979
8.2KOhm 8.2KOhm
/CPTH /CPTH

1
CLK_REQ1_LAN# X_1X16_CLKQ#_R

SU1G
+3VSB +3VSB ST115 1 BE33
GPP_A16/CLKOUT_48
CLK_48M_PCH Y3
D7
CLKOUT_ITPXDP_N
Y4 For XDP
For CPU 35 C_CPU_NSCCCLK
C_CPU_NSCCCLK C6
CLKOUT_CPUNSSC_P CLKOUT_ITPXDP_P
35 C_CPU_NSCCCLK# CLKOUT_CPUNSSC_N
2

2
C_CPU_NSCCCLK# B6
SR867 SR149 B8
CLKOUT_CPUPCIBCLK_N
A6 C_PCIBCLK#
C_PCIBCLK# 35 For CPU
8.2KOhm 8.2KOhm To CLKGEN 35,86 C_CPU0
C_CPU0 C8
CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK_P
C_PCIBCLK
C_PCIBCLK 35
35,86 C_CPU0# CLKOUT_CPUBCLK_N
/CPTH /CPTH C_CPU0# AJ6 1 ST188
CLKOUT_PCIE_N0
U9 AJ7 1 ST189
XTAL_OUT CLKOUT_PCIE_P0
1

1
S_24M_OUT U10
XTAL_IN
SR200 S_24M_IN AH9
CLK_REQ7_M.2_1_SSD# 1 2 T3
CLKOUT_PCIE_N1
AH10 C_PCIE_L1#
C_PCIE_L1# 81 Intel LAN I225V
XCLK_BIASREF CLKOUT_PCIE_P1 C_PCIE_L1 81
XCLK_RBIAS C_PCIE_L1
60.4Ohm BA49 AE14
/CPTH 1% S_RTCX1 BA48
RTCX1 CLKOUT_PCIE_N2
AE15 PCIEX1_1
RTCX2 CLKOUT_PCIE_P2
+3VSB GND S_RTCX2
ST770 1 BF31 AE6
TP_PCH_BF31 BE31
GPP_B5/SRCCLKREQ0# CLKOUT_PCIE_N3
AE7 C_PCIEX16#_1
C_PCIEX16#_1 60 For PCIe Slot X16_1
81 CLK_REQ1_LAN# GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_P3 C_PCIEX16_1 60
AR32 C_PCIEX16_1
GPP_B7/SRCCLKREQ2#
2

BB30 AC2
SR868
60 X_1X16_CLKQ#_R
X_1X16_CLKQ#_R BA30
GPP_B8/SRCCLKREQ3# CLKOUT_PCIE_N4
AC3 For PCIe Slot X16_2
GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_P4
8.2KOhm AN29
GPP_B10/SRCCLKREQ5#
/CPTH AE47 AB2
GPP_H0/SRCCLKREQ6# CLKOUT_PCIE_N5
AC48 AB3
97 CLK_REQ7_M.2_1_SSD# GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_P5
1

CLK_REQ7_M.2_1_SSD# AE41
97 CLK_REQ8_M.2_2_SSD# GPP_H2/SRCCLKREQ8#
CLK_REQ8_M.2_2_SSD# AF48 W4
GPP_H3/SRCCLKREQ9# CLKOUT_PCIE_N6
CLK_REQ8_M.2_2_SSD# AC41 W3
GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_P6
AC39
GPP_H5/SRCCLKREQ11#
AE39 W7
GPP_H6/SRCCLKREQ12# CLKOUT_PCIE_N7 C_PCIE_M2_1# 97
AB48 W6 C_PCIE_M2_1#
AC44
GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_P7
C_PCIE_M2_1
C_PCIE_M2_1 97 For M.2_1
GPP_H8/SRCCLKREQ14#
AC43 AC14
GPP_H9/SRCCLKREQ15# CLKOUT_PCIE_N8 C_PCIE_M2_2# 97
AC15 C_PCIE_M2_2#
V2
CLKOUT_PCIE_P8
C_PCIE_M2_2
C_PCIE_M2_2 97 For M.2_2
CLKOUT_PCIE_N15
V3 U2
CLKOUT_PCIE_P15 CLKOUT_PCIE_N9
U3
CLKOUT_PCIE_P9
T2
CLKOUT_PCIE_N14
T1 AC9
CLKOUT_PCIE_P14 CLKOUT_PCIE_N10
AC11
CLKOUT_PCIE_P10
AA1
CLKOUT_PCIE_N13
Y2 AE9
CLKOUT_PCIE_P13 CLKOUT_PCIE_N11
AE11
CLKOUT_PCIE_P11
AC7
CLKOUT_PCIE_N12
AC6 R6
CLKOUT_PCIE_P12 CLKIN_XTAL CNVi_CLKIN_XTAL 87

7 OF 13
FH82Z490

W > 4mils ; other trace > 15 mils 02001-00860000 <9000mil, <2vias


Follow CRB Routing on bottom side

For RTD3 use


SR807
2 0Ohm 1 S_24M_IN
SR144 /CPTH
1 2
200KOHM
/CPTH
mbs_r0402 SR806
1% 2 0Ohm 1 S_24M_OUT 20190731 Allen Remove
S_24M_OUT_R

SR47 /CPTH
22OHM
/CPTH
S_24M_IN_R

1%
SX2 24MHZ
1 2 1 3
SR805 0Ohm S_24M_IN_SX2
/CPTH
PEG 100MHz
2

07009-00067500
20190926 change SMD XTL allen
1

SC8 SC9 For RTD3


22PF/50V 22PF/50V
2

SC109 1.5PF/50V /X/CPTH /CPTH /CPTH


C_PCIE_L1# SC108 1 2 1.5PF/50V /X/CPTH
C_PCIE_L1 1 2
GND
SC17 1.5PF/50V /X/CPTH 20190807 Remove RTD3
C_PCIEX16#_1 SC18 1 2 1.5PF/50V /X/CPTH
C_PCIEX16_1 1 2 20190731 Allen Remove

SC441 1.5PF/50V /X/CPTH For SB ESD Protection


C_PCIE_M2_1# SC442 1 2 1.5PF/50V /X/CPTH
C_PCIE_M2_1 1 2
XDP 100MHz
X_1X16_CLKQ#_R
SC440 1.5PF/50V /X/CPTH S_RTCX1

1
C_PCIE_M2_2# SC439 1 2 1.5PF/50V /X/CPTH S_RTCX2
C_PCIE_M2_2 1 2 SR1607 10MOHM SC405
0.22UF/6.3V

2
mbs_r0603 2 1
10G213100513010 /X/CPTH

SX1
1 2
20180806 change SMD XTL allen GND

32.768Khz
1

SC143 SC144
to CPU 100MHz 15PF/50V
07009-00112800
15PF/50V
SC13 1.5PF/50V /X/CPTH Trace < 1.5
2

C_CPU0 SC15 1 2 1.5PF/50V /X/CPTH


C_CPU0# 1 2

PCIE ref CLK to CPU 100MHz


SC1 1.5PF/50V /X/CPTH RTC (10 MOHM RES): DO NOT CHANGE TO 0402 PACK_TYPE
C_PCIBCLK SC2 1 2 1.5PF/50V /X/CPTH
C_PCIBCLK# 1 2

CLK from Crystal to CPU 24MHz


SC4 2 1 1PF/50V /CPTH
C_CPU_NSCCCLK 2 1 /CPTH Title : CPTH(CLOCK)
C_CPU_NSCCCLK# SC5 1PF/50V

ASUSTek Computer Inc.


Engineer: Aaron_Su
GND
Size Project Name Rev
GND
C Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 47 of 152


+1.05V_A +3VSB +1.05V_A +1.05V_A_VCCAMPHYPLL
+BAT_3V +VCCPRTC_3P3
SU1H SJP10 SHORTPIN_0603_NM
AA22 AW9 1 2 SR156
VCCPRIM_1P05_1 VCCPRIM_3P3_2
AA23 X5R X5R X5R
VCCPRIM_1P05_2

1
AB20 BF47 /X/SPTH SC76 SC77 SC78 X5R 2 1 X5R X7R
VCCPRIM_1P05_3 DCPRTC1

1
AB22 BG47 VCC_RTCEXT_CAP
+3VSB X7R 22UF/6.3V 22UF/6.3V 1UF/6.3V SC19 0Ohm SC81 SC190
VCCPRIM_1P05_4 DCPRTC2
AB23 +VCCSPI SC188 mbs_c0603 mbs_c0603 /X/CPTH 1UF/6.3V mbs_r0603 1UF/6.3V 0.1UF/16V
VCCPRIM_1P05_5

2
AB27 V23 0.1UF/16V /X/CPTH /X/CPTH /X/CPTH
VCCPRIM_1P05_6 VCCPRIM_3P3_5

2
AB28 AN44
VCCPRIM_1P05_7 VCCSPI
AB30 +VCCPRTC_3P3 Place close to PCH Pin C49 , D49 , E49
VCCPRIM_1P05_8
AD20 BC49 GND GND Place close to PCH pin BC49 BD49
VCCPRIM_1P05_9 VCCRTC1
AD23 BD49 +3VSB GND
VCCPRIM_1P05_10 VCCRTC2
AD27 +3VSB
VCCPRIM_1P05_11
AD28 AN21 +1.8V_A +1.8V_A_LDO
VCCPRIM_1P05_12 VCCPGPPG_3P3
AD30 AY8 20190806 SR959 stuff Allen
VCCPRIM_1P05_13 VCCPRIM_3P3_3
AF23 BB7 SR959 +1.05V_A +1.05V_A_VCCDUSB
VCCPRIM_1P05_16 VCCPRIM_3P3_4
AF27 +3VSB
VCCPRIM_1P05_17
AF30 AC35 2 1 X5R X5R SJP14 SHORTPIN_0603_NM
VCCPRIM_1P05_18 VCCPGPPHK1

1
U26 AC36 /CPTH 0Ohm SC198 SC197 1 2

1
VCCPRIM_1P05_23 VCCPGPPHK2
U29 AE35 SC596 mbs_r0603 22UF/6.3V 22UF/6.3V SR849 X5R X5R
VCCPRIM_1P05_24 VCCPGPPEF1

1
V25 AE36 4.7UF/6.3V /CPTH mbs_c0603 mbs_c0603 0Ohm /X/SPTH SC185 SC184
VCCPRIM_1P05_25 VCCPGPPEF2

2
V27 GPP_EFHK mbs_c0603 /X/CPTH /X/CPTH /X/CPTH 22UF/6.3V 22UF/6.3V
VCCPRIM_1P05_26
V28 AN24 +3VSB mbs_c0603 mbs_c0603

2
VCCPRIM_1P05_27 VCCPGPPD

2
+1.05V_A V30 AN26 Place close to PCH Pin AF19, AF20 /CPTH /CPTH
VCCPRIM_1P05_28 VCCPGPPBC1
V31 AP26 +VCCPGPPA GND
VCCPRIM_1P05_29 VCCPGPPBC2
GPP_BCD GND Place close to PCH Pin W22,W23
+1.05V_A_VCCDUSB AD31 AN32 GND
VCCPRIM_1P05_14 VCCPGPPA
AE17 +3VSB +3VSB_ERP +1.05V_A +1.05V_A_BCLK
VCCPRIM_1P05_15
AT44
VCCPRIM_3P3_1
W22 BE48 SJP12 SHORTPIN_0603_NM
VCCDUSB_1P05_1 VCCDSW_3P3_1
W23 BE49 1 2
VCCDUSB_1P05_2 VCCDSW_3P3_2
+1.05V_A +1.05V_A_VCCDSW +3VSB_HDA X5R X5R

1
BG45 BB14 /X/SPTH SC183 SC182 SC454 +1.05V_A_VCCDSW +1.24V_A
VCCDSW_1P05_1 VCCHDA
BG46 AG19 +1.8V_A 22UF/6.3V 22UF/6.3V 0.1UF/16V
VCCDSW_1P05_2 VCCPRIM_1P8_1
W31 AG20 mbs_c0603 mbs_c0603 mbs_c0402
VCCPRIM_MPHY_1P05 VCCPRIM_1P8_2

2
AN15 /X/CPTH /X/CPTH /X/CPTH X5R X5R
VCCPRIM_1P8_3

1
+1.05V_A_VCCAMPHYPLL D1 AR15 SC187 SC186
VCCPRIM_1P05_21 VCCPRIM_1P8_4
E1 BB11 Place close to PCH Pin V19 1UF/6.3V 4.7UF/6.3V
VCCPRIM_1P05_22 VCCPRIM_1P8_5
C49 +1.8V_A_LDO GND /CPTH /CPTH
VCCAMPHYPLL_1P05_1

2
+1.05V_A_XCLK D49 AF19
VCCAMPHYPLL_1P05_2 VCCPHVLDO_1P8_1
E49 AF20 +1.05V_A
VCCAMPHYPLL_1P05_3 VCCPHVLDO_1P8_2
+1.05V_A +1.24V_A GND
P2 AG31 +1.05V_A +1.05V_A_XCLK GND
VCCA_XTAL_1P05_1 VCCPRIM_1P05_20
P3 AF31
VCCA_XTAL_1P05_2 VCCPRIM_1P05_19
W19 AK22 SJP13 SHORTPIN_0603_NM
VCCA_SRC_1P05_1 VCCDPHY_1P24_3
W20 AK23 1 2 Place close to PCH Pin BG45/BG46 Place close to PCH Pin BG5
VCCA_SRC_1P05_2 VCCDPHY_1P24_4
+1.05V_A_BCLK X5R X5R X5R

1
C1 AJ22 /X/SPTH SC66 SC67 SC68
VCCAPLL_1P05_4 VCCDPHY_1P24_1
+1.05V_A C2 AJ23 22UF/6.3V 22UF/6.3V 1UF/6.3V
VCCAPLL_1P05_5 VCCDPHY_1P24_2
V19 BG5 mbs_c0603 mbs_c0603 /CPTH
VCCA_BCLK_1P05 VCCDPHY_1P24_5

2
/CPTH /CPTH
B1 K47
VCCAPLL_1P05_1 VCCMPHY_SENSE VCCMPHY_SENSE 19
B2 K46 Place close to PCH Pin P2 , P3
VCCAPLL_1P05_2 VSSMPHY_SENSE VSSMPHY_SENSE 19
B3 GND
VCCAPLL_1P05_3

8 OF 13
FH82Z490
02001-00860000

+1.05V_A

X5R X5R X5R X5R X5R X5R X5R X5R

1
+3VSB +VCCPGPPA +3VSB +VCCSPI +3VSB +3VSB_HDA SC79 SC181 SC80 SC180
SC69 SC70 SC71 SC72 SC73 1UF/6.3V 1UF/6.3V 22UF/6.3V 22UF/6.3V
JP3 JP2 JP1 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V mbs_c0603 mbs_c0603

2
1 2 1 2 1 2

SHORTPIN_0603_NM SHORTPIN_0603_NM SHORTPIN_0603_NM Place close to PCH


/X/SPTH /X/SPTH /X/SPTH GND

+3VSB

X5R X5R X5R X5R X5R


1

1
SC191 SC189 SC196 SC84 SC85 SC86 SC87 SC88
1UF/6.3V 1UF/6.3V 1UF/6.3V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 1UF/6.3V
/X/CPTH /X/CPTH /X/CPTH /X/CPTH /X/CPTH /X/CPTH /X/CPTH /CPTH
2

2
USE 3 PAD USE 3 PAD USE 3 PAD

Place close to PCH pin AW9, V23, AN21, AY8, BB7, AT44
GND GND GND GND
Place close to PCH Pin AN44 Place close to PCH Pin BB14
Place close to PCH Pin AN32

+1.05V_A

+3VSB_ERP
+3VSB

1
SC452 SC453
0.1UF/16V 22UF/6.3V
SR971 mbs_c0402 mbs_c0603

2
GPP_EFHK GPP_BCD 2 1 /CPTH /CPTH
0Ohm
mbs_r0603
1

SC193 SC451 /CPTH


1UF/6.3V 1UF/6.3V GND
/X/CPTH /X/CPTH
2

X7R Place close to PCH pin B1,B2,B3,C1,C2,E1,D1


SC195
GND
Place close to PCH Pin AE35, AE36
GND
Place close to PCH Pin AP26, AN26,AE24 0.1UF/16V
Title : CPTH (POWER)
2

Place close to PCH Pin BE48, BE49


ASUSTek Computer Inc.
Engineer: Aaron_Su
GND Size Project Name Rev
A3 Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 48 of 152


SU1I
A2 AL12 SU1L
VSS_1 VSS_73
A28 AL17 BG3 M24
VSS_2 VSS_74 VSS_145 VSS_196
A3 AL21 BG33 M32
VSS_3 VSS_75 VSS_146 VSS_197
A33 AL24 BG37 M34
VSS_4 VSS_76 VSS_147 VSS_198
A37 AL26 BG4 M49
VSS_5 VSS_77 VSS_148 VSS_199
A4 AL29 BG48 M5
VSS_6 VSS_78 VSS_149 VSS_200
A45 AL33 C12 N12
VSS_7 VSS_79 VSS_150 VSS_201
A46 AL38 C25 N16
VSS_8 VSS_80 VSS_151 VSS_202
A47 AM1 C30 N34
VSS_9 VSS_81 VSS_152 VSS_203
A48 AM18 C4 N35
VSS_10 VSS_82 VSS_153 VSS_204
A5 AM32 C48 N37 SU1J
VSS_11 VSS_83 VSS_154 VSS_205
A8 AM49 C5 N38 Y14 1 ST762
VSS_12 VSS_84 VSS_155 VSS_206 RSVD20
AA19 AN12 D12 P26 Y15 PCH_RSVD20 1 ST763
VSS_13 VSS_85 VSS_156 VSS_207 RSVD21
AA20 AN16 D16 P29 U37 PCH_RSVD21 1 ST764
VSS_14 VSS_86 VSS_157 VSS_208 RSVD22
AA25 AN34 D17 P4 U35 PCH_RSVD22 1 ST765
VSS_15 VSS_87 VSS_158 VSS_209 RSVD23
AA27 AN38 D30 P46 PCH_RSVD23
VSS_16 VSS_88 VSS_159 VSS_210
AA28 AP4 D33 R12 N32 1 ST766
VSS_17 VSS_89 VSS_160 VSS_211 RSVD24
AA30 AP46 D8 R16 R32 PCH_RSVD24 1 ST767
VSS_18 VSS_90 VSS_161 VSS_212 RSVD25
AA31 AR12 E10 R26 PCH_RSVD25

1
VSS_19 VSS_91 VSS_162 VSS_213
AA49 AR16 E13 R29 AH15 SR832 SR831
VSS_20 VSS_92 VSS_163 VSS_214 RSVD26
AA5 AR34 E15 R3 AH14 PCH_EDM2 0Ohm 0Ohm
VSS_21 VSS_93 VSS_164 VSS_215 RSVD27
AB19 AR38 E17 R34 PCH_EDM1 /X/CPTH /X/CPTH
VSS_22 VSS_94 VSS_165 VSS_216
AB25 AT1 E19 R38

2
VSS_23 VSS_95 VSS_166 VSS_217
AB31 AT16 E22 R4
VSS_24 VSS_96 VSS_167 VSS_218
AC12 AT18 E24 T17 AL2
VSS_25 VSS_97 VSS_168 VSS_219 PREQ#
AC17 AT21 E26 T18 AM5
VSS_26 VSS_98 VSS_169 VSS_220 PRDY#
AC33 AT24 E31 T32 AM4 GND GND
VSS_27 VSS_99 VSS_170 VSS_221 CPU_TRST#
AC38 AT26 E33 T4 AK3 /CPTH
VSS_28 VSS_100 VSS_171 VSS_222 TRIGGER_OUT
AC4 AT29 E35 T49 AK2 1 SR833 2 30OHM
VSS_29 VSS_101 VSS_172 VSS_223 TRIGGER_IN PCH_2_CPU_TRIGGER 36
AC46 AT32 E40 T5 PCH_2_CPU_TRIGGER_R
VSS_30 VSS_102 VSS_173 VSS_224 10 OF 13
AD1 AT34 E42 T7
VSS_31 VSS_103 VSS_174 VSS_225 CPU_2_PCH_TRIGGER 36
AD19 AT45 E8 U12 FH82Z490
VSS_32 VSS_104 VSS_175 VSS_226
AD2 AV11 F41 U15
VSS_33 VSS_105 VSS_176 VSS_227 02001-00860000
AD22 AV39 F43 U17
VSS_34 VSS_106 VSS_177 VSS_228
AD25 AW10 F47 U21
VSS_35 VSS_107 VSS_178 VSS_229
AD49 AW4 G44 U24
VSS_36 VSS_108 VSS_179 VSS_230
AE12 AW40 G6 U33
VSS_37 VSS_109 VSS_180 VSS_231
AE33 AW46 H8 U38
VSS_38 VSS_110 VSS_181 VSS_232
AE38 B47 J10 V20
VSS_39 VSS_111 VSS_182 VSS_233
AE4 B48 J26 V22
VSS_40 VSS_112 VSS_183 VSS_234
AE46 B49 J29 V4
VSS_41 VSS_113 VSS_184 VSS_235
AF22 BA12 J4 V46
VSS_42 VSS_114 VSS_185 VSS_236
AF25 BA14 J40 W25
VSS_43 VSS_115 VSS_186 VSS_237
AF28 BA44 J46 W27
VSS_44 VSS_116 VSS_187 VSS_238
AG1 BA5 J47 W28
VSS_45 VSS_117 VSS_188 VSS_239
AG22 BA6 J48 W30
VSS_46 VSS_118 VSS_189 VSS_240
AG23 BB41 J9 Y10
VSS_47 VSS_119 VSS_190 VSS_241
AG25 BB43 K11 Y12
VSS_48 VSS_120 VSS_191 VSS_242
AG27 BB9 K39 Y17
VSS_49 VSS_121 VSS_192 VSS_243
AG28 BC10 M16 Y33
VSS_50 VSS_122 VSS_193 VSS_244
AG30 BC13 M18 Y38
VSS_51 VSS_123 VSS_194 VSS_245
AG49 BC15 M21 Y9
VSS_52 VSS_124 VSS_195 VSS_246
AH12 BC19
VSS_53 VSS_125 12 OF 13
AH17 BC24
VSS_54 VSS_126
AH33 BC26 FH82Z490
VSS_55 VSS_127
AH38 BC31 02001-00860000
VSS_56 VSS_128
AJ19 BC35
VSS_57 VSS_129
AJ20 BC40
VSS_58 VSS_130
AJ25 BC45
VSS_59 VSS_131
AJ27 BC8
VSS_60 VSS_132
AJ28 BD43
VSS_61 VSS_133
AJ30 BE44
VSS_62 VSS_134
AJ31 BF1
VSS_63 VSS_135
AK19 BF2 GND GND
VSS_64 VSS_136
AK20 BF3
VSS_65 VSS_137
AK25 BF48
VSS_66 VSS_138
AK27 BF49
VSS_67 VSS_139
AK28 BG17
VSS_68 VSS_140
AK30 BG2
VSS_69 VSS_141
AK31 BG22
VSS_70 VSS_142
AK4 BG25
VSS_71 VSS_143
AK46 BG28
VSS_72 VSS_144
9 OF 13
FH82Z490
02001-00860000

GND GND

Title : CPTH (GND)

ASUSTek Computer Inc.


Engineer: Aaron_Su
Size Project Name Rev
Maximus XI Extreme
A3 R1.01

Date: Thursday, December 12, 2019 Sheet 49 of 152


SU1K
IPD BA26 BA20
GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0# O2_BIOS_WP# 73
BD30 BB20
20190731 Remove GPP_B21 CF_FTI_AUX3 GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK
AU26 BB16
55 S_LED4 GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/ GP_BSSB_CLK/GSPI2_MISO
AW26 AN18
55 S_LED3 GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/ GP_BSSB_DI/GSPI2_MOSI
IPD BE30
GPP_B18/GSPI0_MOSI
BD29 BF14
97 PCH_M2_1_CONFIG3/PRESENT# GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS#/CNV_WCEN
BF29 AR18
71 CF_FTI_CPU GPP_B16/GSPI0_CLK GPP_D15/ISH_UART0_RTS#/ GSPI2_CS1#/CNV_WFEN S_LED1 55
BB26 BF17
71 CF_FTI_AUX4 GPP_B15/GSPI0_CS0# GPP_D14/ISH_UART0_TXD/I2C2_SCL L1U1_PWREN 111
BE17
20191023 add GPP_B15 CF_FTI_AUX4 GPP_D13/ISH_UART0_RXD/I2C2_SDA WIFI_PWREN 111
ST7813 1 BB24
GPP_C9/UART0A_TXD
TP_GPP_C9 BE23
97 PCH_M.2_1_SSD_SATA_PEDET# GPP_C8/UART0A_RXD
AP24
97 PCH_M2_2_CONFIG3/PRESENT# GPP_C11/UART0A_CTS#
BA24
97 PCH_M.2_2_SSD_SATA_PEDET# GPP_C10/UART0A_RTS#

BD21 AG45
20191023 Remove GPP_C15 CF_FTI_AUX0 GPP_C15/UART1_CTS# /ISH_UART1_CTS# GPP_H20/ISH_I2C0_SCL
AW24 AH46 S_PCB1
GPP_C14/UART1_RTS# /ISH_UART1_RTS# GPP_H19/ISH_I2C0_SDA
AP21 S_PCB0
71 CF_FTI_SYS GPP_C13/UART1_TXD/ISH_UART1_TXD
AU24 AH47 1 ST105
45 S_ME_UNLOCK GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H22/ISH_I2C1_SCL
AH48 TP_GPP_H22
GPP_H21/ISH_I2C1_SDA
AV21 S_PCB2
21 USBPWR_SW GPP_C23/UART2_CTS#
AW21
72 O2_SCI# GPP_C22/UART2_RTS#
BE20
GPP_C21/UART2_TXD
BD20 AV34
GPP_C20/UART2_RXD GPP_A23/ISH_GP5
AW32
GPP_A22/ISH_GP4
BE21 BA33
GPP_C19/I2C1_SCL GPP_A21/ISH_GP3
BF21 BE34
GPP_C18/I2C1_SDA GPP_A20/ISH_GP2
BC22 BD34
115 O3_SMB_SWITCH GPP_C17/I2C0_SCL GPP_A19/ISH_GP1 20190807 Remove GPP_A19 CPU_PRESENT_L
BF23 BF35
55 S_LED2 GPP_C16/I2C0_SDA GPP_A18/ISH_GP0
BD38
GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
BE15
GPP_D4/ISH_I2C2_SDA/I2C3_SDA /SBK4/BK4
BE14
GPP_D23/ISH_I2C2_SCL/I2C3_SCL

FH82Z490 11 OF 13

02001-00860000 +3V_S0IX

2
20190812 Remove
SR994 SR995 SR996
Boot BIOS Destination 8.2KOhm 8.2KOhm 8.2KOhm
0 SPI (Default) /X/CPTH /X/CPTH /X/CPTH
1 LPC

1
20190812 Remove S_PCB0

S_PCB1

S_PCB2

2
SR997 SR998 SR999
BOOT SELECT STRAP NO REBOOT IF SAMPLED HIGH 8.2KOhm 8.2KOhm 8.2KOhm
/CPTH /CPTH /CPTH

1
IF SAMPLED HIGH, LPC IS SELECTED PCH HAS INTERNAL WEAK PD
ELSE SPI PCH HAS INTERNAL WEAK PD STUFFED SR32 FOR LPT-H INTERPOSER

0 = Disable “No Reboot” mode. (Default)


1 = Enable “No Reboot” mode (PCH will disable the TCO
Timer system reboot feature). This function is useful GND
when running ITP/XDP.

Title : CPTH (GPIO)

ASUSTek Computer Inc.


Engineer: Aaron_Su
Size Project Name Rev
A3 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 50 of 152


If use CNVi => SR354 close to CNVi If use CNVi => SR760 Remove/ SR313 stuff
If don't use CNVi =>SR354 close to PCH If don't use CNVi =>SR760 stuff
+1.8V_A
+1.8V_A

1
SR760
2

20KOhm
SR354 GPP_J4 Strap
8.2KOhm /X/CNVI

2
1%
/CNVI
1

CNV_RGI_RSP
CNV_BRI_DT SU1M
BD4
CNV_WR_CLKN CNV_WR_CLK_DN 87
XTAL FREQUENCY SELECTION AW13 BE3
GPP_G0/SD_CMD CNV_WR_CLKP CNV_WR_CLK_DP 87
1 = 24MHZ BE9
0 = 38.4/19.2MHZ GPP_G1/SD_DATA0
BF8 BB3
PCH HAS INTERNAL 20K PD GPP_G2/SD_DATA1 CNV_WR_D0N CNV_WR_0_DN 87
BF9 BB4
GPP_G3/SD_DATA2 CNV_WR_D0P CNV_WR_0_DP 87
BG8 BA3
96 U31_FORCE_PWR_EN GPP_G4/SD_DATA3 CNV_WR_D1N CNV_WR_1_DN 87
BE8 BA2
GPP_G5/SD_CD# CNV_WR_D1P CNV_WR_1_DP 87
BD8
GPP_G6/SD_CLK
AV13 BC5
If use CNVi => SR761 Remove/ WR314 stuff GPP_G7/SD_WP CNV_WT_CLKN CNV_WT_CLK_DN 87
BB6
If don't use CNVi =>SR761 stuff CNV_WT_CLKP CNV_WT_CLK_DP 87
AP3
GPP_I11/M2_SKT2_CFG0
+1.8V_A AP2 BE6
GPP_I12/M2_SKT2_CFG1 CNV_WT_D0N CNV_WT_0_DN 87
AN4 BD7
GPP_I13/M2_SKT2_CFG2 CNV_WT_D0P CNV_WT_0_DP 87
AM7 BG6
GPP_I14/M2_SKT2_CFG3 CNV_WT_D1N CNV_WT_1_DN 87
BF6
CNV_WT_D1P CNV_WT_1_DP 87
2

AV6 BA1 SR631 1 150Ohm 2


87 CNV_GNSS_PA_BLANKING GPP_J0/CNV_PA_BLANKING CNV_WT_RCOMP
SR761 CNV_GNSS_PA_BLANKING AY3 /CPTH 1%
13 CPU_C10_GATE_N_10 GPP_J1/CPU_C10_GATE#
20KOhm GPP_J6 Strap AR13 B12
GPP_J11/A4WP_PRESENT PCIE_RCOMPN
/X/CNVI AV7 A13 S_PCIE_RCOMPN 2100Ohm 1 SR848 GND
GPP_J10 PCIE_RCOMPP
AW3 BE5 S_PCIE_RCOMPP /CPTH 1% 1 SR633 2
GPP_J2 SD_1P8_RCOMP
1

AT10 BE4 200Ohm /CPTH 1%


GPP_J3 SD_3P3_RCOMP
IPD AV4 BD1
87 CNV_BRI_DT GPP_J4/CNV_BRI_DT/UART0B_RTS# GPPJ_RCOMP_1P8_1
CNV_RGI_DT CNV_BRI_DT AY2 BE1 1 SR630 2 1 SR632 2 GND
87 CNV_BRI_RSP GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P8_2
1 = Integrated CNVi disable CNV_BRI_RSP IPU BA4 BE2 200Ohm /CPTH 1% 200Ohm /CPTH 1%
87 CNV_RGI_DT GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P8_3
0 =Integrated CNVi enable CNV_RGI_DT AV3
PCH HAS INTERNAL weak PU. 87 CNV_RGI_RSP GPP_J7/CNV_RGI_RSP/UART0B_CTS#
CNV_RGI_RSP AW2 Y35 GND
87 CNV_MFUART2_RXD GPP_J8/CNV_MFUART2_RXD RSVD28
CNV_MFUART2_RXD IPD AU9 Y36
87 CNV_MFUART2_TXD GPP_J9/CNV_MFUART2_TXD RSVD29
CNV_MFUART2_TXD GND
GPIO J Group = 1.8V BC1
RSVD30
AL35
TP2
13 OF 13

FH82Z490
02001-00860000
+1.8V_A
GPP_J9 Strap

SR1853
/X 2 8.2KOhm 1 1% CNV_MFUART2_TXD

SR1854
/X 2 8.2KOhm 1 1%

GND
Select the SPI BIOS flash interface
operation voltage
1=VCCPSPI Connecte to 1.8V rail
0=VCCPSPI Connecte to 3.3V rail -Default
PCH HAS INTERNAL 20K PD

If use CNVi => SR759 Remove/ SR312 stuff


If don't CNVi =>SR759 stuff

+1.8V_A
1

SR759
20KOhm

/X/CNVI
2

CNV_BRI_RSP

www.teknisi-indonesia.com

Title : CPTH (CNVi)

ASUSTek Computer Inc.


Engineer: Aaron_Su
Size Project Name
Maximus XI Extreme Rev
A3 R1.01

Date: Thursday, December 12, 2019 Sheet 51 of 152


+3VSB
+3V_S0IX

Power LED
20191023 SR77 SR76 SR870 stuff

+VDDQ

1
SR74 SR73 SR76 SR77
1KOhm 1KOhm 1KOhm 1KOhm
/CPTH /CPTH /CPTH /CPTH
Power LED

2
2

2
SR711
SQ1A
8.2KOhm S_PLED- 78
2N7002KDW
/SPTH
45,60,114,115 S_SMBCLK_PCI S_SMBCLK_MAIN 39,40

1
6 1
3
SQ1B C

2
2N7002KDW +12V 1 B
/CPTH
45,60,115 S_SMBDATA_PCI S_SMBDATA_MAIN 39,40 E
3 4 OQ205
SR870 1 1% 2 1KOhm PMBS3904 2

5
1

1
SC56 SC57 /CPTH +3VSB
/CPTH
10PF/50V 10PF/50V mbs_r0603
/X/CPTH /X/CPTH
2

2
NPO NPO To

2
SC402 CPU XDP
1.5PF/50V DRAM SR71
/X +3VSB CK525 8.2KOhm

2
3 CPT
XDP /SPTH
SQ3 C SR305 1KOhm 3
GND

1
PMBS3904 B 1 1 2 SDVO C
from PCH
/CPTH 1 B
GND 42 O_PLED_BLNK#
E
Place near PCH /CPTH
2 OQ203 E
PMBS3904 2

GND GND

1
SC403
1.5PF/50V
3 /X

3
D

2
SQ40 6/15 simplized for channel boards
H2N7002 6/18 connect with GPIO25 for led work immediately
11 /CPTH when power on
45,54 O_PWROK
G GND
S
1

SC401 2
1.5PF/50V 2
/X
2

GND GND

+3VSB_ATX 12017-00021000 BATT


BATT_CON LITHIUM
BATT 3V/220mAh
CR2032
WTOB_CON_2P
2

SIDE1

SIDE2

SR164 黑色connector 0B100-00021100


1
2

0Ohm
/CPTH 20190806 change Battery @allen
3
1
2
4
1

SR118
1KOhm

+BAT_R 2 1 +BAT
/CPTH
Battery
Socket
GND
1

SD1

BAT54CW S_RTCRST#_R 72

+BAT_3V
3

S_RTCRST# 45
2 1 SR123 2 1
1KOhm
SR119 1% Clear RTC
20KOhm CLRTC
/CPTH 1
1

1% SC59 2
1UF/10V
/CPTH HEADER_1X2P
2

+BAT_3V
GND
GND

S_SRTCRST# 45
2 1
SR121 Clear ME
20KOhm
1

/CPTH SC60
1% 1UF/10V
/CPTH
2

CRB use 30.1k ohm


GND

CPTH (SMBUS/CLRTC)
Title :
ASUSTek Computer Inc.
Engineer: Aaron_Su
Size Project Name Rev
A1 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 52 of 152


Stuff: Non Deep Sx mode
SJP20 SHORTPIN_0603_NM
1 2

/X/NonDSW

Can be Simplified?
DSW PWROK, Monitoring Deep Sleep Power

S_DSWPWROK 45

DSW rails must be


stable for at least
10ms before DPWROK
is asserted to PCH

RC Delay
(CRB:47Kohm)
(Payton)

O_RSMRST# 19,66,72,73

BackFeed Cut DSW &


Backfeed Cut Logic

Title : CPTH (DSW SEQUENCE)


ASUSTek Computer Inc.
Engineer: Aaron_Su
Size Project Name Rev
A3 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 53 of 152


PCH_SYSPWROK Sequence Control Ckts +3V_S0IX +3VDUAL_AUX

2
PCH_PWROK Sequence Control Ckts SR126 0Ohm /X/CPTH SR131 SR923
1 2 8.2KOhm 8.2KOhm
/X/CPTH /X/CPTH 吃Dual Power

1
+3V_S0IX +3VSB +3V_S0IX SR991 0Ohm /CPTH

6,23,54 VRMPWRGD_5 PCH_SYSPWROK 45


1 2

2
SR127 SR128 SR924 0Ohm /X/CPTH SD5

8.2KOhm 8.2KOhm 1
S_SLPS3# 21,23,30,45,54,66,72
O_PWROK 1 2 3
/CPTH /CPTH

2
2

1
SR1638
O_PWROK 45,52
8.2KOhm O_PWROK BAT54AW

/CPTH /CPTH

3
1

1
SQ6B SC24
5 2N7002KDW 0.1UF/16V
O_PWROK_SIO_Q /X/CPTH

2
/CPTH

6
SQ6A
2 2N7002KDW GND GND
64,66 O_PWROK_SIO

1
/CPTH

1
SC23 +VCCST

ALL_SYS_PWRGD 0.1UF/16V
/X/CPTH 1. PCH will have a minimum of a 1ms delay from

2
PCH_PWROK to assertion of PROCPWRGD.

2
SR129 2. PLTRST# = AND (PCH_PWROK, SYS_PWROK, PROCPWRGD)
Refer to PDG Figure 40-1 SKL S Flow Diagram for
8.2KOhm SYS_PWROK/PCH_PWROK Generation
GND /CPTH 3. It is recommended that SYS_PWROK be
asserted after both PWROK assertion and processor

1
PCH does not monitor
H_VCCST_PWRGD 35 4. PCH_PWROK and SYS_PWROK both needs to be high
to exit reset, but either signal can come up first.
SYS_PWROK be asserted after both PWROK assertion

1
SR130 and processor core VR PWRGD assertion.

3
SR1640 SQ7A 0Ohm SQ7B
1 2 2 2N7002KDW /X/CPTH 5 2N7002KDW
21,23,30,45,54,66,72 S_SLPS3#

1
SC26

4
0Ohm 4.7UF/6.3V
/CPTH /CPTH
/X/CPTH 1 SC25 /X/CPTH

2
0.1UF/16V mbs_c0603
SR1641 /X/CPTH
2

1 2
6,23,54 VRMPWRGD_5

0Ohm
/CPTH GND GND GND GND

VCCST_PWRGD Sequence Control Ckts


BATX Sequence Control Ckts

S0ix Sequence Control Ckts

S0ix:
PS_ON_B = 1
SLP_S0_N = 0
SLP_S0_PLT_N_10 = 0

PCIE_Reset (S0ix)
20190803 Remobe S0ix Allen

PS_ON# Logic

20190731 Remove PCIEX16_2 RDT3 Allen

20190731 Remove PCIEX16_2 RDT3 Allen

CPTH (PCH/SYS/PROC_PWROK)
Title :
ASUSTek Computer Inc.
Engineer: Aaron_Su
Size Project Name Rev
A0 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 54 of 152


20180112
Note:
1. PWM(Server/ WS only) +5V
2. TACH(Server/ WS only) +5V +5V +5V

layout request

2
SR235 1 /CPTH 2 8.2KOhm SR225 SR226 SR227 SR988
S_LED4 SR236 1 /CPTH 2 8.2KOhm 300Ohm RN change to R 300Ohm RN change to R 300Ohm 300Ohm
S_LED3 SR11728 1 /CPTH 2 8.2KOhm mbs_r0603 mbs_r0603 mbs_r0603 mbs_r0603
S_LED2 /CPTH /CPTH /CPTH /CPTH

1
+3V
GND
2

SR230 CPU

+ 1

1
8.2KOhm RED VGA BOOT DRAM

+
/CPTH /CPTH WHITE YELLOW
YELLOW&GREEN
/CPTH 07G015200612
1

/CPTH
S_LED1

2
2

SR231
1KOhm
/X/CPTH
1

GND

66 OVT2

S_LED3 50
S_LED3

50 S_LED4
S_LED4 SQ31 SQ33

1 S1 D1 6 1 S1 D1 6

2 G2 5 2 G2 5
50 S_LED1 S_LED2 50
S_LED1 G1 G1 S_LED2

3 D2 4 3 D2 4
S2 S2

2N7002KDW 2N7002KDW
/CPTH /CPTH

3
3

D
SQ44
H2N7002
11 /CPTH
35,42,66,81 S_PLTRST#
G
S
2
2

GND

<Variant Name>

TitleCPTH
: EUP/LED Control

ASUSTeK COMPUTER INC


Engineer: Aaron_Su
Size Project Name Rev
A3 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 55 of 152


+VDDQ

X5R X5R X5R X5R X5R X5R X5R X5R X5R 20190812 Remove for 2DIMM

1
Layout to 0603 PCB1 PCB2 PCB3 PCB4 PCB5 PCB6 PCB7 PCB8 PCB45
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603

2
Layout Layout Layout Layout

DIMM 附近
GND

+VDDQ
20190812 Remove for 2DIMM
Put near DIMM Slot DIMM_A1
1

1
X5R X5R X5R X5R X5R X5R X5R X5R
PCB9 PCB10 PCB11 PCB12 PCB13 PCB14 PCB15 PCB16
1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V
2

2
/X/DDR4

GND

+VDDQ
20190812 Remove for 2DIMM
Put near DIMM Slot DIMM_B1
1

X5R X5R X5R X5R X5R X5R X5R X5R


PCB25 PCB26 PCB27 PCB28 PCB29 PCB30 PCB31 PCB32
1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 0.1UF/10V 0.1UF/10V 0.1UF/10V 0.1UF/10V
2

/X/DDR4 /X/DDR4 /X/DDR4 /X/DDR4

GND

+VTTDDR +VTTDDR +VPPDDR +VPPDDR

X5R Y5V X5R Y5V X5R Y5V X5R Y5V


1

1
D4C15 D4C16 D4C17 D4C18 D4C19 D4C20 D4C21 D4C22 X7R X7R X7R X7R X7R X7R X7R X7R
4.7UF/6.3V 0.1UF/16V 4.7UF/6.3V 0.1UF/16V 4.7UF/6.3V 0.1UF/16V 4.7UF/6.3V 0.1UF/16V D4C29 D4C30 D4C31 D4C32 D4C33 D4C34 D4C35 D4C36
/X/DDR4 /X/DDR4 /X/DDR4 /X/DDR4 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V
2

2
/X/DDR4 /X/DDR4 /X/DDR4 /X/DDR4
/X/DDR4

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Put near DIMM Slot DIMM_A Put near DIMM Slot DIMM_B Put near DIMM Slot DIMM_A Put near DIMM Slot DIMM_B

<Variant Name>

Title : DDR4 (Power CAPs)


ASUSTek Computer Inc.
Engineer: Aaron_Su
Size Project Name Rev
Maximus XI Extreme
A3 R1.01

Date: Thursday, December 12, 2019 Sheet 56 of 152


DRAM SMBUS From PCH (Thru Level Shift)

39,40,52 S_SMBCLK_MAIN S_SMBCLK_DDR 39,40,52


39,40,52 S_SMBDATA_MAIN S_SMBDATA_DDR 39,40,52

<Variant Name>

Title : DDR4 (SMBUS/SPD)


ASUSTeK Computer Inc.
Engineer: Eason
Size Project Name Rev
A3 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 57 of 152


Title : CPTH (CNVi)

ASUSTek Computer Inc.


Engineer: Aaron_Su
Size Project Name
Maximus XI Extreme Rev
A1 R1.01

Date: Thursday, December 12, 2019 Sheet 58 of 152


For add-in card only in X16_1 & X16_2

ALL CFG 1 = NO TERMAINATION ON BOARD DEFAULT HIGH


ALL CFG 0 = PHYSICAL STRAP LOW ON BOARD
CoffeeLake Strap Table Rev 0.5
All Have Internal Pull-Ups +VCCIO
CFG H = 1 L = 0 Description
0 Normal STALL EAR
1 Reserved
2 Normal Lane Reverse PCIEX16 Lane Reversal
3 Reserved
4 disable enable eDP
5 PCIE Config PCIE Config SEL[0]
6 PCIE Config PCIE Config SEL[1]
7 RESET# BIOS REQ PEG Training
8-19 Reserved

<Variant Name>

Title : QUICK SWITCH(PCIEX16_1)

ASUSTek COMPUTER INC.


Engineer: Aaron_Su
Size Project Name Rev
R1.01
A3 Maximus XI Extreme
Date: Thursday, December 12, 2019 Sheet 59 of 152
Title : CPTH (CNVi)

ASUSTek Computer Inc.


Engineer: Aaron_Su
Size Project Name
Maximus XI Extreme Rev
A1 R1.01

Date: Thursday, December 12, 2019 Sheet 61 of 152


+3VSB => +1.2V_CON_DVDD FOR HDMI 2.0
(Ripple requirement: Vpp = 60mV)
+1.2V/0.3A +3V +3VSB +5VDUAL_AUX +3V PR8337
8.2KOhm

2
2 /PWR 1 P_+1.2V_PG_10
PR8338

2
10Ohm
PU2012
PR8335 mbs_r0603
/PWR 13 +1.2V_CON_DVDD
Remove Enable 8.2KOhm GND3

1
/PWR 5% 12
GND2
11
GND1

1
10 1 PJP2021
VCNTL POK
P_1.2V_ CTRL_10 9 2 1MM_OPEN_5MIL
63 P_1.2V_EN_10 EN FB
P_1.2V_EN_10 8 3 1 2
VIN3 VOUT1 1 2
7 4 +1.2V_O
VIN2 VOUT2
6 5 PR8334
VIN1 VOUT3
499Ohm /X/PWR
Enable level 1 2
UP0132QDDA

1
High:1.4V PC8307

1
Low: 0.8V 1UF/6.3V PC8305 PC8306 1% PC8304 PC8321
/PWR/X 10UF/6.3V 1UF/16V /PWR P_1.2V_R_10
/PWR 10UF/6.3V 10UF/6.3V
2

2
mbs_c0805 mbs_c0603 mbs_c0805 mbs_c0805

2
/PWR /PWR PR8336 /PWR /PWR

P_1.2V_FB_10
5.1KOhm
/PWR
1%

1
GND 請放置在Device附近 @0920
GND GND GND GND GND

2
VOUT=0.8V(1+R2/R1) PR8333
10KOhm
/PWR
1%

1
GND

www.teknisi-indonesia.com

Title : CPTH (CNVi)

ASUSTek Computer Inc.


Engineer: Aaron_Su
Size Project Name
Maximus XI Extreme Rev
A2 R1.01

Date: Thursday, December 12, 2019 Sheet 62 of 152


Parade 2017/11/22 Bowei
Main Link Docking need PD 100K

+3V_PCON
GU2A +3V_PCON
GCX66 2 1 0.1UF/16V A8 H2
32 H_HDMI_C_TXP2 DRX0P HDMICKP
GCX67 2 1 0.1UF/16V H_HDMI_C_TXP2_C A7 H1 G_TXC+_HDMI WP Enable - (1-X) default
TS modify ok 32 H_HDMI_C_TXN2 void
H_HDMI_C_TXN2_C
DRX0N HDMICKN
G_TXC-_HDMI WP Disable - (1-2)

2
GCX68 2
void 1 0.1UF/16V A6 H4 X5R
32 H_HDMI_C_TXP1 DRX1P HDMID0P
GCX69 2 1 0.1UF/16V H_HDMI_C_TXP1_C A5 H3 G_TX0+_HDMI GRX27 GCX93 GRX61
32 H_HDMI_C_TXN1 void
DRX1N HDMID0N
H_HDMI_C_TXN1_C G_TX0-_HDMI 4.7KOhm 0.1UF/10V 4.7KOhm

2
GCX70 2
void 1 0.1UF/16V A4 H6 /Parade/V /Parade/V
32 H_HDMI_C_TXP0 DRX2P HDMID1P
GCX71 2 1 0.1UF/16V H_HDMI_C_TXP0_C A3 H5 G_TX1+_HDMI
32 H_HDMI_C_TXN0 DRX2N HDMID1N

1
void H_HDMI_C_TXN0_C G_TX1-_HDMI GND
GCX72 2
void 1 0.1UF/16V A2 H8
32 H_HDMI_C_TXPC DRX3P HDMID2P
GCX73 2 1 0.1UF/16V H_HDMI_C_TXPC_C A1 H7 G_TX2+_HDMI GU2U1
32 H_HDMI_C_TXNC DRX3N HDMID2N
void
H_HDMI_C_TXNC_C G_TX2-_HDMI 1 8
CS# VCC
void C7 F1 SPI_CSN_PCON 2 7
AUXP DDC_SDA G_DDC_DATA_HDMI 65 DO/IO1 HOLD#
+1.2V_CON_AVDD H_DP_C_AUXP_R C8 E1 SPI_DI_PCON 3 6 SPI_HOLD_PCON
AUXN DDC_SCL G_DDC_CLK_HDMI 65 WP# CLK
H_DP_C_AUXN_R SPI_WPN_PCON 4 5 SPI_CLK_PCON
GND DI/IO0
46 S_HDMI_C_HPD
B1
DP_HPD SPI_D_IN
C2
MCA :SPI_DO_PCON
05006-00080700 (4M)

2
SPI_D_OUT
D1 SPI_DI_PCON +3V_PCON W25X20CLSNIG Parade : 05006-00100000 (2M)
G1 D2 SPI_DO_PCON GRX62
HDMI_HPD SPI_CK_OUT

2
X5R G_HPDET_HDMI_C E2 SPI_CLK_PCON 10KOhm GND flash F > 75MHz
GT6 SPI_WR_PROT

1
GCX79 GRX57 F2 C1 SPI_WPN_PCON PS175:Remove GRX88
HDMI_CEC SPI_CS

2
0.1UF/10V 249Ohm 1 TP_HDMI_CEC SPI_CSN_PCON

1
/MCA/V_Parade/X 1% B8 C3 GRX88
RESETB PDB

2
TPC26b D7
/MCA/V_Parade/X PCON_RESET FN1_C3 4.7KOhm
GPIO5

1
/X F7 D8 PCON_FUNC2 /MCA/V_Parade/X GND
NC HDMI_ID/GPIO6 CRB : 100k PD
HDMID_LS_CEXT C6 F3 TP_PS175_D8 /X HDT1 1
GND REXT CONFIG1/GPIO3 FAE : 4.7k PD or NC

1
HDMID_LS_REXT E7 TP_PCON_FUNC4 /X HDT2 1 PCON_FUNC2
CEC_EN/GPIO4
E8 E6 TP_PCON_FUNC5 /X HDT3 1 TP_PCON_FUNC5
1 XTLI CSCL

2
X5R XTAL_27M_GU_IN F8 F6 I2C_DATA_R /X HDT4 1 TP_PCON_FUNC4
XTLO CSDA
/MCA/V_Parade/X GCX80 GRX58 GRX91 XTAL_27M_GU_OUT I2C_CLK_R GRX1001 /X HDT5 1 TP_PS175_C5
GRX63 : CRB 0 ohm ; FAE 100k ohm
2.2UF/6.3V 5.1KOhm 100KOhm 4.7KOhm /X HDT6 1 TP_PS175_D3
2

/MCA/X_Parade 4.99KOhm PS175HDMBGA64GTR2-B2 CRB : UART_RX ->TP /MCA/V_Parade/X TP_PS175_D8


PS175:Remove GCX80 1% /X/HDMI2.0 +3V_PCON

1
PS175:Remove GRX64

2
FAE request : AUX+ PU 1M ; PD 100K (unstuff) GND GND GND
FAE request : AUX- PD 1M ; PU 100K (unstuff) FAE request HPD 100k PD GRX34 GRX33
CRB : only PU 100K in AUX- ; PD 100K in AXU+ (unstuff) CRB NO GRX91 4.7KOhm 4.7KOhm UART_TX: SPI_CLK_PCON SPI_DO_PCON SPI_CSN_PCON
/HDMI2.0 /HDMI2.0 CRB : float CRB : NO PD CRB : NO PD CRB : no PU
CRB NO GRX79, GRX78 FAE : PU or NC FAE : PD OR NC FAE : PD OR NC FAE : PU or float 4.7k

1
I2C_DATA_R
+3V_PCON +3V_PCON
I2C_CLK_R PS175:GRX82 stuff
+G_HDMI5V_L_HDMI

2
TS modify ok

2
XTAL_27M_GU_OUT GRX56
10KOhm GRX85 GRX60
XTAL_27M_GU_IN 4.7KOhm 4.7KOhm
X5R GU2X1 27MHZ /X/HDMI2.0 /MCA/X_Parade/V

1
GCX97 1 3 GRX67 GRX66

1
GCX74 2 1 0.1UF/10V 2 1 0.1UF/10V FAE OK 2.2KOHM 2.2KOHM PCON_RESET
32 H_DP_C_AUXP

1
H_DP_C_AUXP_C H_DP_C_AUXP_R mbs_r0603 mbs_r0603 SC595 SPI_CLK_PCON SPI_DO_PCON SPI_CSN_PCON

1
X5R 1UF/16V

2
GCX98 GCX94 GCX95 /MCA 22pF_Parade 1uF

2
07009-00044500

2
GCX75 2 1 0.1UF/10V 2 1 0.1UF/10V 15PF/50V 15PF/50V NPO GRX80
32 H_DP_C_AUXN
2

2
H_DP_C_AUXN_C H_DP_C_AUXN_R GND G_DDC_DATA_HDMI 4.7KOhm
/MCA/X_Parade/V
2

G_DDC_CLK_HDMI

1
GRX42 GRX89
68Ohm 68Ohm GND
/Parade /Parade GND
1

+3V_PCON_AVDD PS175:GRX82 stuff

GND GND GPIO2


+3V_PCON
+1.2V_CON_DVDD +1.2V_CON_AVDD

2
GL35 PS175:Remove GRX26,GRX27,GRX28 GRX30 PS175:change to 10K

2
4.7KOhm
2 1 X5R GU2B /X GRX92
GQ10修改BOM及線路 2017/12/20 Bowei
1

120Ohm/100Mhz GCX81 GCX82 GCX83 GCX84 GCX85 /MCA/V_Parade/X B2 B3 10KOhm


VDD33_1 GND1

1
Irat=1.5A 0.01UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 22UF/6.3V 1
0Ohm 2
GRX26 C4 B6
GPOI0 GND2
X7R X7R X7R X7R mbs_c0603 D4
GND3
2

1
+1.2V_CON_AVDD C5 D5 +5V
TESTMODEB GND4
TP_PS175_C5 E4
GND5
D3 E5 GND FN1_C3
GPIO1 GND6
GND TP_PS175_D3 E3 G3
GPIO2 GND7
+3V_PCON GPIO2 G6 GQ10
GND8

2
+3V_PCON_AVDD +1.2V_CON_DVDD G2 8 1 +12V
VDD33_2
G4 GRX93 7 2
VDD33_3
GL36 100KOhm 6 S 3
B4 GND /MCA/V_Parade/X 5 5 D 4
VDDRX12_1
2 1 B5 G
VDDRX12_2

1
1

120Ohm/100Mhz GCX86 GCX87 GCX88


B7 EMB09N03V
Irat=1.5A 0.01UF/16V 0.1UF/16V 0.1UF/16V
VDDRX12_3
X7R X7R X7R D6 /PWR
VDD12_1 GND
2

1
0Ohm 2 F4
VDDA12
GRX99 F5
VDD12_2

GND G5
VDDTX12_1
+3V_PCON +1.2V_CON_DVDD G7 G8 1 0Ohm 2 GRX28
VDDTX12_2 VDD12_ON P_1.2V_EN_10 62
/Parade/X
BOM Change:07013-00030200 Bowei 2017/11/7
X5R +3V +3V_PCON +G_HDMI5V_L_HDMI
1

GCX89 GCX90 GCX91 GCX92


0.1UF/16V 0.01UF/16V 0.1UF/16V 1UF/16V
X7R X7R X7R /X/HDMI2.0 GF5
2

GJP1 1 2
2
/X/HDMI2.0
1 Parade 2017/11/22 Bowei +G_HDMI5V_L_HDMI
Y5V
X7R
1.1A/8V

1
GND GND PS175HDMBGA64GTR2-B2 GCX77
/HDMI 470PF/50V GCX78
check POWER DP CRB +5V GD55 /X/HDMI2.0 0.1UF/16V

2
check POWER DP CRB +5V 1 9 /HDMI2.0
Line-1 NC4
2 8
3
Line-2
GND
NC3
改GF5料 2017/12/28 Bowei
4 7
FAE:要量HF1-9阻抗項目,預留0~10 ohm 電阻 Line-3 NC2 GND
GD52 GD51 5 6
GRX44-51 Line-4 NC1
1 9 1 9
Choke 改回300 mA(原本的) AZ1045-04F

2018/01/30 Bowei 2 8
3
2 8
3
07G028076030

GRX44 0Ohm /X/HDMI2.0 4 7 4 7


GND
2 1 5 6 5 6
GND
1

/HDMI2.0
DIOV

09G092090400 GLX44 ESD3V3U4ULC ESD3V3U4ULC BOM Change:07024-00960000


G_TX2-_HDMI GRX45
90Ohm/100MHz
0Ohm /X/HDMI2.0
/X/HDMI2.0 /X/HDMI2.0
GND HDMI
4

2 1
G_TX2+_HDMI GRX46 0Ohm /X/HDMI2.0

G_TX2-_L_HDMI 65
2 1
G_TX2+_L_HDMI 65
G_TX1-_HDMI
1

/HDMI2.0 G_HPDET_HDMI 65
DIOV

09G092090400 +5V
90Ohm/100MHz

2
GLX45 /X/HDMI2.0 G_TX1-_L_HDMI 65
G_TX1+_HDMI GRX47 0Ohm GRX55
4

G_TX1+_L_HDMI 65
20KOhm 1%
2
GRX48 1 0Ohm /X/HDMI2.0 3

3
D
G_TX0-_HDMI GQX9

1
2 1 BSS138
G_TX0-_L_HDMI 65
11
1

/HDMI2.0 G_TX0+_L_HDMI 65
DIOV

G_TX0+_HDMI 09G092090400 G_HPDET_HDMI G


90Ohm/100MHz S

2
2 GND

2
GRX49 GLX42 /X/HDMI2.0
0Ohm G_DDC_DATA_HDMI GRX54
4

G_TXC-_L_HDMI 65
G_TXC-_HDMI 100KOhm
G_TXC+_L_HDMI 65
2 1 G_DDC_CLK_HDMI /X/HDMI2.0
GRX50 0Ohm /X/HDMI2.0
<Variant Name>

1
G_TXC+_HDMI
2 1 G_HPDET_HDMI_C
Title :
0.4B Beta GND HDMI HOT_PLUG_DETECT HDMI 2.0 MCDP2800
1

/HDMI2.0
DIOV

09G092090400
90Ohm/100MHz
ASUSTek Computer Inc.
Engineer: Morse_Peng
GRX51 GLX43 /X/HDMI2.0
0Ohm
4

Size Project Name Rev


2 1
A2 SkyLake VC R1.00

Date: Thursday, December 12, 2019 Sheet 63 of 152


+3V
1

1
GCX57 GCX54 GCX55 GCX56

10UF/6.3V 0.1UF/16V 0.1UF/16V 0.1UF/16V


2

2
/DP++ /X/DP++ /X/DP++ /X/DP++
From CPU
H_DP_B_AUXN_C
H_DP_B_AUXP_C

GND 46 S_DP_B_CTRL_DATA
46 S_DP_B_CTRL_CLK

From PCH

+G_DP3V_L_DP_B
+3V
GND
+5V

2
19
18
17
16
15
14
13
+3V DU1 DJP1
/X/DP++ SHORTPIN_0603_NM

GND3
GND2
GND1
SCLB
SDAB
P_AUX_DP+
P_AUX_DP-
GRX6
/X/DP++ 1KOhm

1
1
1

GRX2 GRX3 1 12
AUX Output

2
SDAA C_AUX_DP-
2.2KOhm 2.2KOhm DP_A_CTRL_DATA 2 11 G_AUX-_R_DP_B
GRX200 SCLA C_AUX_DP+
/X/DP++ /X/DP++ DP_A_CTRL_CLK 3 10 G_AUX+_R_DP_B
VCCB DP_PWR
1 2 4 9
2
2

54,66 O_PWROK_SIO EN DNG_DET

0Ohm
DP_A_CTRL_DATA

C_HPD
P_HPD

VCCA
GND
DP_A_CTRL_CLK /DP++
G_HDMI_DNG_DT_DP_B 65

NCT3532Y

5
6
7
8
06015-00250100 +3V
20190823:06015-00250000 的B版本新料號為06015-00250100
DJP4

G_HPDET_DP_B 65
S_DP_B_HPD_H 2 1
SHORTPIN
2

/X/DP++ +3V
GRX8 GND
100KOhm S_DP_B_HPD_H
/X/DP++
S_DP_B_HPD 46
1

to PCH

1
GRX95
GND Place near con. 1KOhm

2
HPD PASS GATE-PREVENT DRIVING S_DP_B_HPD
HPD IN POWER OFF

Layout Guide: 20190807 Remove


1.)Place the input capacitor(s) near the VCCB pin as close as possible.
2.)Output decoupling capacitor(s) have to be placed near the load as close as possible for decoupling high frequency ripple.
3.)Keep VCCB and DP_PWR traces wide and short. +G_DP3V_L_DP_B
4.)The GND should be connected to a strong ground plane for heat sink

X7R

1
GCX6 GCX59
check POWER DP CRB +5V check POWER DP CRB +5V GCX5 1UF/16V 470PF/50V
0.1UF/16V mbs_c0603 /X/DP++

2
GND
GD47 GD48
1 9 1 9

2 8 2 8
GRX10 1 2 0OHM 3 3
From CPU 4 7 4 7
void

DP B 5 6 5 6
2

/X/DP++
VOID

90Ohm/100MHz ESD3V3U4ULC ESD3V3U4ULC


GLX46
3

/X/DP++ /X/DP++
32 H_DP_B_TXP0
GCX45 2

void
1 0.1UF/16V
G_TX0+_DP_B
GRX11 1
void
2 0OHM

GND GND
DP
GCX46 2 1 0.1UF/16V GRX12 1 2 0OHM
32 H_DP_B_TXN0 G_TX0+_L_DP_B 65
G_TX0-_DP_B void
/X/DP++ G_TX0-_L_DP_B 65
3

void
VOID

GCX47 2 1 0.1UF/16V 90Ohm/100MHz


32 H_DP_B_TXP1 GLX49
G_TX1+_DP_B
void G_TX1+_L_DP_B 65
G_TX1-_L_DP_B 65
2

GCX48 2 1 0.1UF/16V GRX13 1 2 0OHM


32 H_DP_B_TXN1
G_TX1-_DP_B void
void GRX14 1 2 0OHM
GCX49 2 1 0.1UF/16V void
32 H_DP_B_TXP2 G_TX2+_L_DP_B 65
G_TX2+_DP_B
2

/X/DP++ G_TX2-_L_DP_B 65
VOID

void

GCX50 2 1 0.1UF/16V 90Ohm/100MHz


32 H_DP_B_TXN2 GLX47
G_TX2-_DP_B
3

G_TX3+_L_DP_B 65
void GRX15 1 2 0OHM
G_TX3-_L_DP_B 65
GCX51 2 1 0.1UF/16V void
32 H_DP_B_TXP3
G_TX3+_DP_B
void GRX16 1 2 0OHM
GCX52 2 1 0.1UF/16V void
32 H_DP_B_TXN3 /X/DP++
3

G_TX3-_DP_B
VOID

void
X5R 90Ohm/100MHz
GLX48
2

GRX17 1 2 0OHM
void

swap
GD49
1 9

2 8
+3V 3
4 7
+3V
5 6
2

GRX2101 swap ESD3V3U4ULC


100KOhm /X/DP++ GRX2000 /X/DP++ GND
100KOhm
1

GCX53 2 1 0.1UF/16V
32 H_DP_B_AUXN
H_DP_B_AUXN_C 1 2
G_AUX-_DP_B 65
GCX58 2
void 1 0.1UF/16V G_AUX-_R_DP_B GRX2103 0Ohm
32 H_DP_B_AUXP
H_DP_B_AUXP_C 1 2
G_AUX+_DP_B 65
2

void G_AUX+_R_DP_B GRX2104 0Ohm


GRX2102 /X/DP++
2

100KOhm S_DP_B_HPD_H
GRX2100
100KOhm <Variant Name>
1

Title : DP++
1

GND Engineer:
ASUSTek COMPUTER INC. Aaron_Su
GND Size Project Name Rev
A2 CoffeeLake VC R1.00

Date: Thursday, December 12, 2019 Sheet 64 of 152


2.2

2016.03.30 Remove VGA Connector

HDMI+Display Port

HDMI_DP GND
40
41
43
45
47
NP_NC
P_GND1
P_GND3
P_GND5
P_GND7

1
64 G_TX0+_L_DP_B ML_Lane0(p)
2 21
GND1 TMDS_DATA2+ G_TX2+_L_HDMI 63
3 22
64 G_TX0-_L_DP_B ML_Lane0(n) TMDS_DATA2_SHIELD
4 23
64 G_TX1+_L_DP_B ML_Lane1(p) TMDS_DATA2- G_TX2-_L_HDMI 63
5 24
GND2 TMDS_DATA1+ G_TX1+_L_HDMI 63
6 25
64 G_TX1-_L_DP_B ML_Lane1(n) TMDS_DATA1_SHIELD
7 26
64 G_TX2+_L_DP_B ML_Lane2(p) TMDS_DATA1- G_TX1-_L_HDMI 63
8 27
GND3 TMDS_DATA0+ G_TX0+_L_HDMI 63
9 28
64 G_TX2-_L_DP_B ML_Lane2(n) TMDS_DATA0_SHIELD
10 29
64 G_TX3+_L_DP_B ML_Lane3(p) TMDS_DATA0- G_TX0-_L_HDMI 63
11 30
GND4 TMDS_CLOCK+ G_TXC+_L_HDMI 63
12 31
64 G_TX3-_L_DP_B ML_Lane3(n) TMDS_CLOCK_SHIELD
13 32
64 G_HDMI_DNG_DT_DP_B CONFIG1 TMDS_CLOCK- G_TXC-_L_HDMI 63
+G_DP3V_L_DP_B 14 33
CONFIG2 CEC
HDMI_CONFIG2 15 34 +G_HDMI5V_L_HDMI
64 G_AUX+_DP_B AUX_CH(p) RESERVED(NC_ON_DEVICE)
16 35
GND5 SCL G_DDC_CLK_HDMI 63
17 36
64 G_AUX-_DP_B AUX_CH(n) SDA G_DDC_DATA_HDMI 63
18 37
64 G_HPDET_DP_B HOT_PLUG_DETECT1 DDC/CEC_GROUND
19 38
RETURN +5V_POWER
20 39
DP_PWR HOT_PLUG_DETECT2 G_HPDET_HDMI 63
P_GND2
P_GND4
P_GND6
P_GND8
2

GR68
SKL CRB 1MOhm
/DP DISPLAY_HDMI_39P
42
44
46
48

GR68 NEAR CONNECTOR PIN


1

12022-00060000
GND GND GND

GND Z97 R1.00 (Follow deluxe)

G_DDC_CLK_HDMI

G_DDC_DATA_HDMI

G_HPDET_HDMI
1

GC52 GC53 GC54


0.1UF/16V 0.1UF/16V 0.1UF/16V
/X/HDMI /X/HDMI /X/HDMI
2

GND GND GND

<Variant Name>

Title : BACK IO_VGA/HDMI/DP

ASUSTek COMPUTER INC.


Engineer: Aaron_Su
Size Project Name Rev
A2 CoffeeLake VC R1.00

Date: Thursday, December 12, 2019 Sheet 65 of 152


(A) 1.1

3擇1, By Project 需求:


KB MS
1. 如無Onboard KBMS connector , 請保留(C)框, 刪除(A)(B)框.
2. 如connector只有一個KBMS孔 請留(A)框, 刪除(B)(C)框.
3. 如connector分別各有一個KB, 一個MOS孔, 請留(A)(B)框, 刪除(C)框.

MS

KB

+5V_DUAL_USBKB +5V_DUAL_USBKB +5V_DUAL_USBKB +5V_DUAL_USBKB (C)


2

OR2048 OR2050 OR2049 OR2047


4.7KOhm 4.7KOhm 4.7KOhm 4.7KOhm
1

O_KB_CLK 66 O_MS_CLK 66

O_KB_DATA 66 O_MS_DATA 66

<Variant Name>

Title : NCT6796D_BF-2

ASUSTek COMPUTER INC.


Engineer: Eagle
Size Project Name Rev
R1.01
A3 Standard Circiut
Date: Thursday, December 12, 2019 Sheet 67 of 152
1.1

/X/Comport DT96 1
O_DCD1#_R 66
/X/Comport DT97 1
O_DSR1#_R 66
/X/Comport DT98 1
O_RXD1_R 66
/X/Comport DT99 1
O_RTS1#_R 66
/X/Comport DT100 1
O_TXD1_R 66,75
/X/Comport DT101 1
O_CTS1#_R 66
/X/Comport DT102 1
O_DTR1#_R 66
/X/Comport DT103 1
O_RI1#_R 66

RING Function COM


Box Header

remove RING Wake


remove COM port header

<Variant Name>

Title : NCT6796D_BF-3

ASUSTeK COMPUTER INC


Engineer: Aaron_Su
Size Project Name Rev
A3 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 68 of 152


1.1
MemOK II Circuit
6/12 revised the circuits to two 0 ohm style

20180112
SKL PDG CRB CPU PECI to EC PECI have 43 ohm

+3VSB_ATX
Z97 OR1012 0 ohm

PECI
2

OR1009
8.2KOhm 1 2 OR1012 to SIO
O_H_PECI 66
1%
43Ohm
1

35 H_PECI

From CPU 1 0Ohm 2 OR1013


S_H_PECI 44
/X/6798D to SB
O_MEM_OK_R 66

OR1012 and OR1013靠近擺放,勿留殘線

Hardware Monitor for VIN

+12V

Hardware Monitor for Temperature

2
O_VREF 66
R25
5.49KOHM
1% +5V

1
1

OC16
0.1UF/16V
+3V
2

2
2

OR52 OR20 R26 OR22


10KOhm 10KOhm 5.49KOHM 12KOHM
1% 1% 1% mbs_r0603
1%
1

1
GND O_+12VIN 66 O_+5VIN 66

Detect +3V
internally.

2
OR23
O_TR_CPU 66
1KOhm OR24
mbs_r0603 3KOhm
1% mbs_r0603
1%
O_TR_MB 66

1
change to 0603 footprint

GND GND
2

OT1 OT2
10KOHM 10KOHM
1

(40)
<Variant Name>

GND GND
Title : NCT6796D_BF-4

ASUSTeK COMPUTER INC


Engineer: Eagle
Size Project Name Rev
A3 Standard Circiut R1.01

Date: Thursday, December 12, 2019 Sheet 69 of 152


Port 80 (7 Segment). SIO is common athode.
1.1

Q_CODE_High byte

For Stealth mode

<Variant Name>

Title : NCT6796D_BF-5

ASUSTek COMPUTER INC.


Engineer: Eagle
Size Project Name Rev
A3 Standard Circiut R1.01

Date: Thursday, December 12, 2019 Sheet 70 of 152


[W_PUMP+] or [W_PUMP+1]

NCT3961SAF new function - FON/OFF# :


High=Full Speed
Low=Turn OFF
Floating=Normal Operating Mode
06053-01090100

+12V +CPUFANPWR

+3V
+CPUFANPWR
CPU_FAN
1

1
1
1

CFC18 2
Color:Dark Gray

1
2
CFC5 10UF/16V CFR21 3
3 (Tin plating)
2

10UF/16V 2.7KOhm O_SEN_CPU_R 4 5


4 NP_NC
2

CF_PWM_CPU 12008-00015500
CF1U1 +3V
GND

2
WAFER_HD_4P
GND 1 8 GND
VIN VOUT
1

2 7 CFR1 1 2
66 O_MODE_CPU MODE POS O_POS_CPU 66 66 O_SEN_CPU
2.7KOhm O_SEN_CPU_R
CFR16
3 6 /PWMPU
50 CF_FTI_CPU FTI PWMOUT 2.7KOhm
CF_PWM_CPU
2

1
4 5
FON/OFF# PWMIN O_PWM_CPU 66
CFC28
9 0.1UF/16V
GND1

2
10 /X/CPU_FAN
GND2
11
GND3
12
GND4
13 GND
GND5
14
GND6

NCT3961S-AF
/FAN3961 GND

+12V +SYSFANPWR
+3V
1

CFC7 CFC20 CFR23


10UF/16V 10UF/16V 2.7KOhm
CHA_FAN
2
2

+SYSFANPWR
CF2U1 +3V 1
2

1 GND
GND 1 8 GND 2
VIN VOUT 2 +12V
3
Color:Black
1

3 SENSE
2 7 CFR2 1 2 O_SEN_SYS_R 4
66 O_MODE_SYS MODE POS O_POS_SYS 66
2.7KOhm
66 O_SEN_SYS
O_SEN_SYS_R CF_PWM_SYS 5
4 PWM (Tin plating)
CFR18 NP_NC
3 6 /PWMPU 12008-00014000
50 CF_FTI_SYS FTI PWMOUT 2.7KOhm
CF_PWM_SYS GND WAFER_HD_4P
2

4 5
FON/OFF# PWMIN O_PWM_SYS 66
CFC30
9 0.1UF/16V
GND1
2

10 /X//SYS_FAN
GND2
11
GND3
12
GND4
13 GND
GND5
14
GND6

NCT3961S-AF
/FAN3961 GND

+3V
+12V +AUXFAN4PWR

+AUXFAN4PWR
AIO_PUMP
1

CFR24 1
1 GND
1

2.7KOhm 2
2 +12V
CFC8 CFC21 3
10UF/16V 10UF/16V O_SEN_AUX4_R 4
3 SENSE Color:Black
2

4 (Tin plating)
2
2

PWM
CF_PWM_AUX4 5
CF3U1 NP_NC
+3V 12008-00014000
GND 1 8 GND 1 2 GND WAFER_HD_4P
VIN VOUT 66 O_SEN_AUX4
O_SEN_AUX4_R
1

CFR19
2 7 CFR3
66 O_MODE_AUX4 MODE POS O_POS_AUX4 66 2.7KOhm
2.7KOhm
/PWMPU
1

3 6
50 CF_FTI_AUX4 FTI PWMOUT
CF_PWM_AUX4 CFC31
2

4 5 0.1UF/16V
FON/OFF# PWMIN O_PWM_AUX4 66
2

/X/AUX0FAN
9
GND1
10
GND2
11 GND
GND3
12
GND4
13
GND5
14
GND6

NCT3961S-AF
GND
/FAN3961

Title : FAN

ASUSTek COMPUTER INC.


Engineer: Yodream_Chen
Size Project Name Rev

<Variant Name>
Custom Innovation Circuit -

Date: Thursday, December 12, 2019 Sheet 71 of 152


+3VSB +3VSB_EC +3VSB_EC +3VSB_EC

2
0Ohm EC 填值偵測
1 2 O2R2

1
O2R1 O2R8 8.2KOhm
mbs_r0805 8.2KOHM

1
1

1
O2C1 O2_VRMVCC_IN

2
0.1UF/16V O2C2
1UF/16V O2Q1A

6
2

VR_VBOOT_SELECT 2N7002KDW
3 2
GND GND

3
D 13,17,23 P_+VCCIO_0_EN_5

1
O2Q9
11 H2N7002
35,66,76 H_SKTOCC#

1
G N/A 0.1UF/16V
S
2 O2C3

2
/X/KB3728 GND

2
+3VSB_EC
GND
VR_VBOOT_SELECT 為HIGH VBOOT填為0V GND
O2U1 VR_VBOOT_SELECT 為LOW VBOOT不填值
O2R3 請連接到南橋可當SCI的pin O2_CPU_ID_10
43 8 用來強制open/short CML.RKL時 CPU與VCCSA Controller的Alert
TX0/GPIO48 SCI#/GPIO18 O2_SCI# 50
2 8.2KOHM 1 O2_TX 9 1 O2R248 2 0Ohm CML: Default GPI為斷開 GPOH:連接
SMI#/GPIO19 O2_CPU_ID_10 12,35
RKL: Default GPI為連接 GPOL:斷開
10 +3VSB_EC

8051/UART debug
eSPI_Reset/GPIO1A
11 OC_INT#
eSPI_Alert/GPIO1B 若無支援node,此pin不可floating, OC_PLUG# 請pull down 8.2K
12 OC_PLUG# OC_PLUG#

1
SIRQ/GPIO1C F_SERIRQ# 46,66
20190731 Remove GPIO6A no support node 13 O2R247

LPC/eSPI
eSPI_IO0/LAD0 F_LAD0 46,66
14 20190731 Remove no support node 8.2KOhm
eSPI_IO1/LAD1 F_LAD1 46,66
16 /KB3728
eSPI_IO2/LAD2 F_LAD2 46,66
+3VSB_EC 17 O2R16 8.2KOhm

2
eSPI_IO3/LAD3 F_LAD3 46,66
19 O2R19 2 1 8.2KOhm O2_SCI#
eSPI_CLK/LPC_CLK C_PCI_EC1 46
20 2 1 OC_INT#
20190731 Remove GPIO68 OPT_SEN eSPI_CS#/LFRAME# F_FRAME# 46,66
58 21 GND

1
FANFB0/GPIO68 LPC_RST#/GPIO1D PCH_PLTRST# 42
O2R244 59 若無支援NODE機種, OC_PLUG#仍需Pull down
13,46 GPP_F_22 FANFB1/GPIO69
8.2KOhm 60
FANFB2/GPIO6A
61
120 O2_SEN_HSFAN FANFB3/GPIO6B

FAN Tacho
62
2
107 O2_RSTBTN_LED_SW FANFB4/GPIO6C
64
6,23 P_VRM_EN_5 FANFB5/GPIO6D
For Flexkey (Aura On/Off use) 57
EC或Aura擇一路pull high SPI_CS# O2_SPI_CS# 73
20190813 add O2_SEN_HSFAN 55
SPI_CLK O2_SPI_CLK 73
56
SPI_MOSI O2_SPI_MOSI 73

SPI
54
SPI_MISO O2_SPI_MISO 73

Only KB3728 Support


SIO EC EATXPWR
34
AD4/GPIO36
VR_VBOOT_SELECT
O2JP2 36 O_PSON# O2_PSON# EATXPWR
+VCCST AD5/GPIO37

ADC
O2JP3 2 1 O2_ADC5 37
+VCCSTG AD6/GPIO38
1 0Ohm 2 O2R242 2 1 O2_ADC6 38
66 O_RSTCONI#_R AD7/GPIO39 O2_PSON# 23,24
39 EATXPWR端請Pull high
AD8/GPIO3A

0.1UF/16V
SB_TEMP O2_ADC8 40 20K電阻到+5VSB_ATX
AD9/GPIO3B
O2_TS1_10 O2_ADC9 O2Q1B
DIMM.2

3
20KOhm
FlexKey使用, 請確認SIO需pull up到VSB power,而非main power 2N7002KDW
1 1KOhm O2R28 5
FANPWM0/GPIO08
2 O2_CUT_PSON#_R 2 1

4
FANPWM1/GPIO09 O_RSTCONO# 45,66

1
3 1 2

1
FANPWM2/GPIO0A O_PWRBTN#IN_R 66
4 0Ohm O2R30 SIO

O2C5
Thermal Detect

O2R31
FANPWM3/GPIO0B O2_PLTRST# 42 O_PSON# 66
5

FAN PWM
FANPWM4/GPIO0C O2_PWM_HSFAN 120

2
6 1 2 +O2_3.2V
FANPWM5/GPIO0D CPU_ID_10 13,35 O2_CUT_PSON# 114
0Ohm O2R249 AI1314

2
20190813 add O2_PWM_HSFAN +O2_3.2V

1
GND GND 6MR1

2
4.7KOhm
O2R32 1%
Power request 4.7KOHM

2
1. 1%

0.1UF/16V
/X/KB3728
SB_TEMP

O2C6

2
T_SENSOR O2_TS1_10

1
1 6M_WRT1 6MC1
2 10KOHM 0.1UF/16V
/X/KB3728

2
HEADER_1X2P
20191030 add O2R246

1
12006-00161200
O2R246 1 8.2KOhm 2 28
GND DA0/GPIO28
29 GND GND
13,46 GPP_F_23 DA1/GPIO29
30 亮灰:12006-00160500 GND
DA2/GPIO2A
O2R39 1 0Ohm 2 31 黑 :12006-00161200
17 P_+VTTDDR_REFIN_10 DA3/GPIO2B
O2R41 1 0Ohm 2 32
O2_VDDQ_VREF預留給低階機種使用 17 O2_VDDQ_VREF DA4/GPIO2C

INTRUDER test
DAC

Only KB3728 Support

22
PWM0/GPIO20
PWM1/GPIO21
23 O2_VRMVCC_IN
S_SLPS3# 21,23,30,45,54,66
THERMALTRIP
24
PWM2/GPIO22 S_SLPS4#_SIO 21,23,30,45,66,115
25
PWM3/GPIO23 O2_CLK_PWREN 86
27
PWM4/GPIO24 O2_RELATCH 86
PWM

O2D6 +3VSB_EC

2
Only KB3728 Support
3
/KB3724
1
BAT54AW
O2R53 20KOhm
S_RTCRST#_R 52 Header type CLRTC
O2D1 BAT54AW
2 1
Switch type CLRTC
41 2
RESET#
ECRST

+3VSB_EC O2_RSMRST# 3 1 O2R216 2


O_RSMRST# 19,53,66,73
1

1
/X/KB3728 1 /X/KB3728 0Ohm
O2R54 1 8.2KOhm 2 O2C8
O2R55 1 8.2KOhm 2 I2CD# O2C7 1UF/10V
O2_RSMRST# 114
2

TRAP# 0.1UF/16V AI1315


/X/KB3728
O2R56 1 8.2KOhm 2 42
+3VSB_EC O2R57 1 8.2KOhm 2 44
I2CD#/GPIO47 GND GND ADC CAP/Resistor
TRAP/GPIO49
Strap Pin

/X/KB3728
O2R58 1 8.2KOhm 2

O2_ADC5
O2_ADC6

O2_ADC8
O2_ADC9
O2R59 1 8.2KOhm 2 GND

O2_ADC5
O2_ADC6

O2_ADC8
O2_ADC9
O2R61 1 8.2KOhm 2

0.1UF/16V
0.1UF/16V

0.1UF/16V
0.1UF/16V

100KOhm
100KOhm

100KOhm
100KOhm
O2R62 1 8.2KOhm 2 46
35 O2_CFG10_TEST I2CSCLK/GPIO52/I2CDCLK
47
35 O2_CFG9 I2CSDAT/GPIO53/I2CDDAT
O2L1 120Ohm/100Mhz
O2JP10 /X/KB3728 SHORTPIN Host 48 33 1 2
6,80 O2_SMB1_CLK SMBCLK0/GPIO54 AVCC +O2_3.2V
Analog PWR

2
O2JP11 /X/KB3728 1 SHORTPIN Host 49 O2C10
/X/KB3728/

SMBDAT0/GPIO55 GND
/X/KB3728

/X/KB3728

/X/KB3728

6,80 O2_SMB1_DATA 2 1 1 2 0.1UF/16V O2L2 120Ohm/100Mhz


SMBUS

O2C27
O2C28

O2C30
O2C31

1 O2R78
1 O2R79

1 O2R81
1 O2R82
O2JP12 /X/KB3728 SHORTPIN Host 50 26 1 2
SMBCLK1/GPIO56 VCCPWM +O2_3.2V
10PF/50V

10PF/50V

10PF/50V

10PF/50V

45,66,73 O2_SMB2_CLK 2 1 SHORTPIN 51


O2JP13 /X/KB3728 Host O2C11
45,66,73 O2_SMB2_DATA SMBDAT1/GPIO57 GND
2 1 15 1 2 0.1UF/16V 0Ohm O2R213
VCCLPC +3VSB_EC
2
/KB3728 1
0.1UF/16V

0.1UF/16V

/X/KB3728 0.1UF/16V

/X/KB3728 0.1UF/16V

1
1

1
1
52 O2C22 O2R214

/X/KB3728
/X/KB3728
VCC1 GND +1.8V_A

/KB3728
/KB3728

/KB3728
/KB3728

/KB3728
/KB3728
1 2 0.1UF/16V 2
/X/KB3728 1 0Ohm
Power

O2C37

O2C38

O2C39

O2C40
O2C32

O2C33

O2C34

O2C35

35 7

2
2

2
2
AGND

AGND VCC2 +3VSB_EC

2
2

2
2
1

18 53
GND1 V18R
45 O2_1.8V_Ref
GND2
2

63 1UF/10V
GND3
GND

/KB3728
1

GND GND GND GND O2C36


2

GND KB3724Q_D
GND GND
2

Z390 導入D版本IC 06037-00200300 GND


<Variant Name>

GND GND GND GND

O2C37.O2C38要靠近pin102.pin19
Title : KB3724_EC_Z490

ASUSTek Computer Inc.


Engineer: Roy hu
Size Project Name Rev
A2
Standard Circiut 0.2A

Date: Thursday, December 12, 2019 Sheet 72 of 152


+O2_3VSB +3VSB_EC

O2RN1C 33OHM O2R83 0Ohm


5 6 6 SCK VDD 8 1 2
72 O2_SPI_CLK
O2_SPI_CLK_Q

1
O2C41 O2C42 /KB3728
10PF/50V 0.1UF/16V 為了開發燒錄使用,
/X/KB3728 請保留

2
GND GND
EMI

SMD2Mb Flash +O2_3VSB


O2U2
O2RN1D 33OHM 1 8 +3VSB_EC
CS# VCC
7 8 2 SO O2_SPI_CS#_Q 2 7
72 O2_SPI_MISO DO/IO1 HOLD#

2
O2_SPI_MISO_R O2_SPI_MISO_R 3 6 O2_SPI_HOLD#
WP# CLK

1
O2C47 O2_BIOS_WP#_Q 4 5 O2_SPI_CLK_Q +5VDUAL_AUX O2R93
GND DI/IO0
10PF/50V O2_SPI_MOSI_Q 10KOhm
/X/KB3728 W25X20CLSNIG
2

GND s_soic_8p_50_197x236 O2PQ1 +O2_3.2V

1
1 5
N/A SHDN# SET
2
GND
GND 3 4
EMI
EC SPI Flash請選用==>05006-00100000 IN OUT
2Mbit
APL5325ABI-TRG
06007-02040000

2
/KB3728
O2RN1B 33OHM O2PC2 O2C49 O2PR1

1
3 4 5 SI 1UF/16V 2.2UF/10V 1 2 O2PC3

1
72 O2_SPI_MOSI

2
O2_SPI_MOSI_Q /KB3728 10UF/6.3V
1

2
O2C48 95.3KOhm

2
10PF/50V O2PR2
/X/KB3728 31.6KOHM
2

1
GND GND GND
GND GND GND
EMI
Vout=0.8 * (1 + R_hign/R_low) = 3.214V

+O2_3VSB 12V06110010M
更改為2.0mm header
O2SPI
1

O2R90 O2R91 請開發階段必須


BOM於PVT前版本再移除
8.2KOhm 8.2KOhm
2

7 HOLD# BOM Option EVT.DVT PVT.MP


O2R92
1 2 O2_SPI_HOLD# 3 WP# +3VSB
50 O2_BIOS_WP#
O2_BIOS_WP#_Q O2SPI1
0Ohm Stuff

2
O2SPI1 1 2
請接到SB的GPIO Pin Remove O2R116 O2R117 0Ohm
8.2KOhm /X/KB3728

O_RSMRST# 19,53,66,72

1
1
3
45 S_RSMRST# 2
Vout=0.8 * (1 + R_hign/R_low) = 3.214V
O2D4
BAT54AW 1 2
O3_FLASHBK# 114
O2RN1A 33OHM /KB3728 O2R118 0Ohm
1 2 1 CE# VSS 4 /KB3728
72 O2_SPI_CS#
O2_SPI_CS#_Q
1

O2C50
10PF/50V GND
/X/KB3728
2

GND
SPI Circuit
EMI

若需刪除請詢問Peter 該案子是否需加入此AI 機制

EEPROM Circuit (Peter MR use)


用於紀錄CPU.Cooler特性及記錄CPU電壓for BIOS 套入對應的MR profile

+3VSB_EC

O2U3
1 8
NC1 VCC
2 7
NC2 WP
3 6
NC3 SCL O2_SMB2_CLK 45,66,72
4 5
GND SDA O2_SMB2_DATA 45,66,72

1
AT24C16C-SSHM-T O2C57

EXT_FAN CARD Remove 2K Byte 0.1UF/16V

2
GND GND GND

O2U3請擺放於O2U1附近
請搭配Jack提供的NODE線路
2017.12.21 add

<Variant Name>

Title : KB3724_EC_Z490

ASUSTek Computer Inc.


Engineer: Roy hu
Size Project Name Rev
A2
Standard Circiut 0.2A

Date: Thursday, December 12, 2019 Sheet 73 of 152


訊號從CHIPSET來, x=12,34,56...
訊號從Descrete IC來, x=E12,E34...
請自行修改為所需編號. LAN+1 port USB3.0(BACK IO)
LAN

+U_USB67_5V +U_USB67_5V +U_USB2_5V

U32G1_78 USB3
1
2
Vbus1
19
LAN_U32G2_3
43,92 U3_U3RXDN7_R RX1- Vbus2
3 18 29 GREEN 32
43,92 U3_U3RXDP7_R RX1+ RX2- U3_U3RXDN8_R 43,92 81,83 L1_ACTLEDP 29 32 L1_LINK100# 81,83
4 17
GND1 RX2+ U3_U3RXDP8_R 43,92
5 16
92 U3_U3TXDN7_R TX1- GND4
6 15
92 U3_U3TXDP7_R TX1+ TX2- U3_U3TXDN8_R 92
7 14 SPEED LED:
GND2 TX2+ U3_U3TXDP8_R 92

GREEN

ORANGE
8 13 1. GREEN : 2500Mbps
43,92 U_USB6-_R D1- GND3 2. ORANGE : 1000Mbps
9 12 30 31
43,92 U_USB6+_R D1+ D2- U_USB7-_R 43,92 81,83 L1_ACTLEDN 30 31 L1_LINK1000_2500# 81,83 3. ORANGE : 100Mbps
10 11
ID D2+ U_USB7+_R 43,92 4. ORANGE : 10Mbps
U3_OTG_2
1

10pin 接編碼小 U3R1 BOX_HD_2X10P_K20 9pin 接編碼大


0Ohm 27 28
ex: USB3_ 2 12007-00016000 ex: USB3_1 81,83 L1_MDI_3- TRD4- GND2
1 /X/CONN 2 25 26
81,83 L1_MDI_2- TRD3- TRD4+ L1_MDI_3+ 81,83
23 24
2

81,83 L1_MDI_1- TRD2- TRD3+ L1_MDI_2+ 81,83


請自行修改R and net所需編號. GND 21 22
81,83 L1_MDI_0- TRD1- TRD2+ L1_MDI_1+ 81,83
19 20
83 L1_CTR VCC TRD1+ L1_MDI_0+ 81,83
GND

10 18

43,90 U_USB2-_R
11
12
VBUS
D-
STDA_SSTX+
STDA_SSTX-
17
16
U31_U31TXDP3_R
U31_U31TXDN3_R
90
90 2 port USB2.0 接編碼小
43,90 U_USB2+_R
13
D+ GND_DRAIN
15
USB
GND1 STDA_SSRX+ U31_U31RXDP3_R 88,90
14
STDA_SSRX- U31_U31RXDN3_R 88,90
接編碼大 USB
35 36 x=12, 34, 56,...
P_GND3 P_GND4
請自行修改為所需編號
33 34
P_GND1 P_GND2

LAN_USB_23P
+U_USB12_5V
USB1213
12014-00801300
+U_USB11_5V
Port 4,5

11

9
GND GND
5 SIDE_G11 SIDE_G9

1
6 VCC1 VCC2
94 U_USB11-_R
2
只使用一顆LAN, 94 U_USB12-_R
7 +U_USB_E12_5V
LAN1_U32G1_x改為LAN_U32G1_x, 94 U_USB11+_R
3
1P- 2P-
Box Header
USB3_x: IREF = 94Name = U_USB12+_R
8
訊號從CHIPSET來, x=12,34,56... 1P+ 2P+
4
訊號從Descrete IC來, x=E12,E34..
請自行修改為所需編號. GND1 GND2
SIDE_G12 SIDE_G10
USB_E12
1 2
USB_CON_2X4P 3 4

12

10
94 U2H1_DN2_R U2H1_DN1_R 94
5 6
94 U2H1_DP2_R U2H1_DP1_R 94
7 8
10
4pin接編碼大 5pin接編碼小
ex:USB5 HEADER_2X5P ex:USB 6
GND 6
mbs_hd_2x5p_100_k9_usb_lf3 5
20190123:change SPEC 12006-00026200

pin 2 ,3為下port接編碼大
1 port Type C USB3.1 (CE team update) pin 6 ,7為上port接編碼小 GND

+U31_+VCCCH12_5V_C

G/F
1C USB3.1 TypeC Header (Front)
U32G2_C4
B12 A1
GND2 GND1
B11 A2
96 U31_U3RXDP2_R_SW2_R SSRXp1 SSTXp1 U31_U3TXDP2_R_SW2_R 96
U35MC19 B10 void A3 U35MC22
96 U31_U3RXDN2_R_SW2_R SSRXn1 SSTXn1 U31_U3TXDN2_R_SW2_R 96
2 1 B9 A4 2 1
VBUS3 VBUS1
B8 A5
SBU2 CC1 U31_DFP_CC1 90,96
U31_RFU2 B7 A6 +5V_UC_P1
0.47UF/6.3V 43,74,96 U_USB3-_R Dn2 Dp1 U_USB3+_R 43,74,96 0.47UF/6.3V
B6 A7
43,74,96 U_USB3+_R Dp2 Dn1 U_USB3-_R 43,74,96
U35MC20 B5 A8 U35MC21
2 1
90,96 U31_DFP_CC2
B4
CC2
VBUS4
SBU1
VBUS2
A9 U31_RFU1 2 1 需要確認命名???
B3 A10
96 U31_U3TXDN2_R_SW1_R SSTXn2 SSRXn2 U31_U3RXDN2_R_SW1_R 96
B2 void A11
0.47UF/6.3V 96 U31_U3TXDP2_R_SW1_R SSTXp2 SSRXp2 U31_U3RXDP2_R_SW1_R 96 0.47UF/6.3V
B1 A12
GND4 GND3
GND GND
1 3
USB3.2_1
NP_NC1 GND5
2 4
NP_NC2 GND6
5
GND7
6
GND8
7 U32_DFP_CC2
P_GND1 43,89 U_USB0+_R U31_U31TXDP1_R 89
8

void
P_GND2 43,89 U_USB0-_R U31_U31TXDN1_R 89
9
P_GND3
10
P_GND4 89,119 U31_U31RXDN2_R U31_U31RXDP1_R 89,119
U31R90 0Ohm

void

void
1 2 89,119 U31_U31RXDP2_R U31_U31RXDN1_R 89,119
USB_CON_24P
U31_RFU1 U31_RFU2 12013V00112600 89 U31_U31TXDN2_R
/X/ASM1142/ASM2142 U32_DFP_CC1

void
89 U31_U31TXDP2_R
U32_RFU1
U32_RFU2

GND GND

BOX_HD_20P

GND GND

CC Termination Requirement

For CC1 For CC2


+5V_DUAL_USBKB
+5V_DUAL_USBKB
U32R34 U32R35
1 2 1 2

10KOhm Silkscreen:High 10KOhm


Current (HC) 3A
U32_DFP_CC1 89 U32_DFP_CC2 89
U32_DFP_CC1 U32_DFP_CC2

BACK U32G1_910_G2_56
U32R57
由於BACK IO connector:命名不能超過15個字元(無法轉BOM) 1 2
(1)USB3.1_E12_USB3_E34 =>19個字元 U32_RFU2 0Ohm U32_RFU1
/X/ASM3142
(2)U3.1_E12_U3_E34 =>14個字元

+U_USB45_5V +U_USB45_5V

+U_USB89_5V +U_USB89_5V
U32G1_910_G2_56
A1 B1
VBUS1 VBUS2
A2 B2
U32G2_6 43,91 U_USB5-_R
A3
D-1 D-2
B3
U_USB4-_R 43,91
43,91 U_USB5+_R D+1 D+2 U_USB4+_R 43,91
A4 B4
GND1 GND2
A5 B5
88,91 U31_U31RXDN6_R STDA_SSRX-1 STDA_SSRX-2 U31_U31RXDN5_R 88,91
A6 B6
88,91 U31_U31RXDP6_R
A7
STDA_SSRX+1 STDA_SSRX+2
B7
U31_U31RXDP5_R 88,91 U32G2_5
GND_DRAIN1 GND_DRAIN2
A8 B8
91 U31_U31TXDN6_R STDA_SSTX-1 STDA_SSTX-2 U31_U31TXDN5_R 91
A9 B9
91 U31_U31TXDP6_R STDA_SSTX+1 STDA_SSTX+2 U31_U31TXDP5_R 91

C1 D1
VBUS3 VBUS4
C2 D2
43,93 U_USB9-_R D-3 D-4 U_USB8-_R 43,93
C3 D3
43,93 U_USB9+_R D+3 D+4 U_USB8+_R 43,93
C4 D4
GND3 GND4
C5 D5
43,93 U3_U3RXDN10_R STDA_SSRX-3 STDA_SSRX-4 U3_U3RXDN9_R 43,93
C6 D6
U32G1_10 43,93 U3_U3RXDP10_R
C7
STDA_SSRX+3 STDA_SSRX+4
D7
U3_U3RXDP9_R 43,93 U32G1_9
GND_DRAIN3 GND_DRAIN4
C8 D8
93 U3_U3TXDN10_R STDA_SSTX-3 STDA_SSTX-4 U3_U3TXDN9_R 93
C9 D9
93 U3_U3TXDP10_R STDA_SSTX+3 STDA_SSTX+4 U3_U3TXDP9_R 93

1 2
P_GND1 P_GND2
3 4
P_GND3 P_GND4
5 6
USB下port接編碼大 P_GND5 P_GND6 USB 上port接編碼小
ex:USB3_1 2 ex:USB3_ 2
USB_CON_36P 1
12013-00130200 Same R6E

GND 接編碼小 USB3

接編碼大 USB3

<Variant Name>

from CPU Title : Front&Back IO_USB3.0

ASUSTek COMPUTER INC.


Engineer: Aaron_Su
Size Project Name Rev
A1 Maximus XII Extreme R1.01

Date: Friday, December 20, 2019 Sheet 74 of 152


0.5B
+3VSB power
+3V_SPI
F1C8 close to Pin 8 VDD. F1JP1 Standard Circuit
1 2

SHORTPIN BIOS SPI


+3V main power /X/SPI_SMD
+F1_SPI_PWR
REV. F1_0.5B

F1R12 62Ohm SPI /X/SPI_SMD


1 2 6 SCK VDD 8
114 F_SPI_CLK_R
F_SPI_CLK_L

1
F1C8
0.1UF/16V +3VSB +3V_SPI

2
F1D2

1
GND 3
2

BAT54CW

F1R13 62Ohm F1R20


1 2 2 SO 1 2
Using
114 F_SPI_MISO_R
F_SPI_MISO_L +3VSB,
0Ohm +3V,
/X/SPI_SMD +1.8VSB,
+1.8V
depends on project spec.

F1R14 62Ohm
1 2 5 SI
114 F_SPI_MOSI_R
F_SPI_MOSI_L

+F1_SPI_PWR
1KOhm

1KOhm
2

12V06110010M for 水平插入SPI CARD 12006V00023300 for 垂直插入SPI CARD


mbs_hd_2x5p_79_k10_pin_lf3 mbs_hd_2x5p_79_k10_ls_lf3
F1R10

F1R11
1

F1R5 1 62Ohm 2 7 HOLD#


42 F_SPI_IO3
F1R6 1 62Ohm 2 F_SPI_HOLD# 3 WP#
42 F_SPI_IO2
F_SPI_WP#
2

F1R16 F1R15
1.2KOhm 1.2KOhm
1% 1%
/X/SPI_SMD /X/SPI_SMD
1

GND GND

1 CE# VSS 4
75,114 F_SPI_CS0#_R
5-Pin 這一面靠近SMD BIOS.
使Header限制區剛好在SMD BIOS上方.

GND

SMT FLASH 256M +F1_SPI_PWR


F1U1
9
GND2
1 8
CS# VCC
F_SPI_CS0#_R 2 7
DO(IO1) HOLD#/RESET#(IO3)
F_SPI_MISO_L 3 6 F_SPI_HOLD#
WP#(IO2) CLK
F_SPI_WP# 4 5 F_SPI_CLK_L
GND1 DI(IO0)
F_SPI_MOSI_L
W25Q256JVEIQ
05006-00032100
GND GND
s_dfn_8p_236x315_pad_colay
<Variant Name>

Title : SINGLE BIOS_SPI SMD-1

ASUSTek COMPUTER INC.


Engineer: Eagle Liu
Size Project Name Rev
0.5B
A2 Standard Circiut
Date: Thursday, December 12, 2019 Sheet 75 of 152

LPC Debug Port


2019029 folow Z390-I
+3V
LPC_DEBUG
12
12
11 14
COM Debug 10
11
10
SIDE2
+F1_SPI_PWR 9
66,68 O_TXD1_R 9 Debug Connector Pool :
8
8 12018-00103000 FPC CON 12P 0.5MM,R/A,SMT ACES/51578-01201-002
7
7 躺式(掀)(X,Y,Z)10.4,4.45,1.5 nbfpc12p202hdraace
F_SPI_HOLD# 6
6 12018-00102900 FPC CON 12P 0.5MM,R/A,SMT ENTERY/6705K-Y12N-20L
F_SPI_CLK_L 5
5 躺式(掀)(X,Y,Z)10.1,4.47,1.5 nbfpc12p202hdraace
F_SPI_MOSI_L 4
4 12G183301208 FPC CON 12P,0.5mm,S/T,SMT ACES/87152-12071
3
3 抽屜式(X,Y,Z) 10.4,6.3,1.9 nbs_fpc_12p_002c
F_SPI_WP# 2 13
2 SIDE1
F_SPI_MISO_L 1
75,114 F_SPI_CS0#_R 1

FPC_CON_12P

SPI 12018-00102300

GND
24 Pin ATX Connector
+5VSB_ATX

Short pin:

/PWR_CON
JP7, JP15 don't open stencil for version1 connector
EATXPWR

20KOhm BR2
2
+3V +5VSB_ATX +3V +3V +5V 顏色: Black
Short pin:
顏色: T-C
+12V +5V -12V
8 Pin +12V Connector C8H / C8F用12015-00059800 JP14, JP16 don't open stencil for version2 connector

25
帶鐵殼_DET-pin

1
1 13
+3V1 +3V4
2 14

NP_NC
+3V2 -12V
3 15
GND1 GND4
4
5
+5V1 PSON#
16
17
O3_PSON# 24 8-Pin POWER 實心 +12V_CPU
GND2 GND5
6 18
+5V2 GND6
7 19
8
GND3 GND7
20
EATX12V
66 B_ATX_PWROK PWR0K -5V
9 21 +3VDUAL_AUX
5VSB +5V3

1
10 22 9
+12V1 +5V4 P_GND
1 11 23 BC3 4 8
+12V2 +5V5 4 8
BC15 12 24 0.1UF/16V 2X4_GND 3 7
+3V3 GND8 3 7

2
0.1UF/16V /PWR_CON 2 6

1
2 6
2

/PWR_CON POWER_CON_24P BR18 1 5


1 5

2
12015V00035400 8.2KOhm
/X/8PinDET_Ver2 BR6

1
實心 1KOhm PWR_2X4P

2
GND GND GND GND /8PinDET_Ver2
GND 12015-00059800 BC5
100NF/16V

2
/PWR_CON
/X/PWR_CON

Bypass/EMI Capacitor 66 2X4_POWER_DETECT


2X4_POWER_DETECT
GND GND

+3V +5V -12V +12V X599 Remove O2_CUT_PSON# path

3
D

BQ4
H2N7002 11
H_SKTOCC# 35,66,72
1

1
BC9 BC10 BC11 BC12 BC13 BC14 G
1

S
BR4 0.1UF/16V 0.1UF/16V BR5 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 2

2
100Ohm 100Ohm
2

2
/X/PWR_CON /X/PWR_CON /X/PWR_CON /X/PWR_CON /X/PWR_CON /X/PWR_CON /X/PWR_CON /X/PWR_CON
mbs_r1206 mbs_r1206
2

GND
GND GND GND GND GND GND GND GND
ATX power 會漏電

+5VSB_ATX DET pin.9 Ver1 12015-00059800 Stuff


Option : /8PinDET_Ver1 -> Stuff
Option : /8PinDET_Ver2 -> unstuff unstuff

placemented on power source of 24pin.

DET pin.9 Ver2 料號未出來


1

BC7 BC8 unstuff


0.1UF/16V 0.1UF/16V Option : /8PinDET_Ver1 -> unstuff
Option : /8PinDET_Ver2 -> stuff Stuff
2

/X/PWR_CON /X/PWR_CON
20190807 Remove 24pin DIP CAP
X399 CPU DET
Ver1 / Ver2 DET 方式剛好相反
X599 SIO DET
GND GND Same C6E SIO pin

SMD & DIP colay@20141205

20190807 Remove 8pin LED Function

Ver1 :
DETECT 有沒有插8PIN的CPU EATX12V
High 沒插需秀出警示
Low 有插不需秀出警示
Ver2 : 以上相反

X599 only

X399歷代是兩個都有插才不會跳出F1警示

NO CPU: High 有安裝CPU?8Pin LED燈號Default亮燈,若插入8-pin PWR Cable則燈號OFF


With CPU: LOW

無安裝CPU?8Pin LED燈號Default不亮燈,若插入8-pin PWR Cable則燈號OFF

C6H have CUT-power

C6E have DET power, NO CUT

R6E have DET power, and CUT power

www.teknisi-indonesia.com
<Variant Name>

Title : Power Connnecter

ASUSTek COMPUTER INC.


Engineer: Aaron_Su
Size Project Name Rev
A2 Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 76 of 152


1.22

Screw Hole Fiducial Mask


(光學點)
Mini-ITX Screw Hole 大顆光學點
Delete it for EMS

H1 H4
1 13 1 13
NP_NC GND12 NP_NC GND12
2 12 2 12
GND1 GND11 GND1 GND11
3 11 3 11
GND2 GND10 GND2 GND10
4 10 4 10
GND3 GND9 GND3 GND9
5 9 5 9
GND4 GND8 GND4 GND8
6 8 6 8
GND5 GND7 GND5 GND7
7 7
GND6 GND6

C380D160N C380D160N
GND s_hole_c380d160n_up_v12 GND GND s_hole_c380d160n_ur_v12 GND
/X /X
origin-xy:(1300.00, 6450.00) origin-xy:(6500.00, 6450.00)

小顆光學點

大顆十字光學點
6.7 inch

AH2 H5
1 13 1 13
NP_NC GND12 NP_NC GND12
2 12 2 12
3
GND1 GND11
11 3
GND1 GND11
11
小顆十字光學點
GND2 GND10 GND2 GND10
4 10 4 10
GND3 GND9 GND3 GND9
5 9 5 9
GND4 GND8 GND4 GND8
6 8 6 8
GND5 GND7 GND5 GND7
7 7 INDEX31 INDEX32 INDEX33 INDEX34 INDEX35 INDEX36
GND6

C380D160N
A C380D160N
GND6
1
1
1
1
1
1
1
1
1
1
1
1

s_hole_c380d160n_d_v12 GND GND s_hole_c380d160n_dr_v12 GND INDEX_PLUS INDEX_PLUS INDEX_PLUS INDEX_PLUS INDEX_PLUS INDEX_PLUS
/X /X /X/FIDUCIAL MASK /X/FIDUCIAL MASK /X/FIDUCIAL MASK /X/FIDUCIAL MASK /X/FIDUCIAL MASK /X/FIDUCIAL MASK
origin-xy:(400.00, 250.00) origin-xy:(6500, 250.00)

(X,Y)=(0,0)

6.7 inch

9.6 inch

MB SCREW FOOTPRINT

Screw Select
s_hole_c280d160n_t_v8
Standard scale down

(9.6 x 9.6) (9.6 x <9.6)

H1
V V
H2 s_hole_c280d160n_t_u_v8
V V
H3
V V
H4
V V
H5 s_hole_c280d160n_t_r_v8
V V
H6
V V
H7
V X <Variant Name>
uATX Screw Hole/Fiducial Mask
H8 s_hole_c280d160n_t_ur_v8 Title :
V X
ASUS TeK Computer INC
Engineer: Ben Hsieh
Size Project Name Rev
A2 Standard Circuit 1.22

Date: Thursday, December 12, 2019 Sheet 77 of 152


1.15

Front Panel 20-3pin Colay 20-5 pin 20-3 Pin Front Panel 20-5 Pin Front Panel

PART Reference 與SIO共用O 並從200編起

52 S_PLED-

ESD protec�on diode


default請預留不上件for RD驗證

二選一 OD3

20190806 Remove +3V_S0iX Allen 1 6


78 I_HD_LED- O_PWRBTN#IN 66,78

+3VSB +3V Strix Z390-I


依SB power I_HD_LED+ S_PLED+
plate選擇. I_HD_LED- S_PLED-
OC206 OC207

1
OD2 2 5

1
2

1
OC205 OC204 G料號
OR500 OR204 /X/PANEL /X/PANEL /X/PANEL /X/PANEL

2
8.2KOhm 8.2KOhm 1000PF/50V 1000PF/50V GND
1000PF/50V

2
/PANEL /X/PANEL F_PANEL 1000PF/50V
3 4

2
66,78 O_RSTCONI#
1

1 2 GND
3 4 +5V
78 I_HD_LED- 5 6
GND GND IP4220CZ6
7 8 /PANEL
66,78 O_RSTCONI# SPEAKER
9
1
OC214

1
OC200 HEADER_2X5P_K10 2
0.1UF/16V 12V602025BA0 3
X7R 4

2
/X/PANEL A_PCBEEP
1UF/10V
OC203 OC208

2
HEADER_1X4P OR202
/SPEAKER_4PIN
12006-00152600 /X/PANEL /X/PANEL

2
33Ohm
0.1UF/16V 0.1UF/16V

1
GND

3
OQ200 A_SPKR_Q
C
1 B
GND
GND GND
E
OR203 2 +5V +5VDUAL_AUX
PMBS3904
1 2
45 S_SPKR
S_SPKR need to S_SPKR_R
check the SB 2.7KOhm
output type of 66,78 O_PWRBTN#IN

2
Push-pull or

1
O/D OC201 OR220 OR221
0.01UF/16V
X7R
For Stealth mode 300Ohm 300Ohm

2
N/A N/A

1
mbs_r0603 mbs_r0603

GND

GND
I_HD_LED+ S_PLED+

chassis intruder
FP HDLED FP PLED
support Footprint P/N 實際上料 BOM option

3
Front Panel P/N pull high 2M Ohm OQ6004A OQ6004B
to +3V_BAT & 2 2N7002KDW 5 2N7002KDW
100PF Cap to GND

4
on SIO side or
20-3 Pin 20-3 Pin Chipset side /NA /NA
支援 紅框內線路全上件
12006-00201700 12006-00201700
20-3 Pin 20-5 Pin
不支援(預留不上) 紅框內線路為/X 預留不上 GND GND
12006-00201700 12006-00202000
20-5 Pin 20-5 Pin
不支援 移除紅框內線路
12006-00202000 12006-00202000
PWR_LED_R

3
OQ6003B
5 2N7002KDW
STEALTH_MODE_EN_Q

4
/NA

GND

+5VDUAL_AUX
Default : GPI
Stealth mode : GPO Low STEALTH_MODE_EN_Q 102

1
OR8333
8.2KOhm
/NA

2
CLOSE TO PANEL

+3VSB 1.02 1k change to 330 ohm@0315A

On board HD_LED

1
OR8337
8.2KOhm
/NA

6
OQ6003A
2 2N7002KDW
66 STEALTH_MODE_EN_SIO

1
/NA

GND

若使用Standby LED,把PWR Button+RST Button移除;

若使用PWR Button+RST Button,把Standby LED移除.

OD201
1
97 M2_SSDLED#
3
2 I_HD_LED-
44 T_SATALED#

SB LED BAW56W

O_PWRBTN#IN 66,78
1

+3VSB
OC5051
0.1UF/16V
2

/X
2

OR8022
1.8KOHM
GND /PANEL
1

Change the net name to combine the HD LED active

請按照下列 Net name 修改: T1_SATALED#


PWR Button PWR_LED_R T2_SATALED#

M2_SSDLED#
M2_2_SSDLED#

用不到的 net 請Delete,並打x

<Variant Name>

Title : Panel&HotStart&Stealth
ASUS TeK Computer INC
Engineer: Aaron_Su
Size Project Name Rev
A1 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 78 of 152


1.9

Near Connector (Void)

SATA6G_1
1 8
44 T_SATA_TXP0 GND1 NC1
T_SATA_TXP0 2
A+
3
44 T_SATA_TXN0 A-
Connector 顏色 T_SATA_TXN0 4
GND2
5
44 T_SATA_RXN0 B-
T_SATA_RXN0 6
B+
SATA6G_123456 LIGHT GRAY 7 9
44 T_SATA_RXP0 GND3 NC2
T_SATA_RXP0

BROWN SATA_CON_7P
GND 12015-00066700

180度connector
SATA6G_2
1 8
44 T_SATA_TXP1 GND1 NC1
T_SATA_TXP1 2
A+
3
44 T_SATA_TXN1 A-
T_SATA_TXN1 4
GND2
5
44 T_SATA_RXN1 B-
T_SATA_RXN1 6
B+
7 9
44 T_SATA_RXP1 GND3 NC2
T_SATA_RXP1

SATA_CON_7P
GND 12015-00066700

R/A Connector擺放與板端切齊,
如上圖黑色箭頭處.

Near Connector (Void)

SATA6G_3
1 8
44 T_SATA_TXP2 GND1 NC1
Connector 顏色 T_SATA_TXP2 2
A+
3
44 T_SATA_TXN2 A-
T_SATA_TXN2 4
GND2
SATA6G_123456 LIGHT GRAY 5
44 T_SATA_RXN2 B-
T_SATA_RXN2 6
B+
7 9
44 T_SATA_RXP2 GND3 NC2
BROWN T_SATA_RXP2

SATA_CON_7P
GND 12015-00066700

180度connector
SATA6G_4
1 8
44 T_SATA_TXP3 GND1 NC1
T_SATA_TXP3 2
A+
3
44 T_SATA_TXN3 A-
T_SATA_TXN3 4
GND2
5
44 T_SATA_RXN3 B-
T_SATA_RXN3 6
B+
7 9
44 T_SATA_RXP3 GND3 NC2
T_SATA_RXP3

SATA_CON_7P
GND 12015-00066700
R/A Connector擺放與板端切齊,
如上圖黑色箭頭處.

<Variant Name>

Title : SATA6G_123456(CHIPSET)

ASUSTek COMPUTER INC.


Engineer: Aaron_Su
Size Project Name Rev
A2 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 79 of 152


Address : 0x22

+5VDUAL_AUX

D3C53

1
D3R127 0.1UF/16V
1.3KOhm /3933

2
/3933
20190821 remove 0 ohm

1
GND

D3UP4

1
D3R128 1 8
VCC OUT1 +VCCIO_0_REF_3933_10 13
3.9KOhm 2 7
ADD_SEL OUT2 +VCCIO_1_2_REF_3933_10 13
/3933 3 6
GND OUT3 +VCCSTG_REF_3933_10 30
4 5

2
SDA SCL

NCT3933U

GND
6,72,80 O2_SMB1_DATA
6,72,80 O2_SMB1_CLK

1
D3C54

1
330PF/50V D3C52
/X/3933 330PF/50V

2
/X/3933

2
GND GND

Address : 0x28 Address : 0x2A

+5VDUAL_AUX +5VDUAL_AUX

D3C37 D3C38
1

1
1

1
D3R11 0.1UF/16V D3R12 0.1UF/16V
3.9KOhm /3933 2.2KOhm /3933
2

2
/3933 /X/3933

20190821 remove 0 ohm


2

2
GND GND
20191029 EE需新增3933
2

2
D3UP2 D3UP3
D3R13 1 8 D3R14 1 8
VCC OUT1 VCC OUT1 +VCCST_REF_3933_10 26
1.3KOhm 2 7 10KOhm 2 7
ADD_SEL OUT2 ADD_SEL OUT2 P_+VPPDDR_TEST_3933 18
/3933 3 6 /3933 3 6
GND OUT3 P_VCCSA_3933_OV_10 12 GND OUT3 +1.05V_A_VREF_3933 19
4 5 4 5
SDA SCL SDA SCL
1

1
NCT3933U NCT3933U

GND GND
1 0Ohm 2 D3R123
6,72,80 O2_SMB1_DATA 6,72,80 O2_SMB1_DATA
1 0Ohm 2 D3R122 D3UP2_SMB1_DATA
6,72,80 O2_SMB1_CLK 6,72,80 O2_SMB1_CLK
D3UP2_SMB1_CLK
1

1
D3C39 D3C41
1

1
330PF/50V D3C40 330PF/50V D3C42
/X/3933 330PF/50V /X/3933 330PF/50V
2

2
/X/3933 /X/3933
2

2
GND GND GND GND

<Variant Name>

Title : NCT3933

ASUSTek COMPUTER INC.


Engineer: Aaron_Su
Size Project Name Rev
A3 Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 80 of 152


0.5D

BOM option use ES2 sample


(WW24 19')
share Reset Signal with other devices
Power consumption=700 mA (including 1.0V),建議使用+3V_DUAL power.
/I225-1/Internal 1.0V mount
+3VSB

L1R16 /I225-1/External 1.05V 預留for第一版IC驗證用


1 2

2
0Ohm +3V_DUAL_L1U1 +3VSB_LAN1
L1R98 /X/225-1
8.2KOhm L1JP3
/I225-1
L1D20 2 1

1
+L1_1.0V SHORTPIN_0603_NM
35,42,55,66 S_PLTRST#

1
2 L1U1C129 L1U1C7 L1U1C207 L1U1C307 /X/I225-1
3 GND 10UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
44 O_X1_RST#
BAT54AW 1 mbs_c0603 mbs_c0603 /I225-1/Internal 1.0V /I225-1/Internal 1.0V

2
1

1
/I225-1 L1U1C9 L1U1C38 L1U1C26 L1U1C44 L1U1C50 L1U1C56 /X/I225-1 /I225-1/Internal 1.0V

2
+3V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V +3VSB_LAN1
X7R X7R X7R X7R X7R X7R L1R8

2
/I225-1 /X/I225-1 /I225-1 /I225-1 /X/I225-1 /I225-1 0Ohm GND
2

L1R17

1
8.2KOhm GND L1U1C53 L1U1C47 L1U1C14 L1U1C33 L1U1C23 L1U1C39 L1U1C43
/I225-1 L1L6 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V Standard Circuit
SHORTPIN_0603_NM L1L5 X7R X7R X7R X7R X7R X7R X7R
1

2
1 2 /I225-1 /I225-1 /X/I225-1 /X/I225-1 /I225-1 /I225-1 /X/I225-1

L1_VQPS
L1_DEV_RST# 2 1 +L1_1.0V_VOUT_L +L1_1.0V_VOUT LAN I225

1
L1U1C130 /X/I225-1 L1U1C6 L1U1C205 L1U1C5 1UH
10UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V /I225-1/Internal 1.0V GND
mbs_c0603 mbs_c0603 /I225-1/Internal 1.0V /I225-1/Internal 1.0V REV. L1_0.5D

2
L1_DEV_RST# GPIO select: /I225-1 /I225-1/Internal 1.0V
1. could be GPI & GPO both, default GPI (no internal AOAO I225
pull-down/pull-high resistor) GND
2. main power plane or stand by power plane, 3V tolerance

38

26

44
50
56

53
47

14
33

23

39

43
GND L1U1A

5
6

7
3. default GPI, set GPO low to reset Intel LAN

VDD_CTRL1
VDD_CTRL2

VDD_CORE1
VDD_CORE2

VDD_VP

VDD_A_1
VDD_A_2
VDD_A_3

RESEVRED

+3.3V_A_1
+3.3V_A_2

+3.3V_DC

+3.3V_PAD1
+3.3V_PAD2

+3.3V_VPH

+3.3V_XO

+3.3V_CDB
4.For Glacier Falls Platfotm : 請接至SB : GPP_K2 +3VSB_LAN1
L1C12 2 1 10PF/50V /X/I225-1
L1C13 2 1 10PF/50V /X/I225-1
L1R14 1 300Ohm 2
L1_ACTLEDP 74,83

GND

Place near LAN IC 45 AI/AO


MDI_A_P L1_MDI_0+ 74,83
L1C3 0.1UF/16V X7R AO 25 46 AI/AO
43 S_X1_LAN1_RXP PE_Tx_P MDI_A_N L1_MDI_0- 74,83
1 2 L1C4 0.1UF/16V X7R S_X1_LAN1_RXP_C AO 24
43 S_X1_LAN1_RXN PE_Tx_N
1 2 S_X1_LAN1_RXN_C 48 AI/AO
PCIE IF SL1C1 0.1UF/16V X7R AI 28
MDI_B_P
49 AI/AO
L1_MDI_1+ 74,83
43 S_X1_LAN1_TXP PE_Rx_P MDI_B_N L1_MDI_1- 74,83
1 2 27
勿接在chipset PCIE port0
43 S_X1_LAN1_TXN
Place near ChipSet
SL1C2
1 2
0.1UF/16V X7R S_X1_LAN1_TXP_C
S_X1_LAN1_TXN_C
AI
PE_Rx_N
Foxville MDI_C_P
51 AI/AO
L1_MDI_2+ 74,83
AI 21 52 AI/AO
47 C_PCIE_L1 PE_CLK_P MDI_C_N L1_MDI_2- 74,83
AI 22
47 C_PCIE_L1# PE_CLK_N
54 AI/AO
pull high on Chipset Side MDI_D_P L1_MDI_3+ 74,83
I/O 3 55 AI/AO
47 CLK_REQ1_LAN# PE_CLKREQ_N MDI_D_N L1_MDI_3- 74,83
L1R100 0Ohm /I225-1 I/O 12
45,60,97 X_WAKE# PE_WAKE_N
2 1 L1C14 2 1 10PF/50V /X/I225-1 I 13 32 O L1R15 1 300Ohm 2
PE_RST_N LED0 L1_LINK100# 74,83
L1R101 0Ohm /X/I225-1 L1R54 1 2 1KOhm /X/I225-1 L1_DEV_RST# 31 O L1_LINK100#_R
45 L1_LAN_WAKE# LED1 L1_LINK1000_2500# 74,83
2 1 I/O 11 30 O
SMB_CLK LED2 L1_ACTLEDN 74,83
L1_SMBCLK_R I/O 10 +3VSB_LAN1
SMB_DATA
GND +3VSB_LAN1 L1_SMBDATA_R I/O 4
ULP_WAKE_N
L1_SMBALRT# 1 I L1R6 1 2 10KOhm
I/O 36
LAN_PWR_GOOD
2 I L1_LAN_PWR_GOOD L1R13 1 8.2KOhm 2
建議使用Cut-off power solu�on解決Disable LED issue
Optional Security Strapping L1R34 1 2 10KOhm L1_SPI_SODI I/O 34
SPI_DIN/AUX_PWR LAN_DISABLE_N
L1_DEV_OFF#_R 如有接Cut off power線路, 請刪除橘框
SPI_DOUT/SEC_ENA

1
Normal Operation: L1R34上件,預留L1R33 L1R33 1 2 1KOhm /X/I225-1 L1_SPI_SIDO I/O 35 L1C6
SPI_CLK
L1R35 1 2 10KOhm L1_SPI_CLK I/O 37 15 L1R4 1 2 49.9Ohm 0.1UF/16V
SPI_CS_N/PCIE_ENA SDP0
L1R22 1 2 10KOhm /X/I225-1 L1_SPI_CS# L1_SDP0 /X/I225-1 X7R

2
/X/I225-1 L1R97 1 2 0Ohm
L1_LAN_DISABLE# 45
AI 41 /X/I225-1
Debug Disable Strapping GND +3VSB_LAN1 L1_XIN AO 40
XTAL_IN
TPC26b L1T1 /X GND
XTAL_OUT
Normal Operation: L1R35 上件 L1_XOUT 16 1 L1R99 1 2 0Ohm
JTAG_RSTN L1_DEV_OFF# 44
L1R9 1 8.2KOhm 2 18 42 AI/AO L1_TRSTN L1R5 1 2 22KOhm /I225-1
JTAG_TDO/MDI_LANE_SWAP PHY_CAL
L1R10 1 8.2KOhm 2 L1_TDO 19 L1_RCAL
JTAG_TDI_SDP1
L1R11 1 8.2KOhm 2 L1_TDI 17 20 AI/O L1R1 1 2 200Ohm
PCIe Disable Strapping L1R12 1 8.2KOhm 2 L1_TMS 29
JTAG_TMS_SDP2 RBIAS
L1_LREXT
L1_TCK
JTAG_CLK L1_LAN_DISABLE#
Normal Operation: 預留L1R22

2
GND L1_DEV_OFF# GPIO select:
L1R23
VSS1
57 1. could be GPI & GPO both, default GPI no internal
10KOhm pull-down/pull-high resistor)
MDI LANE SWAP STRAPPING: /X/I225-1 I225-V 2. stand by power plane, 3V tolerance
MDI trace routing between I225 and Magnetics 3. GPI to enable Intel LAN
需要Support VPRO func�on才需要接到PCH IC 量產前Sample都只有I225LM,SR請先打I225-LM 4. GPO low to disable Intel LAN
1

has the layout crossing problem, GND


non-VPRO func�on則可以將橘框刪除 we can setup the trapping on pin#18
06112-00450400 L1U1B
5. If support wake-up under Deep S4/S5, require
MDI ABCD lanes will be reversed and become DCBA lanes.
58
+3VSB_ATX power plane GPIO
GND +3VSB_LAN1
VSS2 6.For Glacier Falls Platfotm : 請接至SB:GPP_H15
59
VSS3 7.For CML Platfotm : 請接至SB : GPP_K1
60
VSS4
L1R44 0Ohm /X/I225-1 L1R19 1 2 2.7KOHM /I225-1 61
L1_SMBCLK & 45 L1_SMBCLK
L1R43 2 1 0Ohm /X/I225-1 L1_SMBCLK_R L1R18 1 2 2.7KOHM /I225-1
VSS5
62
L1_SMBDATA 45 L1_SMBDATA
L1R47 2 1 0Ohm /X/I225-1 L1_SMBDATA_R L1R20 1 2 10KOhm /I225-1
VSS6
63
VSS7
2 1 L1_SMBALRT# 64
VSS8
Connect to PCH 65
VSS9
SML0CLK and SML0DATA 66
and need to pull-up VSS10
67
499ohm resistors to VSS11
68
+3VSB at PCH side.
XTAL 二擇一 VSS12
VSS13
69

I225-V
GND

SPI Flash +3VSB_LAN1


SMD Crystal
STD驗證
L1R37 1 10KOhm 2
L1R52 1 2 1MOHM
/X/I225-1 /I225-1 L1U2
1 8

teknisi indonesia
CS# VCC
L1X2 25Mhz L1_SPI_CS# 2 7
DO(IO1) HOLD#/RESET(IO3)
1 3 L1_SPI_SODI 3 6
WP#(IO2) CLK
L1_XOUT L1_XIN 4 5 L1_SPI_CLK
GND DI(IO0)
L1_SPI_SIDO
1

07009-00024100 W25Q80DVSSIG L1U2C8


2

L1C5 L1C7 05006-00040800 0.1UF/16V


22PF/50V 22PF/50V GND X7R
2

/X/I225-1

GND
GND

<Core Design>

Title : L1_I225

ASUSTek Computer Inc.


Engineer: Tom Yang
Size Project Name Rev
A2 Standard Circiut 0.5D

Date: Tuesday, December 17, 2019 Sheet 81 of 152


0.5D
使用ES0 sample 才需要外轉1.05V

1. 外轉1.05V Power consumption=500 mA


2. 外轉1.05V power consumption較大,建議使用+5V_DUAL power.

使用ES0 sample 才需要外轉1.05V


1.05V for I225, 500mA

Power Component place near each other!


20191030 Allen Remove

<Core Design>

Title : I225_PWR

ASUSTek Computer Inc.


Engineer: Tom Yang
Size Project Name Rev
A3 Standard Circiut 0.5D

Date: Thursday, December 12, 2019 Sheet 82 of 152


0.5D
Delete it for EMS STD驗證 Delete it for EMS

L1D1
11
island
1 10
I/O1 I/O2
2 9
VDD GND
3 8
NC1 NC2
4 7
74,81 L1_MDI_0+ I/O3 I/O4 L1_MDI_0- 74,81
5 6
74,81 L1_MDI_1+ I/O5 I/O6 L1_MDI_1- 74,81

AZ1385-06F.R7G
/X/I225-1
GND

L1D2
11
island
1 10
I/O1 I/O2
2 9
VDD GND
3 8
NC1 NC2
4 7
74,81 L1_MDI_2+ I/O3 I/O4 L1_MDI_2- 74,81
5 6
74,81 L1_MDI_3+ I/O5 I/O6 L1_MDI_3- 74,81

AZ1385-06F.R7G
/X/I225-1
GND

L1C90 2 1 1000PF/50V
74,81 L1_ACTLEDP
X7R /X/I225-1 L1_CTR

L1C91 2 1 1000PF/50V
74,81 L1_ACTLEDN

1
X7R /X/I225-1 L1C94 L1C95
100PF/50V 120PF/50V
L1C92 2 1 1000PF/50V /X/I225-1 /X/I225-1
74,81 L1_LINK1000_2500#

2
X7R /X/I225-1

L1C93 2 1 1000PF/50V
74,81 L1_LINK100#
X7R /X/I225-1

Place near LAN Connector


GND GND

Place capacitors near the Lan


Choose a proper LAN Connector in page Back I/O
Connector Connector.
Maybe need to be modified according
to the different EMI consideration.
L1_ACTLEDP
L1_ACTLEDN

GND

L1_MDI_3-
L1_MDI_3+
L1_MDI_2-
L1_MDI_2+
L1_MDI_1-
L1_MDI_1+
L1_MDI_0-
L1_MDI_0+

74 L1_CTR
1

L1C97 L1C46
0.1UF/16V 1UF/10V
L1_LINK1000# /I225V-1 /I225V-1
L1_LINK100#
2

GND

<Core Design>

Title : L1_I225_Connector

ASUSTek Computer Inc.


Engineer: Tom Yang
Size Project Name Rev
A3 Standard Circiut 0.5D

Date: Thursday, December 12, 2019 Sheet 83 of 152


Title : CPTH (CNVi)

ASUSTek Computer Inc.


Engineer: Aaron_Su
Size Project Name
Maximus XI Extreme Rev
C R1.01

Date: Thursday, December 12, 2019 Sheet 84 of 152


Title : CPTH (CNVi)

ASUSTek Computer Inc.


Engineer: Aaron_Su
Size Project Name
Maximus XI Extreme Rev
C R1.01

Date: Thursday, December 12, 2019 Sheet 85 of 152


0.1B Beta
H/W Strapping Note:
PWR&PWRGD Ready後, 1.8mS內會完成所有Latch H/W Strapping 桃紅框可改netname和tune 值
橘框可選option

72 O2_CLK_PWREN

EC GPIO (PP,Standby power)


Default: GPI Low (Clock Gen 有電)

1
Reset Clock Gen: GPO High
CR14
8.2KOhm
/X/CLK

2
CLK GEN在S0和S3有電
(操作電流max約300mA)
SEL_CLK Function Select Table CPU Frequency Selection Table
GND
SEL_CLK X1/CLKIN X2/CLKINB HW_FSEL VCO_SEL VCO(MHz) CPU Divider CPU(MHz)
0 X1 X2 0 0 400 4 100
1 CLKIN CLKINB 0 1 1000 10 100
1 0 412 4 103
1 1 1030 10 103
*Default by hardware latch

35,47,86 C_CPU0#
Sequency
Co-Lay
35,47,86 C_CPU0 若需改由PCH提供Clock Input需額外考慮時序因素:
CR16 & CR19 Co-Lay 開機時序: +VDD_CLK_B → CLK Input → PWRGD
CR17 & CR20 Co-Lay 關機時序: PWRGD → CLK Input → +VDD_CLK_B
Clock input from PCH

C_CPU0# 35,47,86
72 O2_RELATCH

1
C_CPU0 35,47,86 EC GPIO (PP,Standby power) CR23
Default: GPI Low
8.2KOhm
Relatch: GPO High
Clock input from CLKGEN CC12 CC13 Clock output to CPU /X/CLK
2

1.5PF/50V 1.5PF/50V

2
/X /X
1

GND
GND GND

42 C_DOC1
42 C_DOC0

1
請選用Default為GPI CR54 CR53
C_RESET#為OD Pin,需外部Pull-Up 且可推Push-Pull的GPIO 8.2KOhm 8.2KOhm
請確認O_RSTCONO#和O_PWROK是否已Pull-Up /X/CLK /X/CLK

2
GND GND

Device Slave Address: 0xD2

Title : CLKGEN_IDT6V41537

ASUSTek Computer Inc.


Engineer: Scott2_Lin
Size Project Name Rev
A2
KABYLAKE 0.1B

Date: Thursday, December 12, 2019 Sheet 86 of 152


+3VSB_WIFI_BT2 1.2

CLOSE TO M.2

2
WR303 0Ohm /CNVI
WR305
10KOhm 2 1
/CNVI

1
CFL PCH : GPP_H11

S
D
M.2_WIFI_RF_KILL# 42
3 2
請注意以下short pin需請板卡課協助幫忙開鋼板short

2
WQ100 +3VSB

G
H2N7002
WR3/WR4/WR5/WR6/WR7/WR8/WR9/WR10/WR11/WR12/WR13/WR14

11
/X/CNVI

1
+3VSB_WIFI_BT2 WR304
100KOhm
/X/CNVI

2
GND
CNVI(WiFi)A +3VSB_WIFI_BT2

SHORTPIN_0402 1 WR10 2 /X/CNVI


51 CNV_WT_CLK_DP

1
SHORTPIN_0402 1 WR9 2 /X/CNVI CNV_WT_R_CLK_DP CLOSE TO M.2
51 CNV_WT_CLK_DN

2
CNV_WT_R_CLK_DN CLOSE TO PCH WCX112 WCX113 WR99 0Ohm /CNVI
SHORTPIN_0402 1 WR11 2 /X/CNVI 0.1UF/16V 22UF/6.3V WR301
51 CNV_WT_0_DP

2
SHORTPIN_0402 1 WR12 2 /X/CNVI CNV_WT_R_0_DP SWR31 /CNVI /CNVI 10KOhm 2 1
51 CNV_WT_0_DN CNVi_CLKIN_XTAL 47
CNV_WT_R_0_DN CNVi_CLKIN_XTAL_R 2 0Ohm 1 1.5PF/50V /CNVI
SHORTPIN_0402 1 WR14 2 /X/CNVI SWC1 1 2
/X/CNVI
51 CNV_WT_1_DP

1
SHORTPIN_0402 1 WR13 2 /X/CNVI CNV_WT_R_1_DP 1 SWR306 2 GND GND
51 CNV_WT_1_DN GND CFL PCH : GPP_B3
CNV_WT_R_1_DN 10KOhm
M.2_WIFI_RF_KILL#_Q

S
D
M.2_BT_RF_KILL# 42
M.2_BT_RF_KILL#_Q 3 2

2
WR28 1 33Ohm 2 /X/CNVI WQ99 +3VSB
PCH_SUSCLK 36,45,97

G
CNV_SUSCLK WR21 1 0Ohm 2 /X/CNVI H2N7002

11
1 0Ohm 2 CNV_MFUART2_RXD 51
CNV_MFUART2_RXD_R WR29 /X/CNVI /X/CNVI
CNV_MFUART2_TXD 51
CNV_MFUART2_TXD_R WR30 1 0Ohm 2 /X/CNVI
CNV_GNSS_PA_BLANKING 51
CNV_GNSS_PA_BLANKING_R For LTE function

1
如無使用可remove
+1.8V_A WR302
CLOSE TO M.2 1 SWR313 2 100KOhm
1 SWR18 2 20KOhm /X/CNVI
CNV_BRI_DT 51
CNV_BRI_DT_R 1 WR19 2 33Ohm

2
CNV_RGI_RSP 51
CNV_RGI_RSP_R 22Ohm 1 SWR20 2
CNV_RGI_DT 51
CNV_RGI_DT_R 33Ohm
+1.8V_A +1.8V_A GND
1 WR314 2 CLOSE TO PCH
20KOhm +1.8V_A
1 SWR312 2

2
SHORTPIN_0402 1 WR4 2 /X/CNVI 20KOhm
51 CNV_WR_CLK_DP
SHORTPIN_0402 1 WR3 2 /X/CNVI CNV_WR_R_CLK_DP 1 WR17 2 WR324
51 CNV_WR_CLK_DN CNV_BRI_RSP 51
CNV_WR_R_CLK_DN CNV_BRI_RSP_R 22Ohm 2.7KOhm +3VSB_ATX
SHORTPIN_0402 1 WR6 2 /X/CNVI
51 CNV_WR_0_DP 1 WR5 2
SHORTPIN_0402 /X/CNVI CNV_WR_R_0_DP

1
51 CNV_WR_0_DN
CNV_WR_R_0_DN

1
SHORTPIN_0402 1 WR8 2 /X/CNVI M.2_WIFI_CLKREQ WR352
51 CNV_WR_1_DP 1 WR7 2
SHORTPIN_0402 /X/CNVI CNV_WR_R_1_DP 100KOhm
51 CNV_WR_1_DN

3
CNV_WR_R_1_DN M.2_CRF_RST# 2N7002KDW

1
WR320 WQ103B

2
60.4KOhm 5
/X/CNVI M.2_WIFI_CLKREQ_G

4
CFL PCH Pin BA17

6
MINI_PCI_75P_REMOVE8 2N7002KDW

1
WCX110 WCX111 WQ103A
0.1UF/16V 22UF/6.3V 2
S_M.2_WIFI_CLKREQ 45
12003V00077700 /CNVI /CNVI GND GND

1
2

2
/CNVI

1
CNVI(WiFi)B SWR107
GND GND 60.4KOhm
GND GND GND

2
+1.8V_A CLOSE TO PCH

2
GND
WR325 +3VSB_WIFI_BT2
2.7KOhm

2
請依照電流需求選擇POWER WR353

1
Imax = 1.36A 2.7KOhm

MINI_PCI_75P_REMOVE8

3
GND 2N7002KDW

1
+3VSB_WIFI_BT +3VSB_WIFI_BT2 WR37 WQ105B
cut off 75KOhm 5
/X/CNVI M.2_CRF_RST#_G

4
CFL PCH Pin BE16

6
W2JP1 /X/CNVI 2N7002KDW
1 2 WQ105A
2
S_M.2_CRF_RST# 45
SHORTPIN_0603_NM GND GND

2
W2JP2 /X/CNVI
1 2
SWR108
SHORTPIN_0603_NM 75KOhm
GND

1
CLOSE TO PCH
請注意所選用的PWR rail需follow CNVI sequence需求, +3VSB_WIFI_BT2需ready後, RSMRST#才能ready
GND

<Variant Name>

Title :
intel_CNVi
ASUSTeK COMPUTER INC
Engineer: Adam Pan
Size Project Name Rev
A2 Standard Circiut 1.2

Date: Thursday, December 12, 2019 Sheet 87 of 152


+5V_DUAL_USBKB +5V_UC_P1 Strix Gaming , -A , 2.1
UF1 TUF Gaming系列
PCH USB3.0 1 2
ROG , Deluxe系列 PRIME H/B Chip系列

1. 900 mA for each port


2. 兩個port共用一組OC# & VBUS PWR 2.6A/8V
3. 確認connector VBUS PWR

1
20190812 'Remove UCE18 follow Z390-I
netname是否一致 UC1
0.1UF/16V

2
/X/USB3

UR159~UR162 U3R139~U3R146

GND Connect to Connector UR167~UR170


請依PES需求選擇DIP CAP type GND
U3R80

請RD做BOM時,手動刪除不需要的料件 1 2

4.7KOhm

U3R81
1 2
43 U_USBOC#01

8.2KOhm GND

Connect to Redriver or Retimer


74,119 S_U3D1RXDN1_RDT

74,119 S_U3D1RXDP1_RDT
U31C148 1 2 SHORTPIN_0402_NM
119 S_U3D1TXDN1_RDT
/X/USB31
U31C147 1 2 SHORTPIN_0402_NM
119 S_U3D1TXDP1_RDT
/X/USB31

43,74 U_USB0-
43,74 U_USB0+

U31_U31TXDP1_R 74

U31_U31TXDN1_R
U31G2_C1
74

U31_U31RXDP1_R
port1
74,119

U31_U31RXDN1_R 74,119

A B
U_USB0+_R 43,74,89
U_USB0-_R 43,74,89
U31GEN2 PIN ESD
Connect to Redriver or Retimer
74,119 S_U3D1RXDN2_RDT U31G2_C1 1
U31U111
9
port1 2
Line-1 NC4

void
U31_U31TXDP1_R 8
74,119 S_U3D1RXDP2_RDT Line-2 NC3
U31_U31TXDN1_R 3
GND
U31C150 1 2 SHORTPIN_0402_NM 4 7
119 S_U3D1TXDN2_RDT Line-3 NC2
/X/USB31 U31_U31TXDN2_R 5 6

void
Line-4 NC1
U31C149 1 2 SHORTPIN_0402_NM U31_U31TXDP2_R
119 S_U3D1TXDP2_RDT
/X/USB31 AZ174S-04F.R7G

GND

A B
U31_U31TXDP2_R 74

U31_U31TXDN2_R U31G2_C1
74

U31_U31RXDP2_R port2
74,119 U31GEN2 PIN ESD
U31_U31RXDN2_R 74,119

U31G2_C1 U31U112

ASUS PIN ESD SPEC 1 9


port2 2
Line-1 NC4

void
U31_U31RXDP1_R 8
Back I/O : +/- 8KV U31_U31RXDN1_R 3
Line-2 NC3

Front I/O : +/- 10KV 4


GND
Line-3 NC2
7
U31_U31RXDN2_R 5 6

void
Line-4 NC1
U31_U31RXDP2_R
ESD橘框選擇方式: AZ174S-04F.R7G

GND
橘框
A B C
組合

Front I/O Keep Keep Delete

Back I/O layout空間夠 Keep Keep Delete

Back I/O layout空間不夠 Keep Delete Delete

Back I/O layout空間不夠 Delete Delete Keep


且Pin ESD打不過8KV

A U3U10
B U3U13
C
1 6 1 6
74,89 U32_DFP_CC1 U32_DFP_CC2 74,89 43,74,89 U_USB0+_R U_USB0-_R 43,74,89

+5V_UC_P1 +5V_UC_P1

Port 7,8 2 5 2 5
<Variant Name>

GND GND Title : CHIPSET U3_Port7,8

43,74,89 U_USB0+_R
3 4
U_USB0-_R 43,74,89 74,89 U32_DFP_CC2
3 4
U32_DFP_CC1 74,89 ASUSTeK COMPUTER INC
Engineer: Brian Hsieh
Size Project Name Rev
IP4220CZ6 IP4220CZ6
A2 Standard Circiut 2.1
/X/USB3
Date: Thursday, December 12, 2019 Sheet 89 of 152
+5V_DUAL_USBKB +U_USB2_5V Strix Gaming , -A , 2.1
TUF Gaming系列
請確認是否為 USB3.1GEN1 或GEN2 ROG , Deluxe系列 PRIME H/B Chip系列
UR84~UR87 U31R123~U31R130
1.GEN1請選擇2.6A/GEN2請選擇3.5A
2. 兩個port共用一組OC# & VBUS PWR UR147~UR150
3. 確認connector VBUS PWR

1
20190812 'Remove UCE19 follow Z390-I
netname是否一致 UC2
UF2 0.1UF/16V
USB2.0 Guard

2
1 2 /X/USB31

3.5A/6V

Connect to Connector 預防PCH USB2 Signal被Device高壓damaged問題


請依PES需求選擇DIP CAP type GND
GND
請RD做BOM時,手動刪除不需要的料件 U31R100 xxx_USB31_xx
1 2

Connect to Chipset 4.7KOhm

U31R99
1 2
43 U_USBOC#2

8.2KOhm GND
LAN
+U_USB2_5V +U_USB2_5V

Connect to Redriver or Retimer 74,88,90 U31_U31RXDN3_R


74,88,90 U31_U31RXDP3_R USB31_1
74,88 S_U3D1RXDN3_RDT
74,90 U31_U31TXDN3_R
74,88 S_U3D1RXDP3_RDT 74,90 U31_U31TXDP3_R

U31C140 1 2 SHORTPIN_0402_NM
88 S_U3D1TXDN3_RDT
/X/USB31
43,74,90 U_USB2-_R USB31_2
43,74,90 U_USB2+_R
U31C139 1 2 SHORTPIN_0402_NM
88 S_U3D1TXDP3_RDT
/X/USB31

43,74 U_USB2-
43,74 U_USB2+

U31 GEN2 & GEN1 PIN ESD 橘框選擇方式:

U31_U31TXDP3_R 74,90
橘框
U31_U31TXDN3_R 74,90 A B
組合
U31_U31RXDP3_R 74,88,90 USB3
U31_U31RXDN3_R 74,88,90 U31 GEN 2 PIN ESD Keep Delete

U31 GEN 1 PIN ESD Delete Keep

U_USB2+_R 43,74,90
U_USB2-_R 43,74,90

A B

U31GEN2 PIN ESD

U31U3
1 9
Port 3 2
Line-1 NC4

void
U31_U31TXDP3_R 8
Line-2 NC3
U31_U31TXDN3_R 3
GND
4 7
Line-3 NC2
U31_U31RXDP3_R 5 6

void
Line-4 NC1
U31_U31RXDN3_R
AZ174S-04F.R7G

GND

ESD橘框選擇方式:

橘框
A B C
組合

Front I/O Keep Keep Delete

Back I/O layout空間夠 Keep Keep Delete

Back I/O layout空間不夠 Keep Delete Delete

Back I/O layout空間不夠 Delete Delete Keep


且Pin ESD打不過8KV

A U31U11

1 6
74,96 U31_DFP_CC1 U31_DFP_CC2 74,96

+U_USB2_5V

Port 3,4 2 5

<Variant Name>
GND

43,74,90 U_USB2+_R
3 4
U_USB2-_R 43,74,90
Title : CHIPSET U31_Port3,4

ASUSTeK COMPUTER INC


Engineer: Brian Hsieh
IP4220CZ6
Size Project Name Rev
A2 Standard Circiut 2.1

Date: Thursday, December 12, 2019 Sheet 90 of 152


+5V_DUAL_USBKB +U_USB45_5V Strix Gaming , -A , 2.1
TUF Gaming系列
請確認是否為 USB3.1GEN1 或GEN2 ROG , Deluxe系列 PRIME H/B Chip系列
1.GEN1請選擇2.6A/GEN2請選擇3.5A
2. 兩個port共用一組OC# & VBUS PWR
3. 確認connector VBUS PWR

1
20190812 Remove UCE20 follow Z390-I
netname是否一致 UC3 UR88~UR91 U31R131~U31R138
UF3 0.1UF/16V

2
1 2 /X/USB31 UR151~UR154

3.5A/6V

請依PES需求選擇DIP CAP type GND


GND
Connect to Connector USB2.0 Guard
請RD做BOM時,手動刪除不需要的料件 U31R102
1 2
xxx_USB31_xx
預防PCH USB2 Signal被Device高壓damaged問題
Connect to Chipset 4.7KOhm

U31R101
1 2
43 U_USBOC#45

8.2KOhm GND
LAN
+U_USB45_5V +U_USB45_5V

Connect to Redriver or Retimer 74,88,91


74,88,91
U31_U31RXDN5_R
U31_U31RXDP5_R USB31_1
U31_U31RXDN6_R
U31_U31RXDP6_R
74,88,91
74,88,91

74,88 S_U3D1RXDN5_RDT 74,91 U31_U31TXDN5_R U31_U31TXDN6_R 74,91


74,91 U31_U31TXDP5_R U31_U31TXDP6_R 74,91
74,88 S_U3D1RXDP5_RDT
U31C144 1 2 SHORTPIN_0402_NM
43,74,91 U_USB4-_R USB31_2
88 S_U3D1TXDN5_RDT 43,74,91 U_USB4+_R

teknisi indonesia
/X/USB31
U31C143 1 2 SHORTPIN_0402_NM
88 S_U3D1TXDP5_RDT
/X/USB31

43,74 U_USB4-
43,74 U_USB4+

U31_U31TXDP5_R 74,91

U31_U31TXDN5_R 74,91 USB5


U31_U31RXDP5_R 74,88,91 U31 GEN2 & GEN1 PIN ESD 橘框選擇方式:
U31_U31RXDN5_R 74,88,91

橘框
A B
組合

U_USB4+_R 43,74,91 U31 GEN 2 PIN ESD Keep Delete


U_USB4-_R 43,74,91

U31 GEN 1 PIN ESD Delete Keep

Connect to Redriver or Retimer


74,88 S_U3D1RXDN6_RDT
A B
74,88 S_U3D1RXDP6_RDT
U31C146 1 2 SHORTPIN_0402_NM
88 S_U3D1TXDN6_RDT
/X/USB31

88 S_U3D1TXDP6_RDT
U31C145 1 2 SHORTPIN_0402_NM
/X/USB31
U31GEN2 PIN ESD
43,74 U_USB5-
43,74 U_USB5+

U31U5
1 9
Port 5 2
Line-1 NC4

void
U31_U31TXDP5_R 8
Line-2 NC3
U31_U31TXDN5_R 3
GND
4 7
Line-3 NC2
U31_U31RXDP5_R 5 6

void
Line-4 NC1
U31_U31RXDN5_R
AZ174S-04F.R7G

U31_U31TXDP6_R 74,91
GND

U31_U31TXDN6_R 74,91
USB6
U31_U31RXDP6_R 74,88,91

U31_U31RXDN6_R 74,88,91

A B
ASUS PIN ESD SPEC U_USB5+_R 43,74,91
Back I/O : +/- 8KV U_USB5-_R 43,74,91
Front I/O : +/- 10KV U31GEN2 PIN ESD
ESD橘框選擇方式:

橘框 U31U6
A B C 1 9
Port 6 2
Line-1 NC4

void
組合 U31_U31TXDN6_R 8
Line-2 NC3
U31_U31TXDP6_R 3
GND
4 7
Line-3 NC2
Front I/O Keep Keep Delete U31_U31RXDN6_R 5 6

void
Line-4 NC1
U31_U31RXDP6_R
AZ174S-04F.R7G
Back I/O layout空間夠 Keep Keep Delete
GND

Back I/O layout空間不夠 Keep Delete Delete

Back I/O layout空間不夠 Delete Delete Keep


且Pin ESD打不過8KV

A U31U12
B C
1 6
43,74,91 U_USB4+_R U_USB4-_R 43,74,91

+U_USB45_5V

2 5
Port 5,6 <Variant Name>

GND Title : CHIPSET U31_Port5,6

43,74,91 U_USB5+_R
3 4
U_USB5-_R 43,74,91 ASUSTeK COMPUTER INC
Engineer: Brian Hsieh
Size Project Name Rev
IP4220CZ6
A2 Standard Circiut 2.1

Date: Thursday, December 12, 2019 Sheet 91 of 152


+5V_DUAL_USBKB +U_USB67_5V Strix Gaming , -A , 2.1
UF4 TUF Gaming系列
PCH USB3.0 1 2
ROG , Deluxe系列 PRIME H/B Chip系列
1. 900 mA for each port
2. 兩個port共用一組OC# & VBUS PWR 2.6A/8V
3. 確認connector VBUS PWR

1
netname是否一致 UC4 20190812 Remove UCE21 follow Z390-I
0.1UF/16V

2
/X/USB3

UR159~UR162 U3R139~U3R146

GND Connect to Connector UR167~UR170


請依PES需求選擇DIP CAP type GND

請RD做BOM時,手動刪除不需要的料件 U3R156 xxx_USB3_xx


1 2
USB2.0 Guard
4.7KOhm

U3R155 預防PCH USB2 Signal被Device高壓damaged問題


1 2

8.2KOhm GND
LAN
+U_USB67_5V +U_USB67_5V

43,74,92 U3_U3RXDN7_R U3_U3RXDN8_R 43,74,92


43,74,92 U3_U3RXDP7_R USB3_1 U3_U3RXDP8_R 43,74,92

74,92 U3_U3TXDN7_R U3_U3TXDN8_R 74,92


74,92 U3_U3TXDP7_R U3_U3TXDP8_R 74,92

43,74,92 U_USB6-_R USB3_2 U_USB7-_R 43,74,92


43,74,92 U_USB6+_R U_USB7+_R 43,74,92

Connect to Chipset U3U22


1
Line-1
U3_U3TXDP8_R 2 9
Line-2 NC4
U3_U3TXDN8_R 3 8
GND NC3
4 7
Line-3 NC2
U3_U3TXDP7_R 5 6
Line-4 NC1
U3_U3TXDN7_R
43 U_USBOC#67
AZ174S-04F.R7G

GND
Port 7 Close to connector

U3C147 2 1 0.1UF/16V
43 U3_U3TXDP7_C U3_U3TXDP7_R 74,92
U3_U3TXDP7
U3C148 2
void 1 0.1UF/16V
43 U3_U3TXDN7_C U3_U3TXDN7_R 74,92
U3_U3TXDN7

43,74 U3_U3RXDP7
void
U3_U3RXDP7_R 43,74,92 USB7
43,74 U3_U3RXDN7 U3_U3RXDN7_R 43,74,92

43,74 U_USB6+ U_USB6+_R 43,74,92


43,74 U_USB6- U_USB6-_R 43,74,92

Symbol 修改為Pad
reference挖空

U3U23
1
Line-1
U3_U3RXDP7_R 2 9
Line-2 NC4
U3_U3RXDN7_R 3 8
GND NC3
4 7
Line-3 NC2
U3_U3RXDP8_R 5 6
Line-4 NC1
U3_U3RXDN8_R
AZ174S-04F.R7G

GND

Close to connector
Port 8
U3C149 2 1 0.1UF/16V
43 U3_U3TXDP8_C U3_U3TXDP8_R 74,92
U3_U3TXDP8
U3C150 2
void 1 0.1UF/16V
43 U3_U3TXDN8_C U3_U3TXDN8_R 74,92
U3_U3TXDN8

43,74 U3_U3RXDP8
void
U3_U3RXDP8_R 43,74,92 USB8
43,74 U3_U3RXDN8 U3_U3RXDN8_R 43,74,92

43,74 U_USB7+ U_USB7+_R 43,74,92


43,74 U_USB7- U_USB7-_R 43,74,92

Reserve for EMI


ASUS PIN ESD SPEC
Back I/O : +/- 8KV
Front I/O : +/- 10KV

ESD橘框選擇方式:

橘框
A B C
組合

Front I/O Keep Keep Delete

Back I/O layout空間夠 Keep Keep Delete

Back I/O layout空間不夠 Keep Delete Delete

Back I/O layout空間不夠 Delete Delete Keep


且Pin ESD打不過8KV

A U3U26
B U3U27
C
1 6 1 6
43,74,92 U_USB7+_R U_USB7-_R 43,74,92 43,74,92 U_USB6+_R U_USB6-_R 43,74,92

+U_USB67_5V +U_USB67_5V

Port 7,8 2 5 2 5
<Variant Name>

GND GND Title : CHIPSET U3_Port7,8

43,74,92 U_USB6+_R
3 4
U_USB6-_R 43,74,92 43,74,92 U_USB7+_R
3 4
U_USB7-_R 43,74,92 ASUSTeK COMPUTER INC
Engineer: Brian Hsieh
Size Project Name Rev
IP4220CZ6 IP4220CZ6
A2 Standard Circiut 2.1
/X/USB3
Date: Thursday, December 12, 2019 Sheet 92 of 152
+5V_DUAL_USBKB +U_USB89_5V Strix Gaming , -A , 2.1
UF5 TUF Gaming系列
PCH USB3.0 1 2
ROG , Deluxe系列 PRIME H/B Chip系列
1. 900 mA for each port
2. 兩個port共用一組OC# & VBUS PWR 2.6A/8V
3. 確認connector VBUS PWR

1
20190812 Remove UCE22 follow Z390-I
netname是否一致 UC5 UR163~UR166 U3R147~U3R154
0.1UF/16V

2
/X/USB3 UR171~UR174

Connect to Connector
USB2.0 Guard
GND

請依PES需求選擇DIP CAP type GND

請RD做BOM時,手動刪除不需要的料件 1
U3R158
2
xxx_USB3_xx
預防PCH USB2 Signal被Device高壓damaged問題
4.7KOhm

U3R157
1 2

8.2KOhm GND
LAN
+U_USB89_5V +U_USB89_5V

43,74,93 U3_U3RXDN9_R U3_U3RXDN10_R 43,74,93


43,74,93 U3_U3RXDP9_R USB3_1 U3_U3RXDP10_R 43,74,93

74,93 U3_U3TXDN9_R U3_U3TXDN10_R 74,93


74,93 U3_U3TXDP9_R U3_U3TXDP10_R 74,93

43,74,93 U_USB8-_R USB3_2 U_USB9-_R 43,74,93


43,74,93 U_USB8+_R U_USB9+_R 43,74,93

Connect to Chipset 1
U3U28

Line-1
U3_U3TXDN9_R 2 9
Line-2 NC4
U3_U3TXDP9_R 3 8
GND NC3
4 7
Line-3 NC2
U3_U3TXDN10_R 5 6
Line-4 NC1
U3_U3TXDP10_R
AZ174S-04F.R7G
43 U_USBOC#89
GND

Port 9 Close to connector

U3C151 2 1 0.1UF/16V
43 U3_U3TXDP9_C U3_U3TXDP9_R 74,93
U3_U3TXDP9
U3C152 2
void 1 0.1UF/16V
43 U3_U3TXDN9_C U3_U3TXDN9_R 74,93
U3_U3TXDN9

43,74 U3_U3RXDP9
void
U3_U3RXDP9_R 43,74,93 USB9
43,74 U3_U3RXDN9 U3_U3RXDN9_R 43,74,93

43,74 U_USB8+ U_USB8+_R 43,74,93


43,74 U_USB8- U_USB8-_R 43,74,93

Symbol 修改為Pad
reference挖空

U3U29
1
Line-1
U3_U3RXDN9_R 2 9
Line-2 NC4
U3_U3RXDP9_R 3 8
GND NC3
4 7
Line-3 NC2
U3_U3RXDN10_R 5 6
Line-4 NC1
U3_U3RXDP10_R
AZ174S-04F.R7G

GND

Close to connector
Port 10
U3C153 2 1 0.1UF/16V
43 U3_U3TXDP10_C U3_U3TXDP10_R 74,93
U3_U3TXDP10
U3C154 2
void 1 0.1UF/16V
43 U3_U3TXDN10_C U3_U3TXDN10_R 74,93
U3_U3TXDN10

43,74 U3_U3RXDP10
void
U3_U3RXDP10_R 43,74,93 USB10
43,74 U3_U3RXDN10 U3_U3RXDN10_R 43,74,93

43,74 U_USB9+ U_USB9+_R 43,74,93


43,74 U_USB9- U_USB9-_R 43,74,93

ASUS PIN ESD SPEC


Back I/O : +/- 8KV
Front I/O : +/- 10KV

ESD橘框選擇方式:

橘框
A B C
組合

Front I/O Keep Keep Delete

Back I/O layout空間夠 Keep Keep Delete

Back I/O layout空間不夠 Keep Delete Delete

Back I/O layout空間不夠 Delete Delete Keep


且Pin ESD打不過8KV

A U3U32
B C
1 6
43,74,93 U_USB8+_R U_USB8-_R 43,74,93

+U_USB89_5V

2 5
Port 9,10 <Variant Name>

GND Title : CHIPSET U3_Port9,10

43,74,93 U_USB9+_R
3 4
U_USB9-_R 43,74,93 ASUSTeK COMPUTER INC
Engineer: Brian Hsieh
Size Project Name Rev
IP4220CZ6
A2 Standard Circiut 2.1

Date: Monday, December 16, 2019 Sheet 93 of 152


2.1
請依PES需求選擇DIP CAP type
請RD做BOM時,手動刪除不需要的料件
Connect to Connector
UR127~UR130 UR135~UR142 UR155~UR158

USB2.0 Guard
預防PCH USB2 Signal被Device高壓damaged問題
Connect to Chipset

+5V_DUAL_USBKB +U_USB_E12_5V Strix Gaming , -A , +U_USB_E12_5V


UF81 TUF Gaming系列 ROG , Deluxe系列 PRIME H/B Chip系列
1 2

1
1.75A
UC242
0.1UF/16V 20190812 Remove UCE32 follow Z390-I 請依PES需求選擇DIP CAP type
請RD做BOM時,手動刪除不需要的料件

2
/X/USB2

UR574
1 2

Front ULX13

3
4.7KOhm GND GND
UR570
1 2
43 U_USBOC#E12
/USB2

2
8.2KOhm GND 90Ohm/100MHz
Port 11,12 122 U2H1_DP1
UR155
UR156
1
1
2
2
0Ohm
0Ohm
/X/USB2
/X/USB2
U2H1_DP1_R 74,94
122 U2H1_DN1 U2H1_DN1_R 74,94
UR157 1 2 0Ohm /X/USB2
122 U2H1_DP2 U2H1_DP2_R 74,94
UR158 1 2 0Ohm /X/USB2
122 U2H1_DN2 U2H1_DN2_R 74,94

ULX14

3
/USB2

2
90Ohm/100MHz

A B
UD77

1 6
74,94 U2H1_DP1_R U2H1_DN1_R 74,94

+U_USB_E12_5V
Port 11, 12 2 5

GND

3 4
74,94 U2H1_DP2_R U2H1_DN2_R 74,94

IP4220CZ6

+5V_DUAL_USBKB +U_USB12_5V Strix Gaming , -A , +U_USB12_5V


UF7 TUF Gaming系列 ROG , Deluxe系列 PRIME H/B Chip系列
1 2

1.75A
1

UCE26
100UF/6.3V 請依PES需求選擇DIP CAP type
請RD做BOM時,手動刪除不需要的料件
2

UR78
1 2
4

4.7KOhm ULX11
BACK
GND
UR77 90OHM
1 2 /USB2
43,115 U_USBOC#1112
09G092090303 如無上 USB2.0 Guard線路
1

8.2KOhm GND 請short net 至 右側 net


UR135 1 2 0Ohm /X/USB2
Port 13,14 43
43
U_USB12+
U_USB12-
UR136
UR137
1
1
2
2
0Ohm
0Ohm
/X/USB2
/X/USB2
U_USB12+_R
U_USB12-_R
74,94
74,94
114 O3_CON_USB11+ U_USB11+_R 74,94
UR138 1 2 0Ohm /X/USB2
114 O3_CON_USB11- U_USB11-_R 74,94
4

ULX12
90OHM
/USB2
09G092090303
ASUS PIN ESD SPEC
Back I/O : +/- 8KV
1

Front I/O : +/- 10KV

ESD橘框選擇方式:

橘框
A B C
組合

A Front I/O Keep Keep Delete


UD7
Back I/O layout空間夠 Keep Keep Delete
1 6
74,94 U_USB11+_R U_USB11-_R 74,94

Back I/O layout空間不夠 Keep Delete Delete


+U_USB12_5V
Port 13,14 2 5 Back I/O layout空間不夠 Delete Delete Keep
且Pin ESD打不過8KV

GND

3 4
74,94 U_USB12+_R U_USB12-_R 74,94
<Variant Name>

IP4220CZ6
Title : CHIPSET U2_Port13,14

ASUSTeK COMPUTER INC


Engineer: Brian Hsieh
Size Project Name Rev
A2 Standard Circiut 2.1

Date: Tuesday, December 17, 2019 Sheet 94 of 152


1.1

Port B : Type A Connector


USB3.1
EMI-Protection

USB2.0 USB3.1/USB 2.0


EMI-Protection ESD-Protection

USB 2.0
ESD-Protection Reserve USB2.0 Guard
By 區域自行決定是否刪除線路
U31U110

1 6
43,74,96 U_USB3-_R U_USB3+_R 43,74,96

Port A : Type C Connector +5V_DUAL_USBKB

USB2.0 2 5

EMI-Protection GND

3 4

IP4220CZ6

USB3.1
EMI-Protection
0805

88 S_U3D1RXDN4_RDT
88 S_U3D1RXDP4_RDT
0805
88 S_U3D1TXDN4_RDT 43,74 U_USB3+ U_USB3+_R 43,74,96
88 S_U3D1TXDP4_RDT 43,74 U_USB3- U_USB3-_R 43,74,96
Connect to connector
+U31_3VSB U31U50 如無上 USB2.0 Guard線路
2
DA_a DA_a1
24
U31_U3RXDN2_R_SW2_R 74
請short net 至 右側 net
3 23 U31_U3RXDN2_R_SW2
DA_b DA_b1 U31_U3RXDP2_R_SW2_R 74
1 U31R52 2 2.7KOhm /X/ASM3142 6 22 U31_U3RXDP2_R_SW2 U31CX10 2 1 0.22UF/10V
DB_a DB_a1 U31_U3TXDN2_R_SW2_R 74
1 U31R53 2 2.7KOhm /X/ASM3142 7 21 U31_U3TXDN2_R_SW2_C U31CX9 2 1 0.22UF/10V U31_U3TXDN2_R_SW2
DB_b DB_b1 U31_U3TXDP2_R_SW2_R 74
1 U31R54 2 2.7KOhm /X/ASM3142 U31_U3TXDP2_R_SW2_C void
Close to ASM1543 U31_U3TXDP2_R_SW2
void
GND
IPU 32 20 Close to ASM1543
MODE_SEL DA_a2 U31_U3RXDN2_R_SW1_R 74
+U31_3VSB U31_MODE_SEL IPU 15 19 U31_U3RXDN2_R_SW1
ROLE_SEL DA_b2 U31_U3RXDP2_R_SW1_R 74
1 U31R62 2 2.7KOhm /X/ASM3142 U31_ROLE_SEL IPU 30 18 U31_U3RXDP2_R_SW1 U31CX12 2 1 0.22UF/10V
VCONN_EN DB_a2 U31_U3TXDN2_R_SW1_R 74
U31_VCONN_EN 17 U31_U3TXDN2_R_SW1_C U31CX11 2 1 0.22UF/10V U31_U3TXDN2_R_SW1
DB_b2 U31_U3TXDP2_R_SW1_R 74
U31R63 1 8.2KOhm 2 1 U31_U3TXDP2_R_SW1_C void SHORTPIN_0402_NM /X/ASM3142
U31_U3TXDP2_R_SW1
I_SEL0/MUX_EN#
U31R64 1 8.2KOhm 2 U31_I_SEL0 8 13 U31JP8 1 void 2
I_SEL1/MUX_SEL CC1 U31_DFP_CC1 74,90
U31R65 1 8.2KOhm 2 U31_I_SEL1 31 11 U31_CC1_DFP_CC1 1 2
PWR_EN CC2 U31_DFP_CC2 74,90
U31_PWR_EN 28 U31_CC2_DFP_CC2
26
CC_IND
14
SWAP
U31JP9 SHORTPIN_0402_NM /X/ASM3142
status_ind1 DFP_CC1
27 10 +U31_3VSB
status_ind2 DFP_CC2

9 12
REXT VCONN
U31_REXT 5 +U31_VCONN
1

5
4
3
2
1

5
4
3
2
1
VCC1
U31R27 4 29 U31U90 U31U100
1

Line-4
Line-3
GND
Line-2
GNDA1 VCC2

Line-4
Line-3
GND
Line-2
Line-1

Line-1
U31R28 8.2KOhm 16 AZ174S-04F.R7G AZ174S-04F.R7G
1

GNDA2
1

8.2KOhm /X/ASM3142 U31R18 25 U31U3C12 U31U3C212 U31U3C5 U31U3C29


GNDA3
/X/ASM3142 12.1KOHM 33 1UF/10V 10UF/16V 0.1UF/16V 0.1UF/16V
2

GND1 void void void void


1% 34 38 /ASM3142
2

GND2 GND6
2

35 39

NC1
NC2

NC3
NC4

NC1
NC2

NC3
NC4
2

GND3 GND7
36 40
GND4 GND8
GND U31R18擺放靠近ASM1543, 37 41 GND GND

6
7

8
9

6
7

8
9
GND5 GND9
GND trace length < 1
ASM1543
GND GND Max Current = 500 mA
GND For Debug Usage
GND

G料號 +5V_DUAL_USBKB
USB 3.1 GPIO for PE tool detect 請使用 MAIN Power GPI
U31U3D2
Max Current = 500 mA
2 1
ESD-Protection ASM1543 CC output ASM1543 CC output

SS0540 Device U31_CC_LINK STATUS U31_WHICH_LINK


/ASM3142

Attached 1 CC1 Link 0

Detached 0 CC2 Link 1


+U31_3VSB +U31_3VSB +5V_DUAL_USBKB +U31_+VCCCH12_5V_C +U31_3VSB
請依PES需求選擇DIP CAP type
請RD做BOM時,手動刪除不需要的料件
2

U31R32 SEL pin


1

U31R19 U31R34 2.7KOhm


2.7KOhm 2.7KOhm /ASM3142 Near to Connector Strix Gaming ,-A , CC1 U31_GP_TYPEC_DETECT_1 : 0
U31PU5 TUF Gaming系列 U31_GP_TYPEC_DETECT_2 : 1
1

5 1
2

IN OUT
2 CC2 U31_GP_TYPEC_DETECT_1 : 0
GND U31_GP_TYPEC_DETECT_2 : 0
1

4 3
EN(EN#) FLAG
1
1

U31_PRON U31PU5_OC# U31C14 + U31CE4


1

U31PU5C7 G517G1TO1U U31C15 0.01UF/16V


10UF/10V G料號 470PF/50V /X/ASM3142
220UF/6.3V
2

/X/ASM3142
2
6

U31PU5Q3A To ASM2142 OC pin GND ROG , Deluxe系列 PRIME H/B Chip系列


2 2N7002KDW GND GND U_USBOC#3 43
GND
1

U31PU5Q3B
3

/ASM3142

5 2N7002KDW
U31_PRON_G Force Power Enable
4

/ASM3142
請接至PCH GPIO (KBL) : GPP_C19
U31PR42
1 2
Near to Connector
U31_FORCE_PWR_EN 51

0Ohm
請使用Standby Power
default GPI, Output is GPO Low
1

U31C18
1UF/10V
/X/ASM3142
2

GND GND GND


請依project 需求修改+3VSB 來源

+U31_3VSB +3VSB
U31MJP15
1 2

SHORTPIN_0603_NM
/X/ASM1142/ASM2142
<Variant Name>

Title : ASM1543
ASUSTek Computer Inc.
Engineer: Leo Chen
Size Project Name Rev
A1 Standard Circiut 1.1

Date: Thursday, December 12, 2019 Sheet 96 of 152


M2_card_hold

CT217CB156D126

13020-04421100
s_smt_nut_c177d126

GND

change list:
0710:拿掉ROG logo;
0714:AU1C6換 1UF/6.3V ,解DVDDIO noise fail 換3.1*3.6mm橢圓螺孔

RX redriver在主板上,所以audio card上直連

BTOB_CON_60P BTOB_CON_60P

61
61
1 2 +3V 2 1

NP_NC1
1 2 47 CLK_REQ7_M.2_1_SSD# 2 1 PCH_M2_1_CONFIG3/PRESENT# 50
3 4 4 3

NP_NC1
44 PE_M2_TXP0/SA 3 4 PE_M2_2_RXN3 44 47 CLK_REQ8_M.2_2_SSD# 4 3 PCH_M2_2_CONFIG3/PRESENT# 50
5 6 6 5 +3V
44 PE_M2_TXN0/SA 5 6 PE_M2_2_RXP3 44 66 O_PCIRST#_PCIEX16_3 6 5 X_WAKE# 45,60,81
7 8 8 7
7 8 36,45,87 PCH_SUSCLK 8 7 M2_SSDLED# 78
9 10 10 9
44 PE_M2_RXN0/SA 9 10 PE_M2_2_TXN3 44 10 9
11 12 12 11
44 PE_M2_RXP0/SA 11 12 PE_M2_2_TXP3 44 12 11
13 14 14 13
13 14 14 13
15 16 16 15
44 PE_M2_TXP1 15 16 PE_M2_2_RXN2 44 16 15
17 18 18 17
44 PE_M2_TXN1 17 18 PE_M2_2_RXP2 44 18 17
19 20 20 19
19 20 20 19 PCH_M.2_1_SSD_SATA_PEDET# 50
21 22 22 21
44 PE_M2_RXP1 21 22 PE_M2_2_TXN2 44 22 21 PCH_M.2_2_SSD_SATA_PEDET# 50 +3VSB
23 24 24 23 +12V -12V
44 PE_M2_RXN1 23 24 PE_M2_2_TXP2 44 24 23 M2/SE0_DEVSLP 46
25 26 26 25
25 26 98 A_LINE_L_L 26 25 M2/SE1_DEVSLP 46
27 28 28 27
44 PE_M2_TXP2 27 28 PE_M2_2_RXN1 44 28 27
29 30 30 29
44 PE_M2_TXN2 29 30 PE_M2_2_RXP1 44 102 A_JD_LINE 30 29
31 32 32 31 +5V
31 32 32 31
33 34 34 33 +5VDUAL_AUX
44 PE_M2_RXP2 33 34 PE_M2_2_TXN1 44 98 A_LINE_R_L 34 33
35 36 36 35
44 PE_M2_RXN2 35 36 PE_M2_2_TXP1 44 36 35
37 38 38 37
37 38 98 A_LOUT_L_L 38 37
39 40 40 39
44 PE_M2_TXP3 39 40 PE_M2_2_RXP0/SA 44 40 39
41 42 42 41
44 PE_M2_TXN3 41 42 PE_M2_2_RXN0/SA 44 102 A_JD_LOUT 42 41
43 44 44 43
43 44 44 43
45 46 46 45
44 PE_M2_RXP3 45 46 PE_M2_2_TXN0/SA 44 98 A_LOUT_R_L 46 45 LED1_ADD1 107
47 48 48 47
44 PE_M2_RXN3 47 48 PE_M2_2_TXP0/SA 44 48 47 LED1_ADD2 107
49 50 50 49
49 50 98 A_MIC1_R_L 50 49 A_Z_BITCLK_R 98
51 52 52 51
47 C_PCIE_M2_1 51 52 C_PCIE_M2_2# 47 52 51 A_Z_SYNC_R 98
+3V 53 54 +3V 54 53 A_Z_BITCLK_R
47 C_PCIE_M2_1# 53 54 C_PCIE_M2_2 47 102 A_JD_MIC1 54 53 A_Z_SDIN0 45

NP_NC2
55 56 56 55
55 56 56 55 A_Z_SDOUT_R 98
NP_NC2

57 58 58 57
57 58 98 A_MIC1_L_L 58 57

1
59 60 60 59
59 60 60 59
EBC1
0.1UF/16V
62

2
62
/X/EMI

BTOB_CARD1_M BTOB_CARD1_A
12016-00041000 12016-00041000
GND

GND GND
GND A_GND
GND

<Variant Name>
Title : ST072CB(1.3OLED)

ASUSTek Computer Inc.


Engineer: Allen_Cheng
Size Project Name Rev
A2 BtoB CON Circiut 1.3

Date: Thursday, December 19, 2019 Sheet 97 of 152


2.17
AR7 /X/AUDIO
45,97 A_Z_SDIN0
1 75Ohm 2 AL17 1 2
97 A_LINE_L_L A_LINE_L 102,103
1 2 SARN1A A_LINE_L_L AR8 SHORTPIN_0603_NM
45 A_Z_SDOUT 33OHM A_Z_SDOUT_R 97
3 4 SARN1B A_Z_SDOUT_R 1 75Ohm 2 AL18 1 2
45 A_Z_SYNC 33OHM A_Z_SYNC_R 97 97 A_LINE_R_L A_LINE_R 102,103
5 6 SARN1C ALC1220 support Reset less A_Z_SYNC_R A_LINE_R_L SHORTPIN_0603_NM
33OHM

1
IBL Doc#536048 AVS implementa�on guide /X/AUDIO AC3 AC4
7 8 SARN1D 1 0Ohm 2 AR5978 100PF/50V 100PF/50V
45 A_Z_BITCLK 33OHM A_Z_BITCLK_R 97
NPO NPO

2
1
SAC40 /X/AUDIO /X/AUDIO
10PF/50V
A_GND
/X/AUDIO

2
NPO AL3 75Ohm 1%
靠近SB擺放 1 2
97 A_LOUT_L_L A_LOUT_L 102,103
GND AL4 75Ohm 1%
1 2
97 A_LOUT_R_L A_LOUT_R 102,103

1
AC6 AC7
100PF/50V 100PF/50V
NPO NPO

2
/X/AUDIO /X/AUDIO

A_GND

/X/AUDIO
AL5 1 2
97 A_MIC1_L_L A_MIC1_L 102,103
A_MIC1_L_L SHORTPIN_0603_NM
AL6 1 2
97 A_MIC1_R_L A_MIC1_R 102,103
A_MIC1_R_L SHORTPIN_0603_NM

1
/X/AUDIO AC10 AC11
100PF/50V 100PF/50V
NPO NPO

2
/X/AUDIO /X/AUDIO

A_GND

Close to
connector

www.teknisi-indonesia.com

<Variant Name>

Title : ALC1220-1(5.1CH/MR)

ASUSTek Computer Inc.


Engineer: Adam_Pan
Size Project Name Rev
A3
Standard Circiut
2.17
Date: Monday, December 23, 2019 Sheet 98 of 152
2.17
Standard Circuit

AUDIO ALC1220

REV. A_2.17

ALC1220 /X/AUDIO

Front Panel Back Panel


7.1 Channel Connector(示意圖)

A_MIC2_L GND 橘 藍
A_MIC2_R A_FP_PRES# (floating)

A_FRONT_R A_JD_MIC2 黑 綠
A_JD_FRONT
A_FRONT_L A_JD_LINE2 灰 粉紅

Back Panel
5.1Channel Connector
+SPDIF OUT(Optical)(示意圖)

橘 藍

黑 綠
SPDIF OUT
(Optical) 粉紅

SPDIF OUT (Optical)(示意圖)

<Variant Name>

Title : ALC1220-2(Connector)

ASUSTek Computer Inc.


Engineer: Adam_Pan
Size Project Name Rev
A3
Standard Circiut 2.17

Date: Thursday, December 12, 2019 Sheet 99 of 152


<Core Design>

Title : ALC1220-3 (AMP)

ASUSTek Computer Inc.


Engineer: Adam_Pan
Size Project Name Rev
A3
Standard Circiut 2.17

Date: Thursday, December 12, 2019 Sheet 100 of 152


2.17

請依PES是否有上LDO 選擇相對應線路

二選一

自Z390開始Audio Cap選擇如下
ROG / Strix series : Nichicon
PRIME / TUF : ELNA

Vendor strongly suggested for OVP ALC1220

<Variant Name>

Title : ALC1220-5 (LDO)

ASUSTek Computer Inc.


Engineer: Adam_Pan
Size Project Name Rev
A3
Standard Circiut 2.17

Date: Thursday, December 12, 2019 Sheet 101 of 152


3.2

+5VSB_AUDIO

Back Panel 20160607_Audio Phone Jack follow M8H-AR(Steve)

8 Channel
Connector Super Audio
AUDIO mbs_r0603
1 AR389 2 0Ohm
P_GND1 14
A_CGND1 15 14 +5VSB_14 1 AR390 2 0Ohm
13
13 GND_13 mbs_r0603
P_GND3 12 A_LINE_L 98,103
A_CGND1 17 12
11 A_JD_LINE 97
11
10 A_LINE_R 98,103
10
9
9
8 A_LOUT_L 98,103
8 GND
7 A_JD_LOUT 97
7
6 A_LOUT_R 98,103
6 +5VDUAL_AUX
5 SLQ4555
5 +5VSB_AUDIO
4 A_MIC1_L 98,103 AP2301GN
4
P_GND2 3 A_JD_MIC1 97
A_CGND 16 3
2 A_MIC1_R 98,103
2

D
P_GND4 1
A_CGND 18 1 2 3

3
AC24 2 1
0.1UF/50V

G
AUDIO_COVER_14P

11
13020-04890000

1
A_GND A_GND GND APC5

1
AC234 A_CGND1 0.1UF/16V

1
0.1UF/16V AC34 AC35

2
A_CGND 2 /X/AUDIO 0.1UF/16V 0.1UF/16V
1

AC233 AC232 /X/AUDIO /X/AUDIO

2
0.1UF/16V 0.1UF/16V
APR11
/X/AUDIO /X/AUDIO
2

GND_13 1 2
78 STEALTH_MODE_EN_Q
(有外觀鍍金環) A_GND
20KOhm
A_GND

Default : GPI

1
APC4
20190306 Stealth mode : high 0.1UF/16V
1.修改6 PORT AUDIO to 3PORT AUDIO. /X

2
7.1CH時,
LINE IN變成Side Surround

GND

Front Panel

顏色 : Black

<Variant Name>

Title : BACK IO_AUDIO

ASUSTek Computer Inc.


Engineer: Jim Yang
Size Project Name Rev
A3
Standard Circiut 3.1

Date: Thursday, December 12, 2019 Sheet 102 of 152


2.17

VARISTOR

Pin ESD spec (自Z370起spec)

Line Out Headphone Center Surrund Front Mic Line In Back Mic

5KV 5KV 4.5KV 4.5KV 5KV 4.5KV 5KV

For ALC1220 B2 : 所有Varistor皆需上件

Line In A_LINE_L 98,102 Center


A_LINE_R 98,102

AD15 AD14

1
2

2
A_GND

Line Out A_LOUT_L 98,102 Surrund


A_LOUT_R 98,102

AD17 AD16

1
2

2
A_GND

Back Mic A_MIC1_L 98,102


A_MIC1_R 98,102

AD19 AD18
1

1
2

A_GND

<Variant Name>

Title : ALC1220-6 (VARISTOR)

ASUSTek Computer Inc.


Engineer: Adam_Pan
Size Project Name Rev
A3
Standard Circiut 2.17

Date: Thursday, December 12, 2019 Sheet 103 of 152


ASUS PCB Logo
LOGO41
1
SFIS LABEL

SFIS_LABEL
/X

LOGO7 LOGO5
1 1
PCB MADE IN CHINA WEEE_LOGO
LOGO8 PCB_MADE_IN_CHINA WEEE_LOGO
1 /X /X
VCCI

VCCI
/X

因應歐盟針對無線指令的修改,有Wi-Fi機種也請選用CE
ASUS LOGO
LOGO6
1
CE
CE 無Wi-Fi機種請選用CE
/X

X=1.5mm

X=2.5mm
LOGO2
1
FCC
FCC
X=3.0mm
/X
2018年後FCC LOGO需使用新版本

X=3.5mm

X=4.0mm

LOGO3
1
RCM
X=4.5mm
RCM
/X

X=5.0mm

LOGO1
1
EMI_D33005_H 文字在右方
EMI_D33005_H X=6.0mm
/X

LOGO21
1
ASUS X=2.0mm
ASUS
文字在下方 /X
M/B Default請留Symbol (2mm)和Symbol
(5.5mm),若圖騰有包含Layout會通知從線路移除
X=5.5mm

LOGO9
1
CAN ICES-3(B)/NMB-3(B)
CAN_ICES_3B_NMB_3B
/X

<Variant Name>

Title : PCB Logo


ASUSTEK COMPUTER INC
Engineer: Kell_Huang
Size Project Name Rev
A3
Silkscreen
0.2N

Date: Thursday, December 12, 2019 Sheet 104 of 152


烏克蘭LOGO
ASUS PCB Logo LOGO38
1
UKRAINE 有/無Wi-Fi機種使用
UKRAINE

DRAM Slot Naming Rule


DIMM slot ‘*’ 命名方式, 若 MR team 建議先插
1. DIMM_x1 就叫做 DIMM_A1_STAR, DIMM_B1_STAR … 以此類推
2. DIMM_x2 就叫做 DIMM_A2_STAR, DIMM_B2_STAR … 以此類推
Model name字體選擇
3.RD請與MR確認後提Modify給Layout確認'*'擺放位置

M1

teknisi indonesia
1 RX.XX
2號字/主板使用
LOGO30 /X
1 RX_XX
ASTERISK

ASTERISK

LOGO31 /X
1
ASTERISK

ASTERISK

4號字/小卡使用
2 Channel 4 Channel

新版KCC LOGO (2018-8-6之後開案新單1.00的機種使用)

LOGO40
有/無Wi-Fi Module機種使用
無Wi-Fi Module機種 1
KC R-R-MSQ-XXXXXXXXXXXXXX
R-R-MSQ-XXXXXXXXXXXX 10mm for主板使用
KC_R_R_LOGO
/X

有WiFi Module機種
R-R-MSQ-XXXXXXXXXXXX 有/無Wi-Fi Module機種使用

6.8mm for小卡使用

WiFi IC on board特殊機種
R-C-MSQ-XXXXXXXXXXXX Wi-Fi IC on board特殊機種使用

10mm for主板使用

Wi-Fi IC on board特殊機種使用

6.8mm for小卡使用

<Variant Name>

Title : PCB Logo


ASUSTEK COMPUTER INC
Engineer: Kell_Huang
Size Project Name Rev
A3
Silkscreen
0.2N

Date: Thursday, December 12, 2019 Sheet 105 of 152


<Variant Name>

Title : M2_TEXT

ASUSTEK COMPUTER INC


Engineer: Grace Wu
Size Project Name Rev
A3
Silkscreen
0.2N

Date: Thursday, December 12, 2019 Sheet 106 of 152


Ver 1.4
Addressable Header

LED Driver對LED內部的Net LED Driver需連接外部的Net 根據ID規格可更換其他功能的Pin腳

依據Intel/AMD平台修改Power net 依據ID規格/空間,刪減LED組數/顆數/Header 註解

Addressable Header(支援2組) 20190219修改

ADD_HEADER1 反白文字面

(請依主機板類型選擇對應的文字面)
第1組
ADD LED Power1
ROG/ ROG STRIX Channel /TUF Gaming

Addreesable LED Header 1

ADD_HEADER2 反白文字面

(請依主機板類型選擇對應的文字面)

ROG/ ROG STRIX Channel /TUF Gaming

<Variant Name>

Title : ADD_Header

ASUSTek Computer Inc.


Engineer: Kaizer_Luo
Size Project Name Rev
20190312修改
Custom LED Standard Circiut 1.0

Date: Thursday, December 12, 2019 Sheet 108 of 152


Title : LGA1200 (XDP)

ASUSTek Computer Inc.


Engineer: Martino_Yang
Size Project Name Rev
A2 Maximus XII Extreme R1.00

Date: Thursday, December 12, 2019 Sheet 38 of 126


PWM_Port_D Ver 1.0

1.LED燈數 的接線方式
<4顆 (請依需求選擇或刪減LED燈類型及顆數)
LED電流<20mA

2.LED燈數 ,但>4顆
的接線方式 不超過20顆 (請依需求選擇或刪減LED燈類型及顆數) 零件待需重新命名

50mA<LED電流<100mA

3.LED燈數 >20顆 (請依需求選擇或刪減LED燈類型及顆數) 零件待需重新命名

LED電流>100mA

4.外接一組燈條的情境

LED1A_R1
1

LED1DC109001
LED1DQ109001 3 0.1UF/16V
3

D
AP2306GN /X/6K582
2

X5R
11
107 LED1A_R
G GND
S
2
2

GND

LED1A_B1
1

LED1DC109002
LED1DQ109002 3 0.1UF/16V
3

AP2306GN
D
/X/6K582
限流保護IC 2 [layout空間不夠且SPM同意,才可以使用]
2

X5R
11 OCP=3A
107 LED1A_B
G GND
S
2
2

LED1PU
13
GND3
12
GND2
GND 11
GND1
1 10
dV/dT ILIM
2 9 1 DT56 /X/AURA
EN/UVLO TEST
+12V +12V 3 8 +12V_efuse
White Header VIN1 OUT3 GND
1

LED1A_G1 LED1C1 4 7
VIN2 OUT2
0.1UF/16V 5 6
1

VIN3 OUT1
1

LED1DC109003 /X/AURA LED1R104


2

LED1DQ109003 3 0.1UF/16V +12V_efuse LED1A_B1 4 LED1R102 NCT3581Y-D 82.5KOhm


3

D
1

AP2306GN /X/6K582 LED1A_R1 3 8.2KOhm LED1C3


2

X5R LED1A_G1 2 GND 1UF/16V LED1C4


2

11 1
107 LED1A_G 10UF/16V
1

G GND RGB_HEADER
S
2

2
2

HEADER_1X4P
反白文字面
1

LED1R103 LED1C2
4.7KOhm 1UF/16V GND GND
RGB_HEADER_TA /X/AURA
2

GND 1
2

GND
RGB HEADER
EMI用(預留不上件) 限流=3A,(R*2.5)/10^5 = IOL-1
請考慮C值大小,避免PWM訊號失真
RGB_HEADER
/X/6K582 GND GND

<Variant Name>

Title : PWM_Port_A
ASUSTek Computer Inc.
Engineer: Kaizer_Luo
Size Project Name Rev
Custom LED Standard Circiut 1.3

Date: Tuesday, December 17, 2019 Sheet 109 of 152


<Variant Name>

Title : Node
ASUSTek Computer Inc.
Engineer: Aaron_Su
Size Project Name Rev
C Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 110 of 152


WIFI

+3VSB +3VSB_WIFI_BT +3VDUAL_AUX


JR410 0Ohm
1 2
/X mbs_r0805
JU7

0.1UF/16V

0.1UF/16V
JR408 2 /NA 1
8.2KOhm 1 5
OUT IN
2 JR407 1KOhm
GND
1 2 3 4 1 2
50 WIFI_PWREN EN DIS
JR409 /NA 0Ohm /NA +3VSB_WIFI_BT
NCT3521U
/Z390E

1
/NA

/NA
JC50

JC51
2

2
GND GND GND

I225V

+3VSB +3V_DUAL_L1U1 +3VDUAL_AUX


JR413 0Ohm
1 2
/X mbs_r0805
JU6

0.1UF/16V

0.1UF/16V
2
JR411 1
8.2KOhm 1 5
OUT IN
2 JR412 1KOhm
GND
JR414 1 0Ohm 2 3 4 1 2
50 L1U1_PWREN EN DIS
+3V_DUAL_L1U1
NCT3521U
N/A

1
/X

/X
JC40

JC41
2

2
GND GND GND

<Variant Name>

Title : Power Cut off - detect


ASUSTek COMPUTER INC.
Engineer: Aaron_Su
Size Project Name Rev
A1 Maximus XI Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 111 of 152


20190731 Remove GP17 CPU_OV

CPU_OV Default GPI


High: VCCIN --->2.7V
Low: VCCIN ---->3.04V

Z97_R1.01

<Variant Name>

Title : CPU_OV

ASUSTek Computer Inc.


Engineer: Eason
Size Project Name Rev
A
Z270-STRIX 1.02

Date: Thursday, December 12, 2019 Sheet 112 of 152


4.2

Follow SIO to select +3V or +3V_S0IX

Modify Part Number by color


2擇1

For Intel S0ix

BOM TPM Header Onboard TPM

N/A mount mount

For not Intel S0ix /X unmount unmount

/TPM HEADER mount unmount

/TPM IC unmount mount

<Variant Name>

Title : TPM

ASUSTEK Computer INC


Engineer: Ben Hsieh
Size Project Name Rev
A3 Standard Circiut 4.2

Date: Thursday, December 12, 2019 Sheet 113 of 152


O3U1

請改成PCH端的名稱 請改成flash端的名稱
20 21
42 F_SPI_CS0# A_SPI_CS# B_SPI_CS# F_SPI_CS0#_R 75

SPI from Chipset

SPI to BIOSflash
18 19
42 F_SPI_CLK A_SPI_CLK B_SPI_CLK F_SPI_CLK_R 75

22 23
42 F_SPI_MOSI A_SPI_MOSI B_SPI_MOSI F_SPI_MOSI_R 75

16 17
42 F_SPI_MISO A_SPI_MISO B_SPI_MISO F_SPI_MISO_R 75

預留16/32 MB strapping pin VCC1833


請改成PCH端的名稱 請改成connector端的名稱
30 33
43 U_USB11+ DP_A DP_B O3_CON_USB11+ 94
1

O3R28
43 U_USB11-
31
DM_A DM_B
34 接到Connector
O3_CON_USB11- 94
8.2KOhm
/X/AI1315

USB from Chipset

USB to Connector
45 2

teknisi indonesia
2

U31_TXP_A U31_TXP_B

F_SPI_MOSI_R 46 1
U31_TXN_A U31_TXN_B
1

O3R29 47 4
U31_RXP_A U31_RXP_B
8.2KOhm
/X/AI1315 48 3
U31_RXN_A U31_RXN_B
2

GND 39
REXT 靠近connector (choke)

USB
PHY
1 2
預留USB pattern strapping pin
O3R10 1% 11KOHM O3_REXT
測AI1315 U2眼圖:

/AI1315

/AI1315
+3VSB VCC1833

33PF/50V

33PF/50V
O3R14、O3R37上件,
再按flashback按鈕3秒, O3RN1B 3
8.2KOHM
4 41
BCS0 SCL
11
S_SMBCLK_PCI 45,52,60,115
即會發pattern. BCS0

Battery

SMBus
Charge
O3RN1C 5 6 42 12
8.2KOHM BCS1 SDA O3_SMB1_DATA 115
BCS1
1

O3R14 O3R37

O3C1

O3C2
1

1
8.2KOhm 8.2KOhm GND
/X/AI1315 /X/AI1315
2

2
O3_UART_TX GND GND
O3RN1A 1 2 40
8.2KOHM TESTIN

Test
O3_TESTIN
F_SPI_MISO_R 9
UART_TX
GND O3_UART_TX

UART
10 1 DT32 /X/AI1315
UART_RX
O3RN1D 7 8 O3_UART_RX
+3VSB 8.2KOHM

43
SWI# VCC1833請接到BIOS flash 的power
116 O3_SWI#
O3R15 1 2
1KOhm O3_SWI#_R (+3VSB or + 1.8VSB)
VCC1833 +3VSB
+3VSB

O3JP2
73 O3_FLASHBK#

SPI level
2
O3R16 1
8.2KOhm 14 1 2
VCC1833
13
FLASHBK#
/X/AI1315
FLASHBK# SHORTPIN_0402_NM
0: PWRBTN無效 O3C3 1 2
0.1UF/16V
1: PWRBTN有效 GND

+3VSB
8

MISC
115 O3_PWRSUS# PWRSUS#
O3D5
1 5
72 O2_CUT_PSON# VCC33
3
SPI_CS#
2 0: normal 29

+3.3V Power
115 O3_WP VCC33U
+3VSB 1: Force BIOS update
BAT54CW 38
VCC33OSC
/X/AI1315
15 25
SPI_CS# VCC33RGL
2
O3R17 1
8.2KOhm

1
O3U1C1 O3U1C2 O3U1C3 O3U1C4
0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V

2
+3VSB

GND GND GND GND


1 2 44
SPI_UPD
2
O3R18 1
8.2KOhm O3R19 0Ohm O3_SPI_UPD_R +O3_1.2VSB

24
115 O3_SPI_UPD 具有斷電線路功能 +1.2V Power
VCC12

28
VDD12U

27
VCC12O
7
RST#
RESET

1
O3_RSMRST# O3U1C5 O3U1C6 O3U1C7
有EC1上這路 1UF/10V 1UF/10V 1UF/10V O3U1C8
/X/AI1315 mbs_c0402 mbs_c0402 mbs_c0402 10UF/6.3V

2
/X/AI1315 /X/AI1315 mbs_c0603
72 O2_RSMRST#
O3JP1 1 2
SHORTPIN
GND GND GND GND

6
116 O3_BACKUP_LED GPO0
26
GPIO

GNDARGL
32
GNDA_1
35
O3X1 SMD Xtal Only For ROG GNDA_2
GND

49
GND1
36 50
XI GND2
O3_XCLKI 51
GND3
XTAL

2 1 37 52
XO GND4
O3U1C9 12PF/50V O3_XCLKO 53
GND5

O3X1 25Mhz
1 3 AI1315
06106-00400000 GND
XCLKI and XCLKO
width=4,Length=<1 07009-00024100
2

/CLK
Title : AI1315
20170309:Modify O3U1X1 to SMD part

ASUSTek Computer Inc.


Engineer: Yodream_Chen
GND
Size Project Name Rev
Custom
Flashback Circuit R1.01

Date: Thursday, December 12, 2019 Sheet 114 of 152


+3VSB

EEPROM Circuit

1
O3R43
+3VSB +3VSB 8.2KOhm

2
O3U2
1 8
A0 VCC
2 7
A1 WP
3 6
A2 SCL
4 5 S_SMBCLK_PCI
GND SDA
O3_SMB1_DATA
AT24C02BN

1
05V02S211300 O3C5

0.1UF/16V O3Q2A

6
2
2N7002KDW
請擺放於O3U1附近 2
50,115 O3_SMB_SWITCH O3_WP 114

1
GND WP: GND
0 : Normal Operation
1 : Write Protect
GND

FlashBack Lock Circiut SMBUS Switch Circuit ( for update EEPROM FW )

AMD平台⾛這 INTEL平台⾛這

/AI1315
1 2
S_SLPS4#_SIO 21,23,30,45,66,72 45,52,60,114 S_SMBCLK_PCI
O3R42 0Ohm S_SMBCLK_PCI

1. Default = GPI,
2. PCH link = GPO High (P.P.)
O3Q2B
2N7002KDW

O3_PWRSUS# 114 4 3
45,52,60 S_SMBDATA_PCI O3_SMB1_DATA 114
O3_SMB1_DATA

5
請接到GPIO Pin

50,115 O3_SMB_SWITCH

1
O3R23 O3C6
8.2KOhm 0.1UF/16V O3_SMB_SWITCH L (default) H

2
S5 after
Net Name S0 S3 S4 S5 CLRCMOS SMBUS Host Indivitual Mix(PCH link)

O3_PWRSUS#
GND GND
1=不⾏flashback 1 1 0 0 0
0=可以flashback

U2/3 port flashback circuit (1) Net Name EN=0 EN=1


解 : 1. Charge function(Change Charge mode)
2. USB Back port 是 U3 +O3_USB23_5V 0V Vin=Vout
利⽤斷back up USB port power,
使USB device重新reconnect.
USB23的Power請分開接不要合併再⼀起
否則會有⼀起斷電的現象

請接到相對應的power 請接到相對應的power

+5V_DUAL_USBKB +U_USB11_5V

請依PES需求選擇DIP CAP type


經Power team 確認,台/日系一般殼,
屬於同pool 料件, 請RD做BOM時
手動刪除不需要的料件
O3U3
1 8
GND OUT3
2 7
IN1 OUT2
3 6
IN2 OUT1
4 5 OD
114 O3_SPI_UPD EN OC#
1

1
1

NCT3520W-H15 + O3C10 + O3C11


U_USBOC#1112 43,94
1

O3C8 O3C9 150UF/6.3V 150UF/6.3V


O3C7 1UF/10V 10UF/6.3V
請接到相對應的netname
2

10UF/6.3V mbs_c0402 /X/AI1315


2

/X/AI1315 /X/AI1315 mbs_c0603


mbs_c0603

GND GND GND


GND GND GND

OC分壓電阻請使⽤4.7KOhm &
8.2KOhm對地的組合
Title : AI1315
ASUSTek Computer Inc.
Engineer: Yodream_Chen
Size Project Name Rev
A3
Flashback Circuit R1.01

Date: Thursday, December 12, 2019 Sheet 115 of 152


Flashback BTN for 180 degree (單⾊LED) Flashback BTN for 180 degree (單⾊LED)

BIOS_FLBK +3VSB

1 2
O3_SWI# 114

3 4

2
TACT_SW_4P O3R26
12009-00175400 300OHM
GND GND 1%
/AI1315

1
FLBK_BTN1請擺放於FLBK_LED1旁

1
FLBK_LED1
12G09003004M H=3.85mm

+
FLBK_LED1請放⾄FLBK_BTN1旁
12G09503304U H=5.85mm YELLOW&GREEN

/AI1315

2
114 O3_BACKUP_LED

Title : AI1315
ASUSTek Computer Inc.
Engineer: Yodream_Chen
Size Project Name Rev
A3
Flashback Circuit R1.01

Date: Thursday, December 12, 2019 Sheet 116 of 152


+U_USB89_5V +5V_DUAL_USBKB

EC1

1
2 1 EC2 EC6
0.1UF/16V 0.1UF/16V

2
/X/EMI /X/EMI
0.1UF/16V

A_GND GND
GND GND

+3V
+U_USB2_5V
1

1
EC1000 EC66
0.1UF/16V 0.1UF/16V
2

2
/X/EMI /X/EMI

GND

GND

Title
<Title>

Size Document Number Rev


A Z390 Golden board R1.01

Date: Monday, December 23, 2019 Sheet 117 of 152


改非剪腳
11031-0001F300 ->11031-0001F500
PL CAP PL CAP

+5V_DUAL_USBKB

PL 560U: 11031V0004F300
1 PL 100U: 11031-0001F400

+ UCE1
560UF/6.3V
mbs_cpl560u6d3v6d3x9lfh_ms
2

11031-0001F500
N/A

GND

USB Power CAP recommend placement


+5V_DUAL_USBKB
if there no USB Port, UCE2
place near UCE1 or
remove
PL 560U: 11031V0004F300
PL 100U: 11031-0001F400

1
+ UCE6
560UF/6.3V
UCE2
mbs_cpl560u6d3v6d3x9lfh_ms
2

11031-0001F500
N/A

GND

UCE1

UCE6

UCE6 place near USB3.x Header,


remove UCE6 if no USB3.x Header

UCE5

<Variant Name>

Title : USB Power CAP


ASUSTEK COMPUTER INC
Engineer: Kell_Huang
Size Project Name Rev
A3
Chipset USB Demo Circuit
0.0

Date: Thursday, December 12, 2019 Sheet 118 of 133


L1 L2

RX RX
PI3EQX1002B
Connector
TX TX
Chipset
in Chipset
Demo place near Connector Net Impedance/Width Space Length

D+/D- TX/RX L1 30 mils < 10'', prefer 5'' - 9''


follow USB 3.1
Controller Rule
TX/RX L2 30 mils < 2.5'', prefer 0.5'' - 1.5''

EQ/FG Setting Table for L2 < 2.5'' +3V_RDP >= 20 mils


PI3EQX1002B & PI3EQX1002B1
EQA FGA SWA EQB FGB SWB

L1 < 7'' R 0 F R 0 F

7'' <= L1 <= 9'' (demo default) F 0 F R F F UU31T1


SWA_UU31 FGA_UU31
1 EN_UU31 EQA_UU31

9'' < L1 < 10'' 1 0 F R 1 F TPC26b


/X

B C
+3V_UU31

31
30
29
28
27
26
UU31A

GND11
EN
SWA
GND10
FGA
EQA
1 25 11V232222416150
VDD1 VDD4
2 24 UU31C33 2 1 0.22UF/10V N/A
46 S_U3D1TXDP2_R AIP AOP S_U3D1TXDP2_RDT 89
3 23 S_U3D1TXDP2_RDT_O_C UU31C34 2 1 0.22UF/10V N/A
USB 3.1 Re-Driver PI3EQX1002B Circuit 46 S_U3D1TXDN2_R
4
5
AIN
GND1
AON
GND9
22
21
S_U3D1TXDN2_RDT_O_C void
void
11V232222416150
S_U3D1TXDN2_RDT 89

GND2 GND8
6 20
GND3 GND7
N/A 7 19 N/A
A. Delete the Re-Driver IC which is not needed by Project UU31C31 2 1 0.22UF/10V 8
GND4 GND6
18 UU31C35 2 1 0.33UF/6.3V
46 S_U3D1RXDN2_R BON BIN S_U3D1RXDN2_RDT 74,89
UU31C32 2 1 0.22UF/10V S_U3D1RXDN2_RDT_O_C 9 17 S_U3D1RXDN2_RDT_I_C UU31C36 2 1 0.33UF/6.3V
46 S_U3D1RXDP2_R BOP BIP S_U3D1RXDP2_RDT 74,89

RXDET_EN
void
N/A S_U3D1RXDP2_RDT_O_C 10 16 S_U3D1RXDP2_RDT_I_C void
N/A UU31R36 1 2 10V212220410 N/A
B. Modify Input USB 3.1 TX/RX Signal Net Name by Project void
VDD2 VDD3 void UU31R35 1 void 2 10V212220410 N/A

GND5
SWB

EQB
FGB
void
GND
C. Modify Output USB 3.1 TX/RX Signal Net Name by Project

Port 2
PI3EQX1002BZLEX GND

11
12
13
14
15
+3V_RDP GND 06113V00210100

D. If UU31 TX output signals send to ASM1543, UU31C33,


UU31C34 change Part Number from 11V232222416150 to EQB_UU31

11V232334150 & mount UU31R33, UU31R34, otherwise

2
SWB_UU31 FGB_UU31 UU31B
UU31R1 32
could delete UU31R33, UU31R34 0Ohm GND 33
GND12
GND13
mbs_r0603 34
GND14
N/A 35
GND15

1
36
GND16
37
E. If UU32 TX output signals send to ASM1543, UU32C33, GND17

UU32C34 change Part Number from 11V232222416150 to PI3EQX1002BZLEX

11V232334150 & mount UU32R33, UU32R34 otherwise

2
UU31C1 UU31C16 GND
could delete UU32R33, UU32R34 0.1UF/16V 0.1UF/16V UU31R3 UU31R5 UU31R7 UU31R9 UU31R11 UU31R13
X7R X7R 1KOhm 1KOhm 1KOhm 1KOhm 1KOhm 1KOhm

2
N/A N/A /X /X /X /X /X /X

1
Place near to power pin
Pin1, Pin10, Pin16, Pin25 EQA_UU31 FGA_UU31 SWA_UU31 EQB_UU31 FGB_UU31 SWB_UU31
GND

2
EQ, FG, SW Pin
UU31R4 UU31R6 UU31R8 UU31R10 UU31R12 UU31R14
0 1K Ohm pull down 68KOhm 68KOhm 1KOhm 68KOhm 1KOhm 1KOhm
N/A N/A /X N/A N/A /X

Power Solution for PI3EQX1002B *1/2pcs R 68K Ohm pull down

1
F Floating
3.3V for PI3EQX1002B, 170mA/pcs@S0 1 1K Ohm Pull High
GND GND GND GND GND GND

Vout=1.25*(2.15k+1.27k)/1.27k=3.366V

+3VDUAL_AUX +3V_RDP

SHORTPIN_0603_NM
UU32T1
UPU41R7 SWA_UU32 FGA_UU32
20190812 change 1 2 1 EN_UU32 EQA_UU32

TPC26b
/X
SHORTPIN_0603_NM /X
1

UPU41R6 UPU30PC3

B C
1 2 10UF/6.3V +3V_UU32

31
30
29
28
27
26
mbs_c0603 UU32A
2

/X X5R

GND11
EN
SWA
GND10
FGA
EQA
N/A
1 25 11V232222416150
VDD1 VDD4
2 24 UU32C33 2 1 0.22UF/10V N/A
46 S_U3D1TXDP1_R AIP AOP S_U3D1TXDP1_RDT 89
GND 3 23 S_U3D1TXDP1_RDT_O_C UU32C34 2 1 0.22UF/10V N/A
46 S_U3D1TXDN1_R AIN AON S_U3D1TXDN1_RDT 89
4 22 S_U3D1TXDN1_RDT_O_C void
11V232222416150
GND1 GND9
5 21 void
GND2 GND8
6 20
GND3 GND7
N/A 7 19 N/A
GND4 GND6
UU32C31 2 1 0.22UF/10V 8 18 UU32C35 2 1 0.33UF/6.3V
46 S_U3D1RXDN1_R BON BIN S_U3D1RXDN1_RDT 74,89
UU32C32 2 1 0.22UF/10V S_U3D1RXDN1_RDT_O_C 9 17 S_U3D1RXDN1_RDT_I_C UU32C36 2 1 0.33UF/6.3V
46 S_U3D1RXDP1_R BOP BIP S_U3D1RXDP1_RDT 74,89

RXDET_EN
void N/A S_U3D1RXDP1_RDT_O_C 10 16 S_U3D1RXDP1_RDT_I_C void N/A UU32R36 1 2 10V212220410 N/A
Power Component place near each other! void
VDD2 VDD3 void UU32R35 1 void 2 10V212220410 N/A

GND5
SWB

EQB
FGB
void
GND

Port 1
PI3EQX1002BZLEX GND
11
12
13
14
15
+3V_RDP GND 06113V00210100 UU32B
32
GND12
33
GND13
EQB_UU32 34
GND14
2

SWB_UU32 FGB_UU32 35
GND15
UU32R1 36
GND16
0Ohm GND 37
GND17
mbs_r0603
N/A PI3EQX1002BZLEX
1

GND
1

2
UU32C1 UU32C16
0.1UF/16V 0.1UF/16V UU32R3 UU32R5 UU32R7 UU32R9 UU32R11 UU32R13
X7R X7R 1KOhm 1KOhm 1KOhm 1KOhm 1KOhm 1KOhm
2

N/A N/A /X /X /X /X /X /X
1

1
Place near to power pin
Pin1, Pin10, Pin16, Pin25 EQA_UU32 FGA_UU32 SWA_UU32 EQB_UU32 FGB_UU32 SWB_UU32
GND
2

2
EQ, FG, SW Pin UU32R4 UU32R6 UU32R8 UU32R10 UU32R12 UU32R14
68KOhm 68KOhm 1KOhm 68KOhm 1KOhm 1KOhm
0 1K Ohm pull down N/A N/A /X N/A N/A /X
1

1
R 68K Ohm pull down
F Floating

1 1K Ohm Pull High


GND GND GND GND GND GND

www.teknisi-indonesia.com

<Variant Name>

Title : PI3EQX1004
Engineer:
ASUSTEK COMPUTER INC SZ Design IP
Size Project Name Rev
Custom
Chipset USB Re-Driver
1.0B

Date: Thursday, December 12, 2019 Sheet 119 of 152


HS_FAN
+3V

2
CFR41
2.7KOhm

1
CFR42
2.7KOhm
1 2
72 O2_SEN_HSFAN
O2_SEN_HSFAN_R

+5V
+3V

2
CFR43 CFR44
2.7KOhm 2.7KOhm
+3V +12V VRM_HS_FAN
4 6
4 SIDE2

1
CF_PWM_HSFAN 3
3
O2_SEN_HSFAN_R 2
2
2

1
CF_PWM_HSFAN 1 5
1 SIDE1
CFR45 CFC66
2.7KOhm 3 1UF/16V WtoB_CON_4P

2
C CFQ12 GND 12017-00071100
1 B PMBS3904
1

O2_PWM_HSFAN_Q GND GND


E
2

72 O2_PWM_HSFAN

Title
<Title>

Size Document Number Rev


A3 <Doc> <RevCode>

Date: Thursday, December 12, 2019 Sheet 120 of 140


HEATSINK_MOSA
1

COVER_h7
1
C106D106N
2
/X

HEATPIPE_MODULE

HEATSINK_PCH COVER_h10
1 1
O106X138DO106X138N
/X

HEATSINK

Text: Remove Hsink Spring

2015.03.25 Update Audio Cover

<Variant Name>

Title : HEAT SINK


ASUSTeK COMPUTER INC
Engineer: Aaron_Su
Size Project Name Rev
A3 Maximus XI Extreme R1.01

Date: Monday, December 16, 2019 Sheet 121 of 152


+3VO_U2H1 +3VO_U2H1 +3V_U2H1
U2U7JP1 GL852-Y5A Downstream port 的 U2H1_OCx#
1. 若用來連接標準USB外接Port,請10KOhm Pull-High
2 1 2. 若連接On-board device,請Floating
SHORTPIN_0603_NM 3. 沒使用到的Downstream port,請100KOhm Pull-Down

1
U2U7C28 U2U7C228 /X U2U7C9 U2U7C14
10UF/6.3V 100NF/16V 100NF/16V 100NF/16V
mbs_c0603 +3VO_U2H1
2

2
X5R
BOM select USB外接Port 接On-board Device 沒使用Downstream Port
U27R7 10KOhm
U2H1_OC1# 2 1
GND GND U27R7 mount unmount unmount

U27R15 unmount unmount mount

+5V_DUAL_USBKB +3VO_U2H1 +3VD_U2H1 +3VO_U2H1


U2U7JP2
BOM select USB外接Port 接On-board Device 沒使用Downstream Port
2 1 U27R11 10KOhm
SHORTPIN_0603_NM U2H1_OC2# 2 1
1

1
U2U7C227 U2U7C27 /X U2U7C21 U2U7C5 U27R11 mount unmount unmount
10UF/6.3V 100NF/16V 100NF/16V 100NF/16V
mbs_c0603 /X
2

2
X5R U27R16 unmount unmount mount

GND GND +3VO_U2H1


BOM select USB外接Port 接On-board Device 沒使用Downstream Port

U27R13 10KOhm
U2H1_OC3# 2 1 U27R13 mount unmount unmount
U27R17 100KOhm
+3VD_U2H1 2 1 /X/GL852
+3V_U2H1 U27R17 unmount unmount mount
U27R9 1 2 10KOhm U27R10 1 2 10KOhm GND
U2H1_PSELF U2H1_RST#
U27R15 1 2 10KOhm U27R8 1 2 47KOhm
/X/GL852 +3VO_U2H1 BOM select USB外接Port 接On-board Device 沒使用Downstream Port

U27C4 1UF/10V U27R14 10KOhm U27R14 mount unmount unmount


U27R5 1 2 100KOhm 1 2 U2H1_OC4# 2 1
U2H1_PGANG /X/GL852 U27R18 100KOhm
GND 2 1 /X/GL852 U27R18 unmount unmount mount
GND

GND

DVDD
self-powered 5V Power input for analog circuits

+3VO_U2H1 +5V_DUAL_USBKB +3VD_U2H1


U2H1_REXT U27R1 2 1% 1
620Ohm

REXT Default值為680Ohm GND


U2H1_OC1# 若需要加大眼圖可降至620 Ohm
U2H1_OC2# 但不建議低於620 Ohm
AVDD
for analog circuits U2H1_PGANG
U2H1_PSELF
+3V_U2H1
33
32
31
30
29
28
27
26
25
24
23
22

USPORT U2U7
GND5
GND4
GND3
GND2
GND1
V33
V5
SDA
OVCUR1#
OVCUR2#
PGANG
PSELF

43 U_USB10-
43 U_USB10+
GND
1 21
DM0 DVDD
2 20
DP0 OVCUR3#
3 19 U2H1_OC3#
94 U2H1_DN1 DM1 OVCUR4#
4 18 U2H1_OC4#
94 U2H1_DP1 DP1 TEST/SCL
5 17 U2H1_TEST
AVDD1 RESET#
6 16 U2H1_RST#
94 U2H1_DN2 DM2 DP4
7 15
94 U2H1_DP2 DP2 DM4
2
AVDD2

AVDD3
RREF

DM3

U27R19
DP3
X1
X2

4.7KOHM
/X
8
9
10
11
12
13
14

GL852G-OHY60
1

06039-00160200

GND
U2H1_REXT U2H1_XOUT
U2H1_XIN
U27X1 12Mhz
1 3
1

U27C1 U27C2
2

33PF/50V 33PF/50V <Variant Name>


mbs_c0201_p0402 mbs_c0201_p0402
2

Title : GL852G-OHY5A
GND
ASUSTeK COMPUTER INC
Engineer: Scott2_Lin
Size Project Name Rev
A3 PRIME X299 EDITION 30 1.0

Date: Tuesday, December 17, 2019 Sheet 122 of 131


For DOA/FA improvement

NET TestPoint name Note

H_SKTOCC# AT3

S_RTCRST# AT4

S_SRTCRST# AT5

S_INTRUDER# AT6

O_CASEOPEN# AT88

<Variant Name>

Title : DOA/FA improvement


ASUSTEK COMPUTER INC
Engineer: Aaron Su
Size Project Name Rev
A
Maximus XI Extreme
R1.01

Date: Thursday, December 12, 2019 Sheet 151 of 152


SU1B
K34 J3 IPD
31 H_DMI_TXN0 DMI0_RXN USB2N_1 U_USB0- 74,89
J35 J2 IPD
31 H_DMI_TXP0 DMI0_RXP USB2P_1 U_USB0+ 74,89 Front U32G2(Type C)
C33 N13 IPD
31 H_DMI_RXN0 DMI0_TXN USB2N_2 U_USB1- 107
B33 N15 IPD
31 H_DMI_RXP0 DMI0_TXP USB2P_2 U_USB1+ 107 AURA
G33 K4 IPD
31 H_DMI_TXN1 DMI1_RXN USB2N_3 U_USB2- 74,90
F34 K3 IPD
31 H_DMI_TXP1 DMI1_RXP USB2P_3 U_USB2+ 74,90 BACK U32G2(Type A)
C32 M10 IPD
31 H_DMI_RXN1 DMI1_TXN USB2N_4 U_USB3- 74,96
B32 L9 IPD
31 H_DMI_RXP1 DMI1_TXP USB2P_4 U_USB3+ 74,96 BACK U32G2(Type C)
K32 M1 IPD
31 H_DMI_TXN2 DMI2_RXN USB2N_5 U_USB4- 74,91
J32 L2 IPD
31 H_DMI_TXP2 DMI2_RXP USB2P_5 U_USB4+ 74,91 BACK U32G2(Type A)
C31 K7 IPD
31 H_DMI_RXN2 DMI2_TXN USB2N_6 U_USB5- 74,91
B31 K6 IPD
31 H_DMI_RXP2 DMI2_TXP USB2P_6 U_USB5+ 74,91 BACK U32G2(Type A)
G30 L4 IPD
31 H_DMI_TXN3 DMI3_RXN USB2N_7 U_USB6- 74,92
F30 L3 IPD
31 H_DMI_TXP3 DMI3_RXP USB2P_7 U_USB6+ 74,92 FRONT U32G1(Type A)
C29 G4 IPD
31 H_DMI_RXN3 DMI3_TXN USB2N_8 U_USB7- 74,92
B29 G5 IPD
31 H_DMI_RXP3 DMI3_TXP USB2P_8 U_USB7+ 74,92 FRONT U32G1(Type A)
M29 M6 IPD
31 H_DMI_TXN4 RSVD3 USB2N_9 U_USB8- 74,93
H_DMI_TXN4_R K29 N8 IPD
31 H_DMI_TXP4 RSVD4 USB2P_9 U_USB8+ 74,93 BACK U32G1(Type A)
H_DMI_TXP4_R E28 H3 IPD
31 H_DMI_RXN4 RSVD5 USB2N_10 U_USB9- 74,93
H_DMI_RXN4_R D29 H2 IPD
31 H_DMI_RXP4 RSVD6 USB2P_10 U_USB9+ 74,93 BACK U32G1(Type A)
H_DMI_RXP4_R M26 R10 IPD
31 H_DMI_TXN5 RSVD7 USB2N_11 U_USB10- 122
H_DMI_TXN5_R L26 P9 IPD
31 H_DMI_TXP5 RSVD8 USB2P_11 U_USB10+ 122 GL852G USB hub
H_DMI_TXP5_R C27 G1 IPD
31 H_DMI_RXN5 RSVD9 USB2N_12 U_USB11- 114
H_DMI_RXN5_R B27 G2 IPD
31 H_DMI_RXP5 RSVD10 USB2P_12 U_USB11+ 114 BACK USB2.0 BIOS Flash BACK
H_DMI_RXP5_R G26 N3 IPD
31 H_DMI_TXN6 RSVD11 USB2N_13 U_USB12- 94
H_DMI_TXN6_R F26 N2 IPD
31 H_DMI_TXP6 RSVD12 USB2P_13 U_USB12+ 94 BACK USB2.0
H_DMI_TXP6_R B26 E5 IPD
31 H_DMI_RXN6 RSVD13 USB2N_14
H_DMI_RXN6_R C26 F6 IPD
31 H_DMI_RXP6 RSVD14 USB2P_14 BT
H_DMI_RXP6_R R24
31 H_DMI_TXN7 RSVD15
H_DMI_TXN7_R P24 AH36 XTAL Input mode:
31 H_DMI_TXP7 RSVD16 GPP_E9/USB2_OC0# U_USBOC#01 89 High:XTAL input is differential
H_DMI_TXP7_R B25 AL40
31 H_DMI_RXN7 RSVD17 GPP_E10/USB2_OC1# Low:XTAL input is single-ended
H_DMI_RXN7_R A25 AJ44 U_USBOC#23 PCH has internal 20K PD.
31 H_DMI_RXP7 RSVD18 GPP_E11/USB2_OC2# U_USBOC#45 91
H_DMI_RXP7_R AL41
GPP_E12/USB2_OC3# U_USBOC#67 92
G17 AV47
74,92 U3_U3RXDN7 PCIE1_RXN/USB3_7_RXN GPP_F15/USB2_OC4# U_USBOC#89 93
F16 AR35
74,92 U3_U3RXDP7 PCIE1_RXP/USB3_7_RXP GPP_F16/USB2_OC5# U_USBOC#E12 94
A17 AR37 +3V +3VSB
92 U3_U3TXDN7_C PCIE1_TXN/USB3_7_TXN GPP_F17/USB2_OC6# U_USBOC#1112 94,115
B17 AV43
USB3.2 GEN1@Front 92 U3_U3TXDP7_C
R21
PCIE1_TXP/USB3_7_TXP GPP_F18/USB2_OC7#
U_USBOC#5 USB2_COMP Place Within 1 inch
74,92 U3_U3RXDN8 PCIE2_RXN/USB3_8_RXN

2
P21 F4 1% SR19 1 /CPTH 2 113OHM SR100

1
74,92 U3_U3RXDP8 PCIE2_RXP/USB3_8_RXP USB2_COMP
B18 F3 USB2_COMP SR20 /CPTH 1KOhm SR22 100KOhm
92 U3_U3TXDN8_C PCIE2_TXN/USB3_8_TXN USB2_VBUSSENSE
C18 U13 1 ST37 2 1 1KOhm 1%
92 U3_U3TXDP8_C PCIE2_TXP/USB3_8_TXP RSVD19
K18 G3 TP_PCH_U13
IPU SR21 /CPTH 1KOhm GND /X/CPTH /CPTH
74,93 U3_U3RXDN9 PCIE3_RXN/USB3_9_RXN USB2_ID
J18 2 1

2
74,93 U3_U3RXDP9 PCIE3_RXP/USB3_9_RXP

1
B19 BE41
93 U3_U3TXDN9_C
C19
PCIE3_TXN/USB3_9_TXN GPD7
GPD7_U_WAKE#
Don't use OTG
USB3.2 GEN1@Back 93 U3_U3TXDP9_C
N18
PCIE3_TXP/USB3_9_TXP
T43 GND GPD7_U_WAKE#
74,93 U3_U3RXDN10 PCIE4_RXN/USB3_10_RXN PCIE21_RXN
R18 R44
74,93 U3_U3RXDP10 PCIE4_RXP/USB3_10_RXP PCIE21_RXP

2
D20 G47
93 U3_U3TXDN10_C PCIE4_TXN/USB3_10_TXN PCIE21_TXN
C20 F46 SR23
93 U3_U3TXDP10_C PCIE4_TXP/USB3_10_TXP PCIE21_TXP
F20 U40 20KOHM
81 S_X1_LAN1_RXN PCIE5_RXN PCIE22_RXN
G20 U41 /X/CPTH
81 S_X1_LAN1_RXP PCIE5_RXP PCIE22_RXP
B21 H47 5%
I225V PCIE5_TXN PCIE22_TXN

1
81 S_X1_LAN1_TXN A22 H48
81 S_X1_LAN1_TXP K21
PCIE5_TXP PCIE22_TXP
W43 PCH_M.2_2
PCIE6_RXN PCIE23_RXN
J21 W44 GND
PCIE6_RXP PCIE23_RXP
D21 G49
PCIE6_TXN PCIE23_TXN
C21 G48
PCIE6_TXP PCIE23_TXP
L24 Y40
PCIE7_RXN PCIE24_RXN
J24 Y41
PCIE7_RXP PCIE24_RXP
C23 G46
PCIE7_TXN PCIE24_TXN
B23 G45
PCIE7_TXP PCIE24_TXP
F24
PCIE8_RXN
G24
PCIE8_RXP
B24
PCIE8_TXN
C24
PCIE8_TXP

FH82Z490 2 OF 13

02001-00860000

+3VSB +3VSB
1

U3HR660 U3HR66
100KOhm 100KOhm
/CPTH /CPTH
2

U3HD4
1
U_USBOC#2 90
3
U_USBOC#23 2 U_USBOC#5
U_USBOC#3 96

BAT54AW /CPTH
Title : CPTH (PCIE/DMI/USB)

ASUSTek Computer Inc.


Engineer: Aaron_Su
Size Project Name Rev
A3 Maximus XII Extreme R1.01

Date: Thursday, December 12, 2019 Sheet 43 of 152


3.2

Support Gen3 +12V


+3V
20190807 Remove RTD3 +3V
+3V
For RTD3 support +3VSB +3VSB

1
+3VSB +12V
PCIEX16 + XCE2 XCE3
GND +12V 100UF/16V 100UF/6.3V

2
1
2
3
4
5
6

2
1

P_GND1
P_GND2
P_GND3
P_GND4
P_GND5
P_GND6
B1 A1
+12V_1 PRSNT1#
XR3 XR4 B2 A2
+12V_2 +12V_3
4.7KOhm 4.7KOhm B3 A3
+12V_5 +12V_4
B4 A4 GND

2
GND1 GND35
1 XR1 2 B5 A5 GND
45,52,114,115 S_SMBCLK_PCI SMCLK JTAG2
0Ohm 1 XR2 2 B6 A6
45,52,115 S_SMBDATA_PCI SMDAT JTAG3
/X/CONN 0Ohm B7 A7
GND2 JTAG4
/X/CONN B8 A8
+3.3V_1 JTAG5
B9 A9
X_WAKE# B10
JTAG1 +3.3V_2
A10
3.3Vaux +3.3V_3
B11 A11
WAKE# PWRGD O_PCIRST#_PCIEX16_1 66
需在SB端Pull-high

1
XC71
45,81,97 X_WAKE#
1000PF/50V
B12 A12 /X
Near Connector (Void) RSVD2 GND36

2
47 X_1X16_CLKQ#_R B13 A13
X5R
GND3 REFCLK+ C_PCIEX16_1 47
XCX1 2 1 0.22UF/10V B14 A14
31 X_1X16_TXP0 HSOP0 REFCLK- C_PCIEX16#_1 47
XCX2 2 1 0.22UF/10V X_1X16_TXP0_C B15 A15
31 X_1X16_TXN0 HSON0 GND37
void
X_1X16_TXN0_C B16 A16 GND
GND4 HSIP0 X_1X16_RXP0 31
void X5R B17 A17
PRSNT2_1# HSIN0 X_1X16_RXN0 31
B18 A18
GND5 GND38

X5R
XCX3 2 1 0.22UF/10V B19 A19
31 X_1X16_TXP1 HSOP1 RSVD6
XCX4 2 1 0.22UF/10V X_1X16_TXP1_C B20 A20
31 X_1X16_TXN1 HSON1 GND39
void
X_1X16_TXN1_C B21 A21
GND6 HSIP1 X_1X16_RXP1 31
X5R void X5R B22 A22
GND7 HSIN1 X_1X16_RXN1 31
XCX5 2 1 0.22UF/10V B23 A23
31 X_1X16_TXP2 HSOP2 GND40
XCX6 2 1 0.22UF/10V X_1X16_TXP2_C B24 A24
31 X_1X16_TXN2 HSON2 GND41
void X_1X16_TXN2_C B25 A25
GND8 HSIP2 X_1X16_RXP2 31
X5R void
X5R B26 A26
GND9 HSIN2 X_1X16_RXN2 31
XCX7 2 1 0.22UF/10V B27 A27
31 X_1X16_TXP3 HSOP3 GND42
XCX8 2 1 0.22UF/10V X_1X16_TXP3_C B28 A28
31 X_1X16_TXN3 HSON3 GND43
void X_1X16_TXN3_C B29 A29
GND10 HSIP3 X_1X16_RXP3 31
void
X5R B30 A30
RSVD3 HSIN3 X_1X16_RXN3 31
B31 A31
PRSNT2_2# GND44
B32 A32
GND11 RSVD7

X5R
XCX9 2 1 0.22UF/10V B33 A33
20190807 Remove RTD3 31
31
X_1X16_TXP4
X_1X16_TXN4
XCX10 2 1 0.22UF/10V X_1X16_TXP4_C B34
HSOP4
HSON4
RSVD8
GND45
A34
void
X_1X16_TXN4_C B35 A35
GND12 HSIP4 X_1X16_RXP4 31
X5R void
X5R B36 A36
GND13 HSIN4 X_1X16_RXN4 31
XCX11 2 1 0.22UF/10V B37 A37
31 X_1X16_TXP5 HSOP5 GND46
XCX12 2 1 0.22UF/10V X_1X16_TXP5_C B38 A38
31 X_1X16_TXN5 HSON5 GND47
void X_1X16_TXN5_C B39 A39
GND14 HSIP5 X_1X16_RXP5 31
X5R void
X5R B40 A40
GND15 HSIN5 X_1X16_RXN5 31
XCX13 2 1 0.22UF/10V B41 A41
31 X_1X16_TXP6 HSOP6 GND48
XCX14 2 1 0.22UF/10V X_1X16_TXP6_C B42 A42
31 X_1X16_TXN6 HSON6 GND49
void
X_1X16_TXN6_C B43 A43
GND16 HSIP6 X_1X16_RXP6 31
X5R void
X5R B44 A44
GND17 HSIN6 X_1X16_RXN6 31
XCX15 2 1 0.22UF/10V B45 A45
31 X_1X16_TXP7 HSOP7 GND50
XCX16 2 1 0.22UF/10V X_1X16_TXP7_C B46 A46
31 X_1X16_TXN7 HSON7 GND51
void
X_1X16_TXN7_C B47 A47
GND18 HSIP7 X_1X16_RXP7 31
void X5R B48 A48
PRSNT2_3# HSIN7 X_1X16_RXN7 31
X5R B49 A49
GND19 GND52
XCX17 2 1 0.22UF/10V B50 A50
31 X_1X16_TXP8 HSOP8 RSVD9
XCX18 2 1 0.22UF/10V X_1X16_TXP8_C B51 A51
31 X_1X16_TXN8 HSON8 GND53
void X_1X16_TXN8_C B52 A52
GND20 HSIP8 X_1X16_RXP8 31
X5R void
X5R B53 A53
GND21 HSIN8 X_1X16_RXN8 31
XCX19 2 1 0.22UF/10V B54 A54
31 X_1X16_TXP9 HSOP9 GND54
XCX20 2 1 0.22UF/10V X_1X16_TXP9_C B55 A55
31 X_1X16_TXN9 HSON9 GND55
void X_1X16_TXN9_C B56 A56
GND22 HSIP9 X_1X16_RXP9 31
X5R void
X5R B57 A57
GND23 HSIN9 X_1X16_RXN9 31
XCX21 2 1 0.22UF/10V B58 A58
31 X_1X16_TXP10 HSOP10 GND56
XCX22 2 1 0.22UF/10V X_1X16_TXP10_C B59 A59
31 X_1X16_TXN10 HSON10 GND57
void X_1X16_TXN10_C B60 A60
GND24 HSIP10 X_1X16_RXP10 31
X5R void
X5R B61 A61
GND25 HSIN10 X_1X16_RXN10 31
XCX23 2 1 0.22UF/10V B62 A62
31 X_1X16_TXP11 HSOP11 GND58
XCX24 2 1 0.22UF/10V X_1X16_TXP11_C B63 A63
31 X_1X16_TXN11 HSON11 GND59
void
X_1X16_TXN11_C B64 A64
GND26 HSIP11 X_1X16_RXP11 31
X5R void
X5R B65 A65
GND27 HSIN11 X_1X16_RXN11 31
XCX25 2 1 0.22UF/10V B66 A66
31 X_1X16_TXP12 HSOP12 GND60
XCX26 2 1 0.22UF/10V X_1X16_TXP12_C B67 A67
31 X_1X16_TXN12 HSON12 GND61
void
X_1X16_TXN12_C B68 A68
GND28 HSIP12 X_1X16_RXP12 31
X5R void
X5R B69 A69
GND29 HSIN12 X_1X16_RXN12 31
XCX27 2 1 0.22UF/10V B70 A70
31 X_1X16_TXP13 HSOP13 GND62
XCX28 2 1 0.22UF/10V X_1X16_TXP13_C B71 A71
31 X_1X16_TXN13 HSON13 GND63
void
X_1X16_TXN13_C
void
X5R B72 A72
GND30 HSIP13 X_1X16_RXP13 31
X5R B73 A73
GND31 HSIN13 X_1X16_RXN13 31
XCX29 2 1 0.22UF/10V B74 A74
31 X_1X16_TXP14 HSOP14 GND64
XCX30 2 1 0.22UF/10V X_1X16_TXP14_C B75 A75
31 X_1X16_TXN14 HSON14 GND65
void X_1X16_TXN14_C B76 A76
GND32 HSIP14 X_1X16_RXP14 31
X5R void
X5R B77 A77
GND33 HSIN14 X_1X16_RXN14 31
XCX31 2 1 0.22UF/10V B78 A78
31 X_1X16_TXP15 HSOP15 GND66
XCX32 2 1 0.22UF/10V X_1X16_TXP15_C B79 A79
31 X_1X16_TXN15 HSON15 GND67
void X_1X16_TXN15_C B80 A80
GND34 HSIP15 X_1X16_RXP15 31
void
X5R B81 A81
PRSNT2_4# HSIN15 X_1X16_RXN15 31
B82 A82
RSVD4 GND68
Near Connector (Void)

PCI_EXPRESS_X16
+3V
12003-00039700

20190806 pull up +3V Allen


2

GND GND
XRX17
8.2KOhm
1

42 X_1X16_DET#

20190807 Remove RTD3

PRSNT# PIN Netname修改

使用此功能(請確認SB 請將PIN B17,B31,B48,B81


端是否要Pull-high) netname
改為X_1X16PRSNT#.

20190807 Remove RTD3 不使用此功能,且不


support SLOT_WARN
& SDVO線路(請確 請將PIN
認SB端是否要Pull-high B17,B31,B48,B81
or Pull-down) netname
改為GND.

<Variant Name>

SLOT 顏色 PCIEX16_1(LIGHT GRAY)


PIN B17 --> X_SDVO_CLK Title :
PCIEX16_1
LIGHT GRAY Only support PIN B31 --> X_SDVO_DATA ASUSTek Computer Inc.
Engineer: Aaron_Su
SDVO線路
PIN B48 --> X_EXP_SM Size Project Name Rev
A2
Z390 Golden board 3.1

Date: Thursday, December 12, 2019 Sheet 60 of 152


+PVDD_SIO 0.5E
OR50 1 2 8.2KOhm /6798D_B A version : 不上件
Choose SIO Power Source by project BOM select LPC Mode eSPI Mode BOM select A version IC B version IC
B version : 上件
OR51 0Ohm /6798D_B Standard Circuit
45 CLK_REQ_SIO# 2 1 O_CLKREQN BOM 無S0iX線路 有S0iX線路 OR8151 mount unmount OR50 unmount mount
SIO NCT6798D
OR8221 mount unmount OR8152 mount unmount OR51 unmount mount
OR8161 1 2 0Ohm /X/ESPI
46 S_ESPI_RST#
ESPI_RESET#_SIO REV. O_0.5I
+PVDD_SIO
could delete this block when LPC Bus OR8236 unmount mount OR8172 unmount mount
NCT6798D
Signal with Chipset side pull-high OR744 2.7KOhm
OR8237 12 1
2 0Ohm /X/ESPI OR8161 unmount mount
46 S_ESPI_ALERT#
OR8202 1 2 0Ohm /LPC +3V_SIO
46,72 F_SERIRQ#
F_SERIRQ_R# +3V
35,42,55,81 S_PLTRST#
OR8237 unmount mount
OC502 10PF/50V OR8221 1 2 0Ohm
1 2 /X/6798D NPO mbs_r0603 +3VSB
Strapping pin
/NON-S0IX SIO_PIN27 6796: P80_EN
GND Starpped by RSMRST#

2
46,72 F_FRAME#
OR8329 Pull up P80 Enabled
46,72 F_LAD[0:3]
20190806 Remove +3V_S0iX Allen 8.2KOhm
F_LAD0 /6798D
46 C_PCI_SIO
F_LAD1 pull down P80 Disabled

1
F_LAD2 +BAT_3V +5VSB_ATX
F_LAD3
+3VSB_ATX
Strapping pin Strapping pin

2
PWRBTN#: OC509 2 1 10PF/50V
PCH Internal pull up GND S_SLPS4#_SIO 21,23,30,45,72,115
+3VSB /X/6798D OU1 +BAT_3V +PVDD_SIO OR8328 OR8332 SIO_PIN31 6796: 2E_4E_SEL SIO_PIN9 6798: AS_SEQ1_EN

2
+3VSB +3V_SIO 2MOHM 8.2KOhm Strapped by LRESET#
OR8218 2.2KOhm +3VSB +3VSB_ATX +5VSB_ATX +3VSB_ATX +3V_SIO /X/6798D mbs_r0603 OR8023 Starpped by RSMRST#

2
1 2 /X/6798D O_RSTCONO#_SIO_R1 +5VSB_ATX +3V_SIO 10V212200510 10V213820240 8.2KOhm Pull up Enabled Pull up AS_SEQ1 Enabled

1
OR205 OR206 mbs_r0402 /6798D 3 /6798D

/X/6798D

3
OR2003

OR7621

OR8129

OR2005

OR2006

OR2007
D

OR760
+3VSB_ATX VHIF 15 1MOhm 8.2KOhm OQ5055

OR2001

OR2002
CLKRUN#

1
OR645

OR209

OR704
OR711
H2N7002 pull down Disabled pull down AS_SEQ1 Disabled
OR8259 8.2KOhm LPC I/F 11 /6798D

1
1 2 /X/6798D O_3VSBSW# VHIF 18 Intruder / 102 VRTC G 2E_4E_SEL: Default disable

1
ESPI_RST#/LDRQ#/GP90/CASE_LED# New CPU SKTOCC# H_SKTOCC# 35,72,76 S
VHIF 19 2 OR30 兩個SIO以上才需要使用此function,

2
2
ESPI_ALERT#/SERIRQ
VSB 26 100 VRTC 1 AT88 /X/6798D OC511 1KOhm 請pull down disabled.
PLFLRST#/LRESET# CASEOPEN0#/THERMTRIP# Strapping pin

2
72

2
VRTC SIO_PIN100 0.1UF/16V /X/6798D

1
1
SLP_S4##/CASEOPEN1#
25

8.2KOhm

8.2KOhm

8.2KOhm
VHIF S_SLPS4##_SIO /X/6798D SIO_PIN10 6798: AS_SEQ2_EN

2
ESPI_CS#/LFRAME#
23 KBMS

8.2KOhm

2.2KOhm

8.2KOhm
GND

/X/6798D
VHIF
Strapping pin

20KOhm
390Ohm

390Ohm
ESPI_IO0/LAD0

1KOhm

1KOhm

1KOhm

1KOhm
VHIF 22 56 VSB Starpped by RSMRST#
ESPI_IO1/LAD1 MCLK/GP23/AUXFANOUT4 O_MS_CLK 67
VHIF 21 57 VSB GND 6796: DDR4_EN Pull up AS_SEQ2 Enabled
SIO_PIN32

2
ESPI_IO2/LAD2 MDAT/GP22/AUXFANIN4 O_MS_DATA 67

1
1

1
VHIF 20 58 VSB Starpped by RSMRST#
ESPI_IO3/LAD3 KCLK/GP21/AUXFANOUT3/CIRRX O_KB_CLK 67
VHIF 17 59 VSB +3V +3VSB_ATX +3VSB_ATX Pull up DDR4 POWER EN
ESDO1C4 2 1 100PF/50V ACPI ESPI_CLK/PCICLK

ACPI
KDAT/GP20/AUXFANIN3
(P80_EN)GA20M/GP91/RLED
27
28
VSB
O_KB_DATA 67
pull down AS_SEQ2 Disabled
/X/6798D S_SLPS4#_SIO_R1 VSB SIO_PIN27
KBRST#/GP92/CASE_LED# O_KB_RST# 46

2
101

2
OR29 0Ohm OD VRTC pull down DDR4 POWER DISABLED Default disable
19,53,72,73 O_RSMRST# RSMRST#
ESDO1C5 2 1 100PF/50V OR310 1 2 100Ohm 2 1 O_RSMRST#_R IPU VSB 61 OR758 OR720 OR663
78 O_PWRBTN#IN PSIN#
/X/6798D S_SLPS3#_SIO_R1 1 2 JP8257 SHORTPIN_0402_NM O_PWRBTN#IN_R OD VSB 60 8.2KOhm 8.2KOhm 8.2KOhm
45 O_PWRBTN#
1 2 JP8258 SHORTPIN_0402_NM O_PWRBTN#_SIO_R1 VSB 84
PSOUT#
/X/6798D /X/6798D
Strapping pin
GND
45 S_SLPS4#_PCH
1 2 JP8259 SHORTPIN_0402_NM S_SLPS4#_SIO_R1 VSB 64
SLP_S5#
COM1 & COM2 Strapping pin
21,23,30,45,54,72 S_SLPS3# SLP_S3# SIO_PIN12 6798: AS_SEQ1_SWAP

1
1

1
OR211 1 2 33Ohm S_SLPS3#_SIO_R1 OD VSB 63 29 VSB
SIO_PIN34 6796: ESPI_EN
72 O_PSON# PSON# CTSA#/GP80 O_CTS1#_R 68
OR8335 1 2 0Ohm /X/6798D O_PSON#_R VSB 80 30 VSB Starpped by RSMRST# Starpped by RSMRST#
Pin 81 - O_PWROK#, 請依對應處power plane pull up 76 B_ATX_PWROK ATXPGD DSRA#/GP81 O_DSR1#_R 68
1 2 JP8255 SHORTPIN_0402_NM B_ATX_PWROK_SIO OD VRTC 82 31 VSB O_2E_4E_SEL Pull up AS_SEQ1_SWAP Enabled
54,64 O_PWROK_SIO PWROK/FDLED1 (2E_4E_SEL)RTSA#/GP82 O_RTS1#_R 68
O_PWROK_SIO_R1 VSB 71 32 VSB DDR4_EN Pull up ESPI Enabled
Delete Pin 81 O_PWROK# if don't need 3VSBSW#/GP33 (DDR4_EN)DTRA#/GP83 O_DTR1#_R 68
O_3VSBSW#OD VRTC 70 33 VSB
19,20,21 O_DEEPS5 DEEP_S5_0 GP84/SINA O_RXD1_R 68
OR8164 1 2 100Ohm VSB 83 34 VSB ESPI_EN pull down AS_SEQ1_SWAP Disabled
78 O_RSTCONI# RESETCONI#/GP30/OVT#_1 /SMI#_1/CIRRX SOUTA_P80/GP85/SOUTA(ESPI_EN) O_TXD1_R 68,75
OR8258 1 2 0Ohm O_RSTCONI#_R OD VSB 37 35 VSB pull down ESPI Disabled (LPC)
45,72 O_RSTCONO# RESETCONO#/GP47/FDLED4 GP86/DCDA# O_DCD1#_R 68
O_RSTCONO#_SIO_R1 65 36
S3,S4,S5 S3,S4,S5 VSB
5VSB_GATE#_CAP/GP93 GP87/RIA#
VSB
O_RI1#_R 68 Default disable
81
1 72 O_RSTCONI#_R
OD VRTC
PWROK# 6796切換成ESPI:

2
7 VSB 20190731 Remove GP17 CPU_OV (1) ESPI_EN pull up

1
72 O_PWRBTN#IN_R CTSB#/GP17/VCCIO_EN#
8 SIO_PIN7 1 DT1 /X/6798D OR7 OR212 OR3
S0 for KEYBOT mode
DSRB#/GP16/VCORE_EN
VSB
(2) LPC_ESPI_VDD接1.8V
RSTOUT 9 IPDSIO_PIN8 680OHM 680OHM 680OHM
0 (AS_SEQ1_EN)RTSB#/GP15
VSB
(default push-pull) VSB 79 10 VSB IPD AS_SEQ1_EN /X/6798D
60 O_PCIRST#_PCIEX16_1 RSTOUT0#/GP74 (AS_SEQ2_EN)DTRB#/GP14
(default push-pull) VSB 78 11 VSB AS_SEQ2_EN 1 DT8 /X/6798D

2
RSTOUT1#/GP75 IRRX0/SINB/GP13/VRM_PG

1
(default push-pull) VSB 12 VSB IPD
97 O_PCIRST#_PCIEX16_3 (AS_SEQ1_SWAP) SOUTB_P80/IRTX0/SOUTB/GP12
77 13 AS_SEQ1_SWAP

/X/6798D
VSB

1UF/10V
RSTOUT2#/GP76/MLED/GPIOE#/BLED DCDB#/GP11/S_PWROK STEALTH_MODE_EN_SIO 78

2OC303 1
Check Pin 120 VTT Power should be CPU PECI Power +VCCST_SIO 14 VSB GND GND GND
Strapping pin(B版) Strapping pin(A版)
RSTOUT OU1C120 1 2 0.1UF/16V VTT 120
PECI/SST
RIB#/GP10/VCCST_PG
+3VSB_ATX
2X4_POWER_DETECT 76
+3VSB_ATX
SIO_PIN69 6798: VSB_CTL_EN SIO_PIN69 6798: DSW_EN VTT
Starpped by RSMRST# Starpped by RSMRST# +3VSB_ATX 118 OR61 8.2KOhm OR8226 8.2KOhm /X/6798D
CPUD-/AGND
Fan Control 1 2 AS_SEQ1_EN OR8227 2 1 8.2KOhm /X/6798D +3VSB
Pull up Enable 5VSB Dual function Pull up DSW Enabled GND AS_SEQ2_EN OR8228 2 1 8.2KOhm /X/6798D
OR552 8.2KOhm GND FANOUT 127 VSB AS_SEQ1_SWAP 2 1
(DC) SYSFANOUT O_PWM_SYS 71
Intel DSW

2
1 2 /X/6798D GND 121 VSB
PECI/TSID O_H_PECI 69
pull down Disable 5VSB Dual function pull down VSB/VCC 93 122 VSB OR8229 OR8230 OR8231
DSW Disabled 71 O_MODE_SYS GP50/RSTOUT3#/SYSFANGPP/PS_ON# GP01/AUXFANOUT1
OR614 680OHM VSB 92 123 VSB 680OHM 680OHM 680OHM OR8342 8.2KOhm
GP51/AUXFANIN3/DDR_VTT_CTL GP02/AUXFANOUT2
Default disable DSW: Intel deep sleep well. 2 1 /6798D VSB/VCC 91 /6798D /6798D /6798D
71 O_POS_SYS GP52/RSTOUT4#/FDLED3 /SYSFANGPL/SLP_S0#
目前沒有support, 請pull down. VSB 90 SIO_PIN7 2 1
GP53/AUXFANOUT3/FDLED2

1
/VTT_DDR_EN
GND VSB/VCC 89 /X/6798D
GP54/SLP_SUS#/AUXFAN0GPP FANOUT
+3VSB VSB/VCC 88 125 VSB
GP55/SLP_SUS_FET/AUXFAN0GPL /PWROK# (PWM) CPUFANOUT O_PWM_CPU 71
O2_SMB2_DATA O2_SMB2_CLK +3VSB 20190807 Remove PS_ON_B VRTC 73 GND GND GND
OR7071

OR7072

DPWROK/PS_ON##
1

VSB 97
PCHVSB/SLP_S0#
1

OC505 (PS_ON#) 20190817 SLPS0# pull up 2 1


OC504 27PF/50V OR8343 8.2KOhm /6798D
2

27PF/50V (SLP_S0#) 20190731 Allen


2

Remove GP53 GP51 FAN3 PWM AUX BCLK STRAP HW MONITOR


2

67 FANIN
8.2KOhm

8.2KOhm

VSB
71 O_SEN_AUX4 5VSB_GATE#/GP72/AUXFANIN4
GND GND VSB 69 3 VSB
GP70/GLED(VSB_CTL_EN) GP04/AUXFANIN0
VSB_CTL_EN 4 VSB 2X4_POWER_DETECT 從PCH移到SIO: (註 PIN 13)
GP05/AUXFANIN1
O_SMBCLK_VSB O_SMBDATA_VSB VSB 66 5 VSB - Pull up +3VSB_ATX在SIO.
71 O_PWM_AUX4 5VSB_DUAL_GATE#/GP73 GP06/AUXFANIN2
1

/AUXFANOUT4/PWROK/3VSBSW#
- 需接至BQ1 MOS 避免漏電.
1

OC152 VSB/VCC 68 ONBOARD_HD_LED+ 為ROG Function,


71 O_MODE_CPU GP71/S_PWROK/CPUFANGPP GPIH: 8 Pin +12V Connector is not dectected. (Default)
OC151 10PF/50V 124 VSB 提供在BIOS下有選項可開關ONBOARD HD LED燈.
CPUFANIN O_SEN_CPU 71 GPIL: 8 Pin +12V Connector is detected.
10PF/50V /X/6798D 20191023 Allen 126 VSB
SYSFANIN O_SEN_SYS 71
2

/X/6798D add GP73 AIO PWM AUX SM BUS


VSB 75 69 O_TR_CPU 69 O_TR_MB
45,72,73 O2_SMB2_CLK GP32/SCL/MSCL/AUXFANIN3
VSB 76 TEMPERATURE IN
45,72,73 O2_SMB2_DATA GP31/SDA/MSDA/AUXFANOUT3
GND GND 112 AVSB OU1C112 0.1UF/16V /X/6798D
CPUTIN
VSB 52 117 AVSB OU1C263 1 2 0.1UF/16V /X/6798D +5V
107 O_SMBCLK_VSB MSCL/SCL/GP41/INIT# VIN8/AUXTIN4
VSB 51 113 AVSB +VCCIO_1_2_SIO_IN OU1C113 1 2 0.1UF/16V /X/6798D
107 O_SMBDATA_VSB MSDA/SDA/BEEP/GP42/SLIN# VIN9/SYSTIN
1 2
FOR AURA CONTROL. 111 AVSB OU1C111 0.1UF/16V /X/6798D
VIN4/AUXTIN0/5VSB_DUAL

2
114 AVSB +VCCGT_SIO_IN OU1C114 1 2 0.1UF/16V /6798D
VDDQ/VIN5/AUXTIN1
80 PORT / LED CONTROL 115 AVSB +VDDQ_SIO_IN OU1C115 1 2 0.1UF/16V /X/6798D OR7631
VCCIO/VIN6/AUXTIN2
VSB 50 116 AVSB +VCCIO_0_SIO_IN OU1C116 1 2 0.1UF/16V /X/6798D 8.2KOhm
LED_A/GP60/PD0 VIN7/AUXTIN3/ATX_5VSB/5VSB_ATX
VSB 49 +VCCSA_SIO_IN 1 2
LED_B/GP61/PD1
VSB 48 VIN
LED_C/GP62/PD2

1
VSB 47 109 AVSB +VCORE_SIO_IN OU1C109 0.1UF/16V /6798D GND
LED_D/GP63/PD3 CPUVCORE
VSB 45 103 VSB 1 2
LED_E/GP64/PD4 SOUTC_P80/OVT#_2/SMI#_2/GP40 OVT2 55
VSB 44 SIO_PIN103 OR8260 1 2 0Ohm
LED_F/GP65/PD5 O_+12VIN 69 O_+5VIN 69 +1.05V_A_IN 19
VSB 43 104 AVSB /6798D OU1C104 0.1UF/16V /6798D
LED_G/GP66/PD6 VIN0
VSB 42 105 AVSB OU1C105 1 2 0.1UF/16V /6798D
VSB 41
DGH0#/GP67/PD7 VIN1
106 AVSB 1 2 to CPU_LED
DGL0#/GP43/ACK# 1.0VSB(VIN2)
107 AVSB OU1C107 0.1UF/16V /X/6798D
VIN3/5VSB
By Project需求: VSB/VCC 40 +VCCPLL_OC_SIO_IN 1 2
1. VPP_PG 若使用SIO DDR4功能, 請保留此框. 12 P_VCCSA_VBOOT1_5 GP44/GRN_LED/BUSY/AUXFAN2GPP
VSB/VCC 39 OU1C106 0.1UF/16V /6798D
2. VPP_PG 若不使用SIO DDR4功能可移除此框. 12 P_VCCSA_VBOOT2_5 GP45/YLW_LED/PE/AUXFAN2GPL
110 AVSB 1 2
VREF O_VREF 69
20191212 add for VCCSA VBoot
OR8114 0Ohm 1 DTS810
18 P_+VPPDDR_PG_5
1 2 POWER +3VSB_ATX +3VSB_ATX +BAT_3V

CIR DIGITAL/ANALOG POWER +3V_SIO +PVDD_SIO


GND
(S0_IDEL#) 0.1UF/16V1 2
OU1C150 VSB 95 119 VSB/VCC GND
VPP_PG/CIRRX/GP24/IRRX1 AUXFAN1GPP/GP26/TSIC/VCCIO_EN#
/X/6798D OR7066 2 1 8.2KOhm SIO_PIN95 VSB 96 1 VCC
GP25/IRTX1/S0_IDLE#(DSW_EN) 3VCC
20191023 Allen VSB 6 24 PAD_VDD OU1C24 2 1 0.1UF/16V
Remove GP00 FAN AUX0 GP00/AUXFANOUT0 1.8VSB/VHIF
/6798D VSB/VCC 38 108 AVSB OU1C108 2 1 0.1UF/16V
GP46/SLCT/AUXFAN3GPL AVSB
+3VSB 20190731 Allen VSB/VCC 98 46 VSB SIO_PIN108_AVCC OU1C46 2 1 0.1UF/16V /X/6798D
Remove GP46 FAN AUX3 AUXFAN1GPL/MLED/GP27/VCORE_EN 3VSB1
GND 85 VSB OU1C85 2 1 0.1UF/16V
3VSB2
/X/6798D 20190731 Allen Misc 99 VBAT OU1C99 2 1 0.1UF/16V
Remove GP34 FAN mode VBAT
OR8027 8.2KOhm VSB/VCC 55
GP34/STB#/AUXFAN3GPP

1
OR8028 2 8.2KOhm 1 20191023 add GP35,36 AIO_FAN mode VSB/VCC 54 OU1C1 OU1C129 10UF/16V /X/6798D
71 O_MODE_AUX4 GP35/DGH1#/AFD#/AUXFAN4GPP
2 1 VSB/VCC 53 0.1UF/16V OU1C130 1 2 10UF/6.3V mbs_c0603 /X/6798D
71 O_POS_AUX4 GP36/DGL1#/ERR#/AUXFAN4GPL
OR7638 0Ohm OD VSB 87 GND OU1C131 1 2 10UF/6.3V mbs_c0603 /X/6798D
17,18 P_+VDDQ_EN_5 VDDQ_EN/GP56/AUXFANOUT4

2
OR7637 2 1 0Ohm SIO_PIN87 OD VSB 86 16 1 2
18 P_+VPPDDR_EN_5 VPP_EN/GP57/AUXFANIN4 VSS1
2 1 SIO_PIN86 VSB 74 94
VRM_PG/GPIOE#/GP77 VSS2
20191023 add GP35,36 AIO_FAN mode SIO_PIN74 PAD_VDD 62 GND GND
PAD_CAP
PAD_CAP VSB/VCC 2
71 O_POS_CPU CPUFANGPL/GP03/VCCST_PG
VSB 128 +PVDD_SIO +3VSB
69 O_MEM_OK_R
SIO_PIN128
(AT_ATX_MODE)GP07/OVT#_1 /SMI#_1
6798: LPC_VDD (PAD_VDD)
OU1C2 OU1C202 OR8151 0Ohm
2

BOM1 適用於下面2點任何一條滿足的情況 1UF/10V 4.7UF/6.3V 2 1 /LPC 6798切換成ESPI:


1.SIO 端 strapping pin 是 pull down 的 mbs_c0402 mbs_c0603 GND +1.8V_A (1) Pin34 ESPI_EN pull up
1

2.S_SLP_S0#_IDLE 後面接的線路可能會影響到 SIO端的 stapping /X/6798D NCT6798D-B (2) LPC_ESPI_VDD接1.8V


上件: OQ6001/OR8327/OR661/OR8326 /6798D OR8172 0Ohm (3) SERIRQ斷開OR8202不上件
不上件: OR8234/OR8135/OU1C261/OU1C262 2 1 /X/ESPI
06116V00380100
GND GND
By Project需求:
1. VDDQ_EN, VPPDDR_EN 採用SIO內部功能, 請Keep 此橘框. +3VSB
2. VDDQ_EN, VPPDDR_EN 採用Project 外兜線路, 請刪除此橘框.
BOM2適用於下面2點都滿足的情況
1.SIO 端 strapping pin 是 pull high 的 +3VSB_ATX
2.S_SLP_S0#_IDLE 後面接的線路不會影響到 SIO端的 stapping
上件: OR8234/OR8135
(Power 的部分請勿做修改, 如需修改請洽標線)
1

OU1C60 OU1C260
Strapping pin(A版)
2

不上件: OQ6001/OR8327/OR661/OR8326/OU1C261/OU1C262 0.1UF/16V 10UF/6.3V


6798: VSB_CTL_EN /X/6798D mbs_c0805
1

X5R
SIO_PIN96
1

OR8081
Starpped by RSMRST# OR8262 /X/6798D /X/6798D
OR8055
8.2KOhm 1 2 OJP503 SHORTPIN /X/6798D
+VCORE
G3->S5 S5 S0 S0iX S0 S3/S4/S5 Pull up Enable 5VSB Dual function /6798D +VCORE_SIO_IN 2 1 +VCORE_IN 1 2 O1JP16 SHORTPIN
+VCCGT
+VCCGT_SIO_IN 2 1 +VCCGT_IN
GND placement on CPU side
2

10KOhm

pull down Disable 5VSB Dual function 1% 10KOhm placement on CPU side

1
2
OR8067 1%
S_SLPS3# Default disable OR8082 CFL Voltage Range 90.9KOhm
90.9KOhm 0.6~1.7V CFL Voltage Range
Strapping pin(B版) 1% 0.6~1.7V

2
Strapping pin 1%

1
SIO_PIN96 SIO_PIN96 6798: DSW_EN
Starpped by RSMRST# SIO_PIN34 6798: AT_ATX_MODE
Starpped by RSMRST# GND
Pull up DSW Enabled GND
SLP_S0_PLT_N_10 Pull up ATX function

pull down DSW Disabled OR8152 1% 1KOhm /X/6798D


pull down AT function 2 1 1 2 OJP504 SHORTPIN
+VCCSA
DSW: Intel deep sleep well. +VCCSA_SIO_IN +VCCSA_IN
OR8066
目前沒有support, 請pull down. Default AT function /X/6798D
placement on CPU side
1 2 O1JP14 SHORTPIN
+VDDQ
AT Mode : AC ON後會直接開機 +VDDQ_SIO_IN 2 1 +VDDQ_IN

placement on CPU side

1
10KOhm
ATX Mode(Default):AC ON後按power button後才能開機 OR8153 CFL Voltage Range

1
OR8068 1% 1KOhm 0.7~1.8V
1%
6798: VTT 90.9KOhm
CFL Voltage Range

2
(10) 1~2.4V

2
1%
20190807 Remove +VCCST +VCCST_SIO
BOM select S0IX Non-S0IX GND
OR8130 GND

1 499Ohm 2 1% OR8327 mount unmount


OR8154 0Ohm /X/6798D
OQ6001A mount unmount 1 2 O1JP18 SHORTPIN
+VCCIO_0
預留線路讓SLP_S0# OR8340 0Ohm /X/6798D +VCCIO_0_SIO_IN 2 1 +VCCIO_0_IN
拉掉給SIO的+VCCST. 1 2 O1JP19 SHORTPIN /6798D
For S0IX驗證. +VCCIO_1_2_SIO_IN 2 1 +VCCIO_1_2_IN
+VCCIO_1_2 placement on CPU side
OQ6001B mount unmount

1
/6798D OR8155
placement on CPU side
0Ohm
1

OR8326 mount unmount OR8341 /X/6798D CFL Voltage Range


0Ohm 0.9~1.8V

2
/X/6798D CFL Voltage Range
6798: For Intel power sequence OR8232 mount unmount 0.9~1.8V
2

GND
OQ5018 mount unmount
GND

O_PWRBTN#_SIO_R1 OR8233 mount unmount


+5VDUAL_AUX
O1C201
O1R201 1 2 4.7KOhm mbs_r0603 /X/6798D OR8236 mount unmount
1 2
O1R202 1 2 8.2KOhm /X/6798D 1UF/16V
mbs_c0603 OR8221 unmount mount
/X/6798D
GND GND

<Variant Name>

Title : NCT6798D_CFL

ASUSTek COMPUTER INC.


Engineer: Eddie Chiu
Size Project Name Rev
R1.01
A1 Standard Circiut
Date: Monday, December 23, 2019 Sheet 66 of 152
L1 L2

RX RX
Connector
PI3EQX1004
TX TX
Chipset
in Chipset
Demo place near Connector

D+/D-

Net Impedance/Width Space Length

TX/RX L1 30 mils < 10'', prefer 5'' - 9''


follow USB 3.1
Controller Rule
TX/RX L2 30 mils < 2.5'', prefer 0.5'' - 1.5''

+3V_RDP2 >= PI3EQX1004 IC Count *20 mils

Other Power Net >= 20 mils

USB 3.1 Re-Driver PI3EQX1004 Circuit

A. Delete the Re-Driver IC which is not needed by Project

B. Modify Input USB 3.1 TX/RX Signal Net Name by Project

C. Modify Output USB 3.1 TX/RX Signal Net Name by Project

D. Choose PI3EQX1004 Power Solution by PI3EQX1004 count

E. If UU41 TXA output signals send to ASM1543, UU41C34 & UU41C35 change
from 11V232222416150 to 11V232334150 & mount UU41R34, UU41R35,
otherwise could delete UU41R34, UU41R35

F. If UU41 TXB output signals send to ASM1543, UU41C26 & UU41C27 change
from 11V232222416150 to 11V232334150 & mount UU41R26, UU41R27,
otherwise could delete UU41R26, UU41R27

G. If UU42 TXA output signals send to ASM1543, UU42C34 & UU42C35 change UU42R27 1 2 10V212220410 /NA
from 11V232222416150 to 11V232334150 & mount UU42R34, UU42R35, UU42R26 1 2
void220KOhm 10V212220410 /NA
GND

Port 34
otherwise could delete UU42R34, UU42R35 void220KOhm

EQA_UU42

GND
H. If UU42 TXB output signals send to ASM1543, UU42C26 & UU42C27 change
from 11V232222416150 to 11V232334150 & mount UU42R26, UU42R27, +3V_UU42

otherwise could delete UU42R26, UU42R27


G

53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
UU42
N/A 11V232334150

GND11
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
EQA
NC5
NC4
NC3
UU42C35 2 1 0.33UF/6.3V
S_U3D1TXDP4_RDT 96
1 38 S_U3D1TXDP4_RDT_O_C UU42C34 2 1 0.33UF/6.3V
I. If UU43 TXA output signals send to ASM1543, UU43C34 & UU43C35 change DT91
FGA_UU42 2
FGA NC2
37 S_U3D1TXDN4_RDT_O_C void
N/A 11V232334150
S_U3D1TXDN4_RDT 96
EN_AB NC1
from 11V232222416150 to 11V232334150 & mount UU43R34, UU43R35, 1 EN_AB_UU42 3
VDD3P3_1 VDD3P3_7
36 void N/A 11V232334150

otherwise could delete UU43R34, UU43R35 46 S_U3D1TXDP4_R


4
5
RXAP TXAP
35
34 S_U3D1RXDP4_RDT_I_C
UU42C31
UU42C30
2
2
1
1
0.33UF/6.3V
0.33UF/6.3V
S_U3D1RXDP4_RDT 96
46 S_U3D1TXDN4_R RXAN TXAN S_U3D1RXDN4_RDT 96
6 33 S_U3D1RXDN4_RDT_I_C void
N/A 11V232334150 UU42R30 1 2 10V212220410 /NA
TEST1#(VDD3P3) NC(VDD3P3)_2
N/A 7 32 void UU42R31 1 2
void220KOhm 10V212220410 /NA
VDD3P3_2 VDD3P3_6 GND
UU42C8 2 1 0.22UF/10V 8 31 void220KOhm
J. If UU43 TXB output signals send to ASM1543, UU43C26 & UU43C27 change 46 S_U3D1RXDP4_R
UU42C9 2 1 0.22UF/10V S_U3D1RXDP4_RDT_O_C 9
TXBP RXBP
30
One USB 3.1 Port use TXA & RXB,
C
TXBN RXBN
from 11V232222416150 to 11V232334150 & mount UU43R26, UU43R27, 46 S_U3D1RXDN4_R void
N/A S_U3D1RXDN4_RDT_O_C 10 29

otherwise could delete UU43R26, UU43R27


void FGC_UU42 11
FGC
EQC
EQB
FGB
28 EQB_UU42 another USB 3.1 Port use TXC & UU42R58 1 2 10V212220410 /X/

46 S_U3D1TXDN3_R
EQC_UU42 12
RXCN TXCN
27 FGB_UU42 RXD, can't swap UU42R46 1 void 2 10V212220410 /X/
GND
13 26 220KOhm 220KOhm

H
void
46 S_U3D1TXDP3_R RXCP TXCP
14 25
VDD3P3_3 VDD3P3_5
N/A 15 24
NC(VDD3P3)_1 TEST2#(VDD3P3)
UU42C16 2 1 0.22UF/10V 16 23 11V232222416150

D.2
46 S_U3D1RXDN3_R TXDN RXDN

VDD3P3_4
UU42C17 2 1 0.22UF/10V S_U3D1RXDN3_RDT_O_C 17 22 UU42C27 2 1 0.22UF/10V N/A
46 S_U3D1RXDP3_R TXDP RXDP S_U3D1TXDN3_RDT 90
void
N/A S_U3D1RXDP3_RDT_O_C S_U3D1TXDN3_RDT_O_C UU42C26 2 1 0.22UF/10V N/A

EN_CD
S_U3D1TXDP3_RDT 90

EQD
FGD
void S_U3D1TXDP3_RDT_O_C void 11V232222416150
void N/A 11V232334150
PI3EQX1004B1ZHEX+FDX UU42C23 2 1 0.33UF/6.3V
One USB 3.1 Port use RXA & TXB, another
Power Solution for PI3EQX1004 *2/3pcs

18
19
20
21
S_U3D1RXDN3_RDT 74,90
S_U3D1RXDN3_RDT_I_C UU42C22 2 1 0.33UF/6.3V
USB 3.1 Port use RXC & TXD, can't swap S_U3D1RXDP3_RDT_I_C void N/A 11V232334150 UU42R22 1 2 10V212220410 /NA
S_U3D1RXDP3_RDT 74,90
void UU42R23 1 2
void220KOhm 10V212220410 /NA
GND
void220KOhm
3.3V for PI3EQX1004, 340mA/pcs@S0 +3V_RDP2
DT92

1
1

1
UU42C3 UU42C7 UU42C14 UU42C21 EQD_UU42 EN_CD_UU42
0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V FGD_UU42
Vout=1.25*(2.15k+1.27k)/1.27k=3.366V
2

X7R X7R X7R X7R


2

2
UU42R1 N/A /X N/A /X
0Ohm
mbs_r0603
N/A
Place near power pin Pin3,
1

+3VDUAL_AUX +3V_RDP2
Pin7, Pin14, Pin21, Pin25,

2
GND
Pin32, Pin36, Pin40 UU42R3 UU42R5 UU42R7 UU42R9 UU42R11 UU42R13 UU42R15 UU42R17
SHORTPIN_0603_NM 1KOhm 1KOhm 1KOhm 1KOhm 1KOhm 1KOhm 1KOhm 1KOhm
UPU41R4 /Preicom1004 /X /X /Preicom1004 /Preicom1004 /X /X /Preicom1004
20190812 change 1 2

1
1

/X UU42C25 UU42C32 UU42C36 UU42C40


SHORTPIN_0603_NM 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V
1

UPU41R5 UPU30PC2 X7R X7R X7R X7R EQA_UU42 FGA_UU42 EQB_UU42 FGB_UU42 EQC_UU42 FGC_UU42 EQD_UU42 FGD_UU42
2

1 2 10UF/6.3V N/A /X N/A /X


mbs_c0603
2

/X X5R

2
N/A
UU42R2 UU42R4 UU42R6 UU42R8 UU42R10 UU42R12 UU42R14 UU42R16
GND EQ, FG Pin 1KOhm 68KOhm 68KOhm 1KOhm 1KOhm 68KOhm 68KOhm 1KOhm
GND /X /Preicom1004 /Preicom1004 /X /X /Preicom1004 /Preicom1004 /X
0 1K Ohm pull down
1

1
R 68K Ohm pull down

F Floating
Power Component place near each other! 1 1K Ohm Pull High GND GND GND GND GND GND GND GND

Port 56 +3V_UU43
GND
EQA_UU43

I
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39

UU43
11V232222416150

B
GND11
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
EQA
NC5
NC4
NC3

UU43C35 2 1 0.22UF/10V /NA


S_U3D1TXDP5_RDT 91
1 38 S_U3D1TXDP5_RDT_O_C UU43C34 2 1 0.22UF/10V /NA
DT5 FGA NC2 S_U3D1TXDN5_RDT 91
FGA_UU43 2 37 S_U3D1TXDN5_RDT_O_C void 11V232222416150
EN_AB NC1
1 EN_AB_UU43 3 36 void N/A 11V232334150
VDD3P3_1 VDD3P3_7
4 35 UU43C31 2 1 0.33UF/6.3V
46 S_U3D1TXDP5_R RXAP TXAP S_U3D1RXDP5_RDT 74,91
5 34 S_U3D1RXDP5_RDT_I_C UU43C30 2 1 0.33UF/6.3V
46 S_U3D1TXDN5_R RXAN TXAN S_U3D1RXDN5_RDT 74,91
6 33 S_U3D1RXDN5_RDT_I_C void
N/A 11V232334150 UU43R30 1 2 10V212220410 /NA
TEST1#(VDD3P3) NC(VDD3P3)_2
/NA 7 32 void UU43R31 1 2
void220KOhm 10V212220410 /NA
VDD3P3_2 VDD3P3_6 GND
UU43C8 2 1 0.22UF/10V 8 31 void220KOhm
46 S_U3D1RXDP5_R TXBP RXBP
UU43C9 2 1 0.22UF/10V S_U3D1RXDP5_RDT_O_C 9 30
One USB 3.1 Port use TXA & RXB,
C
46 S_U3D1RXDN5_R TXBN RXBN
void /NA S_U3D1RXDN5_RDT_O_C 10 29
void FGC_UU43 11
FGC
EQC
EQB
FGB
28 EQB_UU43 another USB 3.1 Port use TXC &
46 S_U3D1TXDN6_R
EQC_UU43 12
RXCN TXCN
27 FGB_UU43 RXD, can't swap
13 26
46 S_U3D1TXDP6_R RXCP TXCP
14 25
VDD3P3_3 VDD3P3_5
/NA 15 24
NC(VDD3P3)_1 TEST2#(VDD3P3)
UU43C16 2 1 0.22UF/10V 16 23 11V232222416150
46 S_U3D1RXDN6_R TXDN RXDN
VDD3P3_4

UU43C17 2 1 0.22UF/10V S_U3D1RXDN6_RDT_O_C 17 22 UU43C27 2 1 0.22UF/10V /NA


46 S_U3D1RXDP6_R TXDP RXDP S_U3D1TXDN6_RDT 91
void /NA S_U3D1RXDP6_RDT_O_C S_U3D1TXDN6_RDT_O_C UU43C26 2 1 0.22UF/10V /NA
EN_CD

S_U3D1TXDP6_RDT 91
EQD
FGD

void S_U3D1TXDP6_RDT_O_C void 11V232222416150


void N/A 11V232334150
PI3EQX1004B1ZHEX+FDX UU43C23 2 1 0.33UF/6.3V
One USB 3.1 Port use RXA & TXB, another
18
19
20
21

S_U3D1RXDN6_RDT 74,91
S_U3D1RXDN6_RDT_I_C UU43C22 2 1 0.33UF/6.3V
USB 3.1 Port use RXC & TXD, can't swap S_U3D1RXDP6_RDT_I_C void N/A 11V232334150 UU43R22 1 2 10V212220410 /NA
S_U3D1RXDP6_RDT 74,91
void UU43R23 1 2
void220KOhm 10V212220410 /NA
GND
void220KOhm
+3V_RDP2
DT6

1
1

UU43C3 UU43C7 UU43C14 UU43C21 EQD_UU43 EN_CD_UU43


0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V FGD_UU43
2

X7R X7R X7R X7R


2

UU43R1 /NA /X /NA /X


0Ohm
mbs_r0603
N/A
Place near power pin Pin3,
1

Pin7, Pin14, Pin21, Pin25,


2

2
GND
Pin32, Pin36, Pin40 UU43R3 UU43R5 UU43R7 UU43R9 UU43R11 UU43R13 UU43R15 UU43R17
1KOhm 1KOhm 1KOhm 1KOhm 1KOhm 1KOhm 1KOhm 1KOhm
/X /X /X /X /X /X /X /X
1

1
1

UU43C25 UU43C32 UU43C36 UU43C40


0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V
X7R X7R X7R X7R EQA_UU43 FGA_UU43 EQB_UU43 FGB_UU43 EQC_UU43 FGC_UU43 EQD_UU43 FGD_UU43
2

/NA /X /NA /X
2

2
UU43R2 UU43R4 UU43R6 UU43R8 UU43R10 UU43R12 UU43R14 UU43R16
GND EQ, FG Pin 68KOhm 68KOhm 68KOhm 1KOhm 68KOhm 68KOhm 68KOhm 1KOhm
/Preicom1004 /Preicom1004 /Preicom1004 /Preicom1004 /Preicom1004 /Preicom1004 /Preicom1004 /Preicom1004
0 1K Ohm pull down
1

1
R 68K Ohm pull down

F Floating

1 1K Ohm Pull High GND GND GND GND GND GND GND GND

<Variant Name>

Title : PI3EQX1004
Engineer:
ASUSTEK COMPUTER INC SZ Design IP
Size Project Name Rev
Custom
Chipset USB Re-Driver
1.0C

Date: Monday, December 16, 2019 Sheet 88 of 152


Ver 1.5
LED Driver對LED內部的Net LED Driver需連接外部的Net 根據ID規格可更換其他功能的Pin腳

依據Intel/AMD平台修改Power net 依據ID規格/空間,刪減LED組數/顆數/Header 註解

IC Power (Isink=350mA)
IC 超壓 for ADD 訊號VIH(0.7*VDD)用 雙向LVS上件(p.13),則LDO相關零件改不上件
Intel:請接+3VSB
AMD:請接+3.3V_ALW

LED1R20改上件

+5V_LED +5VDUAL_AUX
Net name :請依需求自行規劃
LED1R20
1
0Ohm
2
Intel:請接+5VDUAL_AUX
AMD:請接+5V_ALW Vout=1.25 * (1 + R_low/R_high) = 3.70V Pin define :請注意Pin順序是否主板跟燈卡上相同
/X/6K7750 (不上件) +3V_LED
mbs_r0603 +5VDUAL_AUX
LED1C16 0.1UF/16V LED1U4_PU1
雙向LVS上件,0ohm改上件 1
1 2 2
ADJ/GND
OUT Vout
4 5pin Cable list(請與機構確認cable長度需求):
3
IN
LED1C17 10UF/6.3V
w to b 8pin (S/T) 12017-00430300 w to b 5pin (R/A) 12017-00430200

1
LED1_PR4

5Pin
AZ2117H-ADJTRG1
1 2 1.27KOhm
mbs_c0805
/X/6K7750 (不上件) /6K7750

1
LED1_PC1 LED1_PC4

2
GND 請加大銅箔size 幫助散熱 R_hign LED1C166
請將LED1C16/C17擺放至Pin13、Pin64附近 10UF/6.3V
/6K7750
10UF/6.3V
/6K7750
14011-00770100 96mm 黑色塑膠HD
0.1UF/16V

1
14011-00770200 200mm 黑色塑膠HD

2
14011-00770300 160mm 醋酸膠布
14011-00770500 50mm 醋酸膠布

1
LED1_PR3 14011-00770400 130mm 醋酸膠布
RESET 2.49KOhm
14011-00770600 130mm 熱縮套管
/6K7750
+3VSB Intel:請接+3VSB R_low 14011-00770700 70mm 熱縮套管

2
AMD:請接+3.3V_ALW

因蘇州rule +5VSB_ATX會提高12V做測試,
2

LED1R21
需選用耐壓高的IC 20190219修改
8.2KOhm
/X/6K7750 (不上件)
1

LED1_RESET
使用CLRTC 按鈕連動LED1_RESET關燈
1

LED1C18
0.1UF/16V 請依需刪除offpage
2

X5R

GND
Location (請依照區域命名)

+3V_LED
8Pin
LDO_CAP
LED1U9

LED1_LDO_CAP 6
VDD1 14011-00700100 115mm 醋酸膠布;
w to b 8pin (R/A) 12017-00800100適用

Power
LED1C19
2

1UF/16V
請將LED1C4擺放至Pin14附近 14011-00700200 70mm 醋酸膠布
mbs_c0603 5 13pin 14011-00700300 110mm 醋酸膠布
1

VSS1

31
VSS2

GND 33 17
VSS3 GPIO20/WKU20/PWM4

GND
16
GND
GPIO1E/WKU1E/SPI0_MISO/PWM2 w to b 13pin (S/T) 12017-00960100
ACPI (切換S0 / 非S0特效) 4 15
13Pin

RGB 4
Reset GPIO1C/WKU1C/SPI0_CLK/PWM0
LED1_RESET

RST
+3V 7 12
LDO_CAP GPIO11/WKU11/PWM41
LED1_LDO_CAP 14011-02620200 50mm 醋酸膠布

LDO
LED1R22 8.2KOhm 11
請依各自機種修改net name GPIO10/SWD_SDA/WKU10/PWM40 14011-02620100 370mm 醋酸膠布
2 1 LED1_ACPI9 20 SWD
10 14011-02620300 60mm 醋酸膠布

RGB 3
43 U_USB1+ USB_D+ GPIO0F/SWD_SCK/WKU0F/PWM39
14011-02620000 130mm 醋酸膠布

SWD
PCH USB 19
Full Speed (12 Mbps)
Isink=20mA/pin
43 U_USB1- USB_D-
Control LED/OLED

USB
SMBUS1 (update user code) 要放置在IC的SMBUS1附近 28
GPIO33/WKU33/PWM23

8 27
GPIO0A/WKU0A/X-ISP(EDI)_DA/TXD0 GPIO32/WKU32/PWM22
0Ohm LED1R23 SIO net name SMBUS1 LED1_SMB1_DAT Default SMBUS
SMB(S)
1 2 9

SMBUS1
update
26

RGB 2
O_SMBDATA_VSB 66 update FW GPIO0B/WKU0B/X-ISP(EDI)_CK/RXD0 GPIO31/WKU31/PWM21
LED1_SMB1_DAT LED1_SMB1_CLK Default SMBUS

0Ohm LED1R24
1 2 ACPI 18
GPIO22/WKU22/PWM6/Trap1 GPIO30/WKU30/PWM20
25
O_SMBCLK_VSB 66 change S0/S3,4,5 effect
LED1_SMB1_CLK LED1_ACPI9 LED1A_B
+3VSB
ACPI
24
GPIO2F/WKU2F/PWM19
2.7KOHM LED1R25 LED1A_G
14 23

RGB 1
Tx測點 GPIO1A/WKU1A/TXD1/PWM46 GPIO2E/WKU2E/PWM18
2.7KOHM
1 LED1R26
2 LED1_SMB1_CLK LED1U9_TX LED1A_R
/X/6K7750 Isink=50mA/pin
Tx

Intel:請接+3VSB
AMD:請接+3.3V_ALW
2.7KOHM
1 LED1R126
2 LED1_SMB1_DAT
/X/6K7750
22 32
GPIO28/WKU28/PWM12/Trap0 ADD2 GPIO36/WKU36/OWE1/PWM26 LED1_ADD2 97
1 2 LED1_DIR1 控制ADD LED LVS LED1_DIR1 LED1_ADD2
/X/6K7750
21 30
ADD Header
reset retasking (LED on/off) GPIO27/WKU27/PWM11 ADD1 GPIO35/WKU35/OWE0/PWM25 LED1_ADD1 97
33PF/50V LED1C20 O2_RSTBTN_LED_SW_R LED1_ADD1
3
1 Wire

1
1 2 LED1_SMB1_CLK
+5V_LED GPIO04/WKU04/OSC_IN GPIO00/WKU00/OWE2/PWM27/TrapENB 此pin禁用,為strapping pin,會影響pin10及pin11的訊號輸出
/X/6K7750 2
GPIO02/WKU02/SPI1_CLK/PWM29 /TrapM0
33PF/50V LED1C21
13
GPIO16/WKU16/SDAT
1 2 LED1_SMB1_DAT
/X/6K7750 (不上件)
29
GPIO34/WKU34/PWM24
GPIO

GND

AURA42UA0

reset retasking (LED on/off)


透過reset button 開關LED 特效

使用此功能,LED1R27 改上件

EC1 Netname 0Ohm LED1R27


1 2
72 O2_RSTBTN_LED_SW
O2_RSTBTN_LED_SW_R

未使用此功能,LED1R1029 改上件
+3VSB
LED1R1029 8.2KOhm
Intel:請接+3VSB
AMD:請接+3.3V_ALW
2 1 O2_RSTBTN_LED_SW_R
/X/6K7750

LED1A_B 109
不論S0/S5
(GPI)H: 表示保持目前狀態,不論目前是亮或是暗 LED1A_G 109 RGB Header
GPOL: 將燈光效果做關閉
BIOS.SW 選項不須與此連動 LED1A_R 109

<Variant Name>

請留Header debug
Title : ENE6K7750(64Pin)
1 DT53 /X/6K7750
LED1_SMB1_CLK 1 DT54 /X/6K7750
ASUSTek Computer Inc.
Engineer: Kaizer_Luo
LED1_SMB1_DAT 1 DT55 /X/6K7750
LED1U9_TX Size Project Name Rev
Custom LED Standard Circiut 1.0

Date: Thursday, December 12, 2019 Sheet 107 of 152

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